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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_zcp.h
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: niu_zcp.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38/*%W% %G%*/
39
40/*****************************************************************
41 *
42 * File Name : niu_zcp.h
43 * Author Name : John Lo
44 * Description :
45 * Parent Module:
46 * Child Module:
47 * Interface Mod:
48 * Date Created : 4/29/04
49 *
50 * Copyright (c) 2020, Sun Microsystems, Inc.
51 * Sun Proprietary and Confidential
52 *
53 * Modification :
54 *
55 * Synthesis Notes:
56 *
57 ****************************************************************/
58
59`define RSP_CMD_ERR 4'hF
60`define RSP_DAT_ERR 2'b11
61`define CML_WO_DATA 3'b110
62
63
64/* ----- start copy from xmac.h ----- */
65`define DBUG_W 32
66`define DBUG_W_SUB1 `DBUG_W - 1
67`define DBUG_R `DBUG_W_SUB1:0
68
69/* ----- start copy from xmac.h ----- */
70`define BYTE 7:0
71`define BYTE0 7:0
72`define BYTE1 15:8
73`define BYTE2 23:16
74`define BYTE3 31:24
75`define BYTE4 39:32
76`define BYTE5 47:40
77`define BYTE6 55:48
78`define BYTE7 63:56
79`define BYTE8 71:64
80`define BYTE9 79:72
81`define BYTE10 87:80
82`define BYTE11 95:88
83`define BYTE12 103:96
84`define BYTE13 111:104
85`define BYTE14 119:112
86`define BYTE15 127:120
87`define BYTE16 135:128
88`define BYTE17 143:136
89`define BYTE18 151:144
90`define BYTE19 159:152
91/* ----- end copy from xmac.h ----- */
92
93
94`define WORD0 31:0
95`define WORD1 63:32
96`define WORD2 95:64
97`define WORD3 127:96
98`define WORD4 159:128
99`define WORD5 191:160
100`define WORD6 223:192
101`define WORD7 255:224
102
103`define W32D0 31:0
104`define W32D1 63:32
105`define W32D2 95:64
106`define W32D3 127:96
107`define W32D4 159:128
108`define W32D5 191:160
109`define W32D6 223:192
110`define W32D7 255:224
111`define W32D8 287:256
112`define W32D9 319:288
113`define W32D10 351:320
114`define W32D11 383:352
115`define W32D12 415:384
116`define W32D13 447:416
117`define W32D14 479:448
118`define W32D15 511:480
119`define W32D16 543:512
120`define W32D17 575:544
121`define W32D18 607:576
122`define W32D19 639:608
123`define W32D20 671:640
124`define W32D21 703:672
125`define W32D22 735:704
126`define W32D23 767:736
127`define W32D24 799:768
128`define W32D25 831:800
129`define W32D26 863:832
130`define W32D27 895:864
131`define W32D28 927:896
132`define W32D29 959:928
133`define W32D30 991:960
134`define W32D31 1023:992
135
136`define W128D0 127:0
137`define W128D1 255:128
138`define W128D2 383:256
139`define W128D3 511:384
140`define W128D4 639:512
141`define W128D5 767:640
142`define W128D6 895:768
143`define W128D7 1023:896
144
145
146/**********************************
147 ********* Zero copy stuff ********
148 **********************************/
149`define TCP_SEQ_SPACE 31:0
150`define TCP_SEQ_MSB 32
151`define XPAN_TCP_SEQ_SPACE 32:0
152`define PKT_LEN_W 16
153`define PKT_LEN_R 15:0
154
155// ----- zcp ififo -----------------------------------------
156`define IFIFO_W 216
157`define IFIFO_W_SUB1 `IFIFO_W - 1
158`define IFIFO_W_R `IFIFO_W_SUB1:0
159`define IFIFO_A 2
160`define IFIFO_A_SUB1 `IFIFO_A - 1
161`define IFIFO_A_R `IFIFO_A_SUB1:0
162`define IFIFO_PTR `IFIFO_A:0
163`define IFIFO_A_ADD1 `IFIFO_A +1
164`define IFIFO_D 4
165`define IFIFO_D_SUB1 `IFIFO_D -1
166`define IFIFO_D_R `IFIFO_D_SUB1:0
167
168// ----- start of REQ RSP FIFO area -------------------------
169// --reqfifo address and depth--
170`define REQFIFO_W 72
171`define REQFIFO_W_SUB1 `REQFIFO_W - 1
172`define REQFIFO_W_R `REQFIFO_W_SUB1:0
173`define REQFIFO_W_ECC `REQFIFO_W +8
174`define REQFIFO_W_ECC_SUB1 `REQFIFO_W_ECC - 1
175`define REQFIFO_W_ECC_R `REQFIFO_W_ECC_SUB1:0
176
177// --rrfifo address and depth--
178`define RRFIFO_W 23
179`define RRFIFO_W_SUB1 `RRFIFO_W - 1
180`define RRFIFO_W_R `RRFIFO_W_SUB1:0
181`define RRFIFO_W_ECC `RRFIFO_W + 7
182`define RRFIFO_W_ECC_SUB1 `RRFIFO_W_ECC - 1
183`define RRFIFO_W_ECC_R `RRFIFO_W_ECC_SUB1:0
184
185// --rspfifo address and depth--
186`define RSPFIFO_W 1024
187`define RSPFIFO_W_SUB1 `RSPFIFO_W - 1
188`define RSPFIFO_W_R `RSPFIFO_W_SUB1:0
189`define RSPFIFO_W_ECC 1152
190`define RSPFIFO_W_ECC_SUB1 `RSPFIFO_W_ECC - 1
191`define RSPFIFO_W_ECC_R `RSPFIFO_W_ECC_SUB1:0
192
193// --sftfifo address and depth--
194`define SFTFIFO_W 128
195`define SFTFIFO_W_SUB1 `SFTFIFO_W - 1
196`define SFTFIFO_W_R `SFTFIFO_W_SUB1:0
197`define SFTFIFO_W_ECC `SFTFIFO_W + 8
198`define SFTFIFO_W_ECC_SUB1 `SFTFIFO_W_ECC - 1
199`define SFTFIFO_W_ECC_R `SFTFIFO_W_ECC_SUB1:0
200
201// --va common section for all req and response fifo --
202`define VAFIFO_A 4
203`define VAFIFO_A_SUB1 `VAFIFO_A - 1
204`define VAFIFO_A_R `VAFIFO_A_SUB1:0
205`define VAFIFO_A_PTR `VAFIFO_A:0
206`define VAFIFO_A_ADD1 `VAFIFO_A +1
207`define VAFIFO_D 16
208`define VAFIFO_D_SUB1 `VAFIFO_D -1
209`define VAFIFO_D_R `VAFIFO_D_SUB1:0
210// ----- end of REQ RSP FIFO area -------------------------
211
212// ----- cfifo ---------------------------------------------
213// --cfifo width--
214`define CFIFO_W 130
215`define CFIFO_W_SUB1 `CFIFO_W - 1
216`define CFIFO_W_SUB2 `CFIFO_W - 2
217`define CFIFO_W_R `CFIFO_W_SUB1:0
218`define CFIFO_SOP 2'b01
219`define CFIFO_EOP 2'b10
220
221// --cfifo with ECC width--
222`define CFIFO_W_ECC `CFIFO_W + 16
223`define CFIFO_W_ECC_SUB1 `CFIFO_W_ECC - 1
224`define CFIFO_W_ECC_SUB2 `CFIFO_W_ECC - 2
225`define CFIFO_W_ECC_R `CFIFO_W_ECC_SUB1:0
226
227// --cfifo address and depth--
228// 32KB
229`define CFIFO_A11 11
230`define CFIFO_A11_R 10:0
231`define CFIFO_D2K 12'd1664
232`define CFIFO_D2K_SUB1 `CFIFO_D2K - 12'd01
233`define CFIFO_A11_PTR `CFIFO_A11:0
234`define CFIFO_A11_ADD1 `CFIFO_A11 +1
235// 16KB
236`define CFIFO_A10 10
237`define CFIFO_A10_R 9:0
238`define CFIFO_D1K 11'd832
239`define CFIFO_D1K_SUB1 `CFIFO_D1K - 11'd01
240`define CFIFO_A10_PTR `CFIFO_A10:0
241`define CFIFO_A10_ADD1 `CFIFO_A10 +1
242`define THRESHOLD_A10 10'd1000
243// 8KB
244`define CFIFO_A9 9
245`define CFIFO_A9_R 8:0
246`define CFIFO_D512 10'd512
247`define CFIFO_A9_PTR `CFIFO_A9:0
248`define CFIFO_A9_ADD1 `CFIFO_A9 +1
249
250// ----- tt word ---------------------------------------------
251`define DWORD0 31:0
252`define DWORD1 63:32
253`define DWORD2 95:64
254`define DWORD3 127:96
255`define DWORD4 159:128
256`define DWORD5 191:160
257`define DWORD6 223:192
258`define DWORD7 255:224
259
260// ----- va_ram ---------------------------------------------
261 // 128 data bits/va_ram
262`define VA_W 128
263`define VA_W_SUB1 `VA_W -1
264`define VA_R `VA_W_SUB1:0
265 // 16 parity bits/va_ram
266`define VA_PW 16
267`define VA_PW_SUB1 `VA_PW -1
268`define VA_PR `VA_PW_SUB1:0
269
270// ----- dn_ram ---------------------------------------------
271`define DN_W 136
272`define DN_W_SUB1 `DN_W -1
273`define DN_R `DN_W_SUB1:0
274`define DN_PW 17
275`define DN_PW_SUB1 `DN_PW -1
276`define DN_PR `DN_PW_SUB1:0
277
278// ----- st_ram ---------------------------------------------
279`define ST_W 112
280`define ST_W_SUB1 `ST_W -1
281`define ST_R `ST_W_SUB1:0
282`define ST_PW 14
283`define ST_PW_SUB1 `ST_PW -1
284`define ST_PR `ST_PW_SUB1:0
285// ----- dmaw -----------------------------------------------
286`define DMA_W 44
287`define DMA_W_SUB1 `DMA_W -1
288`define DMA_R `DMA_W_SUB1:0
289
290// ----- header field definition ---------------------------
291// ----- Big Endian, byte definition -----------------
292`define BW 216
293`define BMSB0 `BW -1
294`define BMSB1 `BMSB0 -8
295`define BMSB2 `BMSB1 -8
296`define BMSB3 `BMSB2 -8
297`define BMSB4 `BMSB3 -8
298`define BMSB5 `BMSB4 -8
299`define BMSB6 `BMSB5 -8
300`define BMSB7 `BMSB6 -8
301`define BMSB8 `BMSB7 -8
302`define BMSB9 `BMSB8 -8
303`define BMSB10 `BMSB9 -8
304`define BMSB11 `BMSB10 -8
305`define BMSB12 `BMSB11 -8
306`define BMSB13 `BMSB12 -8
307`define BMSB14 `BMSB13 -8
308`define BMSB15 `BMSB14 -8
309`define BMSB16 `BMSB15 -8
310`define BMSB17 `BMSB16 -8
311`define BMSB18 `BMSB17 -8
312`define BMSB19 `BMSB18 -8
313`define BMSB20 `BMSB19 -8
314`define BMSB21 `BMSB20 -8
315`define BMSB22 `BMSB21 -8
316`define BMSB23 `BMSB22 -8
317`define BMSB24 `BMSB23 -8
318`define BMSB25 `BMSB24 -8
319`define BMSB26 `BMSB25 -8
320`define BMSB27 `BMSB26 -8
321`define BMSB28 `BMSB27 -8
322`define BMSB29 `BMSB28 -8
323`define BMSB30 `BMSB29 -8
324`define BMSB31 `BMSB30 -8
325`define BMSB32 `BMSB31 -8
326`define BMSB33 `BMSB32 -8
327`define BMSB34 `BMSB33 -8
328`define BMSB35 `BMSB34 -8
329`define BMSB36 `BMSB35 -8
330`define BMSB37 `BMSB36 -8
331`define BMSB38 `BMSB37 -8
332`define BMSB39 `BMSB38 -8
333`define BMSB40 `BMSB39 -8
334`define BMSB41 `BMSB40 -8
335`define BMSB42 `BMSB41 -8
336`define BMSB43 `BMSB42 -8
337`define BMSB44 `BMSB43 -8
338`define BMSB45 `BMSB44 -8
339`define BMSB46 `BMSB45 -8
340`define BMSB47 `BMSB46 -8
341`define BMSB48 `BMSB47 -8
342`define BMSB49 `BMSB48 -8
343`define BMSB50 `BMSB49 -8
344`define BMSB51 `BMSB50 -8
345`define BMSB52 `BMSB51 -8
346`define BMSB53 `BMSB52 -8
347`define BMSB54 `BMSB53 -8
348`define BMSB55 `BMSB54 -8
349`define BMSB56 `BMSB55 -8
350`define BMSB57 `BMSB56 -8
351`define BMSB58 `BMSB57 -8
352`define BMSB59 `BMSB58 -8
353`define BMSB60 `BMSB59 -8
354`define BMSB61 `BMSB60 -8
355`define BMSB62 `BMSB61 -8
356`define BMSB63 `BMSB62 -8
357
358`define BLSB0 `BMSB0 -7
359`define BLSB1 `BMSB1 -7
360`define BLSB2 `BMSB2 -7
361`define BLSB3 `BMSB3 -7
362`define BLSB4 `BMSB4 -7
363`define BLSB5 `BMSB5 -7
364`define BLSB6 `BMSB6 -7
365`define BLSB7 `BMSB7 -7
366`define BLSB8 `BMSB8 -7
367`define BLSB9 `BMSB9 -7
368`define BLSB10 `BMSB10 -7
369`define BLSB11 `BMSB11 -7
370`define BLSB12 `BMSB12 -7
371`define BLSB13 `BMSB13 -7
372`define BLSB14 `BMSB14 -7
373`define BLSB15 `BMSB15 -7
374`define BLSB16 `BMSB16 -7
375`define BLSB17 `BMSB17 -7
376`define BLSB18 `BMSB18 -7
377`define BLSB19 `BMSB19 -7
378`define BLSB20 `BMSB20 -7
379`define BLSB21 `BMSB21 -7
380`define BLSB22 `BMSB22 -7
381`define BLSB23 `BMSB23 -7
382`define BLSB24 `BMSB24 -7
383`define BLSB25 `BMSB25 -7
384`define BLSB26 `BMSB26 -7
385`define BLSB27 `BMSB27 -7
386`define BLSB28 `BMSB28 -7
387`define BLSB29 `BMSB29 -7
388`define BLSB30 `BMSB30 -7
389`define BLSB31 `BMSB31 -7
390`define BLSB32 `BMSB32 -7
391`define BLSB33 `BMSB33 -7
392`define BLSB34 `BMSB34 -7
393`define BLSB35 `BMSB35 -7
394`define BLSB36 `BMSB36 -7
395`define BLSB37 `BMSB37 -7
396`define BLSB38 `BMSB38 -7
397`define BLSB39 `BMSB39 -7
398`define BLSB40 `BMSB40 -7
399`define BLSB41 `BMSB41 -7
400`define BLSB42 `BMSB42 -7
401`define BLSB43 `BMSB43 -7
402`define BLSB44 `BMSB44 -7
403`define BLSB45 `BMSB45 -7
404`define BLSB46 `BMSB46 -7
405`define BLSB47 `BMSB47 -7
406`define BLSB48 `BMSB48 -7
407`define BLSB49 `BMSB49 -7
408`define BLSB50 `BMSB50 -7
409`define BLSB51 `BMSB51 -7
410`define BLSB52 `BMSB52 -7
411`define BLSB53 `BMSB53 -7
412`define BLSB54 `BMSB54 -7
413`define BLSB55 `BMSB55 -7
414`define BLSB56 `BMSB56 -7
415`define BLSB57 `BMSB57 -7
416`define BLSB58 `BMSB58 -7
417`define BLSB59 `BMSB59 -7
418`define BLSB60 `BMSB60 -7
419`define BLSB61 `BMSB61 -7
420`define BLSB62 `BMSB62 -7
421`define BLSB63 `BMSB63 -7
422
423`define BBYTE0 `BMSB0 : `BLSB0
424`define BBYTE1 `BMSB1 : `BLSB1
425`define BBYTE2 `BMSB2 : `BLSB2
426`define BBYTE3 `BMSB3 : `BLSB3
427`define BBYTE4 `BMSB4 : `BLSB4
428`define BBYTE5 `BMSB5 : `BLSB5
429`define BBYTE6 `BMSB6 : `BLSB6
430`define BBYTE7 `BMSB7 : `BLSB7
431`define BBYTE8 `BMSB8 : `BLSB8
432`define BBYTE9 `BMSB9 : `BLSB9
433`define BBYTE10 `BMSB10: `BLSB10
434`define BBYTE11 `BMSB11: `BLSB11
435`define BBYTE12 `BMSB12: `BLSB12
436`define BBYTE13 `BMSB13: `BLSB13
437`define BBYTE14 `BMSB14: `BLSB14
438`define BBYTE15 `BMSB15: `BLSB15
439`define BBYTE16 `BMSB16: `BLSB16
440`define BBYTE17 `BMSB17: `BLSB17
441`define BBYTE18 `BMSB18: `BLSB18
442`define BBYTE19 `BMSB19: `BLSB19
443`define BBYTE20 `BMSB20: `BLSB20
444`define BBYTE21 `BMSB21: `BLSB21
445`define BBYTE22 `BMSB22: `BLSB22
446`define BBYTE23 `BMSB23: `BLSB23
447`define BBYTE24 `BMSB24: `BLSB24
448`define BBYTE25 `BMSB25: `BLSB25
449`define BBYTE26 `BMSB26: `BLSB26
450`define BBYTE27 `BMSB27: `BLSB27
451`define BBYTE28 `BMSB28: `BLSB28
452`define BBYTE29 `BMSB29: `BLSB29
453`define BBYTE30 `BMSB30: `BLSB30
454`define BBYTE31 `BMSB31: `BLSB31
455
456//////////////////////////////////////////////////////
457// ----- page handle definition -- its a 20 bit bus --
458// ----- little endian -------------------------------
459`define PW 320
460`define PMS15 319
461`define PMS14 `PMS15 -20
462`define PMS13 `PMS14 -20
463`define PMS12 `PMS13 -20
464`define PMS11 `PMS12 -20
465`define PMS10 `PMS11 -20
466`define PMS9 `PMS10 -20
467`define PMS8 `PMS9 -20
468`define PMS7 `PMS8 -20
469`define PMS6 `PMS7 -20
470`define PMS5 `PMS6 -20
471`define PMS4 `PMS5 -20
472`define PMS3 `PMS4 -20
473`define PMS2 `PMS3 -20
474`define PMS1 `PMS2 -20
475`define PMS0 `PMS1 -20
476
477`define PLS0 `PMS0 -19
478`define PLS1 `PMS1 -19
479`define PLS2 `PMS2 -19
480`define PLS3 `PMS3 -19
481`define PLS4 `PMS4 -19
482`define PLS5 `PMS5 -19
483`define PLS6 `PMS6 -19
484`define PLS7 `PMS7 -19
485`define PLS8 `PMS8 -19
486`define PLS9 `PMS9 -19
487`define PLS10 `PMS10 -19
488`define PLS11 `PMS11 -19
489`define PLS12 `PMS12 -19
490`define PLS13 `PMS13 -19
491`define PLS14 `PMS14 -19
492`define PLS15 `PMS15 -19
493
494// ----- Winfifo calculation definition --------------------
495// 4 buffer WINFIFO
496`define WIN2_MSB 2
497`define WIN2_PTR `WIN2_MSB : 0
498`define WIN2_MSB_SUB_1 `WIN2_MSB - 1
499`define WIN2_A `WIN2_MSB_SUB_1 : 0
500`define WIN2_D 3'd4
501
502// 8 buffer WINFIFO
503`define WIN3_MSB 3
504`define WIN3_PTR `WIN3_MSB : 0
505`define WIN3_MSB_SUB_1 `WIN3_MSB - 1
506`define WIN3_A `WIN3_MSB_SUB_1 : 0
507`define WIN3_D 4'd8
508
509// 16 buffer WINFIFO
510`define WIN4_MSB 4
511`define WIN4_PTR `WIN4_MSB : 0
512`define WIN4_MSB_SUB_1 `WIN4_MSB - 1
513`define WIN4_A `WIN4_MSB_SUB_1 : 0
514`define WIN4_D 5'd16
515
516// 32 buffer WINFIFO
517`define WIN5_MSB 5
518`define WIN5_PTR `WIN5_MSB : 0
519`define WIN5_MSB_SUB_1 `WIN5_MSB - 1
520`define WIN5_A `WIN5_MSB_SUB_1 : 0
521`define WIN5_D 6'd32
522
523// ----- HoQ calculation definition ------------------------
524// 8 buffer ring
525`define HOQ3_MSB 3
526`define HOQ3_PTR `HOQ3_MSB : 0
527`define HOQ3_MSB_SUB_1 `HOQ3_MSB - 1
528`define HOQ3_A `HOQ3_MSB_SUB_1 : 0
529`define HOQ3_MSB_ADD_1 `HOQ3_MSB + 1
530`define HOQ3_D 4'd8
531`define HOQ3_DD 16'd8
532// 16 buffer ring
533`define HOQ4_MSB 4
534`define HOQ4_PTR `HOQ4_MSB : 0
535`define HOQ4_MSB_SUB_1 `HOQ4_MSB - 1
536`define HOQ4_A `HOQ4_MSB_SUB_1 : 0
537`define HOQ4_MSB_ADD_1 `HOQ4_MSB + 1
538`define HOQ4_D 5'd16
539`define HOQ4_DD 16'd16
540// 32 buffer ring
541`define HOQ5_MSB 5
542`define HOQ5_PTR `HOQ5_MSB : 0
543`define HOQ5_MSB_SUB_1 `HOQ5_MSB - 1
544`define HOQ5_A `HOQ5_MSB_SUB_1 : 0
545`define HOQ5_MSB_ADD_1 `HOQ5_MSB + 1
546`define HOQ5_D 6'd32
547`define HOQ5_DD 16'd32
548// 64 buffer ring
549`define HOQ6_MSB 6
550`define HOQ6_PTR `HOQ6_MSB : 0
551`define HOQ6_MSB_SUB_1 `HOQ6_MSB - 1
552`define HOQ6_A `HOQ6_MSB_SUB_1 : 0
553`define HOQ6_MSB_ADD_1 `HOQ6_MSB + 1
554`define HOQ6_D 7'd64
555`define HOQ6_DD 16'd64
556//128 buffer ring
557`define HOQ7_MSB 7
558`define HOQ7_PTR `HOQ7_MSB : 0
559`define HOQ7_MSB_SUB_1 `HOQ7_MSB - 1
560`define HOQ7_A `HOQ7_MSB_SUB_1 : 0
561`define HOQ7_MSB_ADD_1 `HOQ7_MSB + 1
562`define HOQ7_D 8'd128
563`define HOQ7_DD 16'd128
564//256 buffer ring
565`define HOQ8_MSB 8
566`define HOQ8_PTR `HOQ8_MSB : 0
567`define HOQ8_MSB_SUB_1 `HOQ8_MSB - 1
568`define HOQ8_A `HOQ8_MSB_SUB_1 : 0
569`define HOQ8_MSB_ADD_1 `HOQ8_MSB + 1
570`define HOQ8_D 9'd256
571`define HOQ8_DD 16'd256
572//512 buffer ring
573`define HOQ9_MSB 9
574`define HOQ9_PTR `HOQ9_MSB : 0
575`define HOQ9_MSB_SUB_1 `HOQ9_MSB - 1
576`define HOQ9_A `HOQ9_MSB_SUB_1 : 0
577`define HOQ9_MSB_ADD_1 `HOQ9_MSB + 1
578`define HOQ9_D 10'd512
579`define HOQ9_DD 16'd512
580// 1K buffer ring
581`define HOQ10_MSB 10
582`define HOQ10_PTR `HOQ10_MSB : 0
583`define HOQ10_MSB_SUB_1 `HOQ10_MSB - 1
584`define HOQ10_A `HOQ10_MSB_SUB_1 : 0
585`define HOQ10_MSB_ADD_1 `HOQ10_MSB + 1
586`define HOQ10_D 11'd1024
587`define HOQ10_DD 16'd1024
588// ---------- crossing 4KB start from here ----------
589 // HoQ
590`define HoQ_4KB_FLAG_BIT 10
591`define HoQ_4KB_FLAG_BIT_ADD_1 `HoQ_4KB_FLAG_BIT + 1
592`define HoQ_4KB_FLAG_BIT_SUB_1 `HoQ_4KB_FLAG_BIT - 1
593`define HoQ_4KB_A `HoQ_4KB_FLAG_BIT_SUB_1 :0
594// 2K buffer ring
595`define HOQ11_MSB 11
596`define HOQ11_PTR `HOQ11_MSB : 0
597`define HOQ11_MSB_SUB_1 `HOQ11_MSB - 1
598`define HOQ11_A `HOQ11_MSB_SUB_1 : 0
599`define HOQ11_MSB_ADD_1 `HOQ11_MSB + 1
600`define HOQ11_D 12'd2048
601`define HOQ11_DD 16'd2048
602 //`define HOQ11_BIT11_UP_A `HOQ11_MSB_SUB_1 : `HoQ_4KB_FLAG_BIT_ADD_1
603// 4K buffer ring
604`define HOQ12_MSB 12
605`define HOQ12_PTR `HOQ12_MSB : 0
606`define HOQ12_MSB_SUB_1 `HOQ12_MSB - 1
607`define HOQ12_A `HOQ12_MSB_SUB_1 : 0
608`define HOQ12_MSB_ADD_1 `HOQ12_MSB + 1
609`define HOQ12_D 13'd4096
610`define HOQ12_DD 16'd4096
611`define HOQ12_BIT11_UP_A `HOQ12_MSB_SUB_1 : `HoQ_4KB_FLAG_BIT_ADD_1
612// 8K buffer ring
613`define HOQ13_MSB 13
614`define HOQ13_PTR `HOQ13_MSB : 0
615`define HOQ13_MSB_SUB_1 `HOQ13_MSB - 1
616`define HOQ13_A `HOQ13_MSB_SUB_1 : 0
617`define HOQ13_MSB_ADD_1 `HOQ13_MSB + 1
618`define HOQ13_D 14'd8192
619`define HOQ13_DD 16'd8192
620`define HOQ13_BIT11_UP_A `HOQ13_MSB_SUB_1 : `HoQ_4KB_FLAG_BIT_ADD_1
621// 16K buffer ring
622`define HOQ14_MSB 14
623`define HOQ14_PTR `HOQ14_MSB : 0
624`define HOQ14_MSB_SUB_1 `HOQ14_MSB - 1
625`define HOQ14_A `HOQ14_MSB_SUB_1 : 0
626`define HOQ14_MSB_ADD_1 `HOQ14_MSB + 1
627`define HOQ14_D 15'd16384
628`define HOQ14_DD 16'd16384
629`define HOQ14_BIT11_UP_A `HOQ14_MSB_SUB_1 : `HoQ_4KB_FLAG_BIT_ADD_1
630// 32K buffer ring
631`define HOQ15_MSB 15
632`define HOQ15_PTR `HOQ15_MSB : 0
633`define HOQ15_MSB_SUB_1 `HOQ15_MSB - 1
634`define HOQ15_A `HOQ15_MSB_SUB_1 : 0
635`define HOQ15_MSB_ADD_1 `HOQ15_MSB + 1
636`define HOQ15_D 16'd32768
637`define HOQ15_DD 16'd32768
638`define HOQ15_BIT11_UP_A `HOQ15_MSB_SUB_1 : `HoQ_4KB_FLAG_BIT_ADD_1
639
640// ----- Ring Base calculation definition --------------------
641`define HOQ3_BAR 38:0
642`define HOQ4_BAR 38:1
643`define HOQ5_BAR 38:2
644`define HOQ6_BAR 38:3
645`define HOQ7_BAR 38:4
646`define HOQ8_BAR 38:5
647`define HOQ9_BAR 38:6
648`define HOQ10_BAR 38:7
649`define HOQ11_BAR 38:8
650`define HOQ12_BAR 38:9
651`define HOQ13_BAR 38:10
652`define HOQ14_BAR 38:11
653`define HOQ15_BAR 38:12
654
655// ----- buffer order definition -----------------------------
656// ----- Little Endian -- 32 bit word definition -------
657`define VW 1024
658
659`define VMSW0 31
660`define VMSW1 `VMSW0 +32
661`define VMSW2 `VMSW1 +32
662`define VMSW3 `VMSW2 +32
663`define VMSW4 `VMSW3 +32
664`define VMSW5 `VMSW4 +32
665`define VMSW6 `VMSW5 +32
666`define VMSW7 `VMSW6 +32
667`define VMSW8 `VMSW7 +32
668`define VMSW9 `VMSW8 +32
669`define VMSW10 `VMSW9 +32
670`define VMSW11 `VMSW10 +32
671`define VMSW12 `VMSW11 +32
672`define VMSW13 `VMSW12 +32
673`define VMSW14 `VMSW13 +32
674`define VMSW15 `VMSW14 +32
675`define VMSW16 `VMSW15 +32
676`define VMSW17 `VMSW16 +32
677`define VMSW18 `VMSW17 +32
678`define VMSW19 `VMSW18 +32
679`define VMSW20 `VMSW19 +32
680`define VMSW21 `VMSW20 +32
681`define VMSW22 `VMSW21 +32
682`define VMSW23 `VMSW22 +32
683`define VMSW24 `VMSW23 +32
684`define VMSW25 `VMSW24 +32
685`define VMSW26 `VMSW25 +32
686`define VMSW27 `VMSW26 +32
687`define VMSW28 `VMSW27 +32
688`define VMSW29 `VMSW28 +32
689`define VMSW30 `VMSW29 +32
690`define VMSW31 `VMSW30 +32
691
692
693`define VLSW0 `VMSW0 -31
694`define VLSW1 `VMSW1 -31
695`define VLSW2 `VMSW2 -31
696`define VLSW3 `VMSW3 -31
697`define VLSW4 `VMSW4 -31
698`define VLSW5 `VMSW5 -31
699`define VLSW6 `VMSW6 -31
700`define VLSW7 `VMSW7 -31
701`define VLSW8 `VMSW8 -31
702`define VLSW9 `VMSW9 -31
703`define VLSW10 `VMSW10 -31
704`define VLSW11 `VMSW11 -31
705`define VLSW12 `VMSW12 -31
706`define VLSW13 `VMSW13 -31
707`define VLSW14 `VMSW14 -31
708`define VLSW15 `VMSW15 -31
709`define VLSW16 `VMSW16 -31
710`define VLSW17 `VMSW17 -31
711`define VLSW18 `VMSW18 -31
712`define VLSW19 `VMSW19 -31
713`define VLSW20 `VMSW20 -31
714`define VLSW21 `VMSW21 -31
715`define VLSW22 `VMSW22 -31
716`define VLSW23 `VMSW23 -31
717`define VLSW24 `VMSW24 -31
718`define VLSW25 `VMSW25 -31
719`define VLSW26 `VMSW26 -31
720`define VLSW27 `VMSW27 -31
721`define VLSW28 `VMSW28 -31
722`define VLSW29 `VMSW29 -31
723`define VLSW30 `VMSW30 -31
724`define VLSW31 `VMSW31 -31
725
726`define BUFF0 `VMSW0 : `VLSW0
727`define BUFF1 `VMSW1 : `VLSW1
728`define BUFF2 `VMSW2 : `VLSW2
729`define BUFF3 `VMSW3 : `VLSW3
730`define BUFF4 `VMSW4 : `VLSW4
731`define BUFF5 `VMSW5 : `VLSW5
732`define BUFF6 `VMSW6 : `VLSW6
733`define BUFF7 `VMSW7 : `VLSW7
734`define BUFF8 `VMSW8 : `VLSW8
735`define BUFF9 `VMSW9 : `VLSW9
736`define BUFF10 `VMSW10: `VLSW10
737`define BUFF11 `VMSW11: `VLSW11
738`define BUFF12 `VMSW12: `VLSW12
739`define BUFF13 `VMSW13: `VLSW13
740`define BUFF14 `VMSW14: `VLSW14
741`define BUFF15 `VMSW15: `VLSW15
742`define BUFF16 `VMSW16: `VLSW16
743`define BUFF17 `VMSW17: `VLSW17
744`define BUFF18 `VMSW18: `VLSW18
745`define BUFF19 `VMSW19: `VLSW19
746`define BUFF20 `VMSW20: `VLSW20
747`define BUFF21 `VMSW21: `VLSW21
748`define BUFF22 `VMSW22: `VLSW22
749`define BUFF23 `VMSW23: `VLSW23
750`define BUFF24 `VMSW24: `VLSW24
751`define BUFF25 `VMSW25: `VLSW25
752`define BUFF26 `VMSW26: `VLSW26
753`define BUFF27 `VMSW27: `VLSW27
754`define BUFF28 `VMSW28: `VLSW28
755`define BUFF29 `VMSW29: `VLSW29
756`define BUFF30 `VMSW30: `VLSW30
757`define BUFF31 `VMSW31: `VLSW31
758
759
760// ----- Little Endian ---------
761// Ram w/o ECC Msb Lsb, Word 0~15
762`define RW 1024
763
764`define RMSW0 63
765`define RMSW1 `RMSW0 +64
766`define RMSW2 `RMSW1 +64
767`define RMSW3 `RMSW2 +64
768`define RMSW4 `RMSW3 +64
769`define RMSW5 `RMSW4 +64
770`define RMSW6 `RMSW5 +64
771`define RMSW7 `RMSW6 +64
772`define RMSW8 `RMSW7 +64
773`define RMSW9 `RMSW8 +64
774`define RMSW10 `RMSW9 +64
775`define RMSW11 `RMSW10 +64
776`define RMSW12 `RMSW11 +64
777`define RMSW13 `RMSW12 +64
778`define RMSW14 `RMSW13 +64
779`define RMSW15 `RMSW14 +64
780
781`define RLSW0 `RMSW0 -63
782`define RLSW1 `RMSW1 -63
783`define RLSW2 `RMSW2 -63
784`define RLSW3 `RMSW3 -63
785`define RLSW4 `RMSW4 -63
786`define RLSW5 `RMSW5 -63
787`define RLSW6 `RMSW6 -63
788`define RLSW7 `RMSW7 -63
789`define RLSW8 `RMSW8 -63
790`define RLSW9 `RMSW9 -63
791`define RLSW10 `RMSW10 -63
792`define RLSW11 `RMSW11 -63
793`define RLSW12 `RMSW12 -63
794`define RLSW13 `RMSW13 -63
795`define RLSW14 `RMSW14 -63
796`define RLSW15 `RMSW15 -63
797
798// Ram Data
799`define RDA0 `RMSW0 : `RLSW0
800`define RDA1 `RMSW1 : `RLSW1
801`define RDA2 `RMSW2 : `RLSW2
802`define RDA3 `RMSW3 : `RLSW3
803`define RDA4 `RMSW4 : `RLSW4
804`define RDA5 `RMSW5 : `RLSW5
805`define RDA6 `RMSW6 : `RLSW6
806`define RDA7 `RMSW7 : `RLSW7
807`define RDA8 `RMSW8 : `RLSW8
808`define RDA9 `RMSW9 : `RLSW9
809`define RDA10 `RMSW10: `RLSW10
810`define RDA11 `RMSW11: `RLSW11
811`define RDA12 `RMSW12: `RLSW12
812`define RDA13 `RMSW13: `RLSW13
813`define RDA14 `RMSW14: `RLSW14
814`define RDA15 `RMSW15: `RLSW15
815
816
817// ----- Little Endian (for resfifo -----
818// SRam w ECC Msb Lsb, Word0~15
819`define SW 1152
820
821`define SMSW0 71
822`define SMSW1 `SMSW0 +72
823`define SMSW2 `SMSW1 +72
824`define SMSW3 `SMSW2 +72
825`define SMSW4 `SMSW3 +72
826`define SMSW5 `SMSW4 +72
827`define SMSW6 `SMSW5 +72
828`define SMSW7 `SMSW6 +72
829`define SMSW8 `SMSW7 +72
830`define SMSW9 `SMSW8 +72
831`define SMSW10 `SMSW9 +72
832`define SMSW11 `SMSW10 +72
833`define SMSW12 `SMSW11 +72
834`define SMSW13 `SMSW12 +72
835`define SMSW14 `SMSW13 +72
836`define SMSW15 `SMSW14 +72
837
838`define SLSW0 `SMSW0 -71
839`define SLSW1 `SMSW1 -71
840`define SLSW2 `SMSW2 -71
841`define SLSW3 `SMSW3 -71
842`define SLSW4 `SMSW4 -71
843`define SLSW5 `SMSW5 -71
844`define SLSW6 `SMSW6 -71
845`define SLSW7 `SMSW7 -71
846`define SLSW8 `SMSW8 -71
847`define SLSW9 `SMSW9 -71
848`define SLSW10 `SMSW10 -71
849`define SLSW11 `SMSW11 -71
850`define SLSW12 `SMSW12 -71
851`define SLSW13 `SMSW13 -71
852`define SLSW14 `SMSW14 -71
853`define SLSW15 `SMSW15 -71
854
855// Sram Data+ECC
856`define SDE0 `SMSW0 : `SLSW0
857`define SDE1 `SMSW1 : `SLSW1
858`define SDE2 `SMSW2 : `SLSW2
859`define SDE3 `SMSW3 : `SLSW3
860`define SDE4 `SMSW4 : `SLSW4
861`define SDE5 `SMSW5 : `SLSW5
862`define SDE6 `SMSW6 : `SLSW6
863`define SDE7 `SMSW7 : `SLSW7
864`define SDE8 `SMSW8 : `SLSW8
865`define SDE9 `SMSW9 : `SLSW9
866`define SDE10 `SMSW10: `SLSW10
867`define SDE11 `SMSW11: `SLSW11
868`define SDE12 `SMSW12: `SLSW12
869`define SDE13 `SMSW13: `SLSW13
870`define SDE14 `SMSW14: `SLSW14
871`define SDE15 `SMSW15: `SLSW15
872
873`define ZCP_TRAINING_SET SELECT_VALUE_OF_DEBUG_MUX
874`define ZCP_TRAINING_LOAD SELECT_VALUE_OF_DEBUG_MUX
875
876////////////////////////////////////////////////////////////////
877`define PIM_24Buffers 16'd24
878
879////////////////////////////////////////////////////////////////
880`define RTL_SIM 1
881
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