Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_zcp_ififo_sm.v
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3// OpenSPARC T2 Processor File: niu_zcp_ififo_sm.v
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35/*%W% %G%*/
36
37/***************************************************************
38 *
39 * File Name : niu_zcp_ififo_sm.v
40 * Author Name : John Lo
41 * Description : niu_zcp_fflp_intf control path
42 * Parent Module:
43 * Child Module:
44 * Interface Mod:
45 * Date Created : 3/18/05
46 *
47 * Copyright (c) 2020, Sun Microsystems, Inc.
48 * Sun Proprietary and Confidential
49 *
50 * Modification :
51 *
52 * Synthesis Notes:
53 *
54 * Design Notes: When adding more CAL states DON'T forget to
55 * modify tt_atomic_op.
56 *
57 *
58 **************************************************************/
59
60
61module niu_zcp_ififo_sm
62 (/*AUTOARG*/
63 // Outputs
64 ififo_ren1, ififo_ren, ififo_state,
65 // Inputs
66 clk, reset, empty
67 );
68
69
70 input clk;
71 input reset;
72 input empty;
73 // outputs
74 output ififo_ren1;
75 output [2:0] ififo_ren;
76 output [2:0] ififo_state;
77
78 wire [2:0] ififo_state;
79 reg [2:0] nx_ififo_state;
80 reg kickoff_rd;
81 parameter ZERO = 3'h0,
82 ONE = 3'h1,
83 TWO = 3'h2,
84 THREE = 3'h3,
85 FOUR = 3'h4,
86 FIVE = 3'h5,
87 SIX = 3'h6,
88 SEVEN = 3'h7;
89
90// comb part
91always @ (/*AUTOSENSE*/empty or ififo_state)
92 begin
93 nx_ififo_state = ZERO;
94 kickoff_rd = 0;
95 casex (ififo_state) // synopsys parallel_case
96 ZERO: if (~empty)
97 begin
98 nx_ififo_state = ONE;
99 kickoff_rd = 1;
100 end // if (~empty)
101 else nx_ififo_state = ififo_state; // stay
102 ONE: nx_ififo_state = TWO;
103 TWO: nx_ififo_state = THREE;
104 THREE: nx_ififo_state = FOUR;
105 FOUR: nx_ififo_state = FIVE;
106 FIVE: nx_ififo_state = SIX;
107 SIX: nx_ififo_state = SEVEN;
108 SEVEN: nx_ififo_state = ZERO;
109 default:begin
110 nx_ififo_state = ZERO;
111 kickoff_rd = 0;
112 // synopsys translate_off
113 $display("(* ERROR: at sim time = %d, niu_zcp_ififo_sm is in forbidden state *) \n", $time);
114 // synopsys translate_on
115 end
116 endcase // casex(ififo_state)
117 end // always @ (...
118
119
120// seq part
121zcp_RegRst #(3) ififo_state_RegRst(.din(nx_ififo_state[2:0]),.clk(clk),.reset(reset),.qout(ififo_state[2:0]));
122
123// glue logic
124zcp_RegRst #(4) ififo_ren_RegRst(.din({4{kickoff_rd}}),.clk(clk),.reset(reset),.qout({ififo_ren1,ififo_ren[2:0]}));
125
126
127
128endmodule // niu_zcp_ififo_sm
129