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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: phy_clock_2ports.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /*%W% %G%*/ | |
36 | ||
37 | /************************************************************************* | |
38 | * | |
39 | * File Name : phy_clock_2ports.v | |
40 | * Author Name : John Lo | |
41 | * Description : This module contains 2 clock muxes modules for each port. | |
42 | * This is the top clock mux module. | |
43 | * Some ASIC vendor requires the phy_clock_top2 to be | |
44 | * outside mac. | |
45 | * | |
46 | * | |
47 | * | |
48 | * Parent Module: None | |
49 | * Child Module: xmac_x2pcs_clk_mux | |
50 | * Interface Mod: | |
51 | * Date Created : 3/5/04 | |
52 | * | |
53 | * | |
54 | * Copyright (c) 2020, Sun Microsystems, Inc. | |
55 | * Sun Proprietary and Confidential | |
56 | * | |
57 | * | |
58 | *************************************************************************/ | |
59 | ||
60 | ||
61 | module phy_clock_2ports (/*AUTOARG*/ | |
62 | // Outputs | |
63 | tx_nbclk_muxd0, tx_clk_muxd0, tx_clk_312mhz_muxd0, rx_nbclk_muxd0, | |
64 | rx_clk_muxd0, rbc0_a_muxd0, rbc0_b_muxd0, rbc0_c_muxd0, | |
65 | rbc0_d_muxd0, tx_nbclk_muxd1, tx_clk_muxd1, tx_clk_312mhz_muxd1, | |
66 | rx_nbclk_muxd1, rx_clk_muxd1, rbc0_a_muxd1, rbc0_b_muxd1, | |
67 | rbc0_c_muxd1, rbc0_d_muxd1, | |
68 | // Inputs | |
69 | tcu_scan_mode, mac_312tx_test_clk, mac_312rx_test_clk, | |
70 | mac_156tx_test_clk, mac_156rx_test_clk, mac_125tx_test_clk, | |
71 | mac_125rx_test_clk, reset, clk, loopback0, sel_por_clk_src0, | |
72 | sel_clk_25mhz0, mii_mode0, gmii_mode0, xgmii_mode0, pcs_bypass0, | |
73 | xpcs_loopback0, tx_heart_beat_timer0, rx_heart_beat_timer0, | |
74 | esr_mac_rclk_0, esr_mac_tclk_0, loopback1, sel_por_clk_src1, | |
75 | sel_clk_25mhz1, mii_mode1, gmii_mode1, xgmii_mode1, pcs_bypass1, | |
76 | xpcs_loopback1, tx_heart_beat_timer1, rx_heart_beat_timer1, | |
77 | esr_mac_rclk_1, esr_mac_tclk_1 | |
78 | ); | |
79 | ||
80 | /* ------------- global signals ------------------------------- */ | |
81 | input tcu_scan_mode; | |
82 | input mac_312tx_test_clk; | |
83 | input mac_312rx_test_clk; | |
84 | input mac_156tx_test_clk; | |
85 | input mac_156rx_test_clk; | |
86 | input mac_125tx_test_clk; | |
87 | input mac_125rx_test_clk; | |
88 | input reset; | |
89 | input clk; | |
90 | /* ------------- xmac_2pcs_clk_mux --- port 0 ----------------- */ | |
91 | input loopback0; | |
92 | input sel_por_clk_src0; | |
93 | input sel_clk_25mhz0; | |
94 | input mii_mode0; | |
95 | input gmii_mode0; | |
96 | input xgmii_mode0; | |
97 | input pcs_bypass0; // select external pcs | |
98 | input xpcs_loopback0; // !tx_clk as xpcs_loopback clock | |
99 | input [3:0] tx_heart_beat_timer0; // from tx_mii_gmii.v | |
100 | input [3:0] rx_heart_beat_timer0; // from rx_mii_gmii.v | |
101 | // outputs to clock tree | |
102 | // 802.3 rx clocks | |
103 | input [3:0] esr_mac_rclk_0; | |
104 | input esr_mac_tclk_0; // use lane 0 tclk for common tclk. | |
105 | output tx_nbclk_muxd0; // to clock tree | |
106 | output tx_clk_muxd0; // to clock tree | |
107 | output tx_clk_312mhz_muxd0; // to clock tree | |
108 | output rx_nbclk_muxd0; // to clock tree | |
109 | output rx_clk_muxd0; // to clock tree | |
110 | output rbc0_a_muxd0; // to clock tree | |
111 | output rbc0_b_muxd0; // to clock tree | |
112 | output rbc0_c_muxd0; // to clock tree | |
113 | output rbc0_d_muxd0; // to clock tree | |
114 | /* ------------- xmac_2pcs_clk_mux --- port 1 ----------------- */ | |
115 | input loopback1; | |
116 | input sel_por_clk_src1; | |
117 | input sel_clk_25mhz1; | |
118 | input mii_mode1; | |
119 | input gmii_mode1; | |
120 | input xgmii_mode1; | |
121 | input pcs_bypass1; // select external pcs | |
122 | input xpcs_loopback1; // !tx_clk as xpcs_loopback clock | |
123 | input [3:0] tx_heart_beat_timer1; // from tx_mii_gmii.v | |
124 | input [3:0] rx_heart_beat_timer1; // from rx_mii_gmii.v | |
125 | // outputs to clock tree | |
126 | // 802.3 rx clocks | |
127 | input [3:0] esr_mac_rclk_1; | |
128 | input esr_mac_tclk_1; // use lance 0 tclk for common tclk. | |
129 | output tx_nbclk_muxd1; // to clock tree | |
130 | output tx_clk_muxd1; // to clock tree | |
131 | output tx_clk_312mhz_muxd1; // to clock tree | |
132 | output rx_nbclk_muxd1; // to clock tree | |
133 | output rx_clk_muxd1; // to clock tree | |
134 | output rbc0_a_muxd1; // to clock tree | |
135 | output rbc0_b_muxd1; // to clock tree | |
136 | output rbc0_c_muxd1; // to clock tree | |
137 | output rbc0_d_muxd1; // to clock tree | |
138 | ||
139 | /************************************ | |
140 | * N2 specific setup and logic | |
141 | ************************************/ | |
142 | wire ref_clk_250mhz = 1'b0; // N2 has no cupper phy (rgmii) | |
143 | wire gmii_rx_clk0 = 1'b0; | |
144 | wire gmii_rx_clk1 = 1'b0; | |
145 | wire FUNC_MODE = ~tcu_scan_mode; | |
146 | ||
147 | // vlint flag_dangling_net_within_module off | |
148 | // vlint flag_net_has_no_load off | |
149 | wire debug_tclk_156mhz0; | |
150 | wire debug_rclk_156mhz0; | |
151 | wire debug_tclk_156mhz1; | |
152 | wire debug_rclk_156mhz1; | |
153 | // vlint flag_net_has_no_load on | |
154 | // vlint flag_dangling_net_within_module on | |
155 | ||
156 | /* ------------- xmac_2pcs_clk_mux --- port 0 ----------------- */ | |
157 | xmac_2pcs_clk_mux xmac_2pcs_clk_mux0( | |
158 | .FUNC_MODE(FUNC_MODE), | |
159 | .mac_312tx_test_clk(mac_312tx_test_clk), | |
160 | .mac_312rx_test_clk({4{mac_312rx_test_clk}}), | |
161 | .mac_156tx_test_clk(mac_156tx_test_clk), | |
162 | .mac_156rx_test_clk(mac_156rx_test_clk), | |
163 | .mac_125tx_test_clk(mac_125tx_test_clk), | |
164 | .mac_125rx_test_clk(mac_125rx_test_clk), | |
165 | .reset(reset), | |
166 | .clk(clk), | |
167 | .loopback(loopback0), | |
168 | .sel_por_clk_src(sel_por_clk_src0), | |
169 | .mii_mode(mii_mode0), | |
170 | .gmii_mode(gmii_mode0), | |
171 | .xgmii_mode(xgmii_mode0), | |
172 | .pcs_bypass(pcs_bypass0), // select external pcs | |
173 | .xpcs_loopback(xpcs_loopback0), // !tx_clk as xpcs_loopback clock | |
174 | .ref_clk_250mhz(ref_clk_250mhz), | |
175 | .sel_clk_25mhz(sel_clk_25mhz0), | |
176 | .tx_heart_beat_timer(tx_heart_beat_timer0), // from tx_mii_gmii.v | |
177 | .rx_heart_beat_timer(rx_heart_beat_timer0), // from rx_mii_gmii.v | |
178 | // 802.3 input rx clocks | |
179 | .gmii_rx_clk(gmii_rx_clk0), | |
180 | // xpcs clock | |
181 | .esr_tclk_312mhz(esr_mac_tclk_0), // for 10G optical lane 0 tclk for all. | |
182 | .esr_mac_rclk0(esr_mac_rclk_0[0]), | |
183 | .esr_mac_rclk1(esr_mac_rclk_0[1]), | |
184 | .esr_mac_rclk2(esr_mac_rclk_0[2]), | |
185 | .esr_mac_rclk3(esr_mac_rclk_0[3]), | |
186 | // pcs clock | |
187 | .atca_GE(1'b0), | |
188 | .esr_tclk_125mhz0(esr_mac_tclk_0), // for 1G optical | |
189 | .esr_tclk_125mhz1(esr_mac_tclk_0), // for 1G optical | |
190 | .esr_rclk_125mhz0(esr_mac_rclk_0[0]), // for 1G optical | |
191 | .esr_rclk_125mhz1(esr_mac_rclk_0[0]), // for 1G optical | |
192 | // outputs to clock tree | |
193 | .tx_nbclk_muxd(tx_nbclk_muxd0), | |
194 | .tx_clk_muxd(tx_clk_muxd0), | |
195 | .tx_clk_312mhz_muxd(tx_clk_312mhz_muxd0), | |
196 | .rx_nbclk_muxd(rx_nbclk_muxd0), | |
197 | .rx_clk_muxd(rx_clk_muxd0), | |
198 | .rbc0_a_muxd(rbc0_a_muxd0), | |
199 | .rbc0_b_muxd(rbc0_b_muxd0), | |
200 | .rbc0_c_muxd(rbc0_c_muxd0), | |
201 | .rbc0_d_muxd(rbc0_d_muxd0), | |
202 | .debug_tclk_156mhz(debug_tclk_156mhz0), | |
203 | .debug_rclk_156mhz(debug_rclk_156mhz0)); | |
204 | ||
205 | /* ------------- xmac_2pcs_clk_mux --- port 1 ----------------- */ | |
206 | xmac_2pcs_clk_mux xmac_2pcs_clk_mux1( | |
207 | .FUNC_MODE(FUNC_MODE), | |
208 | .mac_312tx_test_clk(mac_312tx_test_clk), | |
209 | .mac_312rx_test_clk({4{mac_312rx_test_clk}}), | |
210 | .mac_156tx_test_clk(mac_156tx_test_clk), | |
211 | .mac_156rx_test_clk(mac_156rx_test_clk), | |
212 | .mac_125tx_test_clk(mac_125tx_test_clk), | |
213 | .mac_125rx_test_clk(mac_125rx_test_clk), | |
214 | .reset(reset), | |
215 | .clk(clk), | |
216 | .loopback(loopback1), | |
217 | .sel_por_clk_src(sel_por_clk_src1), | |
218 | .mii_mode(mii_mode1), | |
219 | .gmii_mode(gmii_mode1), | |
220 | .xgmii_mode(xgmii_mode1), | |
221 | .pcs_bypass(pcs_bypass1), // select external pcs | |
222 | .xpcs_loopback(xpcs_loopback1), // !tx_clk as xpcs_loopback clock | |
223 | .ref_clk_250mhz(ref_clk_250mhz), | |
224 | .sel_clk_25mhz(sel_clk_25mhz1), | |
225 | .tx_heart_beat_timer(tx_heart_beat_timer1), // from tx_mii_gmii.v | |
226 | .rx_heart_beat_timer(rx_heart_beat_timer1), // from rx_mii_gmii.v | |
227 | // 802.3 input rx clocks | |
228 | .gmii_rx_clk(gmii_rx_clk1), | |
229 | // xpcs clock | |
230 | .esr_tclk_312mhz(esr_mac_tclk_1), // for 10G optical lane 0 tclk for all. | |
231 | .esr_mac_rclk0(esr_mac_rclk_1[0]), | |
232 | .esr_mac_rclk1(esr_mac_rclk_1[1]), | |
233 | .esr_mac_rclk2(esr_mac_rclk_1[2]), | |
234 | .esr_mac_rclk3(esr_mac_rclk_1[3]), | |
235 | // pcs clock | |
236 | .atca_GE(1'b0), | |
237 | .esr_tclk_125mhz0(esr_mac_tclk_1), // for 1G optical | |
238 | .esr_tclk_125mhz1(esr_mac_tclk_1), // for 1G optical | |
239 | .esr_rclk_125mhz0(esr_mac_rclk_1[0]), // for 1G optical | |
240 | .esr_rclk_125mhz1(esr_mac_rclk_1[0]), // for 1G optical | |
241 | // outputs to clock tree | |
242 | .tx_nbclk_muxd(tx_nbclk_muxd1), | |
243 | .tx_clk_muxd(tx_clk_muxd1), | |
244 | .tx_clk_312mhz_muxd(tx_clk_312mhz_muxd1), | |
245 | .rx_nbclk_muxd(rx_nbclk_muxd1), | |
246 | .rx_clk_muxd(rx_clk_muxd1), | |
247 | .rbc0_a_muxd(rbc0_a_muxd1), | |
248 | .rbc0_b_muxd(rbc0_b_muxd1), | |
249 | .rbc0_c_muxd(rbc0_c_muxd1), | |
250 | .rbc0_d_muxd(rbc0_d_muxd1), | |
251 | .debug_tclk_156mhz(debug_tclk_156mhz1), | |
252 | .debug_rclk_156mhz(debug_rclk_156mhz1)); | |
253 | ||
254 | endmodule // phy_clock_2ports | |
255 |