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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xpcs_pio.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // **************************************************************** | |
36 | // | |
37 | // Sun Proprietary/Confidential: Internal Use Only | |
38 | // | |
39 | // **************************************************************** | |
40 | // Design: Vega | |
41 | // Block: XPCS | |
42 | // Author: Carlos Castil | |
43 | // | |
44 | // Module: xpcs_pio | |
45 | // File: xpcs_pio.v | |
46 | // | |
47 | // Description: This block contains all xpcs reg csrs. | |
48 | // | |
49 | // Revision History | |
50 | // ------------------------------------------------------------ | |
51 | // Ver Date Comments | |
52 | // ------------------------------------------------------------ | |
53 | // 1.0 10/17/02 Created | |
54 | // | |
55 | // **************************************************************** | |
56 | ||
57 | module xpcs_pio ( | |
58 | ||
59 | core_clk, | |
60 | ||
61 | // reset signals | |
62 | ||
63 | reset, | |
64 | sw_reset, | |
65 | clr_sw_reset, | |
66 | hw_reset, | |
67 | ||
68 | // PIO Interface to HT | |
69 | ||
70 | sel_xpcs, | |
71 | pio_rd, | |
72 | pio_addr, | |
73 | pio_wdata, | |
74 | ||
75 | rdata_xpcs, | |
76 | ack_xpcs, | |
77 | pio_err_xpcs, | |
78 | ||
79 | xpcs_interrupt, | |
80 | ||
81 | csr_xpcs_enable, | |
82 | csr_link_status, | |
83 | csr_ebuffer_state, | |
84 | csr_receive_state, | |
85 | csr_bypass_signal_detect, | |
86 | ||
87 | csr_lane_sync_status, | |
88 | ||
89 | csr_loopback, | |
90 | csr_low_power, | |
91 | ||
92 | csr_vendor_debug_sel, | |
93 | csr_vendor_debug_io_test, | |
94 | training_vector, | |
95 | ||
96 | inc_tx_pkt_count, | |
97 | inc_rx_pkt_count, | |
98 | ||
99 | inc_deskew_error, | |
100 | ||
101 | csr_tx_state, | |
102 | ||
103 | csr_trigger_transmit_fault, | |
104 | csr_trigger_receive_fault, | |
105 | ||
106 | csr_tx_test_enable, | |
107 | csr_test_pattern_sel, | |
108 | ||
109 | csr_enable_tx_buffers, | |
110 | ||
111 | csr_lane_sync_state0, | |
112 | csr_lane_sync_state1, | |
113 | csr_lane_sync_state2, | |
114 | csr_lane_sync_state3, | |
115 | ||
116 | trigger_symbol_err_cnt0, | |
117 | trigger_symbol_err_cnt1, | |
118 | trigger_symbol_err_cnt2, | |
119 | trigger_symbol_err_cnt3 | |
120 | ); | |
121 | ||
122 | ||
123 | input core_clk; | |
124 | ||
125 | input reset; | |
126 | input clr_sw_reset; | |
127 | input hw_reset; | |
128 | ||
129 | output sw_reset; | |
130 | ||
131 | input csr_link_status; | |
132 | input [3:0] csr_lane_sync_status; | |
133 | input inc_deskew_error; | |
134 | input [3:0] csr_lane_sync_state0; | |
135 | input [3:0] csr_lane_sync_state1; | |
136 | input [3:0] csr_lane_sync_state2; | |
137 | input [3:0] csr_lane_sync_state3; | |
138 | ||
139 | input trigger_symbol_err_cnt0; | |
140 | input trigger_symbol_err_cnt1; | |
141 | input trigger_symbol_err_cnt2; | |
142 | input trigger_symbol_err_cnt3; | |
143 | ||
144 | input [3:0] csr_tx_state; | |
145 | ||
146 | input [7:0] csr_ebuffer_state; | |
147 | input csr_receive_state; | |
148 | ||
149 | input inc_tx_pkt_count; | |
150 | input inc_rx_pkt_count; | |
151 | ||
152 | input csr_trigger_transmit_fault; | |
153 | input csr_trigger_receive_fault; | |
154 | ||
155 | output xpcs_interrupt; | |
156 | ||
157 | output csr_xpcs_enable; | |
158 | output csr_loopback; | |
159 | output csr_low_power; | |
160 | output csr_bypass_signal_detect; | |
161 | output csr_enable_tx_buffers; | |
162 | ||
163 | output csr_tx_test_enable; | |
164 | output [1:0] csr_test_pattern_sel; | |
165 | ||
166 | output [3:0] csr_vendor_debug_sel; | |
167 | output csr_vendor_debug_io_test; | |
168 | ||
169 | output [31:0] training_vector; | |
170 | ||
171 | ||
172 | // PIO Interface With MAC/HT | |
173 | ||
174 | input sel_xpcs; | |
175 | input pio_rd; | |
176 | input [8:0] pio_addr; | |
177 | input [31:0] pio_wdata; | |
178 | ||
179 | output [31:0] rdata_xpcs; | |
180 | output ack_xpcs; | |
181 | output pio_err_xpcs; | |
182 | ||
183 | reg [8:0] pio_addr_reg; | |
184 | reg [31:0] pio_wdata_reg; | |
185 | reg pio_rd_reg; | |
186 | ||
187 | reg sel_xpcs_reg; | |
188 | reg sel_xpcs_d; | |
189 | ||
190 | reg write_pulse; | |
191 | reg read_pulse; | |
192 | ||
193 | reg csr_bypass_signal_detect; | |
194 | reg csr_xpcs_enable; | |
195 | reg [3:0] csr_vendor_debug_sel; | |
196 | reg csr_vendor_debug_io_test; | |
197 | reg [31:0] training_vector; | |
198 | reg [8:0] addr; | |
199 | reg [31:0] wr_data; | |
200 | ||
201 | reg ack_xpcs; | |
202 | reg [31:0] rdata_xpcs; | |
203 | ||
204 | reg [15:0] csr_tx_pkt_count; | |
205 | reg [15:0] csr_rx_pkt_count; | |
206 | ||
207 | reg [7:0] deskew_error_count; | |
208 | ||
209 | reg [31:0] rd_data; | |
210 | ||
211 | reg csr_link_status_mask; | |
212 | ||
213 | reg csr_enable_tx_buffers; | |
214 | ||
215 | reg sw_reset; | |
216 | ||
217 | reg csr_loopback; | |
218 | reg csr_low_power; | |
219 | ||
220 | reg csr_tx_test_enable; | |
221 | reg [1:0] csr_test_pattern_sel; | |
222 | ||
223 | reg csr_fault_mask; | |
224 | ||
225 | reg pio_err_xpcs; | |
226 | ||
227 | reg csr_fault; | |
228 | reg csr_fault_d; | |
229 | ||
230 | wire control1_wr_en; | |
231 | wire test_control_wr_en; | |
232 | wire conf_wr_en; | |
233 | wire ld_training_vector; | |
234 | wire mask1_wr_en; | |
235 | wire pkt_counter_wr_en; | |
236 | wire deskew_err_wr_en; | |
237 | ||
238 | wire sel_pls; | |
239 | ||
240 | wire csr_trigger_transmit_fault; | |
241 | wire csr_trigger_receive_fault; | |
242 | ||
243 | wire set_xpcs_interrupt; | |
244 | ||
245 | reg xpcs_interrupt; | |
246 | ||
247 | reg csr_link_status_d; | |
248 | reg set_link_status_low; | |
249 | reg link_status_latch_low; | |
250 | ||
251 | reg clear_status1; | |
252 | reg clear_status2; | |
253 | ||
254 | reg csr_trigger_transmit_fault_d; | |
255 | reg set_transmit_fault_high; | |
256 | reg transmit_fault_latch_high; | |
257 | ||
258 | reg csr_trigger_receive_fault_d; | |
259 | reg set_receive_fault_high; | |
260 | reg receive_fault_latch_high; | |
261 | ||
262 | reg inc_rx_pkt_count_d; | |
263 | reg inc_tx_pkt_count_d; | |
264 | ||
265 | reg inc_deskew_error_d; | |
266 | ||
267 | ||
268 | reg [15:0] symbol_err_cnt0; | |
269 | wire clear_symbol_err_cnt0; | |
270 | ||
271 | reg [15:0] symbol_err_cnt1; | |
272 | wire clear_symbol_err_cnt1; | |
273 | ||
274 | reg [15:0] symbol_err_cnt2; | |
275 | wire clear_symbol_err_cnt2; | |
276 | ||
277 | reg [15:0] symbol_err_cnt3; | |
278 | wire clear_symbol_err_cnt3; | |
279 | ||
280 | ||
281 | // ********************************** | |
282 | // PIO Control Logic | |
283 | // ********************************** | |
284 | ||
285 | always @ (posedge core_clk) | |
286 | begin | |
287 | sel_xpcs_reg <= sel_xpcs; | |
288 | sel_xpcs_d <= sel_xpcs_reg; | |
289 | pio_rd_reg <= pio_rd; | |
290 | pio_addr_reg <= pio_addr; | |
291 | pio_wdata_reg <= pio_wdata; | |
292 | end | |
293 | ||
294 | ||
295 | // sel_pls is the select pulse | |
296 | ||
297 | assign sel_pls = (sel_xpcs_reg & ~sel_xpcs_d); | |
298 | ||
299 | ||
300 | // Generate PIO registered ack and read data | |
301 | ||
302 | always @ (posedge core_clk) | |
303 | begin | |
304 | ack_xpcs <= (read_pulse | write_pulse); | |
305 | rdata_xpcs <= rd_data; | |
306 | pio_err_xpcs <= (read_pulse | write_pulse ) & (rd_data == 32'hBADCAFEE); | |
307 | end | |
308 | ||
309 | ||
310 | // Register write PIO data on sel_pls | |
311 | ||
312 | always @ (posedge core_clk) | |
313 | begin | |
314 | read_pulse <= sel_pls & pio_rd_reg ; | |
315 | write_pulse <= sel_pls & ~pio_rd_reg ; | |
316 | addr <= pio_addr_reg; | |
317 | wr_data <= pio_wdata_reg; | |
318 | end | |
319 | ||
320 | ||
321 | assign control1_wr_en = write_pulse & addr[8:0]==9'h000; | |
322 | ||
323 | assign test_control_wr_en = write_pulse & addr[8:0]==9'h009; | |
324 | ||
325 | assign conf_wr_en = write_pulse & addr[8:0]==9'h00a; | |
326 | ||
327 | assign ld_training_vector = write_pulse & addr[8:0]==9'h012; | |
328 | ||
329 | assign mask1_wr_en = write_pulse & addr[8:0]==9'h00c; | |
330 | ||
331 | assign pkt_counter_wr_en = write_pulse & addr[8:0]==9'h00d; | |
332 | ||
333 | assign deskew_err_wr_en = write_pulse & addr[8:0]==9'h00f; | |
334 | ||
335 | ||
336 | // Read Mux | |
337 | ||
338 | always @ (/*AUTOSENSE*/addr or csr_bypass_signal_detect | |
339 | or csr_ebuffer_state or csr_enable_tx_buffers or csr_fault | |
340 | or csr_fault_mask or csr_lane_sync_state0 | |
341 | or csr_lane_sync_state1 or csr_lane_sync_state2 | |
342 | or csr_lane_sync_state3 or csr_lane_sync_status | |
343 | or csr_link_status or csr_link_status_mask or csr_loopback | |
344 | or csr_low_power or csr_receive_state or csr_rx_pkt_count | |
345 | or csr_test_pattern_sel or csr_tx_pkt_count or csr_tx_state | |
346 | or csr_tx_test_enable or csr_vendor_debug_io_test | |
347 | or csr_vendor_debug_sel or csr_xpcs_enable | |
348 | or deskew_error_count or link_status_latch_low | |
349 | or receive_fault_latch_high or sw_reset | |
350 | or transmit_fault_latch_high or symbol_err_cnt0 | |
351 | or symbol_err_cnt1 or symbol_err_cnt2 or symbol_err_cnt3 | |
352 | or training_vector) | |
353 | ||
354 | begin | |
355 | case (addr[7:0]) // synopsys parallel_case full_case | |
356 | ||
357 | // Port Info | |
358 | ||
359 | 8'h00 : rd_data = {16'h0000,sw_reset,csr_loopback,2'b10,csr_low_power,11'b00001000000}; // control1 | |
360 | 8'h01 : rd_data = {24'h000000,csr_fault,4'b0000,link_status_latch_low,2'b00}; // status1 | |
361 | 8'h02 : rd_data = {32'h00000000}; // device id | |
362 | 8'h03 : rd_data = {31'h00000000,1'b1}; // speed ability | |
363 | 8'h04 : rd_data = {4'hC,20'h00000,8'h08}; // devices in package | |
364 | 8'h05 : rd_data = {30'h00000000,2'b01}; // control2 | |
365 | 8'h06 : rd_data = {20'h00000,transmit_fault_latch_high,receive_fault_latch_high,8'h00,2'b10}; // status2 | |
366 | 8'h07 : rd_data = {32'h00000000}; // package id | |
367 | 8'h08 : rd_data = {19'h00000, csr_link_status, 8'h80, csr_lane_sync_status}; | |
368 | 8'h09 : rd_data = {29'h00000000,csr_tx_test_enable,csr_test_pattern_sel}; // test control | |
369 | 8'h0A : rd_data = {24'h000000,csr_vendor_debug_io_test, | |
370 | csr_vendor_debug_sel, | |
371 | csr_bypass_signal_detect, | |
372 | csr_enable_tx_buffers, | |
373 | csr_xpcs_enable}; // configuration | |
374 | 8'h0B : rd_data = {7'h00, csr_lane_sync_state3, // 4 bits | |
375 | csr_lane_sync_state2, // 4 bits | |
376 | csr_lane_sync_state1, // 4 bits | |
377 | csr_lane_sync_state0, // 4 bits | |
378 | csr_ebuffer_state, // 8 bits | |
379 | csr_receive_state}; // 1 bits rx diagnostic | |
380 | 8'h0C : rd_data = {24'h000000,csr_fault_mask,4'h0,csr_link_status_mask,2'b00}; // mask1 | |
381 | 8'h0D : rd_data = {csr_tx_pkt_count,csr_rx_pkt_count}; // packet counter | |
382 | 8'h0E : rd_data = {28'h0000000, csr_tx_state}; // 4 bits tx diagnostic | |
383 | 8'h0F : rd_data = {24'h000000, deskew_error_count}; | |
384 | 8'h10 : rd_data = {symbol_err_cnt1,symbol_err_cnt0}; | |
385 | 8'h11 : rd_data = {symbol_err_cnt3,symbol_err_cnt2}; | |
386 | 8'h12 : rd_data = training_vector[31:0]; | |
387 | ||
388 | default : rd_data = {32'hBADCAFEE}; | |
389 | ||
390 | endcase | |
391 | end // always @ (... | |
392 | ||
393 | ||
394 | ||
395 | always @ (posedge core_clk) | |
396 | if (reset) | |
397 | begin | |
398 | csr_loopback <= 1'b0; | |
399 | csr_low_power <= 1'b0; | |
400 | end | |
401 | else | |
402 | begin | |
403 | csr_loopback <= (control1_wr_en) ? wr_data[14] : csr_loopback; | |
404 | csr_low_power <= (control1_wr_en) ? wr_data[11] : csr_low_power; | |
405 | end | |
406 | ||
407 | always @ (posedge core_clk) | |
408 | if (hw_reset) | |
409 | sw_reset <= 1'b0; | |
410 | else | |
411 | sw_reset <= (control1_wr_en) ? wr_data[15] : (clr_sw_reset) ? 1'b0 : sw_reset; | |
412 | ||
413 | ||
414 | always @ (posedge core_clk) | |
415 | if (reset) | |
416 | begin | |
417 | csr_tx_test_enable <= 1'b0; | |
418 | csr_test_pattern_sel <= 2'b00; | |
419 | end | |
420 | else | |
421 | begin | |
422 | csr_tx_test_enable <= (test_control_wr_en) ? wr_data[2] : csr_tx_test_enable; | |
423 | csr_test_pattern_sel <= (test_control_wr_en) ? wr_data[1:0] : csr_test_pattern_sel; | |
424 | end | |
425 | ||
426 | always @ (posedge core_clk) | |
427 | if (reset) | |
428 | begin | |
429 | csr_vendor_debug_io_test <= 1'b0; | |
430 | csr_vendor_debug_sel <= 4'h0; | |
431 | csr_bypass_signal_detect <= 1'b0; | |
432 | csr_enable_tx_buffers <= 1'b1; | |
433 | csr_xpcs_enable <= 1'b1; | |
434 | end | |
435 | else | |
436 | begin | |
437 | csr_vendor_debug_io_test <= (conf_wr_en) ? wr_data[7] : csr_vendor_debug_io_test; | |
438 | csr_vendor_debug_sel <= (conf_wr_en) ? wr_data[6:3] : csr_vendor_debug_sel; | |
439 | csr_bypass_signal_detect <= (conf_wr_en) ? wr_data[2] : csr_bypass_signal_detect; | |
440 | csr_enable_tx_buffers <= (conf_wr_en) ? wr_data[1] : csr_enable_tx_buffers; | |
441 | csr_xpcs_enable <= (conf_wr_en) ? wr_data[0] : csr_xpcs_enable; | |
442 | end | |
443 | ||
444 | ||
445 | always @ (posedge core_clk) | |
446 | if (reset) | |
447 | begin | |
448 | csr_fault_mask <= 1'b1; | |
449 | csr_link_status_mask <= 1'b1; | |
450 | end | |
451 | else | |
452 | begin | |
453 | csr_fault_mask <= (mask1_wr_en) ? wr_data[7] : csr_fault_mask; | |
454 | csr_link_status_mask <= (mask1_wr_en) ? wr_data[2] : csr_link_status_mask; | |
455 | end | |
456 | ||
457 | /****************************************************************************/ | |
458 | // Logic for packet counts | |
459 | /****************************************************************************/ | |
460 | ||
461 | always @ (posedge core_clk) | |
462 | if (reset) | |
463 | begin | |
464 | inc_tx_pkt_count_d <= 1'b0; | |
465 | inc_rx_pkt_count_d <= 1'b0; | |
466 | end | |
467 | else | |
468 | begin | |
469 | inc_tx_pkt_count_d <= inc_tx_pkt_count; | |
470 | inc_rx_pkt_count_d <= inc_rx_pkt_count; | |
471 | end | |
472 | ||
473 | always @ (posedge core_clk) | |
474 | if (reset) | |
475 | begin | |
476 | csr_tx_pkt_count <= 16'b0; | |
477 | csr_rx_pkt_count <= 16'b0; | |
478 | end | |
479 | else | |
480 | begin | |
481 | csr_tx_pkt_count <= (pkt_counter_wr_en) ? wr_data[31:16] : | |
482 | (csr_link_status & inc_tx_pkt_count & !inc_tx_pkt_count_d) ? csr_tx_pkt_count + 16'h0001 : | |
483 | csr_tx_pkt_count; | |
484 | ||
485 | csr_rx_pkt_count <= (pkt_counter_wr_en) ? wr_data[15:0] : | |
486 | (csr_link_status & inc_rx_pkt_count & !inc_rx_pkt_count_d) ? csr_rx_pkt_count + 16'h0001 : | |
487 | csr_rx_pkt_count; | |
488 | end | |
489 | ||
490 | /****************************************************************************/ | |
491 | // Logic for deskew error count | |
492 | /****************************************************************************/ | |
493 | ||
494 | always @ (posedge core_clk) | |
495 | inc_deskew_error_d <= inc_deskew_error; | |
496 | ||
497 | always @ (posedge core_clk) | |
498 | if (reset) | |
499 | deskew_error_count <= 8'b0; | |
500 | else if (deskew_err_wr_en) | |
501 | deskew_error_count <= wr_data[7:0]; | |
502 | else if (inc_deskew_error & !inc_deskew_error_d & (deskew_error_count != 8'hFF)) | |
503 | deskew_error_count <= deskew_error_count + 8'h01; | |
504 | else | |
505 | deskew_error_count <= deskew_error_count; | |
506 | ||
507 | /****************************************************************************/ | |
508 | // Logic for transmit/receive fault status | |
509 | /****************************************************************************/ | |
510 | ||
511 | always @ (posedge core_clk) | |
512 | if (reset | !csr_xpcs_enable) | |
513 | begin | |
514 | csr_fault <= 1'b0; | |
515 | csr_fault_d <= 1'b0; | |
516 | end | |
517 | else | |
518 | begin | |
519 | csr_fault <= transmit_fault_latch_high | receive_fault_latch_high; | |
520 | csr_fault_d <= csr_fault; | |
521 | end | |
522 | ||
523 | // transmit fault | |
524 | ||
525 | always @ (posedge core_clk) | |
526 | if (reset) | |
527 | csr_trigger_transmit_fault_d <= 1'b0; | |
528 | else | |
529 | csr_trigger_transmit_fault_d <= csr_trigger_transmit_fault; | |
530 | ||
531 | always @ (posedge core_clk) | |
532 | if (reset) | |
533 | set_transmit_fault_high <= 1'b0; | |
534 | else if (csr_trigger_transmit_fault & !csr_trigger_transmit_fault_d) | |
535 | set_transmit_fault_high <= 1'b1; | |
536 | else if (clear_status2) | |
537 | set_transmit_fault_high <= 1'b0; | |
538 | else | |
539 | set_transmit_fault_high <= set_transmit_fault_high; | |
540 | ||
541 | always @ (posedge core_clk) | |
542 | if (reset) | |
543 | transmit_fault_latch_high <= 1'b0; | |
544 | else | |
545 | transmit_fault_latch_high <= set_transmit_fault_high ? 1'b1 : csr_trigger_transmit_fault; | |
546 | ||
547 | // receive fault | |
548 | ||
549 | always @ (posedge core_clk) | |
550 | if (reset) | |
551 | csr_trigger_receive_fault_d <= 1'b0; | |
552 | else | |
553 | csr_trigger_receive_fault_d <= csr_trigger_receive_fault; | |
554 | ||
555 | always @ (posedge core_clk) | |
556 | if (reset) | |
557 | set_receive_fault_high <= 1'b0; | |
558 | else if (csr_trigger_receive_fault & !csr_trigger_receive_fault_d) | |
559 | set_receive_fault_high <= 1'b1; | |
560 | else if (clear_status2) | |
561 | set_receive_fault_high <= 1'b0; | |
562 | else | |
563 | set_receive_fault_high <= set_receive_fault_high; | |
564 | ||
565 | always @ (posedge core_clk) | |
566 | if (reset) | |
567 | receive_fault_latch_high <= 1'b0; | |
568 | else | |
569 | receive_fault_latch_high <= set_receive_fault_high ? 1'b1 : csr_trigger_receive_fault; | |
570 | ||
571 | ||
572 | /****************************************************************************/ | |
573 | // Logic for link up/down status | |
574 | /****************************************************************************/ | |
575 | ||
576 | always @ (posedge core_clk) | |
577 | if (reset) | |
578 | csr_link_status_d <= 1'b0; | |
579 | else | |
580 | csr_link_status_d <= csr_link_status; | |
581 | ||
582 | always @ (posedge core_clk) | |
583 | if (reset) | |
584 | set_link_status_low <= 1'b0; | |
585 | else if (!csr_link_status & csr_link_status_d) | |
586 | set_link_status_low <= 1'b1; | |
587 | else if (clear_status2) | |
588 | set_link_status_low <= 1'b0; | |
589 | else | |
590 | set_link_status_low <= set_link_status_low; | |
591 | ||
592 | always @ (posedge core_clk) | |
593 | if (reset) | |
594 | link_status_latch_low <= 1'b0; | |
595 | else | |
596 | link_status_latch_low <= set_link_status_low ? 1'b0 : csr_link_status; | |
597 | ||
598 | ||
599 | // ************************************ | |
600 | // Interrupt logic | |
601 | // ************************************ | |
602 | ||
603 | ||
604 | // Register interrupt | |
605 | ||
606 | assign set_xpcs_interrupt = ((csr_link_status_d ^ csr_link_status) & (!csr_link_status_mask)) | | |
607 | ( (csr_fault & !csr_fault_d) & (!csr_fault_mask)); | |
608 | ||
609 | always @ (posedge core_clk) | |
610 | if (reset) | |
611 | xpcs_interrupt <= 1'b0; | |
612 | else if (set_xpcs_interrupt) | |
613 | xpcs_interrupt <= 1'b1; | |
614 | else if (clear_status1) | |
615 | xpcs_interrupt <= 1'b0; | |
616 | else | |
617 | xpcs_interrupt <= xpcs_interrupt; | |
618 | ||
619 | ||
620 | // Clear on read signals | |
621 | ||
622 | always @ (posedge core_clk) | |
623 | if (reset) | |
624 | clear_status1 <= 1'b0; | |
625 | else | |
626 | clear_status1 <= (read_pulse & addr[7:0]==8'h01); | |
627 | ||
628 | ||
629 | always @ (posedge core_clk) | |
630 | if (reset) | |
631 | clear_status2 <= 1'b0; | |
632 | else | |
633 | clear_status2 <= (read_pulse & addr[7:0]==8'h06); | |
634 | ||
635 | ||
636 | // ************************************ | |
637 | // Symbol error counters | |
638 | // ************************************ | |
639 | ||
640 | ||
641 | assign clear_symbol_err_cnt0 = read_pulse & (addr == 9'h010); | |
642 | ||
643 | always @ (posedge core_clk) | |
644 | if (reset | clear_symbol_err_cnt0 ) | |
645 | symbol_err_cnt0 <= 16'h0000; | |
646 | else if (trigger_symbol_err_cnt0 & (symbol_err_cnt0 != 16'hFFFF) & csr_xpcs_enable) | |
647 | symbol_err_cnt0 <= symbol_err_cnt0 + 16'h0001; | |
648 | else // else maintain error cnt | |
649 | symbol_err_cnt0 <= symbol_err_cnt0; | |
650 | ||
651 | ||
652 | ||
653 | assign clear_symbol_err_cnt1 = read_pulse & (addr == 9'h010); | |
654 | ||
655 | always @ (posedge core_clk) | |
656 | if (reset | clear_symbol_err_cnt1 ) | |
657 | symbol_err_cnt1 <= 16'h0000; | |
658 | else if (trigger_symbol_err_cnt1 & (symbol_err_cnt1 != 16'hFFFF) & csr_xpcs_enable) | |
659 | symbol_err_cnt1 <= symbol_err_cnt1 + 16'h0001; | |
660 | else // else maintain error cnt | |
661 | symbol_err_cnt1 <= symbol_err_cnt1; | |
662 | ||
663 | ||
664 | assign clear_symbol_err_cnt2 = read_pulse & (addr == 9'h011); | |
665 | ||
666 | always @ (posedge core_clk) | |
667 | if (reset | clear_symbol_err_cnt2 ) | |
668 | symbol_err_cnt2 <= 16'h0000; | |
669 | else if (trigger_symbol_err_cnt2 & (symbol_err_cnt2 != 16'hFFFF) & csr_xpcs_enable) | |
670 | symbol_err_cnt2 <= symbol_err_cnt2 + 16'h0001; | |
671 | else // else maintain error cnt | |
672 | symbol_err_cnt2 <= symbol_err_cnt2; | |
673 | ||
674 | ||
675 | assign clear_symbol_err_cnt3 = read_pulse & (addr == 9'h011); | |
676 | ||
677 | always @ (posedge core_clk) | |
678 | if (reset | clear_symbol_err_cnt3 ) | |
679 | symbol_err_cnt3 <= 16'h0000; | |
680 | else if (trigger_symbol_err_cnt3 & (symbol_err_cnt3 != 16'hFFFF) & csr_xpcs_enable) | |
681 | symbol_err_cnt3 <= symbol_err_cnt3 + 16'h0001; | |
682 | else // else maintain error cnt | |
683 | symbol_err_cnt3 <= symbol_err_cnt3; | |
684 | ||
685 | // ************************************ | |
686 | // training vector | |
687 | // ************************************ | |
688 | ||
689 | ||
690 | ||
691 | always @ (posedge core_clk) | |
692 | begin | |
693 | if (reset) | |
694 | training_vector <= 0; | |
695 | else if (ld_training_vector) | |
696 | training_vector <= wr_data[31:0]; | |
697 | else if (csr_vendor_debug_sel[3:0] == `SEL_xpcs_training_vector) | |
698 | training_vector <= ~training_vector; | |
699 | else training_vector <= training_vector; | |
700 | end | |
701 | ||
702 | ||
703 | ||
704 | ||
705 | endmodule // xpcs_pio |