Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: xpcs_sync.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module xpcs_sync (core_clk, | |
36 | tx_clk, | |
37 | ||
38 | rbc0_a, | |
39 | ||
40 | sw_reset, | |
41 | pio_core_reset, | |
42 | ||
43 | inc_tx_pkt_count_ref, | |
44 | inc_rx_pkt_count_ref, | |
45 | ||
46 | inc_tx_pkt_count, | |
47 | inc_rx_pkt_count, | |
48 | ||
49 | csr_pulse_deskew_error, | |
50 | ||
51 | csr_transmit_fault_ref, | |
52 | csr_receive_fault_ref, | |
53 | ||
54 | csr_trigger_transmit_fault, | |
55 | csr_trigger_receive_fault, | |
56 | ||
57 | inc_deskew_error, | |
58 | ||
59 | reset_rxclk, | |
60 | reset_txclk, | |
61 | ||
62 | clr_sw_reset, | |
63 | ||
64 | rx_error_0, | |
65 | rx_error_1, | |
66 | rx_error_2, | |
67 | rx_error_3, | |
68 | ||
69 | trigger_symbol_err_cnt0, | |
70 | trigger_symbol_err_cnt1, | |
71 | trigger_symbol_err_cnt2, | |
72 | trigger_symbol_err_cnt3, | |
73 | ||
74 | hw_reset, | |
75 | ||
76 | reset | |
77 | ||
78 | ); | |
79 | ||
80 | input core_clk; | |
81 | ||
82 | input tx_clk; // 312 Mhz TCLK from serdes | |
83 | ||
84 | input rbc0_a; // 312 Mhz rx clock from serdes | |
85 | ||
86 | input sw_reset; | |
87 | input pio_core_reset; | |
88 | ||
89 | input csr_pulse_deskew_error; | |
90 | ||
91 | input inc_tx_pkt_count_ref; | |
92 | input inc_rx_pkt_count_ref; | |
93 | ||
94 | input csr_transmit_fault_ref; | |
95 | input csr_receive_fault_ref; | |
96 | ||
97 | input rx_error_0; | |
98 | input rx_error_1; | |
99 | input rx_error_2; | |
100 | input rx_error_3; | |
101 | ||
102 | output reset_txclk; | |
103 | output reset_rxclk; | |
104 | output reset; | |
105 | output hw_reset; | |
106 | output clr_sw_reset; | |
107 | ||
108 | output inc_tx_pkt_count; | |
109 | output inc_rx_pkt_count; | |
110 | ||
111 | output inc_deskew_error; | |
112 | ||
113 | output csr_trigger_transmit_fault; | |
114 | output csr_trigger_receive_fault; | |
115 | ||
116 | output trigger_symbol_err_cnt0; | |
117 | output trigger_symbol_err_cnt1; | |
118 | output trigger_symbol_err_cnt2; | |
119 | output trigger_symbol_err_cnt3; | |
120 | ||
121 | reg trigger_inc_tx_pkt_count_ref; | |
122 | reg inc_tx_pkt_count_ref_d; | |
123 | wire inc_tx_pkt_count; | |
124 | wire clr_trigger_inc_tx_pkt_count_ref; | |
125 | ||
126 | reg trigger_inc_rx_pkt_count_ref; | |
127 | reg inc_rx_pkt_count_ref_d; | |
128 | wire inc_rx_pkt_count; | |
129 | wire inc_rx_pkt_count_ref_coreclk; | |
130 | wire clr_trigger_inc_rx_pkt_count_ref; | |
131 | ||
132 | reg pulse_deskew_error_ref; | |
133 | ||
134 | wire pulse_deskew_error; | |
135 | wire clr_pulse_deskew_error_ref; | |
136 | ||
137 | wire set_receive_fault; | |
138 | reg set_receive_fault_ref; | |
139 | ||
140 | wire set_transmit_fault; | |
141 | reg set_transmit_fault_ref; | |
142 | ||
143 | reg csr_pulse_deskew_error_d; | |
144 | reg csr_transmit_fault_ref_d; | |
145 | reg csr_receive_fault_ref_d; | |
146 | ||
147 | wire clr_set_receive_fault_ref; | |
148 | wire csr_trigger_receive_fault; | |
149 | ||
150 | wire clr_set_transmit_fault_ref; | |
151 | wire csr_trigger_transmit_fault; | |
152 | ||
153 | reg reset; | |
154 | reg hw_reset; | |
155 | ||
156 | wire reset_rxclk; | |
157 | wire reset_txclk; | |
158 | ||
159 | wire clr_sw_reset_int0; | |
160 | wire clr_sw_reset_int1; | |
161 | wire clr_sw_reset; | |
162 | ||
163 | reg [3:0] symbol_err_cnt0; | |
164 | reg [3:0] symbol_err_cnt1; | |
165 | reg [3:0] symbol_err_cnt2; | |
166 | reg [3:0] symbol_err_cnt3; | |
167 | ||
168 | reg symbol_err_cnt0_d; | |
169 | reg trigger_symbol_err_cnt0_rx; | |
170 | reg trigger_symbol_err_cnt0_core_d; | |
171 | wire trigger_symbol_err_cnt0_core; | |
172 | wire clr_trigger_trigger_symbol_err_cnt0_rx; | |
173 | wire trigger_symbol_err_cnt0; | |
174 | ||
175 | reg symbol_err_cnt1_d; | |
176 | reg trigger_symbol_err_cnt1_rx; | |
177 | reg trigger_symbol_err_cnt1_core_d; | |
178 | wire trigger_symbol_err_cnt1_core; | |
179 | wire clr_trigger_trigger_symbol_err_cnt1_rx; | |
180 | wire trigger_symbol_err_cnt1; | |
181 | ||
182 | reg symbol_err_cnt2_d; | |
183 | reg trigger_symbol_err_cnt2_rx; | |
184 | reg trigger_symbol_err_cnt2_core_d; | |
185 | wire trigger_symbol_err_cnt2_core; | |
186 | wire clr_trigger_trigger_symbol_err_cnt2_rx; | |
187 | wire trigger_symbol_err_cnt2; | |
188 | ||
189 | reg symbol_err_cnt3_d; | |
190 | reg trigger_symbol_err_cnt3_rx; | |
191 | reg trigger_symbol_err_cnt3_core_d; | |
192 | wire trigger_symbol_err_cnt3_core; | |
193 | wire clr_trigger_trigger_symbol_err_cnt3_rx; | |
194 | wire trigger_symbol_err_cnt3; | |
195 | ||
196 | ||
197 | // ****************** | |
198 | // xpcs reset logic | |
199 | // ****************** | |
200 | ||
201 | always @ (posedge core_clk) | |
202 | hw_reset <= pio_core_reset; | |
203 | ||
204 | always @ (posedge core_clk) | |
205 | reset <= (hw_reset | sw_reset); | |
206 | ||
207 | SYNC_CELL XPCS_CLR_SW_RESET_INT0 (.D(sw_reset), .CP(tx_clk), .Q(clr_sw_reset_int0)); | |
208 | SYNC_CELL XPCS_CLR_SW_RESET_INT1 (.D(clr_sw_reset_int0), .CP(rbc0_a), .Q(clr_sw_reset_int1)); | |
209 | SYNC_CELL XPCS_CLR_SW_RESET (.D(clr_sw_reset_int1), .CP(core_clk),.Q(clr_sw_reset)); | |
210 | ||
211 | SYNC_CELL reset_txclk_CLK (.D(reset), .CP(tx_clk), .Q(reset_txclk)); | |
212 | SYNC_CELL reset_rxclk_CLK (.D(reset), .CP(rbc0_a), .Q(reset_rxclk)); | |
213 | ||
214 | ||
215 | // ******************************** | |
216 | // Rx packet Counter trigger | |
217 | // ******************************** | |
218 | ||
219 | always @ (posedge rbc0_a) | |
220 | inc_rx_pkt_count_ref_d <= inc_rx_pkt_count_ref; | |
221 | ||
222 | always @ (posedge rbc0_a) | |
223 | trigger_inc_rx_pkt_count_ref <= (reset_rxclk | clr_trigger_inc_rx_pkt_count_ref) ? 1'b0 : | |
224 | (inc_rx_pkt_count_ref & !inc_rx_pkt_count_ref_d) ? 1'b1 : | |
225 | trigger_inc_rx_pkt_count_ref; | |
226 | ||
227 | SYNC_CELL XPCS_INC_RX_PKT_SYNC (.D(trigger_inc_rx_pkt_count_ref), | |
228 | .CP(core_clk), | |
229 | .Q(inc_rx_pkt_count_ref_coreclk)); | |
230 | ||
231 | assign inc_rx_pkt_count = inc_rx_pkt_count_ref_coreclk; | |
232 | ||
233 | SYNC_CELL XPCS_CLR_RX_PKT_SYNC (.D(inc_rx_pkt_count), | |
234 | .CP(rbc0_a), | |
235 | .Q(clr_trigger_inc_rx_pkt_count_ref)); | |
236 | ||
237 | // ******************************** | |
238 | // Tx packet Counter trigger | |
239 | // ******************************** | |
240 | ||
241 | always @ (posedge tx_clk) | |
242 | inc_tx_pkt_count_ref_d <= inc_tx_pkt_count_ref; | |
243 | ||
244 | always @ (posedge tx_clk) | |
245 | trigger_inc_tx_pkt_count_ref <= (reset_txclk | clr_trigger_inc_tx_pkt_count_ref) ? 1'b0 : | |
246 | (inc_tx_pkt_count_ref & !inc_tx_pkt_count_ref_d) ? 1'b1 : | |
247 | trigger_inc_tx_pkt_count_ref; | |
248 | ||
249 | SYNC_CELL XPCS_INC_TX_PKT_SYNC (.D(trigger_inc_tx_pkt_count_ref), | |
250 | .CP(core_clk), | |
251 | .Q(inc_tx_pkt_count)); | |
252 | ||
253 | SYNC_CELL XPCS_CLR_TX_PKT_SYNC (.D(inc_tx_pkt_count), | |
254 | .CP(tx_clk), | |
255 | .Q(clr_trigger_inc_tx_pkt_count_ref)); | |
256 | ||
257 | ||
258 | // ******************************** | |
259 | // Deskew Error Counter trigger | |
260 | // ******************************** | |
261 | ||
262 | always @ (posedge tx_clk) | |
263 | csr_pulse_deskew_error_d <= csr_pulse_deskew_error; | |
264 | ||
265 | always @ (posedge tx_clk) | |
266 | pulse_deskew_error_ref <= (reset_txclk | clr_pulse_deskew_error_ref) ? 1'b0 : | |
267 | (csr_pulse_deskew_error & !csr_pulse_deskew_error_d) ? 1'b1 : | |
268 | pulse_deskew_error_ref; | |
269 | ||
270 | SYNC_CELL XPCS_INC_DESKEW_ERR_SYNC (.D(pulse_deskew_error_ref), | |
271 | .CP(core_clk), | |
272 | .Q(pulse_deskew_error)); | |
273 | ||
274 | assign inc_deskew_error = pulse_deskew_error; | |
275 | ||
276 | SYNC_CELL XPCS_CLR_DESKEW_ERR_SYNC (.D(inc_deskew_error), | |
277 | .CP(tx_clk), | |
278 | .Q(clr_pulse_deskew_error_ref)); | |
279 | ||
280 | ||
281 | // ******************************** | |
282 | // Transmit fault trigger | |
283 | // ******************************** | |
284 | ||
285 | always @ (posedge tx_clk) | |
286 | csr_transmit_fault_ref_d <= csr_transmit_fault_ref; | |
287 | ||
288 | always @ (posedge tx_clk) | |
289 | set_transmit_fault_ref <= (reset_txclk | clr_set_transmit_fault_ref) ? 1'b0 : | |
290 | (csr_transmit_fault_ref & !csr_transmit_fault_ref_d) ? 1'b1 : | |
291 | set_transmit_fault_ref; | |
292 | ||
293 | SYNC_CELL XPCS_INC_TX_FAULT_SYNC (.D(set_transmit_fault_ref), | |
294 | .CP(core_clk), | |
295 | .Q(set_transmit_fault)); | |
296 | ||
297 | assign csr_trigger_transmit_fault = set_transmit_fault; | |
298 | ||
299 | SYNC_CELL XPCS_CLR_TX_FAULT_SYNC (.D(csr_trigger_transmit_fault), | |
300 | .CP(tx_clk), | |
301 | .Q(clr_set_transmit_fault_ref)); | |
302 | ||
303 | ||
304 | ||
305 | // ******************************** | |
306 | // Receive fault trigger | |
307 | // ******************************** | |
308 | ||
309 | always @ (posedge rbc0_a) | |
310 | csr_receive_fault_ref_d <= csr_receive_fault_ref; | |
311 | ||
312 | always @ (posedge rbc0_a) | |
313 | set_receive_fault_ref <= (reset_rxclk | clr_set_receive_fault_ref) ? 1'b0 : | |
314 | (csr_receive_fault_ref & !csr_receive_fault_ref_d) ? 1'b1 : | |
315 | set_receive_fault_ref; | |
316 | ||
317 | SYNC_CELL XPCS_INC_RX_FAULT_SYNC (.D(set_receive_fault_ref), | |
318 | .CP(core_clk), | |
319 | .Q(set_receive_fault)); | |
320 | ||
321 | assign csr_trigger_receive_fault = set_receive_fault; | |
322 | ||
323 | SYNC_CELL XPCS_CLR_RX_FAULT_SYNC (.D(csr_trigger_receive_fault), | |
324 | .CP(rbc0_a), | |
325 | .Q(clr_set_receive_fault_ref)); | |
326 | ||
327 | ||
328 | // ******************************** | |
329 | // Symbol error counter logic 0 | |
330 | // ******************************** | |
331 | ||
332 | always @ (posedge rbc0_a) | |
333 | if (reset_rxclk) | |
334 | symbol_err_cnt0 <= 4'b0; | |
335 | else if (rx_error_0) | |
336 | symbol_err_cnt0 <= symbol_err_cnt0 + 4'h1; | |
337 | else | |
338 | symbol_err_cnt0 <= symbol_err_cnt0; | |
339 | ||
340 | always @ (posedge rbc0_a) | |
341 | symbol_err_cnt0_d <= symbol_err_cnt0[3]; | |
342 | ||
343 | always @ (posedge rbc0_a) | |
344 | if (reset_rxclk) | |
345 | trigger_symbol_err_cnt0_rx <= 1'b0; | |
346 | else | |
347 | trigger_symbol_err_cnt0_rx <= (symbol_err_cnt0[3] & !symbol_err_cnt0_d) ? 1'b1 : | |
348 | (clr_trigger_trigger_symbol_err_cnt0_rx) ? 1'b0 : | |
349 | trigger_symbol_err_cnt0_rx; | |
350 | ||
351 | SYNC_CELL SYMBOL_ERR0_SYNC (.D(trigger_symbol_err_cnt0_rx), | |
352 | .CP(core_clk), | |
353 | .Q(trigger_symbol_err_cnt0_core)); | |
354 | ||
355 | SYNC_CELL CLR_SYMBOL_ERR0_SYNC (.D(trigger_symbol_err_cnt0_core), | |
356 | .CP(rbc0_a), | |
357 | .Q(clr_trigger_trigger_symbol_err_cnt0_rx)); | |
358 | ||
359 | always @ (posedge core_clk) | |
360 | trigger_symbol_err_cnt0_core_d <= trigger_symbol_err_cnt0_core; | |
361 | ||
362 | assign trigger_symbol_err_cnt0 = trigger_symbol_err_cnt0_core & !trigger_symbol_err_cnt0_core_d; | |
363 | ||
364 | ||
365 | ||
366 | // ******************************** | |
367 | // Symbol error counter logic 1 | |
368 | // ******************************** | |
369 | ||
370 | ||
371 | ||
372 | always @ (posedge rbc0_a) | |
373 | if (reset_rxclk) | |
374 | symbol_err_cnt1 <= 4'b0; | |
375 | else if (rx_error_1) | |
376 | symbol_err_cnt1 <= symbol_err_cnt1 + 4'h1; | |
377 | else | |
378 | symbol_err_cnt1 <= symbol_err_cnt1; | |
379 | ||
380 | ||
381 | always @ (posedge rbc0_a) | |
382 | symbol_err_cnt1_d <= symbol_err_cnt1[3]; | |
383 | ||
384 | always @ (posedge rbc0_a) | |
385 | if (reset_rxclk) | |
386 | trigger_symbol_err_cnt1_rx <= 1'b0; | |
387 | else | |
388 | trigger_symbol_err_cnt1_rx <= (symbol_err_cnt1[3] & !symbol_err_cnt1_d) ? 1'b1 : | |
389 | (clr_trigger_trigger_symbol_err_cnt1_rx) ? 1'b0 : | |
390 | trigger_symbol_err_cnt1_rx; | |
391 | ||
392 | SYNC_CELL SYMBOL_ERR1_SYNC (.D(trigger_symbol_err_cnt1_rx), | |
393 | .CP(core_clk), | |
394 | .Q(trigger_symbol_err_cnt1_core)); | |
395 | ||
396 | SYNC_CELL CLR_SYMBOL_ERR1_SYNC (.D(trigger_symbol_err_cnt1_core), | |
397 | .CP(rbc0_a), | |
398 | .Q(clr_trigger_trigger_symbol_err_cnt1_rx)); | |
399 | ||
400 | always @ (posedge core_clk) | |
401 | trigger_symbol_err_cnt1_core_d <= trigger_symbol_err_cnt1_core; | |
402 | ||
403 | assign trigger_symbol_err_cnt1 = trigger_symbol_err_cnt1_core & !trigger_symbol_err_cnt1_core_d; | |
404 | ||
405 | ||
406 | ||
407 | // ******************************** | |
408 | // Symbol error counter logic 2 | |
409 | // ******************************** | |
410 | ||
411 | ||
412 | always @ (posedge rbc0_a) | |
413 | if (reset_rxclk) | |
414 | symbol_err_cnt2 <= 4'b0; | |
415 | else if (rx_error_2) | |
416 | symbol_err_cnt2 <= symbol_err_cnt2 + 4'h1; | |
417 | else | |
418 | symbol_err_cnt2 <= symbol_err_cnt2; | |
419 | ||
420 | ||
421 | always @ (posedge rbc0_a) | |
422 | symbol_err_cnt2_d <= symbol_err_cnt2[3]; | |
423 | ||
424 | always @ (posedge rbc0_a) | |
425 | if (reset_rxclk) | |
426 | trigger_symbol_err_cnt2_rx <= 1'b0; | |
427 | else | |
428 | trigger_symbol_err_cnt2_rx <= (symbol_err_cnt2[3] & !symbol_err_cnt2_d) ? 1'b1 : | |
429 | (clr_trigger_trigger_symbol_err_cnt2_rx) ? 1'b0 : | |
430 | trigger_symbol_err_cnt2_rx; | |
431 | ||
432 | SYNC_CELL SYMBOL_ERR2_SYNC (.D(trigger_symbol_err_cnt2_rx), | |
433 | .CP(core_clk), | |
434 | .Q(trigger_symbol_err_cnt2_core)); | |
435 | ||
436 | SYNC_CELL CLR_SYMBOL_ERR2_SYNC (.D(trigger_symbol_err_cnt2_core), | |
437 | .CP(rbc0_a), | |
438 | .Q(clr_trigger_trigger_symbol_err_cnt2_rx)); | |
439 | ||
440 | always @ (posedge core_clk) | |
441 | trigger_symbol_err_cnt2_core_d <= trigger_symbol_err_cnt2_core; | |
442 | ||
443 | assign trigger_symbol_err_cnt2 = trigger_symbol_err_cnt2_core & !trigger_symbol_err_cnt2_core_d; | |
444 | ||
445 | ||
446 | // ******************************** | |
447 | // Symbol error counter logic 3 | |
448 | // ******************************** | |
449 | ||
450 | ||
451 | always @ (posedge rbc0_a) | |
452 | if (reset_rxclk) | |
453 | symbol_err_cnt3 <= 4'b0; | |
454 | else if (rx_error_3) | |
455 | symbol_err_cnt3 <= symbol_err_cnt3 + 4'h1; | |
456 | else | |
457 | symbol_err_cnt3 <= symbol_err_cnt3; | |
458 | ||
459 | ||
460 | always @ (posedge rbc0_a) | |
461 | symbol_err_cnt3_d <= symbol_err_cnt3[3]; | |
462 | ||
463 | always @ (posedge rbc0_a) | |
464 | if (reset_rxclk) | |
465 | trigger_symbol_err_cnt3_rx <= 1'b0; | |
466 | else | |
467 | trigger_symbol_err_cnt3_rx <= (symbol_err_cnt3[3] & !symbol_err_cnt3_d) ? 1'b1 : | |
468 | (clr_trigger_trigger_symbol_err_cnt3_rx) ? 1'b0 : | |
469 | trigger_symbol_err_cnt3_rx; | |
470 | ||
471 | SYNC_CELL SYMBOL_ERR3_SYNC (.D(trigger_symbol_err_cnt3_rx), | |
472 | .CP(core_clk), | |
473 | .Q(trigger_symbol_err_cnt3_core)); | |
474 | ||
475 | SYNC_CELL CLR_SYMBOL_ERR3_SYNC (.D(trigger_symbol_err_cnt3_core), | |
476 | .CP(rbc0_a), | |
477 | .Q(clr_trigger_trigger_symbol_err_cnt3_rx)); | |
478 | ||
479 | always @ (posedge core_clk) | |
480 | trigger_symbol_err_cnt3_core_d <= trigger_symbol_err_cnt3_core; | |
481 | ||
482 | assign trigger_symbol_err_cnt3 = trigger_symbol_err_cnt3_core & !trigger_symbol_err_cnt3_core_d; | |
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | endmodule |