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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sii_inc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sii_inc_ctl ( | |
36 | ncu_sii_gnt, | |
37 | sii_ncu_req, | |
38 | sii_ncu_data, | |
39 | sii_ncu_dparity, | |
40 | inc_indq_rd_addr, | |
41 | inc_indq_rd_en, | |
42 | indq_inc_dout, | |
43 | inc_ipcc_stop, | |
44 | ipcc_indq_wr_addr, | |
45 | ipcc_indq_wr_en, | |
46 | ipcc_inc_wr_ovfl, | |
47 | l2clk, | |
48 | cmp_io_sync_en_in, | |
49 | io_cmp_sync_en_in, | |
50 | scan_in, | |
51 | scan_out, | |
52 | tcu_scan_en, | |
53 | tcu_aclk, | |
54 | tcu_bclk, | |
55 | tcu_pce_ov, | |
56 | tcu_clk_stop, | |
57 | sii_mb0_run, | |
58 | sii_mb0_ind_rd_en, | |
59 | sii_mb0_addr, | |
60 | sii_mb0_wdata, | |
61 | sii_mb0_ind_fail); | |
62 | wire l1clk; | |
63 | wire spares_scanin; | |
64 | wire spares_scanout; | |
65 | wire se; | |
66 | wire siclk; | |
67 | wire soclk; | |
68 | wire pce_ov; | |
69 | wire stop; | |
70 | wire [67:0] mbist1_data; | |
71 | wire [7:0] sii_mb0_wdata_r; | |
72 | wire [67:0] compare; | |
73 | wire [67:0] mbist1_data_rr; | |
74 | wire [1:0] sii_mb0_ind_fail_l; | |
75 | wire [4:0] cstate_r; | |
76 | wire [31:0] sii_ncu_data_l; | |
77 | wire arc_hdr_data; | |
78 | wire [33:0] new_data; | |
79 | wire [1:0] sii_ncu_dparity_l; | |
80 | wire sii_ncu_req_l; | |
81 | wire make_request; | |
82 | wire sii_mb0_run_r; | |
83 | wire [5:0] sii_mb0_addr_r; | |
84 | wire arc_gnt_hdr; | |
85 | wire cmp_io_sync_en; | |
86 | wire [2:0] cyc_cnt_r; | |
87 | wire [5:0] inc_indq_rd_addr_r; | |
88 | wire sii_mb0_ind_rd_en_r; | |
89 | wire turn_off_rd_en; | |
90 | wire ind_fifo_full; | |
91 | wire [33:0] data_l; | |
92 | wire [33:0] data_h; | |
93 | wire ind_fifo_empty; | |
94 | wire rd_ovfl_l; | |
95 | wire ind_fifo_full_l; | |
96 | wire rd_ovfl_r; | |
97 | wire cyc_cnt_en; | |
98 | wire [2:0] cyc_cnt_l; | |
99 | wire data_end; | |
100 | wire got_gnt_l; | |
101 | wire ncu_sii_gnt_r; | |
102 | wire got_gnt_r; | |
103 | wire arc_start_req; | |
104 | wire arc_req_gnt; | |
105 | wire cmp_io_sync_en_dly2; | |
106 | wire cmp_io_sync_en_dly3; | |
107 | wire arc_data_start; | |
108 | wire arc_data_gnt; | |
109 | wire arc_data_req; | |
110 | wire reg_cstate_scanin; | |
111 | wire reg_cstate_scanout; | |
112 | wire reg_sii_mb0_ind_fail_scanin; | |
113 | wire reg_sii_mb0_ind_fail_scanout; | |
114 | wire reg_mbist1_data_rr_scanin; | |
115 | wire reg_mbist1_data_rr_scanout; | |
116 | wire [67:0] mbist1_data_r; | |
117 | wire reg_mbist1_data_r_scanin; | |
118 | wire reg_mbist1_data_r_scanout; | |
119 | wire reg_rd_ovfl_scanin; | |
120 | wire reg_rd_ovfl_scanout; | |
121 | wire reg_got_gnt_scanin; | |
122 | wire reg_got_gnt_scanout; | |
123 | wire reg_cmp_io_syn_en_scanin; | |
124 | wire reg_cmp_io_syn_en_scanout; | |
125 | wire cmp_io_sync_en_dly; | |
126 | wire reg_cmp_io_syn_en_dly2_scanin; | |
127 | wire reg_cmp_io_syn_en_dly2_scanout; | |
128 | wire reg_cmp_io_syn_en_dly3_scanin; | |
129 | wire reg_cmp_io_syn_en_dly3_scanout; | |
130 | wire reg_ncu_sii_gnt_scanin; | |
131 | wire reg_ncu_sii_gnt_scanout; | |
132 | wire io_cmp_sync_en; | |
133 | wire reg_cyc_cnt_r_scanin; | |
134 | wire reg_cyc_cnt_r_scanout; | |
135 | wire reg_inc_indq_rd_addr_scanin; | |
136 | wire reg_inc_indq_rd_addr_scanout; | |
137 | wire reg_sii_ncu_req_scanin; | |
138 | wire reg_sii_ncu_req_scanout; | |
139 | wire reg_sii_ncu_data_scanin; | |
140 | wire reg_sii_ncu_data_scanout; | |
141 | wire reg_sii_ncu_dparity_scanin; | |
142 | wire reg_sii_ncu_dparity_scanout; | |
143 | wire reg_cmp_io_sync_en_scanin; | |
144 | wire reg_cmp_io_sync_en_scanout; | |
145 | wire reg_io_cmp_sync_en_scanin; | |
146 | wire reg_io_cmp_sync_en_scanout; | |
147 | wire reg_sii_mb0_run_scanin; | |
148 | wire reg_sii_mb0_run_scanout; | |
149 | wire reg_sii_mb0_ind_rd_en_scanin; | |
150 | wire reg_sii_mb0_ind_rd_en_scanout; | |
151 | wire reg_sii_mb0_addr_scanin; | |
152 | wire reg_sii_mb0_addr_scanout; | |
153 | wire reg_sii_mb0_wdata_scanin; | |
154 | wire reg_sii_mb0_wdata_scanout; | |
155 | wire reg_ind_fifo_full_scanin; | |
156 | wire reg_ind_fifo_full_scanout; | |
157 | ||
158 | ||
159 | input ncu_sii_gnt; //io_clk | |
160 | output sii_ncu_req; //io_clk | |
161 | output [31:0] sii_ncu_data; //io_clk | |
162 | output [1:0] sii_ncu_dparity; //io_clk | |
163 | ||
164 | //------inter-submodule signals------- | |
165 | ||
166 | output [5:0] inc_indq_rd_addr; //cmp_clk | |
167 | output inc_indq_rd_en; //cmp_clk | |
168 | input [67:0] indq_inc_dout; | |
169 | ||
170 | output inc_ipcc_stop; //cmp_clk | |
171 | input [5:0] ipcc_indq_wr_addr; //cmp_clk | |
172 | input ipcc_indq_wr_en; //cmp_clk | |
173 | input ipcc_inc_wr_ovfl; //for checking empty/full of fifo | |
174 | ||
175 | input l2clk; | |
176 | input cmp_io_sync_en_in; | |
177 | input io_cmp_sync_en_in; | |
178 | input scan_in ; | |
179 | output scan_out; | |
180 | input tcu_scan_en; | |
181 | input tcu_aclk; | |
182 | input tcu_bclk; | |
183 | input tcu_pce_ov; | |
184 | input tcu_clk_stop; | |
185 | ||
186 | //-------mbist related signals ------- | |
187 | ||
188 | input sii_mb0_run; | |
189 | input sii_mb0_ind_rd_en; | |
190 | input [5:0] sii_mb0_addr; | |
191 | input [7:0] sii_mb0_wdata; | |
192 | output [1:0] sii_mb0_ind_fail; | |
193 | ||
194 | ||
195 | // Clock header | |
196 | sii_inc_ctll1clkhdr_ctl_macro clkgen ( | |
197 | .l2clk (l2clk ), | |
198 | .l1en (1'b1 ), | |
199 | .l1clk (l1clk ), | |
200 | .pce_ov(pce_ov), | |
201 | .stop(stop), | |
202 | .se(se) | |
203 | ); | |
204 | ||
205 | // Spare gates | |
206 | sii_inc_ctlspare_ctl_macro__num_2 spares ( | |
207 | .scan_in(spares_scanin), | |
208 | .scan_out(spares_scanout), | |
209 | .l1clk (l1clk), | |
210 | .siclk(siclk), | |
211 | .soclk(soclk) | |
212 | ); | |
213 | ||
214 | //************************************************************************ | |
215 | // SCAN CONNECTIONS | |
216 | //************************************************************************ | |
217 | // scan renames | |
218 | assign se = tcu_scan_en; | |
219 | assign siclk = tcu_aclk; | |
220 | assign soclk = tcu_bclk; | |
221 | assign pce_ov = tcu_pce_ov; | |
222 | assign stop = tcu_clk_stop; | |
223 | // end scan | |
224 | ||
225 | //************************************************************************ | |
226 | // MBIST CONNECTIONS | |
227 | //************************************************************************ | |
228 | ||
229 | assign mbist1_data[67:0] = {sii_mb0_wdata_r[1:0], sii_mb0_wdata_r[7:6], sii_mb0_wdata_r[7:0], | |
230 | sii_mb0_wdata_r[7:0], | |
231 | sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0], | |
232 | sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0]}; | |
233 | assign compare[67:0] = mbist1_data_rr[67:0] ^ indq_inc_dout[67:0]; | |
234 | ||
235 | assign sii_mb0_ind_fail_l[1] = | compare[67:34]; | |
236 | assign sii_mb0_ind_fail_l[0] = | compare[33:0]; | |
237 | ||
238 | //************************************************************************ | |
239 | // STATE DEFINITION | |
240 | //************************************************************************ | |
241 | ||
242 | `define START_ST 5'b00001 | |
243 | `define REQ_ST 5'b00010 | |
244 | `define GNT_ST 5'b00100 | |
245 | `define HDR_ST 5'b01000 | |
246 | `define DATA_ST 5'b10000 | |
247 | ||
248 | `define START 0 | |
249 | `define REQ 1 | |
250 | `define GNT 2 | |
251 | `define HDR 3 | |
252 | `define DATA 4 | |
253 | ||
254 | ||
255 | reg [4:0] nstate_r; | |
256 | //reg [4:0] cstate_r; | |
257 | ||
258 | wire [4:0] nstate; | |
259 | wire [4:0] cstate; | |
260 | ||
261 | // ------- internal signals -------- | |
262 | ||
263 | //0in one_hot -var cstate[4:0] | |
264 | //0in one_hot -var nstate_r[4:0] | |
265 | ||
266 | assign nstate = {nstate_r[4:1], ~nstate_r[0]}; | |
267 | assign cstate = {cstate_r[4:1], ~cstate_r[0]}; | |
268 | ||
269 | //************************************************************************ | |
270 | // OUTPUT LOGICS | |
271 | //************************************************************************ | |
272 | ||
273 | assign sii_ncu_data_l[31:0] = ((cstate[`HDR] && ~arc_hdr_data ) || cstate[`GNT]) ? | |
274 | indq_inc_dout[31:0] : new_data[31:0]; | |
275 | ||
276 | assign sii_ncu_dparity_l[1:0] = ((cstate[`HDR] && ~arc_hdr_data ) || cstate[`GNT]) ? | |
277 | indq_inc_dout[65:64] : new_data[33:32]; | |
278 | ||
279 | assign sii_ncu_req_l = make_request; | |
280 | ||
281 | assign inc_indq_rd_addr[5:0] = sii_mb0_run_r ? sii_mb0_addr_r[5:0] : | |
282 | (arc_gnt_hdr || (cmp_io_sync_en && cyc_cnt_r[0])) ? | |
283 | ((inc_indq_rd_addr_r[5:0] == 6'd47 ) ? 6'd0 : // 0in range -var inc_indq_rd_addr_r -min 0 -max 47 | |
284 | (inc_indq_rd_addr_r[5:0] + 6'h01)) : | |
285 | inc_indq_rd_addr_r[5:0]; | |
286 | ||
287 | assign inc_indq_rd_en = sii_mb0_run_r ? sii_mb0_ind_rd_en_r : | |
288 | ~turn_off_rd_en; | |
289 | assign inc_ipcc_stop = ind_fifo_full; | |
290 | //************************************************************************ | |
291 | // internal wires assignment | |
292 | //************************************************************************ | |
293 | //assign early_hdr_end = cmp_io_sync_en ; | |
294 | assign new_data[33:0] = cyc_cnt_r[0] ? data_l[33:0] : data_h[33:0]; | |
295 | //assign data_h[33:0] = {indq_inc_dout[67:66], indq_inc_dout[39:32], | |
296 | // indq_inc_dout[47:40], indq_inc_dout[55:48], indq_inc_dout[63:56]}; | |
297 | //assign data_l[33:0] = {indq_inc_dout[65:64], indq_inc_dout[7:0], | |
298 | // indq_inc_dout[15:8], indq_inc_dout[23:16], indq_inc_dout[31:24]}; | |
299 | ||
300 | assign data_h[33:0] = {indq_inc_dout[67:66], indq_inc_dout[63:32]} ; | |
301 | assign data_l[33:0] = {indq_inc_dout[65:64], indq_inc_dout[31:0]} ; | |
302 | ||
303 | ||
304 | assign turn_off_rd_en = (ipcc_indq_wr_addr[5:0] == inc_indq_rd_addr[5:0]) && ipcc_indq_wr_en ; | |
305 | ||
306 | //------------ fifo empty/full handling ---------------- | |
307 | //assign ind_fifo_empty = ((inc_indq_rd_addr[5:0] == ipcc_indq_wr_addr[5:0] ) | |
308 | // && (rd_ovfl_r == ipcc_inc_wr_ovfl)) || | |
309 | // ((inc_indq_rd_addr[5:0] == ipcc_indq_wr_addr[5:0] - 6'h01) | |
310 | // && (rd_ovfl_r == ipcc_inc_wr_ovfl)) || | |
311 | // (inc_indq_rd_addr - ipcc_indq_wr_addr == 6'd47) ; | |
312 | ||
313 | assign ind_fifo_empty = (((ipcc_indq_wr_addr[5:0] - inc_indq_rd_addr[5:0]) < 6'd3) | |
314 | && (rd_ovfl_l == ipcc_inc_wr_ovfl) || | |
315 | ((inc_indq_rd_addr[5:0] - ipcc_indq_wr_addr[5:0]) > 6'd45) | |
316 | && (rd_ovfl_l ^ ipcc_inc_wr_ovfl)) | |
317 | ? 1'b1 : 1'b0; | |
318 | ||
319 | ||
320 | assign ind_fifo_full_l = (ipcc_indq_wr_addr[5:0]- inc_indq_rd_addr_r[5:0] > 6'd44) | |
321 | && (rd_ovfl_r == ipcc_inc_wr_ovfl) || | |
322 | (inc_indq_rd_addr_r - ipcc_indq_wr_addr < 6'd6) | |
323 | && (rd_ovfl_r != ipcc_inc_wr_ovfl) ; | |
324 | assign rd_ovfl_l = (inc_indq_rd_addr_r[5:0] == 6'd47) && (inc_indq_rd_addr[5:0] == 6'd0 ) ? | |
325 | ~rd_ovfl_r : rd_ovfl_r; | |
326 | ||
327 | //------------------payload cycle decoding--------------- | |
328 | assign cyc_cnt_en = (cstate[`DATA] && cmp_io_sync_en ) ; | |
329 | assign cyc_cnt_l[2:0] = (arc_gnt_hdr )? 3'b000 : ((cyc_cnt_en && ~data_end) ? | |
330 | (cyc_cnt_r[2:0] + 3'b001) : cyc_cnt_r[2:0]); | |
331 | ||
332 | assign data_end = cyc_cnt_r[2] ; | |
333 | assign got_gnt_l = ncu_sii_gnt_r && sii_ncu_req ? 1'b1 : cstate[`HDR] ? 1'b0 : got_gnt_r ; | |
334 | assign make_request = ~ind_fifo_empty ; | |
335 | ||
336 | //************************************************************************ | |
337 | // STATE TRANSITION SECTION | |
338 | //************************************************************************ | |
339 | ||
340 | assign arc_start_req = cstate[`START] && make_request; | |
341 | ||
342 | assign arc_req_gnt = cstate[`REQ] && got_gnt_l & cmp_io_sync_en; | |
343 | ||
344 | assign arc_gnt_hdr = cstate[`GNT] && (cmp_io_sync_en ) ; //1 to 4 | |
345 | // ( cmp_io_sync_en_dly2 & cmp_io_sync_en)); // 1 to 3/4 | |
346 | assign arc_hdr_data = cstate[`HDR] && ~cmp_io_sync_en_dly2 && cmp_io_sync_en_dly3; | |
347 | assign arc_data_start = cstate[`DATA] && ind_fifo_empty && data_end; | |
348 | assign arc_data_gnt = cstate[`DATA] && data_end && got_gnt_l & cmp_io_sync_en; | |
349 | assign arc_data_req = cstate[`DATA] && data_end && cmp_io_sync_en && make_request && ~got_gnt_l; | |
350 | ||
351 | always @ (arc_start_req or arc_req_gnt or arc_gnt_hdr or arc_hdr_data or | |
352 | arc_data_gnt or arc_data_req or arc_data_start or cstate ) | |
353 | ||
354 | begin | |
355 | case (1'b1) //synopsys parallel_case full_case | |
356 | cstate[`START] : if (arc_start_req) | |
357 | nstate_r = `REQ_ST; | |
358 | else | |
359 | nstate_r = `START_ST; | |
360 | cstate[`REQ] : if (arc_req_gnt) | |
361 | nstate_r = `GNT_ST; | |
362 | else | |
363 | nstate_r = `REQ_ST; | |
364 | cstate[`GNT] : if (arc_gnt_hdr) | |
365 | nstate_r = `HDR_ST; | |
366 | else | |
367 | nstate_r = `GNT_ST; | |
368 | cstate[`HDR] : if (arc_hdr_data) | |
369 | nstate_r = `DATA_ST; | |
370 | else | |
371 | nstate_r = `HDR_ST; | |
372 | cstate[`DATA] : if (arc_data_gnt) | |
373 | nstate_r = `GNT_ST; | |
374 | else if (arc_data_start) | |
375 | nstate_r = `START_ST; | |
376 | else if (arc_data_req) | |
377 | nstate_r = `REQ_ST; | |
378 | else | |
379 | nstate_r = `DATA_ST; | |
380 | default : begin | |
381 | nstate_r = `START_ST; | |
382 | // 0in < fire -message "ERROR: sii_inc statemachine default case" | |
383 | end | |
384 | ||
385 | endcase | |
386 | end | |
387 | ||
388 | //************************************************************************ | |
389 | // REGISTERS section | |
390 | //************************************************************************ | |
391 | sii_inc_ctlmsff_ctl_macro__width_5 reg_cstate // ASYNC reset active low | |
392 | ( | |
393 | .scan_in(reg_cstate_scanin), | |
394 | .scan_out(reg_cstate_scanout), | |
395 | .dout(cstate_r[4:0]), | |
396 | .l1clk(l1clk), | |
397 | .din(nstate[4:0]), | |
398 | .siclk(siclk), | |
399 | .soclk(soclk) | |
400 | ); | |
401 | ||
402 | sii_inc_ctlmsff_ctl_macro__width_2 reg_sii_mb0_ind_fail // ASYNC reset active low | |
403 | ( | |
404 | .scan_in(reg_sii_mb0_ind_fail_scanin), | |
405 | .scan_out(reg_sii_mb0_ind_fail_scanout), | |
406 | .dout(sii_mb0_ind_fail[1:0]), | |
407 | .l1clk(l1clk), | |
408 | .din(sii_mb0_ind_fail_l[1:0]), | |
409 | .siclk(siclk), | |
410 | .soclk(soclk) | |
411 | ); | |
412 | ||
413 | sii_inc_ctlmsff_ctl_macro__width_68 reg_mbist1_data_rr // ASYNC reset active low | |
414 | ( | |
415 | .scan_in(reg_mbist1_data_rr_scanin), | |
416 | .scan_out(reg_mbist1_data_rr_scanout), | |
417 | .dout(mbist1_data_rr[67:0]), | |
418 | .l1clk(l1clk), | |
419 | .din(mbist1_data_r[67:0]), | |
420 | .siclk(siclk), | |
421 | .soclk(soclk) | |
422 | ); | |
423 | ||
424 | sii_inc_ctlmsff_ctl_macro__width_68 reg_mbist1_data_r // ASYNC reset active low | |
425 | ( | |
426 | .scan_in(reg_mbist1_data_r_scanin), | |
427 | .scan_out(reg_mbist1_data_r_scanout), | |
428 | .dout(mbist1_data_r[67:0]), | |
429 | .l1clk(l1clk), | |
430 | .din(mbist1_data[67:0]), | |
431 | .siclk(siclk), | |
432 | .soclk(soclk) | |
433 | ); | |
434 | ||
435 | sii_inc_ctlmsff_ctl_macro__width_1 reg_rd_ovfl // ASYNC reset active low | |
436 | ( | |
437 | .scan_in(reg_rd_ovfl_scanin), | |
438 | .scan_out(reg_rd_ovfl_scanout), | |
439 | .dout(rd_ovfl_r), | |
440 | .l1clk(l1clk), | |
441 | .din(rd_ovfl_l), | |
442 | .siclk(siclk), | |
443 | .soclk(soclk) | |
444 | ); | |
445 | ||
446 | sii_inc_ctlmsff_ctl_macro__width_1 reg_got_gnt // ASYNC reset active low | |
447 | ( | |
448 | .scan_in(reg_got_gnt_scanin), | |
449 | .scan_out(reg_got_gnt_scanout), | |
450 | .dout(got_gnt_r), | |
451 | .l1clk(l1clk), | |
452 | .din(got_gnt_l), | |
453 | .siclk(siclk), | |
454 | .soclk(soclk) | |
455 | ); | |
456 | ||
457 | sii_inc_ctlmsff_ctl_macro__width_1 reg_cmp_io_syn_en // ASYNC reset active low | |
458 | ( | |
459 | .scan_in(reg_cmp_io_syn_en_scanin), | |
460 | .scan_out(reg_cmp_io_syn_en_scanout), | |
461 | .dout(cmp_io_sync_en_dly), | |
462 | .l1clk(l1clk), | |
463 | // .en(cmp_io_sync_en), | |
464 | .din(cstate[`GNT]), | |
465 | .siclk(siclk), | |
466 | .soclk(soclk) | |
467 | ); | |
468 | ||
469 | sii_inc_ctlmsff_ctl_macro__width_1 reg_cmp_io_syn_en_dly2 // ASYNC reset active low | |
470 | ( | |
471 | .scan_in(reg_cmp_io_syn_en_dly2_scanin), | |
472 | .scan_out(reg_cmp_io_syn_en_dly2_scanout), | |
473 | .dout(cmp_io_sync_en_dly2), | |
474 | .l1clk(l1clk), | |
475 | .din(cmp_io_sync_en_dly), | |
476 | .siclk(siclk), | |
477 | .soclk(soclk) | |
478 | ); | |
479 | ||
480 | sii_inc_ctlmsff_ctl_macro__width_1 reg_cmp_io_syn_en_dly3 // ASYNC reset active low | |
481 | ( | |
482 | .scan_in(reg_cmp_io_syn_en_dly3_scanin), | |
483 | .scan_out(reg_cmp_io_syn_en_dly3_scanout), | |
484 | .dout(cmp_io_sync_en_dly3), | |
485 | .l1clk(l1clk), | |
486 | .din(cmp_io_sync_en_dly2), | |
487 | .siclk(siclk), | |
488 | .soclk(soclk) | |
489 | ); | |
490 | ||
491 | sii_inc_ctlmsff_ctl_macro__en_1__width_1 reg_ncu_sii_gnt // ASYNC reset active low | |
492 | ( | |
493 | .scan_in(reg_ncu_sii_gnt_scanin), | |
494 | .scan_out(reg_ncu_sii_gnt_scanout), | |
495 | .dout(ncu_sii_gnt_r), | |
496 | .l1clk(l1clk), | |
497 | .en (io_cmp_sync_en), | |
498 | .din(ncu_sii_gnt), | |
499 | .siclk(siclk), | |
500 | .soclk(soclk) | |
501 | ); | |
502 | ||
503 | //msff_ctl_macro reg_ind_fifo_empty (width=1) // ASYNC reset active low | |
504 | // ( | |
505 | // .scan_in(reg_ind_fifo_empty_scanin), | |
506 | // .scan_out(reg_ind_fifo_empty_scanout), | |
507 | // .dout(ind_fifo_empty_r), | |
508 | // .l1clk(l1clk), | |
509 | // .din(ind_fifo_empty), | |
510 | // ); | |
511 | ||
512 | ||
513 | sii_inc_ctlmsff_ctl_macro__width_3 reg_cyc_cnt_r // ASYNC reset active low | |
514 | ( | |
515 | .scan_in(reg_cyc_cnt_r_scanin), | |
516 | .scan_out(reg_cyc_cnt_r_scanout), | |
517 | .dout(cyc_cnt_r[2:0]), | |
518 | .l1clk(l1clk), | |
519 | .din(cyc_cnt_l[2:0]), | |
520 | .siclk(siclk), | |
521 | .soclk(soclk) | |
522 | ); | |
523 | ||
524 | sii_inc_ctlmsff_ctl_macro__width_6 reg_inc_indq_rd_addr // ASYNC reset active low | |
525 | ( | |
526 | .scan_in(reg_inc_indq_rd_addr_scanin), | |
527 | .scan_out(reg_inc_indq_rd_addr_scanout), | |
528 | .dout(inc_indq_rd_addr_r[5:0]), | |
529 | .l1clk(l1clk), | |
530 | .din(inc_indq_rd_addr[5:0]), | |
531 | .siclk(siclk), | |
532 | .soclk(soclk) | |
533 | ); | |
534 | ||
535 | ||
536 | sii_inc_ctlmsff_ctl_macro__en_1__width_1 reg_sii_ncu_req // ASYNC reset active low | |
537 | ( | |
538 | .scan_in(reg_sii_ncu_req_scanin), | |
539 | .scan_out(reg_sii_ncu_req_scanout), | |
540 | .dout(sii_ncu_req), | |
541 | .l1clk(l1clk), | |
542 | .en(cmp_io_sync_en), | |
543 | .din(sii_ncu_req_l), | |
544 | .siclk(siclk), | |
545 | .soclk(soclk) | |
546 | ); | |
547 | ||
548 | sii_inc_ctlmsff_ctl_macro__en_1__width_32 reg_sii_ncu_data // ASYNC reset active low | |
549 | ( | |
550 | .scan_in(reg_sii_ncu_data_scanin), | |
551 | .scan_out(reg_sii_ncu_data_scanout), | |
552 | .dout(sii_ncu_data[31:0]), | |
553 | .l1clk(l1clk), | |
554 | .en(cmp_io_sync_en), | |
555 | .din(sii_ncu_data_l[31:0]), | |
556 | .siclk(siclk), | |
557 | .soclk(soclk) | |
558 | ); | |
559 | ||
560 | sii_inc_ctlmsff_ctl_macro__en_1__width_2 reg_sii_ncu_dparity // ASYNC reset active low | |
561 | ( | |
562 | .scan_in(reg_sii_ncu_dparity_scanin), | |
563 | .scan_out(reg_sii_ncu_dparity_scanout), | |
564 | .dout(sii_ncu_dparity[1:0]), | |
565 | .l1clk(l1clk), | |
566 | .en(cmp_io_sync_en), | |
567 | .din(sii_ncu_dparity_l[1:0]), | |
568 | .siclk(siclk), | |
569 | .soclk(soclk) | |
570 | ); | |
571 | ||
572 | sii_inc_ctlmsff_ctl_macro__width_1 reg_cmp_io_sync_en // ASYNC reset active low | |
573 | ( | |
574 | .scan_in(reg_cmp_io_sync_en_scanin), | |
575 | .scan_out(reg_cmp_io_sync_en_scanout), | |
576 | .dout(cmp_io_sync_en), | |
577 | .l1clk(l1clk), | |
578 | .din(cmp_io_sync_en_in), | |
579 | .siclk(siclk), | |
580 | .soclk(soclk) | |
581 | ); | |
582 | ||
583 | sii_inc_ctlmsff_ctl_macro__width_1 reg_io_cmp_sync_en // ASYNC reset active low | |
584 | ( | |
585 | .scan_in(reg_io_cmp_sync_en_scanin), | |
586 | .scan_out(reg_io_cmp_sync_en_scanout), | |
587 | .dout(io_cmp_sync_en), | |
588 | .l1clk(l1clk), | |
589 | .din(io_cmp_sync_en_in), | |
590 | .siclk(siclk), | |
591 | .soclk(soclk) | |
592 | ); | |
593 | ||
594 | sii_inc_ctlmsff_ctl_macro__width_1 reg_sii_mb0_run // ASYNC reset active low | |
595 | ( | |
596 | .scan_in(reg_sii_mb0_run_scanin), | |
597 | .scan_out(reg_sii_mb0_run_scanout), | |
598 | .dout(sii_mb0_run_r), | |
599 | .l1clk(l1clk), | |
600 | .din(sii_mb0_run), | |
601 | .siclk(siclk), | |
602 | .soclk(soclk) | |
603 | ); | |
604 | ||
605 | sii_inc_ctlmsff_ctl_macro__width_1 reg_sii_mb0_ind_rd_en // ASYNC reset active low | |
606 | ( | |
607 | .scan_in(reg_sii_mb0_ind_rd_en_scanin), | |
608 | .scan_out(reg_sii_mb0_ind_rd_en_scanout), | |
609 | .dout(sii_mb0_ind_rd_en_r), | |
610 | .l1clk(l1clk), | |
611 | .din(sii_mb0_ind_rd_en), | |
612 | .siclk(siclk), | |
613 | .soclk(soclk) | |
614 | ); | |
615 | ||
616 | sii_inc_ctlmsff_ctl_macro__width_6 reg_sii_mb0_addr // ASYNC reset active low | |
617 | ( | |
618 | .scan_in(reg_sii_mb0_addr_scanin), | |
619 | .scan_out(reg_sii_mb0_addr_scanout), | |
620 | .dout(sii_mb0_addr_r[5:0]), | |
621 | .l1clk(l1clk), | |
622 | .din(sii_mb0_addr[5:0]), | |
623 | .siclk(siclk), | |
624 | .soclk(soclk) | |
625 | ); | |
626 | ||
627 | sii_inc_ctlmsff_ctl_macro__width_8 reg_sii_mb0_wdata // ASYNC reset active low | |
628 | ( | |
629 | .scan_in(reg_sii_mb0_wdata_scanin), | |
630 | .scan_out(reg_sii_mb0_wdata_scanout), | |
631 | .dout(sii_mb0_wdata_r[7:0]), | |
632 | .l1clk(l1clk), | |
633 | .din(sii_mb0_wdata[7:0]), | |
634 | .siclk(siclk), | |
635 | .soclk(soclk) | |
636 | ); | |
637 | ||
638 | sii_inc_ctlmsff_ctl_macro__width_1 reg_ind_fifo_full // ASYNC reset active low | |
639 | ( | |
640 | .scan_in(reg_ind_fifo_full_scanin), | |
641 | .scan_out(reg_ind_fifo_full_scanout), | |
642 | .dout(ind_fifo_full), | |
643 | .l1clk(l1clk), | |
644 | .din(ind_fifo_full_l), | |
645 | .siclk(siclk), | |
646 | .soclk(soclk) | |
647 | ); | |
648 | ||
649 | // fixscan start: | |
650 | assign spares_scanin = scan_in ; | |
651 | assign reg_cstate_scanin = spares_scanout ; | |
652 | assign reg_sii_mb0_ind_fail_scanin = reg_cstate_scanout ; | |
653 | assign reg_mbist1_data_rr_scanin = reg_sii_mb0_ind_fail_scanout; | |
654 | assign reg_mbist1_data_r_scanin = reg_mbist1_data_rr_scanout; | |
655 | assign reg_rd_ovfl_scanin = reg_mbist1_data_r_scanout; | |
656 | assign reg_got_gnt_scanin = reg_rd_ovfl_scanout ; | |
657 | assign reg_cmp_io_syn_en_scanin = reg_got_gnt_scanout ; | |
658 | assign reg_cmp_io_syn_en_dly2_scanin = reg_cmp_io_syn_en_scanout; | |
659 | assign reg_cmp_io_syn_en_dly3_scanin = reg_cmp_io_syn_en_dly2_scanout; | |
660 | assign reg_ncu_sii_gnt_scanin = reg_cmp_io_syn_en_dly3_scanout; | |
661 | assign reg_cyc_cnt_r_scanin = reg_ncu_sii_gnt_scanout ; | |
662 | assign reg_inc_indq_rd_addr_scanin = reg_cyc_cnt_r_scanout ; | |
663 | assign reg_sii_ncu_req_scanin = reg_inc_indq_rd_addr_scanout; | |
664 | assign reg_sii_ncu_data_scanin = reg_sii_ncu_req_scanout ; | |
665 | assign reg_sii_ncu_dparity_scanin = reg_sii_ncu_data_scanout ; | |
666 | assign reg_cmp_io_sync_en_scanin = reg_sii_ncu_dparity_scanout; | |
667 | assign reg_io_cmp_sync_en_scanin = reg_cmp_io_sync_en_scanout; | |
668 | assign reg_sii_mb0_run_scanin = reg_io_cmp_sync_en_scanout; | |
669 | assign reg_sii_mb0_ind_rd_en_scanin = reg_sii_mb0_run_scanout ; | |
670 | assign reg_sii_mb0_addr_scanin = reg_sii_mb0_ind_rd_en_scanout; | |
671 | assign reg_sii_mb0_wdata_scanin = reg_sii_mb0_addr_scanout ; | |
672 | assign reg_ind_fifo_full_scanin = reg_sii_mb0_wdata_scanout; | |
673 | assign scan_out = reg_ind_fifo_full_scanout; | |
674 | // fixscan end: | |
675 | endmodule | |
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | // any PARAMS parms go into naming of macro | |
683 | ||
684 | module sii_inc_ctll1clkhdr_ctl_macro ( | |
685 | l2clk, | |
686 | l1en, | |
687 | pce_ov, | |
688 | stop, | |
689 | se, | |
690 | l1clk); | |
691 | ||
692 | ||
693 | input l2clk; | |
694 | input l1en; | |
695 | input pce_ov; | |
696 | input stop; | |
697 | input se; | |
698 | output l1clk; | |
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | cl_sc1_l1hdr_8x c_0 ( | |
705 | ||
706 | ||
707 | .l2clk(l2clk), | |
708 | .pce(l1en), | |
709 | .l1clk(l1clk), | |
710 | .se(se), | |
711 | .pce_ov(pce_ov), | |
712 | .stop(stop) | |
713 | ); | |
714 | ||
715 | ||
716 | ||
717 | endmodule | |
718 | ||
719 | ||
720 | ||
721 | ||
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | // Description: Spare gate macro for control blocks | |
728 | // | |
729 | // Param num controls the number of times the macro is added | |
730 | // flops=0 can be used to use only combination spare logic | |
731 | ||
732 | ||
733 | module sii_inc_ctlspare_ctl_macro__num_2 ( | |
734 | l1clk, | |
735 | scan_in, | |
736 | siclk, | |
737 | soclk, | |
738 | scan_out); | |
739 | wire si_0; | |
740 | wire so_0; | |
741 | wire spare0_flop_unused; | |
742 | wire spare0_buf_32x_unused; | |
743 | wire spare0_nand3_8x_unused; | |
744 | wire spare0_inv_8x_unused; | |
745 | wire spare0_aoi22_4x_unused; | |
746 | wire spare0_buf_8x_unused; | |
747 | wire spare0_oai22_4x_unused; | |
748 | wire spare0_inv_16x_unused; | |
749 | wire spare0_nand2_16x_unused; | |
750 | wire spare0_nor3_4x_unused; | |
751 | wire spare0_nand2_8x_unused; | |
752 | wire spare0_buf_16x_unused; | |
753 | wire spare0_nor2_16x_unused; | |
754 | wire spare0_inv_32x_unused; | |
755 | wire si_1; | |
756 | wire so_1; | |
757 | wire spare1_flop_unused; | |
758 | wire spare1_buf_32x_unused; | |
759 | wire spare1_nand3_8x_unused; | |
760 | wire spare1_inv_8x_unused; | |
761 | wire spare1_aoi22_4x_unused; | |
762 | wire spare1_buf_8x_unused; | |
763 | wire spare1_oai22_4x_unused; | |
764 | wire spare1_inv_16x_unused; | |
765 | wire spare1_nand2_16x_unused; | |
766 | wire spare1_nor3_4x_unused; | |
767 | wire spare1_nand2_8x_unused; | |
768 | wire spare1_buf_16x_unused; | |
769 | wire spare1_nor2_16x_unused; | |
770 | wire spare1_inv_32x_unused; | |
771 | ||
772 | ||
773 | input l1clk; | |
774 | input scan_in; | |
775 | input siclk; | |
776 | input soclk; | |
777 | output scan_out; | |
778 | ||
779 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
780 | .siclk(siclk), | |
781 | .soclk(soclk), | |
782 | .si(si_0), | |
783 | .so(so_0), | |
784 | .d(1'b0), | |
785 | .q(spare0_flop_unused)); | |
786 | assign si_0 = scan_in; | |
787 | ||
788 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
789 | .out(spare0_buf_32x_unused)); | |
790 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
791 | .in1(1'b1), | |
792 | .in2(1'b1), | |
793 | .out(spare0_nand3_8x_unused)); | |
794 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
795 | .out(spare0_inv_8x_unused)); | |
796 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
797 | .in01(1'b1), | |
798 | .in10(1'b1), | |
799 | .in11(1'b1), | |
800 | .out(spare0_aoi22_4x_unused)); | |
801 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
802 | .out(spare0_buf_8x_unused)); | |
803 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
804 | .in01(1'b1), | |
805 | .in10(1'b1), | |
806 | .in11(1'b1), | |
807 | .out(spare0_oai22_4x_unused)); | |
808 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
809 | .out(spare0_inv_16x_unused)); | |
810 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
811 | .in1(1'b1), | |
812 | .out(spare0_nand2_16x_unused)); | |
813 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
814 | .in1(1'b0), | |
815 | .in2(1'b0), | |
816 | .out(spare0_nor3_4x_unused)); | |
817 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
818 | .in1(1'b1), | |
819 | .out(spare0_nand2_8x_unused)); | |
820 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
821 | .out(spare0_buf_16x_unused)); | |
822 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
823 | .in1(1'b0), | |
824 | .out(spare0_nor2_16x_unused)); | |
825 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
826 | .out(spare0_inv_32x_unused)); | |
827 | ||
828 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
829 | .siclk(siclk), | |
830 | .soclk(soclk), | |
831 | .si(si_1), | |
832 | .so(so_1), | |
833 | .d(1'b0), | |
834 | .q(spare1_flop_unused)); | |
835 | assign si_1 = so_0; | |
836 | ||
837 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
838 | .out(spare1_buf_32x_unused)); | |
839 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
840 | .in1(1'b1), | |
841 | .in2(1'b1), | |
842 | .out(spare1_nand3_8x_unused)); | |
843 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
844 | .out(spare1_inv_8x_unused)); | |
845 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
846 | .in01(1'b1), | |
847 | .in10(1'b1), | |
848 | .in11(1'b1), | |
849 | .out(spare1_aoi22_4x_unused)); | |
850 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
851 | .out(spare1_buf_8x_unused)); | |
852 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
853 | .in01(1'b1), | |
854 | .in10(1'b1), | |
855 | .in11(1'b1), | |
856 | .out(spare1_oai22_4x_unused)); | |
857 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
858 | .out(spare1_inv_16x_unused)); | |
859 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
860 | .in1(1'b1), | |
861 | .out(spare1_nand2_16x_unused)); | |
862 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
863 | .in1(1'b0), | |
864 | .in2(1'b0), | |
865 | .out(spare1_nor3_4x_unused)); | |
866 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
867 | .in1(1'b1), | |
868 | .out(spare1_nand2_8x_unused)); | |
869 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
870 | .out(spare1_buf_16x_unused)); | |
871 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
872 | .in1(1'b0), | |
873 | .out(spare1_nor2_16x_unused)); | |
874 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
875 | .out(spare1_inv_32x_unused)); | |
876 | assign scan_out = so_1; | |
877 | ||
878 | ||
879 | ||
880 | endmodule | |
881 | ||
882 | ||
883 | ||
884 | ||
885 | ||
886 | ||
887 | // any PARAMS parms go into naming of macro | |
888 | ||
889 | module sii_inc_ctlmsff_ctl_macro__width_5 ( | |
890 | din, | |
891 | l1clk, | |
892 | scan_in, | |
893 | siclk, | |
894 | soclk, | |
895 | dout, | |
896 | scan_out); | |
897 | wire [4:0] fdin; | |
898 | wire [3:0] so; | |
899 | ||
900 | input [4:0] din; | |
901 | input l1clk; | |
902 | input scan_in; | |
903 | ||
904 | ||
905 | input siclk; | |
906 | input soclk; | |
907 | ||
908 | output [4:0] dout; | |
909 | output scan_out; | |
910 | assign fdin[4:0] = din[4:0]; | |
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | ||
917 | dff #(5) d0_0 ( | |
918 | .l1clk(l1clk), | |
919 | .siclk(siclk), | |
920 | .soclk(soclk), | |
921 | .d(fdin[4:0]), | |
922 | .si({scan_in,so[3:0]}), | |
923 | .so({so[3:0],scan_out}), | |
924 | .q(dout[4:0]) | |
925 | ); | |
926 | ||
927 | ||
928 | ||
929 | ||
930 | ||
931 | ||
932 | ||
933 | ||
934 | ||
935 | ||
936 | ||
937 | ||
938 | endmodule | |
939 | ||
940 | ||
941 | ||
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | ||
949 | ||
950 | ||
951 | ||
952 | // any PARAMS parms go into naming of macro | |
953 | ||
954 | module sii_inc_ctlmsff_ctl_macro__width_2 ( | |
955 | din, | |
956 | l1clk, | |
957 | scan_in, | |
958 | siclk, | |
959 | soclk, | |
960 | dout, | |
961 | scan_out); | |
962 | wire [1:0] fdin; | |
963 | wire [0:0] so; | |
964 | ||
965 | input [1:0] din; | |
966 | input l1clk; | |
967 | input scan_in; | |
968 | ||
969 | ||
970 | input siclk; | |
971 | input soclk; | |
972 | ||
973 | output [1:0] dout; | |
974 | output scan_out; | |
975 | assign fdin[1:0] = din[1:0]; | |
976 | ||
977 | ||
978 | ||
979 | ||
980 | ||
981 | ||
982 | dff #(2) d0_0 ( | |
983 | .l1clk(l1clk), | |
984 | .siclk(siclk), | |
985 | .soclk(soclk), | |
986 | .d(fdin[1:0]), | |
987 | .si({scan_in,so[0:0]}), | |
988 | .so({so[0:0],scan_out}), | |
989 | .q(dout[1:0]) | |
990 | ); | |
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | ||
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | endmodule | |
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | // any PARAMS parms go into naming of macro | |
1018 | ||
1019 | module sii_inc_ctlmsff_ctl_macro__width_68 ( | |
1020 | din, | |
1021 | l1clk, | |
1022 | scan_in, | |
1023 | siclk, | |
1024 | soclk, | |
1025 | dout, | |
1026 | scan_out); | |
1027 | wire [67:0] fdin; | |
1028 | wire [66:0] so; | |
1029 | ||
1030 | input [67:0] din; | |
1031 | input l1clk; | |
1032 | input scan_in; | |
1033 | ||
1034 | ||
1035 | input siclk; | |
1036 | input soclk; | |
1037 | ||
1038 | output [67:0] dout; | |
1039 | output scan_out; | |
1040 | assign fdin[67:0] = din[67:0]; | |
1041 | ||
1042 | ||
1043 | ||
1044 | ||
1045 | ||
1046 | ||
1047 | dff #(68) d0_0 ( | |
1048 | .l1clk(l1clk), | |
1049 | .siclk(siclk), | |
1050 | .soclk(soclk), | |
1051 | .d(fdin[67:0]), | |
1052 | .si({scan_in,so[66:0]}), | |
1053 | .so({so[66:0],scan_out}), | |
1054 | .q(dout[67:0]) | |
1055 | ); | |
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | endmodule | |
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | // any PARAMS parms go into naming of macro | |
1083 | ||
1084 | module sii_inc_ctlmsff_ctl_macro__width_1 ( | |
1085 | din, | |
1086 | l1clk, | |
1087 | scan_in, | |
1088 | siclk, | |
1089 | soclk, | |
1090 | dout, | |
1091 | scan_out); | |
1092 | wire [0:0] fdin; | |
1093 | ||
1094 | input [0:0] din; | |
1095 | input l1clk; | |
1096 | input scan_in; | |
1097 | ||
1098 | ||
1099 | input siclk; | |
1100 | input soclk; | |
1101 | ||
1102 | output [0:0] dout; | |
1103 | output scan_out; | |
1104 | assign fdin[0:0] = din[0:0]; | |
1105 | ||
1106 | ||
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | dff #(1) d0_0 ( | |
1112 | .l1clk(l1clk), | |
1113 | .siclk(siclk), | |
1114 | .soclk(soclk), | |
1115 | .d(fdin[0:0]), | |
1116 | .si(scan_in), | |
1117 | .so(scan_out), | |
1118 | .q(dout[0:0]) | |
1119 | ); | |
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | endmodule | |
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 | ||
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | // any PARAMS parms go into naming of macro | |
1147 | ||
1148 | module sii_inc_ctlmsff_ctl_macro__en_1__width_1 ( | |
1149 | din, | |
1150 | en, | |
1151 | l1clk, | |
1152 | scan_in, | |
1153 | siclk, | |
1154 | soclk, | |
1155 | dout, | |
1156 | scan_out); | |
1157 | wire [0:0] fdin; | |
1158 | ||
1159 | input [0:0] din; | |
1160 | input en; | |
1161 | input l1clk; | |
1162 | input scan_in; | |
1163 | ||
1164 | ||
1165 | input siclk; | |
1166 | input soclk; | |
1167 | ||
1168 | output [0:0] dout; | |
1169 | output scan_out; | |
1170 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1171 | ||
1172 | ||
1173 | ||
1174 | ||
1175 | ||
1176 | ||
1177 | dff #(1) d0_0 ( | |
1178 | .l1clk(l1clk), | |
1179 | .siclk(siclk), | |
1180 | .soclk(soclk), | |
1181 | .d(fdin[0:0]), | |
1182 | .si(scan_in), | |
1183 | .so(scan_out), | |
1184 | .q(dout[0:0]) | |
1185 | ); | |
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | ||
1191 | ||
1192 | ||
1193 | ||
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | endmodule | |
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | // any PARAMS parms go into naming of macro | |
1213 | ||
1214 | module sii_inc_ctlmsff_ctl_macro__width_3 ( | |
1215 | din, | |
1216 | l1clk, | |
1217 | scan_in, | |
1218 | siclk, | |
1219 | soclk, | |
1220 | dout, | |
1221 | scan_out); | |
1222 | wire [2:0] fdin; | |
1223 | wire [1:0] so; | |
1224 | ||
1225 | input [2:0] din; | |
1226 | input l1clk; | |
1227 | input scan_in; | |
1228 | ||
1229 | ||
1230 | input siclk; | |
1231 | input soclk; | |
1232 | ||
1233 | output [2:0] dout; | |
1234 | output scan_out; | |
1235 | assign fdin[2:0] = din[2:0]; | |
1236 | ||
1237 | ||
1238 | ||
1239 | ||
1240 | ||
1241 | ||
1242 | dff #(3) d0_0 ( | |
1243 | .l1clk(l1clk), | |
1244 | .siclk(siclk), | |
1245 | .soclk(soclk), | |
1246 | .d(fdin[2:0]), | |
1247 | .si({scan_in,so[1:0]}), | |
1248 | .so({so[1:0],scan_out}), | |
1249 | .q(dout[2:0]) | |
1250 | ); | |
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | endmodule | |
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | // any PARAMS parms go into naming of macro | |
1278 | ||
1279 | module sii_inc_ctlmsff_ctl_macro__width_6 ( | |
1280 | din, | |
1281 | l1clk, | |
1282 | scan_in, | |
1283 | siclk, | |
1284 | soclk, | |
1285 | dout, | |
1286 | scan_out); | |
1287 | wire [5:0] fdin; | |
1288 | wire [4:0] so; | |
1289 | ||
1290 | input [5:0] din; | |
1291 | input l1clk; | |
1292 | input scan_in; | |
1293 | ||
1294 | ||
1295 | input siclk; | |
1296 | input soclk; | |
1297 | ||
1298 | output [5:0] dout; | |
1299 | output scan_out; | |
1300 | assign fdin[5:0] = din[5:0]; | |
1301 | ||
1302 | ||
1303 | ||
1304 | ||
1305 | ||
1306 | ||
1307 | dff #(6) d0_0 ( | |
1308 | .l1clk(l1clk), | |
1309 | .siclk(siclk), | |
1310 | .soclk(soclk), | |
1311 | .d(fdin[5:0]), | |
1312 | .si({scan_in,so[4:0]}), | |
1313 | .so({so[4:0],scan_out}), | |
1314 | .q(dout[5:0]) | |
1315 | ); | |
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | endmodule | |
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | // any PARAMS parms go into naming of macro | |
1343 | ||
1344 | module sii_inc_ctlmsff_ctl_macro__en_1__width_32 ( | |
1345 | din, | |
1346 | en, | |
1347 | l1clk, | |
1348 | scan_in, | |
1349 | siclk, | |
1350 | soclk, | |
1351 | dout, | |
1352 | scan_out); | |
1353 | wire [31:0] fdin; | |
1354 | wire [30:0] so; | |
1355 | ||
1356 | input [31:0] din; | |
1357 | input en; | |
1358 | input l1clk; | |
1359 | input scan_in; | |
1360 | ||
1361 | ||
1362 | input siclk; | |
1363 | input soclk; | |
1364 | ||
1365 | output [31:0] dout; | |
1366 | output scan_out; | |
1367 | assign fdin[31:0] = (din[31:0] & {32{en}}) | (dout[31:0] & ~{32{en}}); | |
1368 | ||
1369 | ||
1370 | ||
1371 | ||
1372 | ||
1373 | ||
1374 | dff #(32) d0_0 ( | |
1375 | .l1clk(l1clk), | |
1376 | .siclk(siclk), | |
1377 | .soclk(soclk), | |
1378 | .d(fdin[31:0]), | |
1379 | .si({scan_in,so[30:0]}), | |
1380 | .so({so[30:0],scan_out}), | |
1381 | .q(dout[31:0]) | |
1382 | ); | |
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | endmodule | |
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | // any PARAMS parms go into naming of macro | |
1410 | ||
1411 | module sii_inc_ctlmsff_ctl_macro__en_1__width_2 ( | |
1412 | din, | |
1413 | en, | |
1414 | l1clk, | |
1415 | scan_in, | |
1416 | siclk, | |
1417 | soclk, | |
1418 | dout, | |
1419 | scan_out); | |
1420 | wire [1:0] fdin; | |
1421 | wire [0:0] so; | |
1422 | ||
1423 | input [1:0] din; | |
1424 | input en; | |
1425 | input l1clk; | |
1426 | input scan_in; | |
1427 | ||
1428 | ||
1429 | input siclk; | |
1430 | input soclk; | |
1431 | ||
1432 | output [1:0] dout; | |
1433 | output scan_out; | |
1434 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | ||
1440 | ||
1441 | dff #(2) d0_0 ( | |
1442 | .l1clk(l1clk), | |
1443 | .siclk(siclk), | |
1444 | .soclk(soclk), | |
1445 | .d(fdin[1:0]), | |
1446 | .si({scan_in,so[0:0]}), | |
1447 | .so({so[0:0],scan_out}), | |
1448 | .q(dout[1:0]) | |
1449 | ); | |
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | endmodule | |
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | ||
1476 | // any PARAMS parms go into naming of macro | |
1477 | ||
1478 | module sii_inc_ctlmsff_ctl_macro__width_8 ( | |
1479 | din, | |
1480 | l1clk, | |
1481 | scan_in, | |
1482 | siclk, | |
1483 | soclk, | |
1484 | dout, | |
1485 | scan_out); | |
1486 | wire [7:0] fdin; | |
1487 | wire [6:0] so; | |
1488 | ||
1489 | input [7:0] din; | |
1490 | input l1clk; | |
1491 | input scan_in; | |
1492 | ||
1493 | ||
1494 | input siclk; | |
1495 | input soclk; | |
1496 | ||
1497 | output [7:0] dout; | |
1498 | output scan_out; | |
1499 | assign fdin[7:0] = din[7:0]; | |
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | dff #(8) d0_0 ( | |
1507 | .l1clk(l1clk), | |
1508 | .siclk(siclk), | |
1509 | .soclk(soclk), | |
1510 | .d(fdin[7:0]), | |
1511 | .si({scan_in,so[6:0]}), | |
1512 | .so({so[6:0],scan_out}), | |
1513 | .q(dout[7:0]) | |
1514 | ); | |
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | endmodule | |
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 |