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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sio_opds_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sio_opds_dp ( | |
36 | opds_packet_data, | |
37 | opds_packet_parity, | |
38 | opddqx0_dout, | |
39 | opddqx1_dout, | |
40 | opddqx0_pout, | |
41 | opddqx1_pout, | |
42 | opdhqx_dout, | |
43 | opcs_new_opdhqx1, | |
44 | opcs_new_opdhqx0, | |
45 | ncu_sio_d_pei, | |
46 | opcs_opds_reloadhdr, | |
47 | opcs_opds_selhdr, | |
48 | sio_mb1_opdhq_sel, | |
49 | sio_mb1_opddq0_sel, | |
50 | sio_mb1_opddq1_sel, | |
51 | opds_read_data, | |
52 | sio_mb1_run, | |
53 | opcs_opddq0_rd_en, | |
54 | opcs_opddq1_rd_en, | |
55 | opcs_opdhq_rd_en, | |
56 | mb1_opddq0_rd_en, | |
57 | mb1_opddq1_rd_en, | |
58 | mb1_opdhq_rd_en, | |
59 | opds_opddq0_rd_en, | |
60 | opds_opddq1_rd_en, | |
61 | opds_opdhq_rd_en, | |
62 | opcs_opddq0_rd_addr, | |
63 | opcs_opddq1_rd_addr, | |
64 | opcs_opdhq_rd_addr, | |
65 | mb1_opddq0_rd_addr, | |
66 | mb1_opddq1_rd_addr, | |
67 | mb1_opdhq_rd_addr, | |
68 | opds_opddq0_rd_addr, | |
69 | opds_opddq1_rd_addr, | |
70 | opds_opdhq_rd_addr, | |
71 | parity_result, | |
72 | iol2clk, | |
73 | tcu_scan_en, | |
74 | scan_in, | |
75 | tcu_aclk, | |
76 | tcu_bclk, | |
77 | tcu_pce_ov, | |
78 | tcu_clk_stop, | |
79 | scan_out); | |
80 | wire se; | |
81 | wire siclk; | |
82 | wire soclk; | |
83 | wire pce_ov; | |
84 | wire stop; | |
85 | wire [63:0] opdhqx1_dout; | |
86 | wire [63:0] opdhqx0_dout; | |
87 | wire [63:0] packet_data0; | |
88 | wire [63:0] packet_data1; | |
89 | wire [7:0] packet_parity; | |
90 | wire ff_packet_data0_h_scanin; | |
91 | wire ff_packet_data0_h_scanout; | |
92 | wire [63:0] packet_data0_next; | |
93 | wire ff_packet_data0_l_scanin; | |
94 | wire ff_packet_data0_l_scanout; | |
95 | wire ff_packet_data1_h_scanin; | |
96 | wire ff_packet_data1_h_scanout; | |
97 | wire [63:0] packet_data1_next; | |
98 | wire ff_packet_data1_l_scanin; | |
99 | wire ff_packet_data1_l_scanout; | |
100 | wire [7:0] packet_parity_next; | |
101 | wire [3:0] packet_parity_next_buf; | |
102 | wire ff_packet_parity_scanin; | |
103 | wire ff_packet_parity_scanout; | |
104 | wire [63:0] opds_qx0_data; | |
105 | wire [63:0] opds_qx1_data; | |
106 | wire [3:0] opddqx0_pout_inv; | |
107 | wire [3:0] opddqx1_pout_inv; | |
108 | wire [3:0] pgenx0_; | |
109 | wire [3:0] pgenx1_; | |
110 | wire err_inj_lsb; | |
111 | wire [63:0] opds_qx0_rewired_data; | |
112 | wire [63:0] opds_qx1_rewired_data; | |
113 | wire ff_opdhqxout_scanin; | |
114 | wire ff_opdhqxout_scanout; | |
115 | wire [31:0] opdhqx_dout_reg; | |
116 | wire mbist_read_unused; | |
117 | ||
118 | ||
119 | output [127:0] opds_packet_data ; | |
120 | output [7:0] opds_packet_parity; | |
121 | ||
122 | input [63:0] opddqx0_dout; | |
123 | input [63:0] opddqx1_dout; | |
124 | input [7:0] opddqx0_pout; | |
125 | input [7:0] opddqx1_pout; | |
126 | input [31:0] opdhqx_dout; | |
127 | input [63:0] opcs_new_opdhqx1; | |
128 | input [63:0] opcs_new_opdhqx0; | |
129 | input ncu_sio_d_pei; | |
130 | ||
131 | input opcs_opds_reloadhdr; | |
132 | input opcs_opds_selhdr; | |
133 | ||
134 | // for mb1 | |
135 | input sio_mb1_opdhq_sel; | |
136 | input sio_mb1_opddq0_sel; | |
137 | input sio_mb1_opddq1_sel; | |
138 | output [71:0] opds_read_data; | |
139 | ||
140 | // for mb1 - mux between the rd_en, rd_addr | |
141 | input sio_mb1_run; | |
142 | input opcs_opddq0_rd_en; | |
143 | input opcs_opddq1_rd_en; | |
144 | input opcs_opdhq_rd_en; | |
145 | input mb1_opddq0_rd_en; | |
146 | input mb1_opddq1_rd_en; | |
147 | input mb1_opdhq_rd_en; | |
148 | output opds_opddq0_rd_en; | |
149 | output opds_opddq1_rd_en; | |
150 | output opds_opdhq_rd_en; | |
151 | ||
152 | input [5:0] opcs_opddq0_rd_addr; | |
153 | input [5:0] opcs_opddq1_rd_addr; | |
154 | input [3:0] opcs_opdhq_rd_addr; | |
155 | input [5:0] mb1_opddq0_rd_addr; | |
156 | input [5:0] mb1_opddq1_rd_addr; | |
157 | input [3:0] mb1_opdhq_rd_addr; | |
158 | output [5:0] opds_opddq0_rd_addr; | |
159 | output [5:0] opds_opddq1_rd_addr; | |
160 | output [3:0] opds_opdhq_rd_addr; | |
161 | output [7:0] parity_result; | |
162 | ||
163 | input iol2clk; | |
164 | input tcu_scan_en; | |
165 | input scan_in; | |
166 | input tcu_aclk; | |
167 | input tcu_bclk; | |
168 | input tcu_pce_ov; | |
169 | input tcu_clk_stop; | |
170 | output scan_out; | |
171 | ||
172 | // scan renames | |
173 | assign se = tcu_scan_en; | |
174 | assign siclk = tcu_aclk; | |
175 | assign soclk = tcu_bclk; | |
176 | assign pce_ov = tcu_pce_ov; | |
177 | assign stop = tcu_clk_stop; | |
178 | // end scan | |
179 | ||
180 | // header format SIO->IO: | |
181 | // [127:122] : Command | |
182 | // 127=Response bit | |
183 | // 126=Posted bit | |
184 | // 125=Read bit | |
185 | // 124=WriteByteMask Active | |
186 | // 123=L2 bit | |
187 | // 122=IOB bit | |
188 | // [121:84] Reserved | |
189 | // [83:83] Reserved | |
190 | // [82:82] Reserved | |
191 | // [81:81] Unmapped Address Error -- will never happen | |
192 | // [80:80] Uncorrectable Error | |
193 | // [79:64] ID[15:0] | |
194 | // [63:62] Reserved | |
195 | // [61:56] CtagEcc[5:0] | |
196 | // [55: 0] Reserved | |
197 | ||
198 | ||
199 | assign opdhqx1_dout[63:0] = opcs_new_opdhqx1[63:0]; | |
200 | assign opdhqx0_dout[63:0] = opcs_new_opdhqx0[63:0]; | |
201 | ||
202 | assign opds_packet_data[127:0] = {packet_data0[63:0], packet_data1[63:0]}; | |
203 | ||
204 | assign opds_packet_parity[7:0] = {packet_parity[7], packet_parity[6], packet_parity[5], packet_parity[4], | |
205 | packet_parity[3], packet_parity[2], packet_parity[1], packet_parity[0]}; | |
206 | ||
207 | sio_opds_dp_msff_macro__stack_32l__width_32 ff_packet_data0_h ( | |
208 | .scan_in(ff_packet_data0_h_scanin), | |
209 | .scan_out(ff_packet_data0_h_scanout), | |
210 | .clk (iol2clk), | |
211 | .din (packet_data0_next[63:32]), | |
212 | .dout (packet_data0[63:32]), | |
213 | .en (1'b1), | |
214 | .se(se), | |
215 | .siclk(siclk), | |
216 | .soclk(soclk), | |
217 | .pce_ov(pce_ov), | |
218 | .stop(stop) | |
219 | ); | |
220 | ||
221 | sio_opds_dp_msff_macro__stack_32l__width_32 ff_packet_data0_l ( | |
222 | .scan_in(ff_packet_data0_l_scanin), | |
223 | .scan_out(ff_packet_data0_l_scanout), | |
224 | .clk (iol2clk), | |
225 | .din (packet_data0_next[31:0]), | |
226 | .dout (packet_data0[31:0]), | |
227 | .en (1'b1), | |
228 | .se(se), | |
229 | .siclk(siclk), | |
230 | .soclk(soclk), | |
231 | .pce_ov(pce_ov), | |
232 | .stop(stop) | |
233 | ); | |
234 | ||
235 | ||
236 | sio_opds_dp_msff_macro__stack_32l__width_32 ff_packet_data1_h ( | |
237 | .scan_in(ff_packet_data1_h_scanin), | |
238 | .scan_out(ff_packet_data1_h_scanout), | |
239 | .clk (iol2clk), | |
240 | .din (packet_data1_next[63:32]), | |
241 | .dout (packet_data1[63:32]), | |
242 | .en (1'b1), | |
243 | .se(se), | |
244 | .siclk(siclk), | |
245 | .soclk(soclk), | |
246 | .pce_ov(pce_ov), | |
247 | .stop(stop) | |
248 | ); | |
249 | ||
250 | sio_opds_dp_msff_macro__stack_32l__width_32 ff_packet_data1_l ( | |
251 | .scan_in(ff_packet_data1_l_scanin), | |
252 | .scan_out(ff_packet_data1_l_scanout), | |
253 | .clk (iol2clk), | |
254 | .din (packet_data1_next[31:0]), | |
255 | .dout (packet_data1[31:0]), | |
256 | .en (1'b1), | |
257 | .se(se), | |
258 | .siclk(siclk), | |
259 | .soclk(soclk), | |
260 | .pce_ov(pce_ov), | |
261 | .stop(stop) | |
262 | ); | |
263 | ||
264 | sio_opds_dp_buff_macro__minbuff_1__stack_4l__width_4 buf_packet_parity ( | |
265 | .din (packet_parity_next[3:0]), | |
266 | .dout (packet_parity_next_buf[3:0]) | |
267 | ); | |
268 | ||
269 | sio_opds_dp_msff_macro__left_32__stack_64c__width_8 ff_packet_parity ( | |
270 | .scan_in(ff_packet_parity_scanin), | |
271 | .scan_out(ff_packet_parity_scanout), | |
272 | .clk (iol2clk), | |
273 | .din ({packet_parity_next[7:4],packet_parity_next_buf[3:0]}), | |
274 | .dout (packet_parity[7:0]), | |
275 | .en (1'b1), | |
276 | .se(se), | |
277 | .siclk(siclk), | |
278 | .soclk(soclk), | |
279 | .pce_ov(pce_ov), | |
280 | .stop(stop) | |
281 | ); | |
282 | ||
283 | ||
284 | assign packet_data0_next[63:0] = opds_qx0_data[63:0]; | |
285 | assign packet_data1_next[63:0] = opds_qx1_data[63:0]; | |
286 | assign packet_parity_next[7:0] = {opddqx0_pout_inv[3:0], opddqx1_pout_inv[3:0]}; | |
287 | ||
288 | //assign packet_parity_next[7:0] = {pgenx0[3], pgenx0[2], pgenx0[1], pgenx0[0], | |
289 | // pgenx1[3], pgenx1[2], pgenx1[1], pgenx1[0]}; | |
290 | ||
291 | sio_opds_dp_xor_macro__ports_2__stack_8r__width_8 xor_compare ( | |
292 | .din0 ({opddqx0_pout[3:0],opddqx1_pout[3:0]}), | |
293 | .din1 ({pgenx0_[3:0], pgenx1_[3:0]}), | |
294 | .dout (parity_result[7:0]) | |
295 | ); | |
296 | ||
297 | ||
298 | sio_opds_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 mx21_opds_qx0_data ( | |
299 | .dout (opds_qx0_data[63:0]), | |
300 | .din0 ({opdhqx0_dout[63:0]}), | |
301 | .din1 ({opddqx0_dout[63:0]}), | |
302 | .sel0 (opcs_opds_selhdr) | |
303 | ); | |
304 | ||
305 | sio_opds_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 mx21_opds_qx1_data ( | |
306 | .dout (opds_qx1_data[63:0]), | |
307 | .din0 ({opdhqx1_dout[63:0]}), | |
308 | .din1 ({opddqx1_dout[63:1],err_inj_lsb}), | |
309 | .sel0 (opcs_opds_selhdr) | |
310 | ); | |
311 | ||
312 | sio_opds_dp_xor_macro__left_1__stack_4r__width_1 xor2_err_inj_lsb ( | |
313 | .din0 (opddqx1_dout[0]), | |
314 | .din1 (ncu_sio_d_pei), | |
315 | .dout (err_inj_lsb) | |
316 | ); | |
317 | ||
318 | ||
319 | ||
320 | // INTERLEAVED PARITY CODE | |
321 | // | |
322 | // pgenx | |
323 | ||
324 | assign opds_qx0_rewired_data[63:0] = { | |
325 | opds_qx0_data[63], opds_qx0_data[61], opds_qx0_data[59], opds_qx0_data[57], | |
326 | opds_qx0_data[55], opds_qx0_data[53], opds_qx0_data[51], opds_qx0_data[49], | |
327 | opds_qx0_data[47], opds_qx0_data[45], opds_qx0_data[43], opds_qx0_data[41], | |
328 | opds_qx0_data[39], opds_qx0_data[37], opds_qx0_data[35], opds_qx0_data[33], | |
329 | ||
330 | opds_qx0_data[62], opds_qx0_data[60], opds_qx0_data[58], opds_qx0_data[56], | |
331 | opds_qx0_data[54], opds_qx0_data[52], opds_qx0_data[50], opds_qx0_data[48], | |
332 | opds_qx0_data[46], opds_qx0_data[44], opds_qx0_data[42], opds_qx0_data[40], | |
333 | opds_qx0_data[38], opds_qx0_data[36], opds_qx0_data[34], opds_qx0_data[32], | |
334 | ||
335 | opds_qx0_data[31], opds_qx0_data[29], opds_qx0_data[27], opds_qx0_data[25], | |
336 | opds_qx0_data[23], opds_qx0_data[21], opds_qx0_data[19], opds_qx0_data[17], | |
337 | opds_qx0_data[15], opds_qx0_data[13], opds_qx0_data[11], opds_qx0_data[ 9], | |
338 | opds_qx0_data[ 7], opds_qx0_data[ 5], opds_qx0_data[ 3], opds_qx0_data[ 1], | |
339 | ||
340 | opds_qx0_data[30], opds_qx0_data[28], opds_qx0_data[26], opds_qx0_data[24], | |
341 | opds_qx0_data[22], opds_qx0_data[20], opds_qx0_data[18], opds_qx0_data[16], | |
342 | opds_qx0_data[14], opds_qx0_data[12], opds_qx0_data[10], opds_qx0_data[ 8], | |
343 | opds_qx0_data[ 6], opds_qx0_data[ 4], opds_qx0_data[ 2], opds_qx0_data[ 0] | |
344 | }; | |
345 | ||
346 | ||
347 | assign opds_qx1_rewired_data[63:0] = { | |
348 | opds_qx1_data[63], opds_qx1_data[61], opds_qx1_data[59], opds_qx1_data[57], | |
349 | opds_qx1_data[55], opds_qx1_data[53], opds_qx1_data[51], opds_qx1_data[49], | |
350 | opds_qx1_data[47], opds_qx1_data[45], opds_qx1_data[43], opds_qx1_data[41], | |
351 | opds_qx1_data[39], opds_qx1_data[37], opds_qx1_data[35], opds_qx1_data[33], | |
352 | ||
353 | opds_qx1_data[62], opds_qx1_data[60], opds_qx1_data[58], opds_qx1_data[56], | |
354 | opds_qx1_data[54], opds_qx1_data[52], opds_qx1_data[50], opds_qx1_data[48], | |
355 | opds_qx1_data[46], opds_qx1_data[44], opds_qx1_data[42], opds_qx1_data[40], | |
356 | opds_qx1_data[38], opds_qx1_data[36], opds_qx1_data[34], opds_qx1_data[32], | |
357 | ||
358 | opds_qx1_data[31], opds_qx1_data[29], opds_qx1_data[27], opds_qx1_data[25], | |
359 | opds_qx1_data[23], opds_qx1_data[21], opds_qx1_data[19], opds_qx1_data[17], | |
360 | opds_qx1_data[15], opds_qx1_data[13], opds_qx1_data[11], opds_qx1_data[ 9], | |
361 | opds_qx1_data[ 7], opds_qx1_data[ 5], opds_qx1_data[ 3], opds_qx1_data[ 1], | |
362 | ||
363 | opds_qx1_data[30], opds_qx1_data[28], opds_qx1_data[26], opds_qx1_data[24], | |
364 | opds_qx1_data[22], opds_qx1_data[20], opds_qx1_data[18], opds_qx1_data[16], | |
365 | opds_qx1_data[14], opds_qx1_data[12], opds_qx1_data[10], opds_qx1_data[ 8], | |
366 | opds_qx1_data[ 6], opds_qx1_data[ 4], opds_qx1_data[ 2], opds_qx1_data[ 0] | |
367 | }; | |
368 | ||
369 | ||
370 | ||
371 | sio_opds_dp_prty_macro__width_16 prty_pgenx03 ( | |
372 | .din (opds_qx0_rewired_data[63:48]), | |
373 | .dout (pgenx0_[3]) | |
374 | ); | |
375 | ||
376 | sio_opds_dp_prty_macro__width_16 prty_pgenx02 ( | |
377 | .din (opds_qx0_rewired_data[47:32]), | |
378 | .dout (pgenx0_[2]) | |
379 | ); | |
380 | ||
381 | sio_opds_dp_prty_macro__width_16 prty_pgenx01 ( | |
382 | .din (opds_qx0_rewired_data[31:16]), | |
383 | .dout (pgenx0_[1]) | |
384 | ); | |
385 | ||
386 | sio_opds_dp_prty_macro__width_16 prty_pgenx00 ( | |
387 | .din (opds_qx0_rewired_data[15:0]), | |
388 | .dout (pgenx0_[0]) | |
389 | ); | |
390 | ||
391 | ||
392 | sio_opds_dp_prty_macro__width_16 prty_pgenx13 ( | |
393 | .din (opds_qx1_rewired_data[63:48]), | |
394 | .dout (pgenx1_[3]) | |
395 | ); | |
396 | ||
397 | sio_opds_dp_prty_macro__width_16 prty_pgenx12 ( | |
398 | .din (opds_qx1_rewired_data[47:32]), | |
399 | .dout (pgenx1_[2]) | |
400 | ); | |
401 | ||
402 | sio_opds_dp_prty_macro__width_16 prty_pgenx11 ( | |
403 | .din (opds_qx1_rewired_data[31:16]), | |
404 | .dout (pgenx1_[1]) | |
405 | ); | |
406 | ||
407 | sio_opds_dp_prty_macro__width_16 prty_pgenx10 ( | |
408 | .din (opds_qx1_rewired_data[15:0]), | |
409 | .dout (pgenx1_[0]) | |
410 | ); | |
411 | ||
412 | sio_opds_dp_inv_macro__left_0__stack_8l__width_8 inv_prty_pgenxyz ( | |
413 | .din ({opddqx0_pout[3:0], opddqx1_pout[3:0]}), | |
414 | .dout ({opddqx0_pout_inv[3:0], opddqx1_pout_inv[3:0]}) | |
415 | ); | |
416 | ||
417 | // for mb1 -- 3:1 mux of {opddqx0_pout[7:0], opddqx0_dout[63:0]} or | |
418 | // {opddqx1_pout[7:0], opddqx1_dout[63:0]} or | |
419 | // {8'd0, 32'd0 , opdhqx_dout} | |
420 | ||
421 | sio_opds_dp_msff_macro__stack_64c__width_32 ff_opdhqxout ( | |
422 | .scan_in(ff_opdhqxout_scanin), | |
423 | .scan_out(ff_opdhqxout_scanout), | |
424 | .clk (iol2clk), | |
425 | .din (opdhqx_dout[31:0]), | |
426 | .dout (opdhqx_dout_reg[31:0]), | |
427 | .en (1'b1), | |
428 | .se(se), | |
429 | .siclk(siclk), | |
430 | .soclk(soclk), | |
431 | .pce_ov(pce_ov), | |
432 | .stop(stop) | |
433 | ); | |
434 | ||
435 | sio_opds_dp_mux_macro__mux_aonpe__ports_3__stack_72c__width_72 mx31_mbist_read_data ( | |
436 | .dout (opds_read_data[71:0]), | |
437 | .din0 ({opddqx0_pout[7:0], opddqx0_dout[63:0]}), | |
438 | .din1 ({opddqx1_pout[7:0], opddqx1_dout[63:0]}), | |
439 | .din2 ({8'h00, {32{1'b0}} , opdhqx_dout_reg[31:0]}), | |
440 | .sel0 (sio_mb1_opddq0_sel), | |
441 | .sel1 (sio_mb1_opddq1_sel), | |
442 | .sel2 (sio_mb1_opdhq_sel) | |
443 | ); | |
444 | ||
445 | // for mb1 -- 2:1 mux of opcs_x or mb1_x -> opds_x | |
446 | // width = 19 = 3 (rd_ens) + 12 (dqx_rd_addr) + 4 (hq_rd_addr) | |
447 | // | |
448 | sio_opds_dp_mux_macro__mux_aope__ports_2__stack_20c__width_20 mx21_mbist_read_controls ( | |
449 | .dout ({mbist_read_unused, opds_opddq0_rd_addr[5:0], opds_opddq1_rd_addr[5:0], opds_opdhq_rd_addr[3:0], | |
450 | opds_opddq0_rd_en, opds_opddq1_rd_en, opds_opdhq_rd_en}), | |
451 | ||
452 | .din0 ({1'b0, mb1_opddq0_rd_addr[5:0], mb1_opddq1_rd_addr[5:0], mb1_opdhq_rd_addr[3:0], | |
453 | mb1_opddq0_rd_en, mb1_opddq1_rd_en, mb1_opdhq_rd_en}), | |
454 | ||
455 | .din1 ({1'b0, opcs_opddq0_rd_addr[5:0], opcs_opddq1_rd_addr[5:0], opcs_opdhq_rd_addr[3:0], | |
456 | opcs_opddq0_rd_en, opcs_opddq1_rd_en, opcs_opdhq_rd_en}), | |
457 | ||
458 | .sel0 (sio_mb1_run) | |
459 | ); | |
460 | ||
461 | ||
462 | ||
463 | ||
464 | // fixscan start: | |
465 | assign ff_packet_data0_h_scanin = scan_in ; | |
466 | assign ff_packet_data0_l_scanin = ff_packet_data0_h_scanout; | |
467 | assign ff_packet_data1_h_scanin = ff_packet_data0_l_scanout; | |
468 | assign ff_packet_data1_l_scanin = ff_packet_data1_h_scanout; | |
469 | assign ff_packet_parity_scanin = ff_packet_data1_l_scanout; | |
470 | assign ff_opdhqxout_scanin = ff_packet_parity_scanout ; | |
471 | assign scan_out = ff_opdhqxout_scanout ; | |
472 | // fixscan end: | |
473 | endmodule | |
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | // any PARAMS parms go into naming of macro | |
481 | ||
482 | module sio_opds_dp_msff_macro__stack_32l__width_32 ( | |
483 | din, | |
484 | clk, | |
485 | en, | |
486 | se, | |
487 | scan_in, | |
488 | siclk, | |
489 | soclk, | |
490 | pce_ov, | |
491 | stop, | |
492 | dout, | |
493 | scan_out); | |
494 | wire l1clk; | |
495 | wire siclk_out; | |
496 | wire soclk_out; | |
497 | wire [30:0] so; | |
498 | ||
499 | input [31:0] din; | |
500 | ||
501 | ||
502 | input clk; | |
503 | input en; | |
504 | input se; | |
505 | input scan_in; | |
506 | input siclk; | |
507 | input soclk; | |
508 | input pce_ov; | |
509 | input stop; | |
510 | ||
511 | ||
512 | ||
513 | output [31:0] dout; | |
514 | ||
515 | ||
516 | output scan_out; | |
517 | ||
518 | ||
519 | ||
520 | ||
521 | cl_dp1_l1hdr_8x c0_0 ( | |
522 | .l2clk(clk), | |
523 | .pce(en), | |
524 | .aclk(siclk), | |
525 | .bclk(soclk), | |
526 | .l1clk(l1clk), | |
527 | .se(se), | |
528 | .pce_ov(pce_ov), | |
529 | .stop(stop), | |
530 | .siclk_out(siclk_out), | |
531 | .soclk_out(soclk_out) | |
532 | ); | |
533 | dff #(32) d0_0 ( | |
534 | .l1clk(l1clk), | |
535 | .siclk(siclk_out), | |
536 | .soclk(soclk_out), | |
537 | .d(din[31:0]), | |
538 | .si({scan_in,so[30:0]}), | |
539 | .so({so[30:0],scan_out}), | |
540 | .q(dout[31:0]) | |
541 | ); | |
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | ||
560 | ||
561 | ||
562 | endmodule | |
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | // | |
573 | // buff macro | |
574 | // | |
575 | // | |
576 | ||
577 | ||
578 | ||
579 | ||
580 | ||
581 | module sio_opds_dp_buff_macro__minbuff_1__stack_4l__width_4 ( | |
582 | din, | |
583 | dout); | |
584 | input [3:0] din; | |
585 | output [3:0] dout; | |
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | buff #(4) d0_0 ( | |
593 | .in(din[3:0]), | |
594 | .out(dout[3:0]) | |
595 | ); | |
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | endmodule | |
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | ||
613 | ||
614 | // any PARAMS parms go into naming of macro | |
615 | ||
616 | module sio_opds_dp_msff_macro__left_32__stack_64c__width_8 ( | |
617 | din, | |
618 | clk, | |
619 | en, | |
620 | se, | |
621 | scan_in, | |
622 | siclk, | |
623 | soclk, | |
624 | pce_ov, | |
625 | stop, | |
626 | dout, | |
627 | scan_out); | |
628 | wire l1clk; | |
629 | wire siclk_out; | |
630 | wire soclk_out; | |
631 | wire [6:0] so; | |
632 | ||
633 | input [7:0] din; | |
634 | ||
635 | ||
636 | input clk; | |
637 | input en; | |
638 | input se; | |
639 | input scan_in; | |
640 | input siclk; | |
641 | input soclk; | |
642 | input pce_ov; | |
643 | input stop; | |
644 | ||
645 | ||
646 | ||
647 | output [7:0] dout; | |
648 | ||
649 | ||
650 | output scan_out; | |
651 | ||
652 | ||
653 | ||
654 | ||
655 | cl_dp1_l1hdr_8x c0_0 ( | |
656 | .l2clk(clk), | |
657 | .pce(en), | |
658 | .aclk(siclk), | |
659 | .bclk(soclk), | |
660 | .l1clk(l1clk), | |
661 | .se(se), | |
662 | .pce_ov(pce_ov), | |
663 | .stop(stop), | |
664 | .siclk_out(siclk_out), | |
665 | .soclk_out(soclk_out) | |
666 | ); | |
667 | dff #(8) d0_0 ( | |
668 | .l1clk(l1clk), | |
669 | .siclk(siclk_out), | |
670 | .soclk(soclk_out), | |
671 | .d(din[7:0]), | |
672 | .si({scan_in,so[6:0]}), | |
673 | .so({so[6:0],scan_out}), | |
674 | .q(dout[7:0]) | |
675 | ); | |
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | endmodule | |
697 | ||
698 | ||
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | // | |
707 | // xor macro for ports = 2,3 | |
708 | // | |
709 | // | |
710 | ||
711 | ||
712 | ||
713 | ||
714 | ||
715 | module sio_opds_dp_xor_macro__ports_2__stack_8r__width_8 ( | |
716 | din0, | |
717 | din1, | |
718 | dout); | |
719 | input [7:0] din0; | |
720 | input [7:0] din1; | |
721 | output [7:0] dout; | |
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | xor2 #(8) d0_0 ( | |
728 | .in0(din0[7:0]), | |
729 | .in1(din1[7:0]), | |
730 | .out(dout[7:0]) | |
731 | ); | |
732 | ||
733 | ||
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | endmodule | |
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
747 | // also for pass-gate with decoder | |
748 | ||
749 | ||
750 | ||
751 | ||
752 | ||
753 | // any PARAMS parms go into naming of macro | |
754 | ||
755 | module sio_opds_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 ( | |
756 | din0, | |
757 | din1, | |
758 | sel0, | |
759 | dout); | |
760 | wire psel0; | |
761 | wire psel1; | |
762 | ||
763 | input [63:0] din0; | |
764 | input [63:0] din1; | |
765 | input sel0; | |
766 | output [63:0] dout; | |
767 | ||
768 | ||
769 | ||
770 | ||
771 | ||
772 | cl_dp1_penc2_8x c0_0 ( | |
773 | .sel0(sel0), | |
774 | .psel0(psel0), | |
775 | .psel1(psel1) | |
776 | ); | |
777 | ||
778 | mux2s #(64) d0_0 ( | |
779 | .sel0(psel0), | |
780 | .sel1(psel1), | |
781 | .in0(din0[63:0]), | |
782 | .in1(din1[63:0]), | |
783 | .dout(dout[63:0]) | |
784 | ); | |
785 | ||
786 | ||
787 | ||
788 | ||
789 | ||
790 | ||
791 | ||
792 | ||
793 | ||
794 | ||
795 | ||
796 | ||
797 | ||
798 | endmodule | |
799 | ||
800 | ||
801 | // | |
802 | // xor macro for ports = 2,3 | |
803 | // | |
804 | // | |
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | module sio_opds_dp_xor_macro__left_1__stack_4r__width_1 ( | |
811 | din0, | |
812 | din1, | |
813 | dout); | |
814 | input [0:0] din0; | |
815 | input [0:0] din1; | |
816 | output [0:0] dout; | |
817 | ||
818 | ||
819 | ||
820 | ||
821 | ||
822 | xor2 #(1) d0_0 ( | |
823 | .in0(din0[0:0]), | |
824 | .in1(din1[0:0]), | |
825 | .out(dout[0:0]) | |
826 | ); | |
827 | ||
828 | ||
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | endmodule | |
836 | ||
837 | ||
838 | ||
839 | ||
840 | ||
841 | // | |
842 | // parity macro (even parity) | |
843 | // | |
844 | // | |
845 | ||
846 | ||
847 | ||
848 | ||
849 | ||
850 | module sio_opds_dp_prty_macro__width_16 ( | |
851 | din, | |
852 | dout); | |
853 | input [15:0] din; | |
854 | output dout; | |
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | ||
862 | prty #(16) m0_0 ( | |
863 | .in(din[15:0]), | |
864 | .out(dout) | |
865 | ); | |
866 | ||
867 | ||
868 | ||
869 | ||
870 | ||
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | endmodule | |
877 | ||
878 | ||
879 | ||
880 | ||
881 | ||
882 | // | |
883 | // invert macro | |
884 | // | |
885 | // | |
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | module sio_opds_dp_inv_macro__left_0__stack_8l__width_8 ( | |
892 | din, | |
893 | dout); | |
894 | input [7:0] din; | |
895 | output [7:0] dout; | |
896 | ||
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | inv #(8) d0_0 ( | |
903 | .in(din[7:0]), | |
904 | .out(dout[7:0]) | |
905 | ); | |
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | endmodule | |
916 | ||
917 | ||
918 | ||
919 | ||
920 | ||
921 | ||
922 | ||
923 | ||
924 | ||
925 | // any PARAMS parms go into naming of macro | |
926 | ||
927 | module sio_opds_dp_msff_macro__stack_64c__width_32 ( | |
928 | din, | |
929 | clk, | |
930 | en, | |
931 | se, | |
932 | scan_in, | |
933 | siclk, | |
934 | soclk, | |
935 | pce_ov, | |
936 | stop, | |
937 | dout, | |
938 | scan_out); | |
939 | wire l1clk; | |
940 | wire siclk_out; | |
941 | wire soclk_out; | |
942 | wire [30:0] so; | |
943 | ||
944 | input [31:0] din; | |
945 | ||
946 | ||
947 | input clk; | |
948 | input en; | |
949 | input se; | |
950 | input scan_in; | |
951 | input siclk; | |
952 | input soclk; | |
953 | input pce_ov; | |
954 | input stop; | |
955 | ||
956 | ||
957 | ||
958 | output [31:0] dout; | |
959 | ||
960 | ||
961 | output scan_out; | |
962 | ||
963 | ||
964 | ||
965 | ||
966 | cl_dp1_l1hdr_8x c0_0 ( | |
967 | .l2clk(clk), | |
968 | .pce(en), | |
969 | .aclk(siclk), | |
970 | .bclk(soclk), | |
971 | .l1clk(l1clk), | |
972 | .se(se), | |
973 | .pce_ov(pce_ov), | |
974 | .stop(stop), | |
975 | .siclk_out(siclk_out), | |
976 | .soclk_out(soclk_out) | |
977 | ); | |
978 | dff #(32) d0_0 ( | |
979 | .l1clk(l1clk), | |
980 | .siclk(siclk_out), | |
981 | .soclk(soclk_out), | |
982 | .d(din[31:0]), | |
983 | .si({scan_in,so[30:0]}), | |
984 | .so({so[30:0],scan_out}), | |
985 | .q(dout[31:0]) | |
986 | ); | |
987 | ||
988 | ||
989 | ||
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | ||
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | endmodule | |
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1018 | // also for pass-gate with decoder | |
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | // any PARAMS parms go into naming of macro | |
1025 | ||
1026 | module sio_opds_dp_mux_macro__mux_aonpe__ports_3__stack_72c__width_72 ( | |
1027 | din0, | |
1028 | sel0, | |
1029 | din1, | |
1030 | sel1, | |
1031 | din2, | |
1032 | sel2, | |
1033 | dout); | |
1034 | wire buffout0; | |
1035 | wire buffout1; | |
1036 | wire buffout2; | |
1037 | ||
1038 | input [71:0] din0; | |
1039 | input sel0; | |
1040 | input [71:0] din1; | |
1041 | input sel1; | |
1042 | input [71:0] din2; | |
1043 | input sel2; | |
1044 | output [71:0] dout; | |
1045 | ||
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | cl_dp1_muxbuff3_8x c0_0 ( | |
1051 | .in0(sel0), | |
1052 | .in1(sel1), | |
1053 | .in2(sel2), | |
1054 | .out0(buffout0), | |
1055 | .out1(buffout1), | |
1056 | .out2(buffout2) | |
1057 | ); | |
1058 | mux3s #(72) d0_0 ( | |
1059 | .sel0(buffout0), | |
1060 | .sel1(buffout1), | |
1061 | .sel2(buffout2), | |
1062 | .in0(din0[71:0]), | |
1063 | .in1(din1[71:0]), | |
1064 | .in2(din2[71:0]), | |
1065 | .dout(dout[71:0]) | |
1066 | ); | |
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | endmodule | |
1081 | ||
1082 | ||
1083 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1084 | // also for pass-gate with decoder | |
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | // any PARAMS parms go into naming of macro | |
1091 | ||
1092 | module sio_opds_dp_mux_macro__mux_aope__ports_2__stack_20c__width_20 ( | |
1093 | din0, | |
1094 | din1, | |
1095 | sel0, | |
1096 | dout); | |
1097 | wire psel0; | |
1098 | wire psel1; | |
1099 | ||
1100 | input [19:0] din0; | |
1101 | input [19:0] din1; | |
1102 | input sel0; | |
1103 | output [19:0] dout; | |
1104 | ||
1105 | ||
1106 | ||
1107 | ||
1108 | ||
1109 | cl_dp1_penc2_8x c0_0 ( | |
1110 | .sel0(sel0), | |
1111 | .psel0(psel0), | |
1112 | .psel1(psel1) | |
1113 | ); | |
1114 | ||
1115 | mux2s #(20) d0_0 ( | |
1116 | .sel0(psel0), | |
1117 | .sel1(psel1), | |
1118 | .in0(din0[19:0]), | |
1119 | .in1(din1[19:0]), | |
1120 | .dout(dout[19:0]) | |
1121 | ); | |
1122 | ||
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | endmodule | |
1136 |