Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / sio / rtl / sio_stg1_dp.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: sio_stg1_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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34// ========== Copyright Header End ============================================
35module sio_stg1_dp (
36 l2clk,
37 l2b_sio_data,
38 l2b_sio_parity,
39 l2b_sio_ue_err,
40 l2b_sio_ctag_vld,
41 l2b_sio_data_r,
42 l2b_sio_parity_r,
43 l2b_sio_ue_err_r,
44 l2b_sio_ctag_vld_r,
45 tcu_muxtest,
46 tcu_dectest,
47 tcu_scan_en,
48 scan_in,
49 tcu_aclk,
50 tcu_bclk,
51 tcu_pce_ov,
52 tcu_clk_stop,
53 scan_out);
54wire muxtst;
55wire test;
56wire se;
57wire siclk;
58wire soclk;
59wire pce_ov;
60wire stop;
61wire dff_l2b_sio_data_scanin;
62wire dff_l2b_sio_data_scanout;
63
64
65 input l2clk;
66 input [31:0] l2b_sio_data;
67 input [1:0] l2b_sio_parity;
68 input l2b_sio_ue_err;
69 input l2b_sio_ctag_vld;
70
71 output [31:0] l2b_sio_data_r;
72 output [1:0] l2b_sio_parity_r;
73 output l2b_sio_ue_err_r;
74 output l2b_sio_ctag_vld_r;
75
76 input tcu_muxtest;
77 input tcu_dectest;
78 input tcu_scan_en;
79
80 input scan_in;
81 input tcu_aclk;
82 input tcu_bclk;
83 input tcu_pce_ov;
84 input tcu_clk_stop;
85 output scan_out;
86
87 ///////////////////////////////////////
88 // Scan chain connections
89 ///////////////////////////////////////
90 // scan renames
91 assign muxtst = tcu_muxtest;
92 assign test = tcu_dectest;
93 assign se = tcu_scan_en;
94
95 assign siclk = tcu_aclk;
96 assign soclk = tcu_bclk;
97 assign pce_ov = tcu_pce_ov;
98 assign stop = tcu_clk_stop;
99 // end scan
100
101
102 ///////////////////////////////////////
103 //
104 // CAPTURE FLOPS for parity, ue and din
105 // -- sol0 cycle
106 //
107 ///////////////////////////////////////
108
109
110 sio_stg1_dp_msff_macro__stack_36c__width_36 dff_l2b_sio_data (
111 .scan_in(dff_l2b_sio_data_scanin),
112 .scan_out(dff_l2b_sio_data_scanout),
113 .clk (l2clk),
114 .din ({l2b_sio_data[31:0], l2b_sio_ctag_vld, l2b_sio_parity[1:0],l2b_sio_ue_err}),
115 .dout ({l2b_sio_data_r[31:0], l2b_sio_ctag_vld_r, l2b_sio_parity_r[1:0],l2b_sio_ue_err_r}),
116 .en (1'b1),
117 .se(se),
118 .siclk(siclk),
119 .soclk(soclk),
120 .pce_ov(pce_ov),
121 .stop(stop)
122 );
123
124
125// fixscan start:
126assign dff_l2b_sio_data_scanin = scan_in ;
127assign scan_out = dff_l2b_sio_data_scanout ;
128// fixscan end:
129endmodule // sio_old_dp
130
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135
136
137
138// any PARAMS parms go into naming of macro
139
140module sio_stg1_dp_msff_macro__stack_36c__width_36 (
141 din,
142 clk,
143 en,
144 se,
145 scan_in,
146 siclk,
147 soclk,
148 pce_ov,
149 stop,
150 dout,
151 scan_out);
152wire l1clk;
153wire siclk_out;
154wire soclk_out;
155wire [34:0] so;
156
157 input [35:0] din;
158
159
160 input clk;
161 input en;
162 input se;
163 input scan_in;
164 input siclk;
165 input soclk;
166 input pce_ov;
167 input stop;
168
169
170
171 output [35:0] dout;
172
173
174 output scan_out;
175
176
177
178
179cl_dp1_l1hdr_8x c0_0 (
180.l2clk(clk),
181.pce(en),
182.aclk(siclk),
183.bclk(soclk),
184.l1clk(l1clk),
185 .se(se),
186 .pce_ov(pce_ov),
187 .stop(stop),
188 .siclk_out(siclk_out),
189 .soclk_out(soclk_out)
190);
191dff #(36) d0_0 (
192.l1clk(l1clk),
193.siclk(siclk_out),
194.soclk(soclk_out),
195.d(din[35:0]),
196.si({scan_in,so[34:0]}),
197.so({so[34:0],scan_out}),
198.q(dout[35:0])
199);
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220endmodule
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