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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: exu_ecc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module exu_ecc_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | ect_mbist_sel, | |
43 | mbi_write_data_p1, | |
44 | edp_rd_ff_w, | |
45 | edp_rd_ff_w2, | |
46 | tlu_cerer_irf, | |
47 | tlu_ceter_pscce, | |
48 | lsu_asi_error_inject_b31, | |
49 | lsu_asi_error_inject_b25, | |
50 | lsu_asi_error_inject, | |
51 | ecc_w_synd_w, | |
52 | ecc_w2_synd_w2, | |
53 | ecc_mbist_write_data_p4, | |
54 | ect_ex_emb_clken, | |
55 | ect_tg_clken, | |
56 | ect_tid_lth_e, | |
57 | ect_rs1_valid_e, | |
58 | ect_rs2_valid_e, | |
59 | ect_rs3_valid_e, | |
60 | ect_two_cycle_m, | |
61 | ect_rs1_addr_e, | |
62 | ect_rs2_addr_e, | |
63 | ect_rs3_addr_e, | |
64 | edp_rcc_data_e, | |
65 | exu_rs2_data_e, | |
66 | edp_rs3_data_e, | |
67 | edp_rcc_ecc_e, | |
68 | edp_rs2_ecc_e, | |
69 | edp_rs3_ecc_e, | |
70 | dec_valid_e, | |
71 | dec_flush_m, | |
72 | exu_ecc_check_m, | |
73 | exu_ecc_addr_m, | |
74 | exu_ecc_m, | |
75 | exu_cecc_m, | |
76 | exu_uecc_m, | |
77 | scan_out); | |
78 | wire pce_ov; | |
79 | wire stop; | |
80 | wire siclk; | |
81 | wire soclk; | |
82 | wire se; | |
83 | wire l1clk_pm1; | |
84 | wire l1clk_pm2; | |
85 | wire mbist_ff_scanin; | |
86 | wire mbist_ff_scanout; | |
87 | wire [7:0] mbi_write_data_p2; | |
88 | wire [7:0] mbi_write_data_p3; | |
89 | wire ecc_mask_en_in; | |
90 | wire debug_ff_scanin; | |
91 | wire debug_ff_scanout; | |
92 | wire cerer_irf_ff; | |
93 | wire [3:0] ceter_pscce_ff; | |
94 | wire [7:0] ecc_mask_data_ff; | |
95 | wire ecc_mask_en_ff; | |
96 | wire ecc_valid_e; | |
97 | wire ecc_enable_e; | |
98 | wire [63:0] d1_e; | |
99 | wire [7:0] p1_e; | |
100 | wire [63:0] d2_e; | |
101 | wire [7:0] p2_e; | |
102 | wire [63:0] d3_e; | |
103 | wire [7:0] p3_e; | |
104 | wire rs1_ne_e; | |
105 | wire rs1_parity_e; | |
106 | wire [6:0] q1_e; | |
107 | wire rs1_ce_e; | |
108 | wire rs1_ue_e; | |
109 | wire rs2_ne_e; | |
110 | wire rs2_parity_e; | |
111 | wire [6:0] q2_e; | |
112 | wire rs2_ce_e; | |
113 | wire rs2_ue_e; | |
114 | wire rs3_ce_e; | |
115 | wire rs3_parity_e; | |
116 | wire rs3_ue_e; | |
117 | wire [6:0] q3_e; | |
118 | wire [7:0] check_e; | |
119 | wire [4:0] addr_e; | |
120 | wire check_e_to_m_scanin; | |
121 | wire check_e_to_m_scanout; | |
122 | wire addr_e_to_m_scanin; | |
123 | wire addr_e_to_m_scanout; | |
124 | wire cecc_e; | |
125 | wire uecc_e; | |
126 | wire ecc_ecc_e; | |
127 | wire ecc_uecc_e; | |
128 | wire ecc_cecc_e; | |
129 | wire ce_ue_ecc_flops_scanin; | |
130 | wire ce_ue_ecc_flops_scanout; | |
131 | wire [7:0] ecc_mask_b; | |
132 | wire [63:0] w_d; | |
133 | wire [7:0] w_p_b; | |
134 | wire [63:0] w2_d; | |
135 | wire [7:0] w2_p_w; | |
136 | wire spares_scanin; | |
137 | wire spares_scanout; | |
138 | ||
139 | ||
140 | // *** Global Inputs *** | |
141 | ||
142 | input l2clk; | |
143 | input scan_in; | |
144 | input tcu_pce_ov; // scan signals | |
145 | input spc_aclk; | |
146 | input spc_bclk; | |
147 | input tcu_scan_en; | |
148 | ||
149 | input ect_mbist_sel; // MBIST | |
150 | input [7:0] mbi_write_data_p1; // MBIST | |
151 | ||
152 | ||
153 | // *** Generate ECC Local Inputs *** | |
154 | ||
155 | input [63:0] edp_rd_ff_w; // w port data | |
156 | input [63:0] edp_rd_ff_w2; // w2 port data | |
157 | ||
158 | input tlu_cerer_irf; // IRF ecc error trap enable | |
159 | input [3:0] tlu_ceter_pscce; // core error trap enable reg precise enable | |
160 | ||
161 | input lsu_asi_error_inject_b31; // [31]=global inject en | |
162 | input lsu_asi_error_inject_b25; // [25]=IRF inject en | |
163 | input [7:0] lsu_asi_error_inject; // [7:0]=mask | |
164 | ||
165 | ||
166 | // *** Generate ECC Local Outputs *** | |
167 | ||
168 | output [7:0] ecc_w_synd_w; // Generated ECC to IRF W port | |
169 | output [7:0] ecc_w2_synd_w2; // Generated ECC to IRF W2 port | |
170 | output [7:0] ecc_mbist_write_data_p4; // MBIST | |
171 | ||
172 | // *** Check ECC Local Inputs *** | |
173 | ||
174 | input ect_ex_emb_clken; // Power Management | |
175 | input ect_tg_clken; // Power Management | |
176 | ||
177 | input [1:0] ect_tid_lth_e; | |
178 | ||
179 | input ect_rs1_valid_e; // Source register valid bit | |
180 | input ect_rs2_valid_e; // - available at output of flop | |
181 | input ect_rs3_valid_e; // - signals valid rs data | |
182 | input ect_two_cycle_m; | |
183 | ||
184 | input [4:0] ect_rs1_addr_e; // Source register address | |
185 | input [4:0] ect_rs2_addr_e; // - available at output of flop | |
186 | input [4:0] ect_rs3_addr_e; // - addr for IRF physical active window | |
187 | ||
188 | input [63:0] edp_rcc_data_e; // Source register ECC and data bit | |
189 | input [63:0] exu_rs2_data_e; // - available at output of flop | |
190 | input [63:0] edp_rs3_data_e; | |
191 | input [7:0] edp_rcc_ecc_e; | |
192 | input [7:0] edp_rs2_ecc_e; | |
193 | input [7:0] edp_rs3_ecc_e; | |
194 | ||
195 | ||
196 | input dec_valid_e; | |
197 | input dec_flush_m; | |
198 | ||
199 | ||
200 | // *** Global Outputs *** | |
201 | ||
202 | output [7:0] exu_ecc_check_m; | |
203 | output [4:0] exu_ecc_addr_m; | |
204 | ||
205 | output exu_ecc_m; | |
206 | ||
207 | output exu_cecc_m; // Flag for detected correctable ECC error | |
208 | output exu_uecc_m; // Flag for detected uncorrectable ECC error | |
209 | ||
210 | ||
211 | // *** Local Outputs *** | |
212 | ||
213 | output scan_out; | |
214 | ||
215 | ||
216 | ||
217 | // scan renames | |
218 | assign pce_ov = tcu_pce_ov; | |
219 | assign stop = 1'b0; | |
220 | assign siclk = spc_aclk; | |
221 | assign soclk = spc_bclk; | |
222 | assign se = tcu_scan_en; | |
223 | // end scan | |
224 | ||
225 | exu_ecc_ctl_l1clkhdr_ctl_macro clkgen_pm1 ( | |
226 | .l2clk( l2clk ), | |
227 | .l1en ( ect_tg_clken ), | |
228 | .l1clk( l1clk_pm1 ), | |
229 | .pce_ov(pce_ov), | |
230 | .stop(stop), | |
231 | .se(se)); | |
232 | ||
233 | ||
234 | exu_ecc_ctl_l1clkhdr_ctl_macro clkgen_pm2 ( | |
235 | .l2clk( l2clk ), | |
236 | .l1en ( ect_ex_emb_clken ), | |
237 | .l1clk( l1clk_pm2 ), | |
238 | .pce_ov(pce_ov), | |
239 | .stop(stop), | |
240 | .se(se)); | |
241 | ||
242 | ||
243 | exu_ecc_ctl_msff_ctl_macro__width_24 mbist_ff ( | |
244 | .scan_in(mbist_ff_scanin), | |
245 | .scan_out(mbist_ff_scanout), | |
246 | .l1clk( l1clk_pm1 ), | |
247 | .din ({mbi_write_data_p1[7:0] , mbi_write_data_p2[7:0] , mbi_write_data_p3[7:0]} ), | |
248 | .dout ({mbi_write_data_p2[7:0] , mbi_write_data_p3[7:0] , ecc_mbist_write_data_p4[7:0]} ), | |
249 | .siclk(siclk), | |
250 | .soclk(soclk)); | |
251 | ||
252 | ||
253 | assign ecc_mask_en_in = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b25; | |
254 | ||
255 | exu_ecc_ctl_msff_ctl_macro__width_14 debug_ff ( | |
256 | .scan_in(debug_ff_scanin), | |
257 | .scan_out(debug_ff_scanout), | |
258 | .l1clk( l1clk_pm1 ), | |
259 | .din ({tlu_cerer_irf , tlu_ceter_pscce[3:0] , lsu_asi_error_inject[7:0] , ecc_mask_en_in} ), | |
260 | .dout ({cerer_irf_ff , ceter_pscce_ff[3:0] , ecc_mask_data_ff[7:0] , ecc_mask_en_ff} ), | |
261 | .siclk(siclk), | |
262 | .soclk(soclk)); | |
263 | ||
264 | ||
265 | assign ecc_valid_e = dec_valid_e | (ect_two_cycle_m & ~dec_flush_m); | |
266 | ||
267 | assign ecc_enable_e = ( ecc_valid_e & cerer_irf_ff & ceter_pscce_ff[0] & (ect_tid_lth_e[1:0] == 2'b00)) | | |
268 | ( ecc_valid_e & cerer_irf_ff & ceter_pscce_ff[1] & (ect_tid_lth_e[1:0] == 2'b01)) | | |
269 | ( ecc_valid_e & cerer_irf_ff & ceter_pscce_ff[2] & (ect_tid_lth_e[1:0] == 2'b10)) | | |
270 | ( ecc_valid_e & cerer_irf_ff & ceter_pscce_ff[3] & (ect_tid_lth_e[1:0] == 2'b11)); | |
271 | ||
272 | ||
273 | ///////////////////////////////////////////////////////////////////////////// | |
274 | // ECC Error Dectection Logic | |
275 | //----------------------------- | |
276 | // - Regenerate ECC [6:0] and compare against retrived ECC | |
277 | // - Check ECC [7] with parity | |
278 | // - Outputs the result of the detection: | |
279 | // - ne: no error - either no valid data to check, | |
280 | // or ECC [6:0] all matched | |
281 | // - ce: correctable error | |
282 | // - parity is 1, so an odd number of bits flipped, | |
283 | // and ECC data is valid and regenerated ECC did not match | |
284 | // - ue: uncorrectable error | |
285 | // - parity is 0, so an even number of bits flipped, | |
286 | // and ECC data is valid and regenerated ECC did not match | |
287 | // - implies more than one bit was corrupted | |
288 | ///////////////////////////////////////////////////////////////////////////// | |
289 | ||
290 | // renaming inputs for shorter assign statements | |
291 | assign d1_e[63:0] = edp_rcc_data_e[63:0]; | |
292 | assign p1_e[ 7:0] = edp_rcc_ecc_e[7:0]; | |
293 | ||
294 | assign d2_e[63:0] = exu_rs2_data_e[63:0]; | |
295 | assign p2_e[ 7:0] = edp_rs2_ecc_e[7:0]; | |
296 | ||
297 | assign d3_e[63:0] = edp_rs3_data_e[63:0]; | |
298 | assign p3_e[ 7:0] = edp_rs3_ecc_e[7:0]; | |
299 | ||
300 | ||
301 | // Detection for RS1 | |
302 | // ----------------------------------- | |
303 | assign rs1_ne_e = ~ect_rs1_valid_e | | |
304 | ~(rs1_parity_e | q1_e[6] | q1_e[5] | q1_e[4] | q1_e[3] | q1_e[2] | q1_e[1] | q1_e[0]); | |
305 | ||
306 | assign rs1_ce_e = ect_rs1_valid_e & rs1_parity_e; | |
307 | ||
308 | assign rs1_ue_e = ect_rs1_valid_e & ~rs1_parity_e & | |
309 | (q1_e[6] | q1_e[5] | q1_e[4] | q1_e[3] | q1_e[2] | q1_e[1] | q1_e[0]); | |
310 | ||
311 | assign q1_e[0] = d1_e[0] ^ d1_e[1] ^ d1_e[3] ^ d1_e[4] ^ d1_e[6] | |
312 | ^ d1_e[8] ^ d1_e[10] ^ d1_e[11] ^ d1_e[13] ^ d1_e[15] | |
313 | ^ d1_e[17] ^ d1_e[19] ^ d1_e[21] ^ d1_e[23] ^ d1_e[25] | |
314 | ^ d1_e[26] ^ d1_e[28] ^ d1_e[30] ^ d1_e[32] ^ d1_e[34] | |
315 | ^ d1_e[36] ^ d1_e[38] ^ d1_e[40] ^ d1_e[42] ^ d1_e[44] | |
316 | ^ d1_e[46] ^ d1_e[48] ^ d1_e[50] ^ d1_e[52] ^ d1_e[54] | |
317 | ^ d1_e[56] ^ d1_e[57] ^ d1_e[59] ^ d1_e[61] ^ d1_e[63] | |
318 | ^ p1_e[0] ; | |
319 | ||
320 | assign q1_e[1] = d1_e[0] ^ d1_e[2] ^ d1_e[3] ^ d1_e[5] ^ d1_e[6] | |
321 | ^ d1_e[9] ^ d1_e[10] ^ d1_e[12] ^ d1_e[13] ^ d1_e[16] | |
322 | ^ d1_e[17] ^ d1_e[20] ^ d1_e[21] ^ d1_e[24] ^ d1_e[25] | |
323 | ^ d1_e[27] ^ d1_e[28] ^ d1_e[31] ^ d1_e[32] ^ d1_e[35] | |
324 | ^ d1_e[36] ^ d1_e[39] ^ d1_e[40] ^ d1_e[43] ^ d1_e[44] | |
325 | ^ d1_e[47] ^ d1_e[48] ^ d1_e[51] ^ d1_e[52] ^ d1_e[55] | |
326 | ^ d1_e[56] ^ d1_e[58] ^ d1_e[59] ^ d1_e[62] ^ d1_e[63] | |
327 | ^ p1_e[1] ; | |
328 | ||
329 | assign q1_e[2] = d1_e[1] ^ d1_e[2] ^ d1_e[3] ^ d1_e[7] ^ d1_e[8] | |
330 | ^ d1_e[9] ^ d1_e[10] ^ d1_e[14] ^ d1_e[15] ^ d1_e[16] | |
331 | ^ d1_e[17] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] ^ d1_e[25] | |
332 | ^ d1_e[29] ^ d1_e[30] ^ d1_e[31] ^ d1_e[32] ^ d1_e[37] | |
333 | ^ d1_e[38] ^ d1_e[39] ^ d1_e[40] ^ d1_e[45] ^ d1_e[46] | |
334 | ^ d1_e[47] ^ d1_e[48] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55] | |
335 | ^ d1_e[56] ^ d1_e[60] ^ d1_e[61] ^ d1_e[62] ^ d1_e[63] | |
336 | ^ p1_e[2] ; | |
337 | ||
338 | assign q1_e[3] = d1_e[4] ^ d1_e[5] ^ d1_e[6] ^ d1_e[7] ^ d1_e[8] | |
339 | ^ d1_e[9] ^ d1_e[10] ^ d1_e[18] ^ d1_e[19] ^ d1_e[20] | |
340 | ^ d1_e[21] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] ^ d1_e[25] | |
341 | ^ d1_e[33] ^ d1_e[34] ^ d1_e[35] ^ d1_e[36] ^ d1_e[37] | |
342 | ^ d1_e[38] ^ d1_e[39] ^ d1_e[40] ^ d1_e[49] ^ d1_e[50] | |
343 | ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55] | |
344 | ^ d1_e[56] | |
345 | ^ p1_e[3] ; | |
346 | ||
347 | assign q1_e[4] = d1_e[11] ^ d1_e[12] ^ d1_e[13] ^ d1_e[14] ^ d1_e[15] | |
348 | ^ d1_e[16] ^ d1_e[17] ^ d1_e[18] ^ d1_e[19] ^ d1_e[20] | |
349 | ^ d1_e[21] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] ^ d1_e[25] | |
350 | ^ d1_e[41] ^ d1_e[42] ^ d1_e[43] ^ d1_e[44] ^ d1_e[45] | |
351 | ^ d1_e[46] ^ d1_e[47] ^ d1_e[48] ^ d1_e[49] ^ d1_e[50] | |
352 | ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55] | |
353 | ^ d1_e[56] | |
354 | ^ p1_e[4] ; | |
355 | ||
356 | assign q1_e[5] = d1_e[26] ^ d1_e[27] ^ d1_e[28] ^ d1_e[29] ^ d1_e[30] | |
357 | ^ d1_e[31] ^ d1_e[32] ^ d1_e[33] ^ d1_e[34] ^ d1_e[35] | |
358 | ^ d1_e[36] ^ d1_e[37] ^ d1_e[38] ^ d1_e[39] ^ d1_e[40] | |
359 | ^ d1_e[41] ^ d1_e[42] ^ d1_e[43] ^ d1_e[44] ^ d1_e[45] | |
360 | ^ d1_e[46] ^ d1_e[47] ^ d1_e[48] ^ d1_e[49] ^ d1_e[50] | |
361 | ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55] | |
362 | ^ d1_e[56] | |
363 | ^ p1_e[5] ; | |
364 | ||
365 | assign q1_e[6] = d1_e[57] ^ d1_e[58] ^ d1_e[59] ^ d1_e[60] ^ d1_e[61] | |
366 | ^ d1_e[62] ^ d1_e[63] | |
367 | ^ p1_e[6] ; | |
368 | ||
369 | assign rs1_parity_e = d1_e[0] ^ d1_e[1] ^ d1_e[2] ^ d1_e[3] ^ d1_e[4] | |
370 | ^ d1_e[5] ^ d1_e[6] ^ d1_e[7] ^ d1_e[8] ^ d1_e[9] | |
371 | ^ d1_e[10] ^ d1_e[11] ^ d1_e[12] ^ d1_e[13] ^ d1_e[14] | |
372 | ^ d1_e[15] ^ d1_e[16] ^ d1_e[17] ^ d1_e[18] ^ d1_e[19] | |
373 | ^ d1_e[20] ^ d1_e[21] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] | |
374 | ^ d1_e[25] ^ d1_e[26] ^ d1_e[27] ^ d1_e[28] ^ d1_e[29] | |
375 | ^ d1_e[30] ^ d1_e[31] ^ d1_e[32] ^ d1_e[33] ^ d1_e[34] | |
376 | ^ d1_e[35] ^ d1_e[36] ^ d1_e[37] ^ d1_e[38] ^ d1_e[39] | |
377 | ^ d1_e[40] ^ d1_e[41] ^ d1_e[42] ^ d1_e[43] ^ d1_e[44] | |
378 | ^ d1_e[45] ^ d1_e[46] ^ d1_e[47] ^ d1_e[48] ^ d1_e[49] | |
379 | ^ d1_e[50] ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] | |
380 | ^ d1_e[55] ^ d1_e[56] ^ d1_e[57] ^ d1_e[58] ^ d1_e[59] | |
381 | ^ d1_e[60] ^ d1_e[61] ^ d1_e[62] ^ d1_e[63] | |
382 | ^ p1_e[0] ^ p1_e[1] ^ p1_e[2] ^ p1_e[3] ^ p1_e[4] | |
383 | ^ p1_e[5] ^ p1_e[6] ^ p1_e[7]; | |
384 | ||
385 | ||
386 | // Detection for RS2 | |
387 | // ----------------------------------- | |
388 | assign rs2_ne_e = ~ect_rs2_valid_e | | |
389 | ~(rs2_parity_e | q2_e[6] | q2_e[5] | q2_e[4] | q2_e[3] | q2_e[2] | q2_e[1] | q2_e[0]); | |
390 | ||
391 | assign rs2_ce_e = ect_rs2_valid_e & rs2_parity_e; | |
392 | ||
393 | assign rs2_ue_e = ect_rs2_valid_e & ~rs2_parity_e & | |
394 | (q2_e[6] | q2_e[5] | q2_e[4] | q2_e[3] | q2_e[2] | q2_e[1] | q2_e[0]); | |
395 | ||
396 | assign q2_e[0] = d2_e[0] ^ d2_e[1] ^ d2_e[3] ^ d2_e[4] ^ d2_e[6] | |
397 | ^ d2_e[8] ^ d2_e[10] ^ d2_e[11] ^ d2_e[13] ^ d2_e[15] | |
398 | ^ d2_e[17] ^ d2_e[19] ^ d2_e[21] ^ d2_e[23] ^ d2_e[25] | |
399 | ^ d2_e[26] ^ d2_e[28] ^ d2_e[30] ^ d2_e[32] ^ d2_e[34] | |
400 | ^ d2_e[36] ^ d2_e[38] ^ d2_e[40] ^ d2_e[42] ^ d2_e[44] | |
401 | ^ d2_e[46] ^ d2_e[48] ^ d2_e[50] ^ d2_e[52] ^ d2_e[54] | |
402 | ^ d2_e[56] ^ d2_e[57] ^ d2_e[59] ^ d2_e[61] ^ d2_e[63] | |
403 | ^ p2_e[0] ; | |
404 | ||
405 | assign q2_e[1] = d2_e[0] ^ d2_e[2] ^ d2_e[3] ^ d2_e[5] ^ d2_e[6] | |
406 | ^ d2_e[9] ^ d2_e[10] ^ d2_e[12] ^ d2_e[13] ^ d2_e[16] | |
407 | ^ d2_e[17] ^ d2_e[20] ^ d2_e[21] ^ d2_e[24] ^ d2_e[25] | |
408 | ^ d2_e[27] ^ d2_e[28] ^ d2_e[31] ^ d2_e[32] ^ d2_e[35] | |
409 | ^ d2_e[36] ^ d2_e[39] ^ d2_e[40] ^ d2_e[43] ^ d2_e[44] | |
410 | ^ d2_e[47] ^ d2_e[48] ^ d2_e[51] ^ d2_e[52] ^ d2_e[55] | |
411 | ^ d2_e[56] ^ d2_e[58] ^ d2_e[59] ^ d2_e[62] ^ d2_e[63] | |
412 | ^ p2_e[1] ; | |
413 | ||
414 | assign q2_e[2] = d2_e[1] ^ d2_e[2] ^ d2_e[3] ^ d2_e[7] ^ d2_e[8] | |
415 | ^ d2_e[9] ^ d2_e[10] ^ d2_e[14] ^ d2_e[15] ^ d2_e[16] | |
416 | ^ d2_e[17] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] ^ d2_e[25] | |
417 | ^ d2_e[29] ^ d2_e[30] ^ d2_e[31] ^ d2_e[32] ^ d2_e[37] | |
418 | ^ d2_e[38] ^ d2_e[39] ^ d2_e[40] ^ d2_e[45] ^ d2_e[46] | |
419 | ^ d2_e[47] ^ d2_e[48] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55] | |
420 | ^ d2_e[56] ^ d2_e[60] ^ d2_e[61] ^ d2_e[62] ^ d2_e[63] | |
421 | ^ p2_e[2] ; | |
422 | ||
423 | assign q2_e[3] = d2_e[4] ^ d2_e[5] ^ d2_e[6] ^ d2_e[7] ^ d2_e[8] | |
424 | ^ d2_e[9] ^ d2_e[10] ^ d2_e[18] ^ d2_e[19] ^ d2_e[20] | |
425 | ^ d2_e[21] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] ^ d2_e[25] | |
426 | ^ d2_e[33] ^ d2_e[34] ^ d2_e[35] ^ d2_e[36] ^ d2_e[37] | |
427 | ^ d2_e[38] ^ d2_e[39] ^ d2_e[40] ^ d2_e[49] ^ d2_e[50] | |
428 | ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55] | |
429 | ^ d2_e[56] | |
430 | ^ p2_e[3] ; | |
431 | ||
432 | assign q2_e[4] = d2_e[11] ^ d2_e[12] ^ d2_e[13] ^ d2_e[14] ^ d2_e[15] | |
433 | ^ d2_e[16] ^ d2_e[17] ^ d2_e[18] ^ d2_e[19] ^ d2_e[20] | |
434 | ^ d2_e[21] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] ^ d2_e[25] | |
435 | ^ d2_e[41] ^ d2_e[42] ^ d2_e[43] ^ d2_e[44] ^ d2_e[45] | |
436 | ^ d2_e[46] ^ d2_e[47] ^ d2_e[48] ^ d2_e[49] ^ d2_e[50] | |
437 | ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55] | |
438 | ^ d2_e[56] | |
439 | ^ p2_e[4] ; | |
440 | ||
441 | assign q2_e[5] = d2_e[26] ^ d2_e[27] ^ d2_e[28] ^ d2_e[29] ^ d2_e[30] | |
442 | ^ d2_e[31] ^ d2_e[32] ^ d2_e[33] ^ d2_e[34] ^ d2_e[35] | |
443 | ^ d2_e[36] ^ d2_e[37] ^ d2_e[38] ^ d2_e[39] ^ d2_e[40] | |
444 | ^ d2_e[41] ^ d2_e[42] ^ d2_e[43] ^ d2_e[44] ^ d2_e[45] | |
445 | ^ d2_e[46] ^ d2_e[47] ^ d2_e[48] ^ d2_e[49] ^ d2_e[50] | |
446 | ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55] | |
447 | ^ d2_e[56] | |
448 | ^ p2_e[5] ; | |
449 | ||
450 | assign q2_e[6] = d2_e[57] ^ d2_e[58] ^ d2_e[59] ^ d2_e[60] ^ d2_e[61] | |
451 | ^ d2_e[62] ^ d2_e[63] | |
452 | ^ p2_e[6] ; | |
453 | ||
454 | assign rs2_parity_e = d2_e[0] ^ d2_e[1] ^ d2_e[2] ^ d2_e[3] ^ d2_e[4] | |
455 | ^ d2_e[5] ^ d2_e[6] ^ d2_e[7] ^ d2_e[8] ^ d2_e[9] | |
456 | ^ d2_e[10] ^ d2_e[11] ^ d2_e[12] ^ d2_e[13] ^ d2_e[14] | |
457 | ^ d2_e[15] ^ d2_e[16] ^ d2_e[17] ^ d2_e[18] ^ d2_e[19] | |
458 | ^ d2_e[20] ^ d2_e[21] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] | |
459 | ^ d2_e[25] ^ d2_e[26] ^ d2_e[27] ^ d2_e[28] ^ d2_e[29] | |
460 | ^ d2_e[30] ^ d2_e[31] ^ d2_e[32] ^ d2_e[33] ^ d2_e[34] | |
461 | ^ d2_e[35] ^ d2_e[36] ^ d2_e[37] ^ d2_e[38] ^ d2_e[39] | |
462 | ^ d2_e[40] ^ d2_e[41] ^ d2_e[42] ^ d2_e[43] ^ d2_e[44] | |
463 | ^ d2_e[45] ^ d2_e[46] ^ d2_e[47] ^ d2_e[48] ^ d2_e[49] | |
464 | ^ d2_e[50] ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] | |
465 | ^ d2_e[55] ^ d2_e[56] ^ d2_e[57] ^ d2_e[58] ^ d2_e[59] | |
466 | ^ d2_e[60] ^ d2_e[61] ^ d2_e[62] ^ d2_e[63] | |
467 | ^ p2_e[0] ^ p2_e[1] ^ p2_e[2] ^ p2_e[3] ^ p2_e[4] | |
468 | ^ p2_e[5] ^ p2_e[6] ^ p2_e[7]; | |
469 | ||
470 | ||
471 | // Detection for RS3 | |
472 | // ----------------------------------- | |
473 | //sign rs3_ne_e = ~ect_rs3_valid_e | | |
474 | // ~(rs3_parity_e | q3_e[6] | q3_e[5] | q3_e[4] | q3_e[3] | q3_e[2] | q3_e[1] | q3_e[0]); | |
475 | ||
476 | assign rs3_ce_e = ect_rs3_valid_e & rs3_parity_e; | |
477 | ||
478 | assign rs3_ue_e = ect_rs3_valid_e & ~rs3_parity_e & | |
479 | (q3_e[6] | q3_e[5] | q3_e[4] | q3_e[3] | q3_e[2] | q3_e[1] | q3_e[0]); | |
480 | ||
481 | assign q3_e[0] = d3_e[0] ^ d3_e[1] ^ d3_e[3] ^ d3_e[4] ^ d3_e[6] | |
482 | ^ d3_e[8] ^ d3_e[10] ^ d3_e[11] ^ d3_e[13] ^ d3_e[15] | |
483 | ^ d3_e[17] ^ d3_e[19] ^ d3_e[21] ^ d3_e[23] ^ d3_e[25] | |
484 | ^ d3_e[26] ^ d3_e[28] ^ d3_e[30] ^ d3_e[32] ^ d3_e[34] | |
485 | ^ d3_e[36] ^ d3_e[38] ^ d3_e[40] ^ d3_e[42] ^ d3_e[44] | |
486 | ^ d3_e[46] ^ d3_e[48] ^ d3_e[50] ^ d3_e[52] ^ d3_e[54] | |
487 | ^ d3_e[56] ^ d3_e[57] ^ d3_e[59] ^ d3_e[61] ^ d3_e[63] | |
488 | ^ p3_e[0] ; | |
489 | ||
490 | assign q3_e[1] = d3_e[0] ^ d3_e[2] ^ d3_e[3] ^ d3_e[5] ^ d3_e[6] | |
491 | ^ d3_e[9] ^ d3_e[10] ^ d3_e[12] ^ d3_e[13] ^ d3_e[16] | |
492 | ^ d3_e[17] ^ d3_e[20] ^ d3_e[21] ^ d3_e[24] ^ d3_e[25] | |
493 | ^ d3_e[27] ^ d3_e[28] ^ d3_e[31] ^ d3_e[32] ^ d3_e[35] | |
494 | ^ d3_e[36] ^ d3_e[39] ^ d3_e[40] ^ d3_e[43] ^ d3_e[44] | |
495 | ^ d3_e[47] ^ d3_e[48] ^ d3_e[51] ^ d3_e[52] ^ d3_e[55] | |
496 | ^ d3_e[56] ^ d3_e[58] ^ d3_e[59] ^ d3_e[62] ^ d3_e[63] | |
497 | ^ p3_e[1] ; | |
498 | ||
499 | assign q3_e[2] = d3_e[1] ^ d3_e[2] ^ d3_e[3] ^ d3_e[7] ^ d3_e[8] | |
500 | ^ d3_e[9] ^ d3_e[10] ^ d3_e[14] ^ d3_e[15] ^ d3_e[16] | |
501 | ^ d3_e[17] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] ^ d3_e[25] | |
502 | ^ d3_e[29] ^ d3_e[30] ^ d3_e[31] ^ d3_e[32] ^ d3_e[37] | |
503 | ^ d3_e[38] ^ d3_e[39] ^ d3_e[40] ^ d3_e[45] ^ d3_e[46] | |
504 | ^ d3_e[47] ^ d3_e[48] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55] | |
505 | ^ d3_e[56] ^ d3_e[60] ^ d3_e[61] ^ d3_e[62] ^ d3_e[63] | |
506 | ^ p3_e[2] ; | |
507 | ||
508 | assign q3_e[3] = d3_e[4] ^ d3_e[5] ^ d3_e[6] ^ d3_e[7] ^ d3_e[8] | |
509 | ^ d3_e[9] ^ d3_e[10] ^ d3_e[18] ^ d3_e[19] ^ d3_e[20] | |
510 | ^ d3_e[21] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] ^ d3_e[25] | |
511 | ^ d3_e[33] ^ d3_e[34] ^ d3_e[35] ^ d3_e[36] ^ d3_e[37] | |
512 | ^ d3_e[38] ^ d3_e[39] ^ d3_e[40] ^ d3_e[49] ^ d3_e[50] | |
513 | ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55] | |
514 | ^ d3_e[56] | |
515 | ^ p3_e[3] ; | |
516 | ||
517 | assign q3_e[4] = d3_e[11] ^ d3_e[12] ^ d3_e[13] ^ d3_e[14] ^ d3_e[15] | |
518 | ^ d3_e[16] ^ d3_e[17] ^ d3_e[18] ^ d3_e[19] ^ d3_e[20] | |
519 | ^ d3_e[21] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] ^ d3_e[25] | |
520 | ^ d3_e[41] ^ d3_e[42] ^ d3_e[43] ^ d3_e[44] ^ d3_e[45] | |
521 | ^ d3_e[46] ^ d3_e[47] ^ d3_e[48] ^ d3_e[49] ^ d3_e[50] | |
522 | ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55] | |
523 | ^ d3_e[56] | |
524 | ^ p3_e[4] ; | |
525 | ||
526 | assign q3_e[5] = d3_e[26] ^ d3_e[27] ^ d3_e[28] ^ d3_e[29] ^ d3_e[30] | |
527 | ^ d3_e[31] ^ d3_e[32] ^ d3_e[33] ^ d3_e[34] ^ d3_e[35] | |
528 | ^ d3_e[36] ^ d3_e[37] ^ d3_e[38] ^ d3_e[39] ^ d3_e[40] | |
529 | ^ d3_e[41] ^ d3_e[42] ^ d3_e[43] ^ d3_e[44] ^ d3_e[45] | |
530 | ^ d3_e[46] ^ d3_e[47] ^ d3_e[48] ^ d3_e[49] ^ d3_e[50] | |
531 | ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55] | |
532 | ^ d3_e[56] | |
533 | ^ p3_e[5] ; | |
534 | ||
535 | assign q3_e[6] = d3_e[57] ^ d3_e[58] ^ d3_e[59] ^ d3_e[60] ^ d3_e[61] | |
536 | ^ d3_e[62] ^ d3_e[63] | |
537 | ^ p3_e[6] ; | |
538 | ||
539 | assign rs3_parity_e = d3_e[0] ^ d3_e[1] ^ d3_e[2] ^ d3_e[3] ^ d3_e[4] | |
540 | ^ d3_e[5] ^ d3_e[6] ^ d3_e[7] ^ d3_e[8] ^ d3_e[9] | |
541 | ^ d3_e[10] ^ d3_e[11] ^ d3_e[12] ^ d3_e[13] ^ d3_e[14] | |
542 | ^ d3_e[15] ^ d3_e[16] ^ d3_e[17] ^ d3_e[18] ^ d3_e[19] | |
543 | ^ d3_e[20] ^ d3_e[21] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] | |
544 | ^ d3_e[25] ^ d3_e[26] ^ d3_e[27] ^ d3_e[28] ^ d3_e[29] | |
545 | ^ d3_e[30] ^ d3_e[31] ^ d3_e[32] ^ d3_e[33] ^ d3_e[34] | |
546 | ^ d3_e[35] ^ d3_e[36] ^ d3_e[37] ^ d3_e[38] ^ d3_e[39] | |
547 | ^ d3_e[40] ^ d3_e[41] ^ d3_e[42] ^ d3_e[43] ^ d3_e[44] | |
548 | ^ d3_e[45] ^ d3_e[46] ^ d3_e[47] ^ d3_e[48] ^ d3_e[49] | |
549 | ^ d3_e[50] ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] | |
550 | ^ d3_e[55] ^ d3_e[56] ^ d3_e[57] ^ d3_e[58] ^ d3_e[59] | |
551 | ^ d3_e[60] ^ d3_e[61] ^ d3_e[62] ^ d3_e[63] | |
552 | ^ p3_e[0] ^ p3_e[1] ^ p3_e[2] ^ p3_e[3] ^ p3_e[4] | |
553 | ^ p3_e[5] ^ p3_e[6] ^ p3_e[7]; | |
554 | ||
555 | ||
556 | ||
557 | ///////////////////////////////////////////////////////////////////////////// | |
558 | // Operand selection for correction | |
559 | //----------------------------------- | |
560 | // - Only one operand can be corrected at a time | |
561 | // - Selection based on hard coded priorty | |
562 | // - rs1 -> rs2 -> rs3 | |
563 | // - If no error, sel defaults to rs3 | |
564 | // | |
565 | // NOTE: Doing operand selection in E stage adds timing pressure to E stage, | |
566 | // but saves about 150 flops. | |
567 | // | |
568 | // If this does not make cycle time, need to pass sel signal to M stage, | |
569 | // must protect sel with rst_tri_en to ensure one-hot property. | |
570 | // | |
571 | // - critical path1 is from (d1_e -> q1_e -> rs1_ne_e -> rs_to_correct) | |
572 | // | |
573 | // (d1_e->q1_e): xor3(fo1) -> xor3(fo1) -> xor2(fo1) -> xor2(fo4) => 245ps | |
574 | // (q1_e -> rs1_ne_e): | |
575 | // nand3(fo1) -> nand3(fo4) -> inv(fo4) -> nand2(fo4)=> 120ps | |
576 | // (rs1_ne_e -> rs_to_correct): | |
577 | // buffer(fo4)(4 levels) -> nand3(fo1) -> nand3(fo4) => 165ps | |
578 | // --------- | |
579 | // 530ps | |
580 | // | |
581 | // - critical path2 is (d1_e -> rs1_parity_e -> rs1_ne_e -> rs_to_correct) | |
582 | // | |
583 | // (d1_e -> rs1_parity_e): | |
584 | // xor3(fo1) -> xor3(fo1) -> xor3(fo1) -> xor3(fo4) => 275ps | |
585 | // (rs1_parity_e -> rs1_ne_e): inv(fo4) -> nand3(fo4) => 55ps | |
586 | // (rs1_ne_e -> rs_to_correct) | |
587 | // buffer(fo4)(4 levels) -> nand3(fo1) -> nand3(fo4) => 165ps | |
588 | // --------- | |
589 | // 495ps | |
590 | // | |
591 | ///////////////////////////////////////////////////////////////////////////// | |
592 | ||
593 | ||
594 | assign check_e[7:0] = ({8{~rs1_ne_e }} & {rs1_parity_e,q1_e[6:0]}) | | |
595 | ({8{ rs1_ne_e & ~rs2_ne_e}} & {rs2_parity_e,q2_e[6:0]}) | | |
596 | ({8{ rs1_ne_e & rs2_ne_e}} & {rs3_parity_e,q3_e[6:0]}); | |
597 | ||
598 | assign addr_e[4:0] = ({5{~rs1_ne_e }} & ect_rs1_addr_e[4:0]) | | |
599 | ({5{ rs1_ne_e & ~rs2_ne_e}} & ect_rs2_addr_e[4:0]) | | |
600 | ({5{ rs1_ne_e & rs2_ne_e}} & ect_rs3_addr_e[4:0]); | |
601 | ||
602 | ||
603 | exu_ecc_ctl_msff_ctl_macro__width_8 check_e_to_m ( | |
604 | .scan_in(check_e_to_m_scanin), | |
605 | .scan_out(check_e_to_m_scanout), | |
606 | .l1clk( l1clk_pm2 ), | |
607 | .din ( check_e[7:0] ), | |
608 | .dout ( exu_ecc_check_m[7:0] ), | |
609 | .siclk(siclk), | |
610 | .soclk(soclk)); | |
611 | ||
612 | ||
613 | exu_ecc_ctl_msff_ctl_macro__width_5 addr_e_to_m ( | |
614 | .scan_in(addr_e_to_m_scanin), | |
615 | .scan_out(addr_e_to_m_scanout), | |
616 | .l1clk( l1clk_pm2 ), | |
617 | .din ( addr_e[4:0] ), | |
618 | .dout ( exu_ecc_addr_m[4:0] ), | |
619 | .siclk(siclk), | |
620 | .soclk(soclk)); | |
621 | ||
622 | ||
623 | ||
624 | ||
625 | // control signals for other blocks | |
626 | // ------------------------------------------- | |
627 | assign cecc_e = rs1_ce_e | (rs1_ne_e & rs2_ce_e) | (rs1_ne_e & rs2_ne_e & rs3_ce_e); | |
628 | assign uecc_e = rs1_ue_e | (rs1_ne_e & rs2_ue_e) | (rs1_ne_e & rs2_ne_e & rs3_ue_e); | |
629 | ||
630 | assign ecc_ecc_e = ecc_enable_e & (uecc_e | cecc_e); | |
631 | assign ecc_uecc_e = ecc_enable_e & uecc_e; | |
632 | assign ecc_cecc_e = ecc_enable_e & cecc_e; | |
633 | ||
634 | exu_ecc_ctl_msff_ctl_macro__width_3 ce_ue_ecc_flops ( | |
635 | .scan_in(ce_ue_ecc_flops_scanin), | |
636 | .scan_out(ce_ue_ecc_flops_scanout), | |
637 | .l1clk( l1clk_pm2 ), | |
638 | .din ({ecc_ecc_e, ecc_cecc_e, ecc_uecc_e} ), | |
639 | .dout ({exu_ecc_m, exu_cecc_m, exu_uecc_m} ), | |
640 | .siclk(siclk), | |
641 | .soclk(soclk)); | |
642 | ||
643 | ///////////////////////////////////////////////////////////////////////////// | |
644 | //*************************************************************************** | |
645 | //***** ECC Generation ****************************************************** | |
646 | //*************************************************************************** | |
647 | ///////////////////////////////////////////////////////////////////////////// | |
648 | // ECC Generation | |
649 | //----------------------------------- | |
650 | // - Encode the 64-bit write data into an 8-bit Error Correction Code | |
651 | // - Encode is first done in two stages: | |
652 | // - IRF write happens in phase 2 of write stage | |
653 | // - ECC will take longer than phase 1 of write stage | |
654 | // - ECC logic will spill over to phase 2 of the stage before write. | |
655 | // - WARNING: this may change as we explore ways to speed up ECC generation | |
656 | // | |
657 | // din= d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 | |
658 | // p0 = x x x x x x x x x x | |
659 | // p1 = x x x x x x x x x | |
660 | // p2 = x x x x x x x x x | |
661 | // p3 = x x x x x x x | |
662 | // p4 = x x x x x | |
663 | // p5 = | |
664 | // p6 = | |
665 | // p7 = x x x x x x x x x x | |
666 | // ------------------------------------------------------------------- | |
667 | // Total 3 3 3 3 3 3 3 3 3 3 5 3 3 3 3 3 | |
668 | // | |
669 | // din=d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 | |
670 | // p0 = x x x x x x x x | |
671 | // p1 = x x x x x x x x x | |
672 | // p2 = x x x x x x x x x | |
673 | // p3 = x x x x x x x x | |
674 | // p4 = x x x x x x x x x x | |
675 | // p5 = x x x x x x | |
676 | // p6 = | |
677 | // p7 = x x x x x x x x | |
678 | // ------------------------------------------------------------------- | |
679 | // total 3 5 3 3 3 5 3 5 5 5 3 3 3 3 3 3 | |
680 | // | |
681 | // din=d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 | |
682 | // p0 = x x x x x x x x | |
683 | // p1 = x x x x x x x x | |
684 | // p2 = x x x x x x x x | |
685 | // p3 = x x x x x x x x | |
686 | // p4 = x x x x x x x | |
687 | // p5 = x x x x x x x x x x x x x x x x | |
688 | // p6 = | |
689 | // p7 = x x x x x x x x x | |
690 | // ------------------------------------------------------------------- | |
691 | // total 5 3 3 3 5 3 5 5 5 3 3 3 5 3 5 5 | |
692 | // | |
693 | // din=d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 | |
694 | // p0 = x x x x x x x x x | |
695 | // p1 = x x x x x x x x x | |
696 | // p2 = x x x x x x x x x | |
697 | // p3 = x x x x x x x x | |
698 | // p4 = x x x x x x x x x | |
699 | // p5 = x x x x x x x x x | |
700 | // p6 = x x x x x x x | |
701 | // p7 = x x x x x x x x | |
702 | // ------------------------------------------------------------------- | |
703 | // total 5 3 5 5 5 5 5 5 7 3 3 3 3 3 3 5 | |
704 | // | |
705 | ///////////////////////////////////////////////////////////////////////////// | |
706 | ||
707 | // Error injection logic for ECC logic testing | |
708 | // - inject error if it is enabled | |
709 | // - the 8-bit ecc_mask is only xored with W port, not W2 port | |
710 | // - xor takes place as part of the W port ECC generation. | |
711 | ||
712 | assign ecc_mask_b[7:0] = {8{ecc_mask_en_ff}} & ecc_mask_data_ff[7:0]; | |
713 | ||
714 | ||
715 | // W port ECC Generation | |
716 | // ------------------------------------------- | |
717 | // assign shorter name to w port write data to make later code more readable | |
718 | assign w_d[63:0] = edp_rd_ff_w[63:0]; | |
719 | assign ecc_w_synd_w[7:0] = ({8{~ect_mbist_sel}} & w_p_b[7:0]) | ({8{ ect_mbist_sel}} & mbi_write_data_p2[7:0]); | |
720 | ||
721 | ||
722 | // w_p_b[0] | |
723 | assign w_p_b[0] = ((w_d[0] ^ w_d[1]) ^ (w_d[3] ^ w_d[4] )) ^ | |
724 | ((w_d[6] ^ w_d[8]) ^ (w_d[10] ^ w_d[11])) ^ | |
725 | ((w_d[13] ^ w_d[15]) ^ (w_d[17] ^ w_d[19])) ^ | |
726 | ((w_d[21] ^ w_d[23]) ^ (w_d[25] ^ w_d[26])) ^ | |
727 | ((w_d[28] ^ w_d[30]) ^ (w_d[32] ^ w_d[34])) ^ | |
728 | ((w_d[36] ^ w_d[38]) ^ (w_d[40] ^ w_d[42])) ^ | |
729 | ((w_d[44] ^ w_d[46]) ^ (w_d[48] ^ w_d[50])) ^ | |
730 | ((w_d[52] ^ w_d[54]) ^ (w_d[56] ^ w_d[57])) ^ | |
731 | ((w_d[59] ^ w_d[61]) ^ (w_d[63] ^ ecc_mask_b[0])); | |
732 | ||
733 | // w_p_b[1] | |
734 | assign w_p_b[1] = ((w_d[0] ^ w_d[2] ) ^ (w_d[3] ^ w_d[5] )) ^ | |
735 | ((w_d[6] ^ w_d[9] ) ^ (w_d[10] ^ w_d[12])) ^ | |
736 | ((w_d[13] ^ w_d[16]) ^ (w_d[17] ^ w_d[20])) ^ | |
737 | ((w_d[21] ^ w_d[24]) ^ (w_d[25] ^ w_d[27])) ^ | |
738 | ((w_d[28] ^ w_d[31]) ^ (w_d[32] ^ w_d[35])) ^ | |
739 | ((w_d[36] ^ w_d[39]) ^ (w_d[40] ^ w_d[43])) ^ | |
740 | ((w_d[44] ^ w_d[47]) ^ (w_d[48] ^ w_d[51])) ^ | |
741 | ((w_d[52] ^ w_d[55]) ^ (w_d[56] ^ w_d[58])) ^ | |
742 | ((w_d[59] ^ w_d[62]) ^ (w_d[63] ^ ecc_mask_b[1])); | |
743 | ||
744 | // w_p_b[2] | |
745 | assign w_p_b[2] = ((w_d[1] ^ w_d[2] ) ^ (w_d[3] ^ w_d[7] )) ^ | |
746 | ((w_d[8] ^ w_d[9] ) ^ (w_d[10] ^ w_d[14])) ^ | |
747 | ((w_d[15] ^ w_d[16]) ^ (w_d[17] ^ w_d[22])) ^ | |
748 | ((w_d[23] ^ w_d[24]) ^ (w_d[25] ^ w_d[29])) ^ | |
749 | ((w_d[30] ^ w_d[31]) ^ (w_d[32] ^ w_d[37])) ^ | |
750 | ((w_d[38] ^ w_d[39]) ^ (w_d[40] ^ w_d[45])) ^ | |
751 | ((w_d[46] ^ w_d[47]) ^ (w_d[48] ^ w_d[53])) ^ | |
752 | ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ w_d[60])) ^ | |
753 | ((w_d[61] ^ w_d[62]) ^ (w_d[63] ^ ecc_mask_b[2])); | |
754 | ||
755 | // w_p_b[3] | |
756 | assign w_p_b[3] = ((w_d[4] ^ w_d[5] ) ^ (w_d[6] ^ w_d[7] )) ^ | |
757 | ((w_d[8] ^ w_d[9] ) ^ (w_d[10] ^ w_d[18])) ^ | |
758 | ((w_d[19] ^ w_d[20]) ^ (w_d[21] ^ w_d[22])) ^ | |
759 | ((w_d[23] ^ w_d[24]) ^ (w_d[25] ^ w_d[33])) ^ | |
760 | ((w_d[34] ^ w_d[35]) ^ (w_d[36] ^ w_d[37])) ^ | |
761 | ((w_d[38] ^ w_d[39]) ^ (w_d[40] ^ w_d[49])) ^ | |
762 | ((w_d[50] ^ w_d[51]) ^ (w_d[52] ^ w_d[53])) ^ | |
763 | ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ ecc_mask_b[3])); | |
764 | ||
765 | // w_p_b[4] | |
766 | assign w_p_b[4] = ((w_d[11] ^ w_d[12]) ^ (w_d[13] ^ w_d[14])) ^ | |
767 | ((w_d[15] ^ w_d[16]) ^ (w_d[17] ^ w_d[18])) ^ | |
768 | ((w_d[19] ^ w_d[20]) ^ (w_d[21] ^ w_d[22])) ^ | |
769 | ((w_d[23] ^ w_d[24]) ^ (w_d[25] ^ w_d[41])) ^ | |
770 | ((w_d[42] ^ w_d[43]) ^ (w_d[44] ^ w_d[45])) ^ | |
771 | ((w_d[46] ^ w_d[47]) ^ (w_d[48] ^ w_d[49])) ^ | |
772 | ((w_d[50] ^ w_d[51]) ^ (w_d[52] ^ w_d[53])) ^ | |
773 | ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ ecc_mask_b[4])); | |
774 | ||
775 | // w_p_b[5] | |
776 | assign w_p_b[5] = ((w_d[26] ^ w_d[27]) ^ (w_d[28] ^ w_d[29])) ^ | |
777 | ((w_d[30] ^ w_d[31]) ^ (w_d[32] ^ w_d[33])) ^ | |
778 | ((w_d[34] ^ w_d[35]) ^ (w_d[36] ^ w_d[37])) ^ | |
779 | ((w_d[38] ^ w_d[39]) ^ (w_d[40] ^ w_d[41])) ^ | |
780 | ((w_d[42] ^ w_d[43]) ^ (w_d[44] ^ w_d[45])) ^ | |
781 | ((w_d[46] ^ w_d[47]) ^ (w_d[48] ^ w_d[49])) ^ | |
782 | ((w_d[50] ^ w_d[51]) ^ (w_d[52] ^ w_d[53])) ^ | |
783 | ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ ecc_mask_b[5])); | |
784 | ||
785 | // w_p_b[6] | |
786 | assign w_p_b[6] = ((w_d[57] ^ w_d[58]) ^ (w_d[59] ^ w_d[60])) ^ | |
787 | ((w_d[61] ^ w_d[62]) ^ (w_d[63] ^ ecc_mask_b[6])); | |
788 | ||
789 | // w_p_b[7] | |
790 | assign w_p_b[7] = ((w_d[0] ^ w_d[1] ) ^ (w_d[2] ^ w_d[4] )) ^ | |
791 | ((w_d[5] ^ w_d[7] ) ^ (w_d[10] ^ w_d[11])) ^ | |
792 | ((w_d[12] ^ w_d[14]) ^ (w_d[17] ^ w_d[18])) ^ | |
793 | ((w_d[21] ^ w_d[23]) ^ (w_d[24] ^ w_d[26])) ^ | |
794 | ((w_d[27] ^ w_d[29]) ^ (w_d[32] ^ w_d[33])) ^ | |
795 | ((w_d[36] ^ w_d[38]) ^ (w_d[39] ^ w_d[41])) ^ | |
796 | ((w_d[44] ^ w_d[46]) ^ (w_d[47] ^ w_d[50])) ^ | |
797 | ((w_d[51] ^ w_d[53]) ^ (w_d[56] ^ w_d[57])) ^ | |
798 | ((w_d[58] ^ w_d[60]) ^ (w_d[63] ^ ecc_mask_b[7])); | |
799 | ||
800 | ||
801 | ||
802 | // W2 port ECC Generation | |
803 | // ------------------------------------------- | |
804 | // assign shorter name to w port write data to make later code more readable | |
805 | assign w2_d[63:0] = edp_rd_ff_w2[63:0]; | |
806 | assign ecc_w2_synd_w2[7:0] = w2_p_w[7:0]; | |
807 | ||
808 | ||
809 | // w2_p_w[0] | |
810 | assign w2_p_w[0] = ((w2_d[0] ^ w2_d[1]) ^ (w2_d[3] ^ w2_d[4] )) ^ | |
811 | ((w2_d[6] ^ w2_d[8]) ^ (w2_d[10] ^ w2_d[11])) ^ | |
812 | ((w2_d[13] ^ w2_d[15]) ^ (w2_d[17] ^ w2_d[19])) ^ | |
813 | ((w2_d[21] ^ w2_d[23]) ^ (w2_d[25] ^ w2_d[26])) ^ | |
814 | ((w2_d[28] ^ w2_d[30]) ^ (w2_d[32] ^ w2_d[34])) ^ | |
815 | ((w2_d[36] ^ w2_d[38]) ^ (w2_d[40] ^ w2_d[42])) ^ | |
816 | ((w2_d[44] ^ w2_d[46]) ^ (w2_d[48] ^ w2_d[50])) ^ | |
817 | ((w2_d[52] ^ w2_d[54]) ^ (w2_d[56] ^ w2_d[57])) ^ | |
818 | ((w2_d[59] ^ w2_d[61]) ^ (w2_d[63] ^ ecc_mask_b[0])); | |
819 | ||
820 | // w2_p_w[1] | |
821 | assign w2_p_w[1] = ((w2_d[0] ^ w2_d[2] ) ^ (w2_d[3] ^ w2_d[5] )) ^ | |
822 | ((w2_d[6] ^ w2_d[9] ) ^ (w2_d[10] ^ w2_d[12])) ^ | |
823 | ((w2_d[13] ^ w2_d[16]) ^ (w2_d[17] ^ w2_d[20])) ^ | |
824 | ((w2_d[21] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[27])) ^ | |
825 | ((w2_d[28] ^ w2_d[31]) ^ (w2_d[32] ^ w2_d[35])) ^ | |
826 | ((w2_d[36] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[43])) ^ | |
827 | ((w2_d[44] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[51])) ^ | |
828 | ((w2_d[52] ^ w2_d[55]) ^ (w2_d[56] ^ w2_d[58])) ^ | |
829 | ((w2_d[59] ^ w2_d[62]) ^ (w2_d[63] ^ ecc_mask_b[1])); | |
830 | ||
831 | // w2_p_w[2] | |
832 | assign w2_p_w[2] = ((w2_d[1] ^ w2_d[2] ) ^ (w2_d[3] ^ w2_d[7] )) ^ | |
833 | ((w2_d[8] ^ w2_d[9] ) ^ (w2_d[10] ^ w2_d[14])) ^ | |
834 | ((w2_d[15] ^ w2_d[16]) ^ (w2_d[17] ^ w2_d[22])) ^ | |
835 | ((w2_d[23] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[29])) ^ | |
836 | ((w2_d[30] ^ w2_d[31]) ^ (w2_d[32] ^ w2_d[37])) ^ | |
837 | ((w2_d[38] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[45])) ^ | |
838 | ((w2_d[46] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[53])) ^ | |
839 | ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ w2_d[60])) ^ | |
840 | ((w2_d[61] ^ w2_d[62]) ^ (w2_d[63] ^ ecc_mask_b[2])); | |
841 | ||
842 | // w2_p_w[3] | |
843 | assign w2_p_w[3] = ((w2_d[4] ^ w2_d[5] ) ^ (w2_d[6] ^ w2_d[7] )) ^ | |
844 | ((w2_d[8] ^ w2_d[9] ) ^ (w2_d[10] ^ w2_d[18])) ^ | |
845 | ((w2_d[19] ^ w2_d[20]) ^ (w2_d[21] ^ w2_d[22])) ^ | |
846 | ((w2_d[23] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[33])) ^ | |
847 | ((w2_d[34] ^ w2_d[35]) ^ (w2_d[36] ^ w2_d[37])) ^ | |
848 | ((w2_d[38] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[49])) ^ | |
849 | ((w2_d[50] ^ w2_d[51]) ^ (w2_d[52] ^ w2_d[53])) ^ | |
850 | ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ ecc_mask_b[3])); | |
851 | ||
852 | // w2_p_w[4] | |
853 | assign w2_p_w[4] = ((w2_d[11] ^ w2_d[12]) ^ (w2_d[13] ^ w2_d[14])) ^ | |
854 | ((w2_d[15] ^ w2_d[16]) ^ (w2_d[17] ^ w2_d[18])) ^ | |
855 | ((w2_d[19] ^ w2_d[20]) ^ (w2_d[21] ^ w2_d[22])) ^ | |
856 | ((w2_d[23] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[41])) ^ | |
857 | ((w2_d[42] ^ w2_d[43]) ^ (w2_d[44] ^ w2_d[45])) ^ | |
858 | ((w2_d[46] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[49])) ^ | |
859 | ((w2_d[50] ^ w2_d[51]) ^ (w2_d[52] ^ w2_d[53])) ^ | |
860 | ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ ecc_mask_b[4])); | |
861 | ||
862 | // w2_p_w[5] | |
863 | assign w2_p_w[5] = ((w2_d[26] ^ w2_d[27]) ^ (w2_d[28] ^ w2_d[29])) ^ | |
864 | ((w2_d[30] ^ w2_d[31]) ^ (w2_d[32] ^ w2_d[33])) ^ | |
865 | ((w2_d[34] ^ w2_d[35]) ^ (w2_d[36] ^ w2_d[37])) ^ | |
866 | ((w2_d[38] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[41])) ^ | |
867 | ((w2_d[42] ^ w2_d[43]) ^ (w2_d[44] ^ w2_d[45])) ^ | |
868 | ((w2_d[46] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[49])) ^ | |
869 | ((w2_d[50] ^ w2_d[51]) ^ (w2_d[52] ^ w2_d[53])) ^ | |
870 | ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ ecc_mask_b[5])); | |
871 | ||
872 | // w2_p_w[6] | |
873 | assign w2_p_w[6] = ((w2_d[57] ^ w2_d[58]) ^ (w2_d[59] ^ w2_d[60])) ^ | |
874 | ((w2_d[61] ^ w2_d[62]) ^ (w2_d[63] ^ ecc_mask_b[6])); | |
875 | ||
876 | // w2_p_w[7] | |
877 | assign w2_p_w[7] = ((w2_d[0] ^ w2_d[1] ) ^ (w2_d[2] ^ w2_d[4] )) ^ | |
878 | ((w2_d[5] ^ w2_d[7] ) ^ (w2_d[10] ^ w2_d[11])) ^ | |
879 | ((w2_d[12] ^ w2_d[14]) ^ (w2_d[17] ^ w2_d[18])) ^ | |
880 | ((w2_d[21] ^ w2_d[23]) ^ (w2_d[24] ^ w2_d[26])) ^ | |
881 | ((w2_d[27] ^ w2_d[29]) ^ (w2_d[32] ^ w2_d[33])) ^ | |
882 | ((w2_d[36] ^ w2_d[38]) ^ (w2_d[39] ^ w2_d[41])) ^ | |
883 | ((w2_d[44] ^ w2_d[46]) ^ (w2_d[47] ^ w2_d[50])) ^ | |
884 | ((w2_d[51] ^ w2_d[53]) ^ (w2_d[56] ^ w2_d[57])) ^ | |
885 | ((w2_d[58] ^ w2_d[60]) ^ (w2_d[63] ^ ecc_mask_b[7])); | |
886 | ||
887 | ||
888 | ||
889 | exu_ecc_ctl_spare_ctl_macro__num_4 spares ( | |
890 | .scan_in(spares_scanin), | |
891 | .scan_out(spares_scanout), | |
892 | .l1clk (l1clk_pm1), | |
893 | .siclk(siclk), | |
894 | .soclk(soclk)); | |
895 | ||
896 | ||
897 | supply0 vss; | |
898 | supply1 vdd; | |
899 | ||
900 | // fixscan start: | |
901 | assign mbist_ff_scanin = scan_in ; | |
902 | assign debug_ff_scanin = mbist_ff_scanout ; | |
903 | assign check_e_to_m_scanin = debug_ff_scanout ; | |
904 | assign addr_e_to_m_scanin = check_e_to_m_scanout ; | |
905 | assign ce_ue_ecc_flops_scanin = addr_e_to_m_scanout ; | |
906 | assign spares_scanin = ce_ue_ecc_flops_scanout ; | |
907 | assign scan_out = spares_scanout ; | |
908 | // fixscan end: | |
909 | endmodule | |
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | // any PARAMS parms go into naming of macro | |
917 | ||
918 | module exu_ecc_ctl_l1clkhdr_ctl_macro ( | |
919 | l2clk, | |
920 | l1en, | |
921 | pce_ov, | |
922 | stop, | |
923 | se, | |
924 | l1clk); | |
925 | ||
926 | ||
927 | input l2clk; | |
928 | input l1en; | |
929 | input pce_ov; | |
930 | input stop; | |
931 | input se; | |
932 | output l1clk; | |
933 | ||
934 | ||
935 | ||
936 | ||
937 | ||
938 | cl_sc1_l1hdr_8x c_0 ( | |
939 | ||
940 | ||
941 | .l2clk(l2clk), | |
942 | .pce(l1en), | |
943 | .l1clk(l1clk), | |
944 | .se(se), | |
945 | .pce_ov(pce_ov), | |
946 | .stop(stop) | |
947 | ); | |
948 | ||
949 | ||
950 | ||
951 | endmodule | |
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | ||
960 | ||
961 | ||
962 | ||
963 | ||
964 | ||
965 | // any PARAMS parms go into naming of macro | |
966 | ||
967 | module exu_ecc_ctl_msff_ctl_macro__width_24 ( | |
968 | din, | |
969 | l1clk, | |
970 | scan_in, | |
971 | siclk, | |
972 | soclk, | |
973 | dout, | |
974 | scan_out); | |
975 | wire [23:0] fdin; | |
976 | wire [22:0] so; | |
977 | ||
978 | input [23:0] din; | |
979 | input l1clk; | |
980 | input scan_in; | |
981 | ||
982 | ||
983 | input siclk; | |
984 | input soclk; | |
985 | ||
986 | output [23:0] dout; | |
987 | output scan_out; | |
988 | assign fdin[23:0] = din[23:0]; | |
989 | ||
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | dff #(24) d0_0 ( | |
996 | .l1clk(l1clk), | |
997 | .siclk(siclk), | |
998 | .soclk(soclk), | |
999 | .d(fdin[23:0]), | |
1000 | .si({scan_in,so[22:0]}), | |
1001 | .so({so[22:0],scan_out}), | |
1002 | .q(dout[23:0]) | |
1003 | ); | |
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | endmodule | |
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | // any PARAMS parms go into naming of macro | |
1031 | ||
1032 | module exu_ecc_ctl_msff_ctl_macro__width_14 ( | |
1033 | din, | |
1034 | l1clk, | |
1035 | scan_in, | |
1036 | siclk, | |
1037 | soclk, | |
1038 | dout, | |
1039 | scan_out); | |
1040 | wire [13:0] fdin; | |
1041 | wire [12:0] so; | |
1042 | ||
1043 | input [13:0] din; | |
1044 | input l1clk; | |
1045 | input scan_in; | |
1046 | ||
1047 | ||
1048 | input siclk; | |
1049 | input soclk; | |
1050 | ||
1051 | output [13:0] dout; | |
1052 | output scan_out; | |
1053 | assign fdin[13:0] = din[13:0]; | |
1054 | ||
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | dff #(14) d0_0 ( | |
1061 | .l1clk(l1clk), | |
1062 | .siclk(siclk), | |
1063 | .soclk(soclk), | |
1064 | .d(fdin[13:0]), | |
1065 | .si({scan_in,so[12:0]}), | |
1066 | .so({so[12:0],scan_out}), | |
1067 | .q(dout[13:0]) | |
1068 | ); | |
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | endmodule | |
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | ||
1095 | // any PARAMS parms go into naming of macro | |
1096 | ||
1097 | module exu_ecc_ctl_msff_ctl_macro__width_8 ( | |
1098 | din, | |
1099 | l1clk, | |
1100 | scan_in, | |
1101 | siclk, | |
1102 | soclk, | |
1103 | dout, | |
1104 | scan_out); | |
1105 | wire [7:0] fdin; | |
1106 | wire [6:0] so; | |
1107 | ||
1108 | input [7:0] din; | |
1109 | input l1clk; | |
1110 | input scan_in; | |
1111 | ||
1112 | ||
1113 | input siclk; | |
1114 | input soclk; | |
1115 | ||
1116 | output [7:0] dout; | |
1117 | output scan_out; | |
1118 | assign fdin[7:0] = din[7:0]; | |
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | dff #(8) d0_0 ( | |
1126 | .l1clk(l1clk), | |
1127 | .siclk(siclk), | |
1128 | .soclk(soclk), | |
1129 | .d(fdin[7:0]), | |
1130 | .si({scan_in,so[6:0]}), | |
1131 | .so({so[6:0],scan_out}), | |
1132 | .q(dout[7:0]) | |
1133 | ); | |
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 | ||
1142 | ||
1143 | ||
1144 | ||
1145 | ||
1146 | endmodule | |
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | ||
1159 | ||
1160 | // any PARAMS parms go into naming of macro | |
1161 | ||
1162 | module exu_ecc_ctl_msff_ctl_macro__width_5 ( | |
1163 | din, | |
1164 | l1clk, | |
1165 | scan_in, | |
1166 | siclk, | |
1167 | soclk, | |
1168 | dout, | |
1169 | scan_out); | |
1170 | wire [4:0] fdin; | |
1171 | wire [3:0] so; | |
1172 | ||
1173 | input [4:0] din; | |
1174 | input l1clk; | |
1175 | input scan_in; | |
1176 | ||
1177 | ||
1178 | input siclk; | |
1179 | input soclk; | |
1180 | ||
1181 | output [4:0] dout; | |
1182 | output scan_out; | |
1183 | assign fdin[4:0] = din[4:0]; | |
1184 | ||
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | dff #(5) d0_0 ( | |
1191 | .l1clk(l1clk), | |
1192 | .siclk(siclk), | |
1193 | .soclk(soclk), | |
1194 | .d(fdin[4:0]), | |
1195 | .si({scan_in,so[3:0]}), | |
1196 | .so({so[3:0],scan_out}), | |
1197 | .q(dout[4:0]) | |
1198 | ); | |
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | endmodule | |
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | ||
1222 | ||
1223 | ||
1224 | ||
1225 | // any PARAMS parms go into naming of macro | |
1226 | ||
1227 | module exu_ecc_ctl_msff_ctl_macro__width_3 ( | |
1228 | din, | |
1229 | l1clk, | |
1230 | scan_in, | |
1231 | siclk, | |
1232 | soclk, | |
1233 | dout, | |
1234 | scan_out); | |
1235 | wire [2:0] fdin; | |
1236 | wire [1:0] so; | |
1237 | ||
1238 | input [2:0] din; | |
1239 | input l1clk; | |
1240 | input scan_in; | |
1241 | ||
1242 | ||
1243 | input siclk; | |
1244 | input soclk; | |
1245 | ||
1246 | output [2:0] dout; | |
1247 | output scan_out; | |
1248 | assign fdin[2:0] = din[2:0]; | |
1249 | ||
1250 | ||
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | dff #(3) d0_0 ( | |
1256 | .l1clk(l1clk), | |
1257 | .siclk(siclk), | |
1258 | .soclk(soclk), | |
1259 | .d(fdin[2:0]), | |
1260 | .si({scan_in,so[1:0]}), | |
1261 | .so({so[1:0],scan_out}), | |
1262 | .q(dout[2:0]) | |
1263 | ); | |
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | endmodule | |
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | // Description: Spare gate macro for control blocks | |
1287 | // | |
1288 | // Param num controls the number of times the macro is added | |
1289 | // flops=0 can be used to use only combination spare logic | |
1290 | ||
1291 | ||
1292 | module exu_ecc_ctl_spare_ctl_macro__num_4 ( | |
1293 | l1clk, | |
1294 | scan_in, | |
1295 | siclk, | |
1296 | soclk, | |
1297 | scan_out); | |
1298 | wire si_0; | |
1299 | wire so_0; | |
1300 | wire spare0_flop_unused; | |
1301 | wire spare0_buf_32x_unused; | |
1302 | wire spare0_nand3_8x_unused; | |
1303 | wire spare0_inv_8x_unused; | |
1304 | wire spare0_aoi22_4x_unused; | |
1305 | wire spare0_buf_8x_unused; | |
1306 | wire spare0_oai22_4x_unused; | |
1307 | wire spare0_inv_16x_unused; | |
1308 | wire spare0_nand2_16x_unused; | |
1309 | wire spare0_nor3_4x_unused; | |
1310 | wire spare0_nand2_8x_unused; | |
1311 | wire spare0_buf_16x_unused; | |
1312 | wire spare0_nor2_16x_unused; | |
1313 | wire spare0_inv_32x_unused; | |
1314 | wire si_1; | |
1315 | wire so_1; | |
1316 | wire spare1_flop_unused; | |
1317 | wire spare1_buf_32x_unused; | |
1318 | wire spare1_nand3_8x_unused; | |
1319 | wire spare1_inv_8x_unused; | |
1320 | wire spare1_aoi22_4x_unused; | |
1321 | wire spare1_buf_8x_unused; | |
1322 | wire spare1_oai22_4x_unused; | |
1323 | wire spare1_inv_16x_unused; | |
1324 | wire spare1_nand2_16x_unused; | |
1325 | wire spare1_nor3_4x_unused; | |
1326 | wire spare1_nand2_8x_unused; | |
1327 | wire spare1_buf_16x_unused; | |
1328 | wire spare1_nor2_16x_unused; | |
1329 | wire spare1_inv_32x_unused; | |
1330 | wire si_2; | |
1331 | wire so_2; | |
1332 | wire spare2_flop_unused; | |
1333 | wire spare2_buf_32x_unused; | |
1334 | wire spare2_nand3_8x_unused; | |
1335 | wire spare2_inv_8x_unused; | |
1336 | wire spare2_aoi22_4x_unused; | |
1337 | wire spare2_buf_8x_unused; | |
1338 | wire spare2_oai22_4x_unused; | |
1339 | wire spare2_inv_16x_unused; | |
1340 | wire spare2_nand2_16x_unused; | |
1341 | wire spare2_nor3_4x_unused; | |
1342 | wire spare2_nand2_8x_unused; | |
1343 | wire spare2_buf_16x_unused; | |
1344 | wire spare2_nor2_16x_unused; | |
1345 | wire spare2_inv_32x_unused; | |
1346 | wire si_3; | |
1347 | wire so_3; | |
1348 | wire spare3_flop_unused; | |
1349 | wire spare3_buf_32x_unused; | |
1350 | wire spare3_nand3_8x_unused; | |
1351 | wire spare3_inv_8x_unused; | |
1352 | wire spare3_aoi22_4x_unused; | |
1353 | wire spare3_buf_8x_unused; | |
1354 | wire spare3_oai22_4x_unused; | |
1355 | wire spare3_inv_16x_unused; | |
1356 | wire spare3_nand2_16x_unused; | |
1357 | wire spare3_nor3_4x_unused; | |
1358 | wire spare3_nand2_8x_unused; | |
1359 | wire spare3_buf_16x_unused; | |
1360 | wire spare3_nor2_16x_unused; | |
1361 | wire spare3_inv_32x_unused; | |
1362 | ||
1363 | ||
1364 | input l1clk; | |
1365 | input scan_in; | |
1366 | input siclk; | |
1367 | input soclk; | |
1368 | output scan_out; | |
1369 | ||
1370 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1371 | .siclk(siclk), | |
1372 | .soclk(soclk), | |
1373 | .si(si_0), | |
1374 | .so(so_0), | |
1375 | .d(1'b0), | |
1376 | .q(spare0_flop_unused)); | |
1377 | assign si_0 = scan_in; | |
1378 | ||
1379 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1380 | .out(spare0_buf_32x_unused)); | |
1381 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1382 | .in1(1'b1), | |
1383 | .in2(1'b1), | |
1384 | .out(spare0_nand3_8x_unused)); | |
1385 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1386 | .out(spare0_inv_8x_unused)); | |
1387 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1388 | .in01(1'b1), | |
1389 | .in10(1'b1), | |
1390 | .in11(1'b1), | |
1391 | .out(spare0_aoi22_4x_unused)); | |
1392 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1393 | .out(spare0_buf_8x_unused)); | |
1394 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1395 | .in01(1'b1), | |
1396 | .in10(1'b1), | |
1397 | .in11(1'b1), | |
1398 | .out(spare0_oai22_4x_unused)); | |
1399 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1400 | .out(spare0_inv_16x_unused)); | |
1401 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1402 | .in1(1'b1), | |
1403 | .out(spare0_nand2_16x_unused)); | |
1404 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1405 | .in1(1'b0), | |
1406 | .in2(1'b0), | |
1407 | .out(spare0_nor3_4x_unused)); | |
1408 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1409 | .in1(1'b1), | |
1410 | .out(spare0_nand2_8x_unused)); | |
1411 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1412 | .out(spare0_buf_16x_unused)); | |
1413 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1414 | .in1(1'b0), | |
1415 | .out(spare0_nor2_16x_unused)); | |
1416 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1417 | .out(spare0_inv_32x_unused)); | |
1418 | ||
1419 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1420 | .siclk(siclk), | |
1421 | .soclk(soclk), | |
1422 | .si(si_1), | |
1423 | .so(so_1), | |
1424 | .d(1'b0), | |
1425 | .q(spare1_flop_unused)); | |
1426 | assign si_1 = so_0; | |
1427 | ||
1428 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1429 | .out(spare1_buf_32x_unused)); | |
1430 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1431 | .in1(1'b1), | |
1432 | .in2(1'b1), | |
1433 | .out(spare1_nand3_8x_unused)); | |
1434 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1435 | .out(spare1_inv_8x_unused)); | |
1436 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1437 | .in01(1'b1), | |
1438 | .in10(1'b1), | |
1439 | .in11(1'b1), | |
1440 | .out(spare1_aoi22_4x_unused)); | |
1441 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1442 | .out(spare1_buf_8x_unused)); | |
1443 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1444 | .in01(1'b1), | |
1445 | .in10(1'b1), | |
1446 | .in11(1'b1), | |
1447 | .out(spare1_oai22_4x_unused)); | |
1448 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1449 | .out(spare1_inv_16x_unused)); | |
1450 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1451 | .in1(1'b1), | |
1452 | .out(spare1_nand2_16x_unused)); | |
1453 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1454 | .in1(1'b0), | |
1455 | .in2(1'b0), | |
1456 | .out(spare1_nor3_4x_unused)); | |
1457 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1458 | .in1(1'b1), | |
1459 | .out(spare1_nand2_8x_unused)); | |
1460 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1461 | .out(spare1_buf_16x_unused)); | |
1462 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1463 | .in1(1'b0), | |
1464 | .out(spare1_nor2_16x_unused)); | |
1465 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1466 | .out(spare1_inv_32x_unused)); | |
1467 | ||
1468 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
1469 | .siclk(siclk), | |
1470 | .soclk(soclk), | |
1471 | .si(si_2), | |
1472 | .so(so_2), | |
1473 | .d(1'b0), | |
1474 | .q(spare2_flop_unused)); | |
1475 | assign si_2 = so_1; | |
1476 | ||
1477 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
1478 | .out(spare2_buf_32x_unused)); | |
1479 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
1480 | .in1(1'b1), | |
1481 | .in2(1'b1), | |
1482 | .out(spare2_nand3_8x_unused)); | |
1483 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
1484 | .out(spare2_inv_8x_unused)); | |
1485 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
1486 | .in01(1'b1), | |
1487 | .in10(1'b1), | |
1488 | .in11(1'b1), | |
1489 | .out(spare2_aoi22_4x_unused)); | |
1490 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
1491 | .out(spare2_buf_8x_unused)); | |
1492 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
1493 | .in01(1'b1), | |
1494 | .in10(1'b1), | |
1495 | .in11(1'b1), | |
1496 | .out(spare2_oai22_4x_unused)); | |
1497 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
1498 | .out(spare2_inv_16x_unused)); | |
1499 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
1500 | .in1(1'b1), | |
1501 | .out(spare2_nand2_16x_unused)); | |
1502 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
1503 | .in1(1'b0), | |
1504 | .in2(1'b0), | |
1505 | .out(spare2_nor3_4x_unused)); | |
1506 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
1507 | .in1(1'b1), | |
1508 | .out(spare2_nand2_8x_unused)); | |
1509 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
1510 | .out(spare2_buf_16x_unused)); | |
1511 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
1512 | .in1(1'b0), | |
1513 | .out(spare2_nor2_16x_unused)); | |
1514 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
1515 | .out(spare2_inv_32x_unused)); | |
1516 | ||
1517 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
1518 | .siclk(siclk), | |
1519 | .soclk(soclk), | |
1520 | .si(si_3), | |
1521 | .so(so_3), | |
1522 | .d(1'b0), | |
1523 | .q(spare3_flop_unused)); | |
1524 | assign si_3 = so_2; | |
1525 | ||
1526 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
1527 | .out(spare3_buf_32x_unused)); | |
1528 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
1529 | .in1(1'b1), | |
1530 | .in2(1'b1), | |
1531 | .out(spare3_nand3_8x_unused)); | |
1532 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
1533 | .out(spare3_inv_8x_unused)); | |
1534 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
1535 | .in01(1'b1), | |
1536 | .in10(1'b1), | |
1537 | .in11(1'b1), | |
1538 | .out(spare3_aoi22_4x_unused)); | |
1539 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
1540 | .out(spare3_buf_8x_unused)); | |
1541 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
1542 | .in01(1'b1), | |
1543 | .in10(1'b1), | |
1544 | .in11(1'b1), | |
1545 | .out(spare3_oai22_4x_unused)); | |
1546 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
1547 | .out(spare3_inv_16x_unused)); | |
1548 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
1549 | .in1(1'b1), | |
1550 | .out(spare3_nand2_16x_unused)); | |
1551 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
1552 | .in1(1'b0), | |
1553 | .in2(1'b0), | |
1554 | .out(spare3_nor3_4x_unused)); | |
1555 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
1556 | .in1(1'b1), | |
1557 | .out(spare3_nand2_8x_unused)); | |
1558 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
1559 | .out(spare3_buf_16x_unused)); | |
1560 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
1561 | .in1(1'b0), | |
1562 | .out(spare3_nor2_16x_unused)); | |
1563 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
1564 | .out(spare3_inv_32x_unused)); | |
1565 | assign scan_out = so_3; | |
1566 | ||
1567 | ||
1568 | ||
1569 | endmodule | |
1570 |