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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ifu_cmu_csm_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ifu_cmu_csm_ctl ( | |
36 | l1clk, | |
37 | scan_in, | |
38 | spc_aclk, | |
39 | spc_bclk, | |
40 | ftu_cmiss, | |
41 | ftu_redirect, | |
42 | ftu_inv_req, | |
43 | lsc_l15_valid, | |
44 | mct_fill_complete, | |
45 | cmu_data_ready, | |
46 | cmu_has_dup_miss, | |
47 | cmu_mbhit_c, | |
48 | mct_rst_dupmiss, | |
49 | mct_ignore_cmiss, | |
50 | mdp_mbhit_q, | |
51 | csm_valid_req, | |
52 | cmu_null_st, | |
53 | cmu_dupmiss_st, | |
54 | cmu_req_st, | |
55 | cmu_canleave_st, | |
56 | scan_out) ; | |
57 | wire siclk; | |
58 | wire soclk; | |
59 | wire inv_req_reg_scanin; | |
60 | wire inv_req_reg_scanout; | |
61 | wire inv_req_ff; | |
62 | wire redirect_reg_scanin; | |
63 | wire redirect_reg_scanout; | |
64 | wire ftu_redirect_lat; | |
65 | wire go_to_null_state; | |
66 | wire null_state; | |
67 | wire req_state; | |
68 | wire canleave_state; | |
69 | wire fillwait_state; | |
70 | wire dupmiss_state; | |
71 | wire invreq_state; | |
72 | wire next_null_state_; | |
73 | wire null_state_; | |
74 | wire null_state_reg_scanin; | |
75 | wire null_state_reg_scanout; | |
76 | wire go_to_req_state; | |
77 | wire next_req_state; | |
78 | wire req_state_reg_scanin; | |
79 | wire req_state_reg_scanout; | |
80 | wire go_to_canleave_state; | |
81 | wire next_canleave_state; | |
82 | wire canleave_state_reg_scanin; | |
83 | wire canleave_state_reg_scanout; | |
84 | wire go_to_retwait_state; | |
85 | wire retwait_state; | |
86 | wire next_retwait_state; | |
87 | wire retwait_state_reg_scanin; | |
88 | wire retwait_state_reg_scanout; | |
89 | wire go_to_fillwait_state; | |
90 | wire next_fillwait_state; | |
91 | wire fillwait_state_reg_scanin; | |
92 | wire fillwait_state_reg_scanout; | |
93 | wire go_to_dupmiss_state; | |
94 | wire next_dupmiss_state; | |
95 | wire dupmiss_state_reg_scanin; | |
96 | wire dupmiss_state_reg_scanout; | |
97 | wire go_to_invreq_state; | |
98 | wire next_invreq_state; | |
99 | wire invreq_state_reg_scanin; | |
100 | wire invreq_state_reg_scanout; | |
101 | ||
102 | ||
103 | input l1clk; | |
104 | input scan_in; | |
105 | input spc_aclk; | |
106 | input spc_bclk; | |
107 | ||
108 | input ftu_cmiss; // cmiss request | |
109 | input ftu_redirect; // indicates the thread is flushed/redirected | |
110 | input ftu_inv_req; // invalidation request | |
111 | input lsc_l15_valid; // req sent to gkt | |
112 | input mct_fill_complete; // indicates that fill has been completed | |
113 | ||
114 | input cmu_data_ready; // gkt rtn data and is ready to be written to I$ | |
115 | input cmu_has_dup_miss; // from MB ctl logic, current thread has outstanding duplicate miss. | |
116 | input cmu_mbhit_c; // from MB ctl logic, current thread hits in missbuff, it is not real miss | |
117 | ||
118 | input mct_rst_dupmiss; // comes on with data_ready, all dup miss waiting on current thread are reset. | |
119 | input mct_ignore_cmiss; // current cmiss is a duplicate miss which needs to be ignored, data sent to I$. | |
120 | input mdp_mbhit_q; // A qualified mbhit | |
121 | ||
122 | ||
123 | output csm_valid_req; // valid request indicator | |
124 | output cmu_null_st; | |
125 | output cmu_dupmiss_st; | |
126 | output cmu_req_st; | |
127 | output cmu_canleave_st; | |
128 | ||
129 | ||
130 | ||
131 | output scan_out; | |
132 | ||
133 | // scan renames | |
134 | assign siclk = spc_aclk; | |
135 | assign soclk = spc_bclk; | |
136 | // end scan | |
137 | ||
138 | ||
139 | // flop inv_req. | |
140 | // It means that inv_req will not take part in arbitration for | |
141 | // two cycles after it arrives. | |
142 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 inv_req_reg ( | |
143 | .scan_in(inv_req_reg_scanin), | |
144 | .scan_out(inv_req_reg_scanout), | |
145 | .l1clk(l1clk), | |
146 | .din (ftu_inv_req), | |
147 | .dout (inv_req_ff), | |
148 | .siclk(siclk), | |
149 | .soclk(soclk) | |
150 | ); | |
151 | ||
152 | // flop ftu_redirect | |
153 | // use the delayed version for qualifying valid req. | |
154 | // clearing of wom bits in mct should also use delayed version. | |
155 | // use raw version to clear dup miss states | |
156 | ||
157 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 redirect_reg ( | |
158 | .scan_in(redirect_reg_scanin), | |
159 | .scan_out(redirect_reg_scanout), | |
160 | .l1clk(l1clk), | |
161 | .din (ftu_redirect), | |
162 | .dout (ftu_redirect_lat), | |
163 | .siclk(siclk), | |
164 | .soclk(soclk) | |
165 | ); | |
166 | ||
167 | /////////////////////////////////////////////////// | |
168 | // CASE STATEMENT DESCRIPTION OF TSM MACHINE | |
169 | /////////////////////////////////////////////////// | |
170 | //case(`CSM_STATE) | |
171 | // `NULL_ST: | |
172 | // if (~(ftu_cmiss & ~mct_ignore_cmiss) & ~inv_req_ff) | |
173 | // next_state = `NULL_ST; | |
174 | // if (ftu_cmiss & ~cmu_mbhit_c) | |
175 | // next_state = `REQ_ST; | |
176 | // if (ftu_cmiss & cmu_mbhit_c & ~ignore_cmiss) | |
177 | // next_state = `DUPMISS_ST; | |
178 | // if (inv_req_ff) | |
179 | // next_state = `INVREQ_ST; | |
180 | // | |
181 | // `REQ_ST: | |
182 | // if (lsc_l15_valid) | |
183 | // next_state = `RETWAIT_ST; | |
184 | // if (~lsc_l15_valid & ftu_redirect_lat & cmu_has_dup_miss) | |
185 | // next_state = `CANLEAVE_ST; | |
186 | // if (~lsc_l15_valid & ftu_redirect_lat & ~cmu_has_dup_miss & mdp_mbhit_q) | |
187 | // next_state = `CANLEAVE_ST; | |
188 | // if (~lsc_l15_valid & ftu_redirect_lat & ~cmu_has_dup_miss & ~mdp_mbhit_q) | |
189 | // next_state = `NULL_ST; | |
190 | // if (~lsc_l15_valid & ~ftu_redirect_lat) | |
191 | // next_state = `REQ_ST; | |
192 | // | |
193 | // `CANLEAVE_ST: | |
194 | // if (lsc_l15_valid) | |
195 | // next_state = `RETWAIT_ST; | |
196 | // if (~lsc_l15_valid & ~cmu_has_dup_miss & ~mdp_mbhit_q) | |
197 | // next_state = `NULL_ST; | |
198 | // if (~lsc_l15_valid & cmu_has_dup_miss) | |
199 | // next_state = `CANLEAVE_ST; | |
200 | // if (~lsc_l15_valid & mdp_mbhit_q) | |
201 | // next_state = `CANLEAVE_ST; | |
202 | // | |
203 | // `RETWAIT_ST: | |
204 | // if (~cmu_data_ready) | |
205 | // next_state = `RETWAIT_ST; | |
206 | // if (cmu_data_ready) | |
207 | // next_state = `FILLWAIT_ST; | |
208 | // | |
209 | // `FILLWAIT_ST: | |
210 | // if (~mct_fill_complete) | |
211 | // next_state = `FILLWAIT_ST; | |
212 | // if (mct_fill_complete) | |
213 | // next_state = `NULL_ST; | |
214 | // | |
215 | // `DUPMISS_ST: | |
216 | // if (~ftu_redirect & ~mct_rst_dupmiss) | |
217 | // next_state = `DUPMISS_ST; | |
218 | // if (ftu_redirect | mct_rst_dupmiss) | |
219 | // next_state = `NULL_ST; | |
220 | // | |
221 | // `INVREQ_ST: | |
222 | // if (lsc_l15_valid) | |
223 | // next_state = `NULL_ST; | |
224 | // if (~lsc_l15_valid) | |
225 | // next_state = `INVREQ_ST; | |
226 | // | |
227 | // endcase | |
228 | // | |
229 | // | |
230 | ||
231 | // 0in one_hot -var {null_state,req_state,canleave_state,retwait_state,fillwait_state,dupmiss_state,invreq_state} | |
232 | //////////////////////////////////////////////////////// | |
233 | // NULL STATE | |
234 | //////////////////////////////////////////////////////// | |
235 | // cmu_mbhit_c indicates a duplicate miss | |
236 | // ignore_cmiss indicates a duplicate miss which needs to be ignored | |
237 | // | |
238 | // null_st is default state. | |
239 | // | |
240 | assign go_to_null_state = (null_state & ~(ftu_cmiss & ~mct_ignore_cmiss) & ~inv_req_ff) | | |
241 | (req_state & ~lsc_l15_valid & ftu_redirect_lat & ~cmu_has_dup_miss & ~mdp_mbhit_q) | | |
242 | (canleave_state & ~lsc_l15_valid & ~cmu_has_dup_miss & ~mdp_mbhit_q) | | |
243 | (fillwait_state & mct_fill_complete) | | |
244 | (dupmiss_state & (ftu_redirect | mct_rst_dupmiss)) | | |
245 | (invreq_state & lsc_l15_valid); | |
246 | ||
247 | assign next_null_state_ = ~go_to_null_state; | |
248 | ||
249 | assign null_state = ~null_state_; | |
250 | ||
251 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 null_state_reg ( | |
252 | .scan_in(null_state_reg_scanin), | |
253 | .scan_out(null_state_reg_scanout), | |
254 | .l1clk(l1clk), | |
255 | .din (next_null_state_), | |
256 | .dout (null_state_), | |
257 | .siclk(siclk), | |
258 | .soclk(soclk) | |
259 | ); | |
260 | ||
261 | //////////////////////////////////////////////////////// | |
262 | // REQUEST STATE | |
263 | //////////////////////////////////////////////////////// | |
264 | // Go to request state on a real miss | |
265 | // Stay in request state until the request is sent out or redirect. | |
266 | assign go_to_req_state = (null_state & ftu_cmiss & ~cmu_mbhit_c) | | |
267 | (req_state & ~lsc_l15_valid & ~ftu_redirect_lat) ; | |
268 | ||
269 | assign next_req_state = go_to_req_state; | |
270 | ||
271 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 req_state_reg ( | |
272 | .scan_in(req_state_reg_scanin), | |
273 | .scan_out(req_state_reg_scanout), | |
274 | .l1clk(l1clk), | |
275 | .din (next_req_state), | |
276 | .dout (req_state), | |
277 | .siclk(siclk), | |
278 | .soclk(soclk) | |
279 | ); | |
280 | ||
281 | //////////////////////////////////////////////////////// | |
282 | // CANLEAVE STATE | |
283 | //////////////////////////////////////////////////////// | |
284 | // Go to canleave_st when a real miss is flushed, but it has | |
285 | // other outstanding duplicate misses waiting on it. | |
286 | // Leave canleave_st when the request is sent out, or it has no | |
287 | // other duplicate misses waiting on it (This can happen if | |
288 | // all duplicate misses get flushed out). | |
289 | assign go_to_canleave_state = (req_state & ftu_redirect_lat & cmu_has_dup_miss & ~lsc_l15_valid) | | |
290 | (req_state & ftu_redirect_lat & mdp_mbhit_q & ~lsc_l15_valid) | | |
291 | (canleave_state & cmu_has_dup_miss & ~lsc_l15_valid) | | |
292 | (canleave_state & mdp_mbhit_q & ~lsc_l15_valid); | |
293 | ||
294 | assign next_canleave_state = go_to_canleave_state; | |
295 | ||
296 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 canleave_state_reg ( | |
297 | .scan_in(canleave_state_reg_scanin), | |
298 | .scan_out(canleave_state_reg_scanout), | |
299 | .l1clk(l1clk), | |
300 | .din (next_canleave_state), | |
301 | .dout (canleave_state), | |
302 | .siclk(siclk), | |
303 | .soclk(soclk) | |
304 | ); | |
305 | ||
306 | //////////////////////////////////////////////////////// | |
307 | // Return Wait State | |
308 | //////////////////////////////////////////////////////// | |
309 | // Go to return wait state when a request is sent to gkt/xbar. | |
310 | // Stay in this state until data comes back and data_ready is | |
311 | // signalled to ifu. | |
312 | assign go_to_retwait_state = (req_state & lsc_l15_valid) | | |
313 | (canleave_state & lsc_l15_valid) | | |
314 | (retwait_state & ~cmu_data_ready); | |
315 | ||
316 | assign next_retwait_state = go_to_retwait_state; | |
317 | ||
318 | ||
319 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 retwait_state_reg ( | |
320 | .scan_in(retwait_state_reg_scanin), | |
321 | .scan_out(retwait_state_reg_scanout), | |
322 | .l1clk(l1clk), | |
323 | .din (next_retwait_state), | |
324 | .dout (retwait_state), | |
325 | .siclk(siclk), | |
326 | .soclk(soclk) | |
327 | ); | |
328 | ||
329 | //////////////////////////////////////////////////////// | |
330 | // Fill Wait State | |
331 | //////////////////////////////////////////////////////// | |
332 | // Fillwait_st indicates that data_ready has been sent, wait | |
333 | // until fill_complete is signalled by ifu | |
334 | assign go_to_fillwait_state = (retwait_state & cmu_data_ready ) | | |
335 | (fillwait_state & ~mct_fill_complete); | |
336 | assign next_fillwait_state = go_to_fillwait_state; | |
337 | ||
338 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 fillwait_state_reg ( | |
339 | .scan_in(fillwait_state_reg_scanin), | |
340 | .scan_out(fillwait_state_reg_scanout), | |
341 | .l1clk(l1clk), | |
342 | .din (next_fillwait_state), | |
343 | .dout (fillwait_state), | |
344 | .siclk(siclk), | |
345 | .soclk(soclk) | |
346 | ); | |
347 | ||
348 | //////////////////////////////////////////////////////// | |
349 | // DupMiss State | |
350 | //////////////////////////////////////////////////////// | |
351 | // go to dupmiss_st on a dup miss. | |
352 | assign go_to_dupmiss_state = (null_state & ftu_cmiss & cmu_mbhit_c & ~mct_ignore_cmiss) | | |
353 | (dupmiss_state & ~ftu_redirect & ~mct_rst_dupmiss); | |
354 | ||
355 | assign next_dupmiss_state = go_to_dupmiss_state; | |
356 | ||
357 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 dupmiss_state_reg ( | |
358 | .scan_in(dupmiss_state_reg_scanin), | |
359 | .scan_out(dupmiss_state_reg_scanout), | |
360 | .l1clk(l1clk), | |
361 | .din (next_dupmiss_state), | |
362 | .dout (dupmiss_state), | |
363 | .siclk(siclk), | |
364 | .soclk(soclk) | |
365 | ); | |
366 | ||
367 | //////////////////////////////////////////////////////// | |
368 | // INVREQ STATE | |
369 | //////////////////////////////////////////////////////// | |
370 | // go to invreq state on a invalidation request. | |
371 | assign go_to_invreq_state = (null_state & inv_req_ff) | | |
372 | (invreq_state & ~lsc_l15_valid); | |
373 | ||
374 | assign next_invreq_state = go_to_invreq_state; | |
375 | ||
376 | ifu_cmu_csm_ctl_msff_ctl_macro__width_1 invreq_state_reg ( | |
377 | .scan_in(invreq_state_reg_scanin), | |
378 | .scan_out(invreq_state_reg_scanout), | |
379 | .l1clk(l1clk), | |
380 | .din (next_invreq_state), | |
381 | .dout (invreq_state), | |
382 | .siclk(siclk), | |
383 | .soclk(soclk) | |
384 | ); | |
385 | ||
386 | //////////////////////////////////////////////////////// | |
387 | // State Machine output signals | |
388 | //////////////////////////////////////////////////////// | |
389 | // csm_valid_req indicates that a valid request exists which | |
390 | // takes part in arbitration | |
391 | // If a request was sent out previous cycle, then the thread | |
392 | // will still be in REQ state this cycle. Validreq will still come | |
393 | // on for this thread, but it will get killed in lsi_ctl before | |
394 | // it takes part in arbitration. | |
395 | ||
396 | // To ease timing, mbhit_q is not used to generate the valid req. | |
397 | // valid_req comes on if | |
398 | // 1. in req state, and no flush or has_dup_miss. | |
399 | // if a flush happens and there are no dup misses, then the thread | |
400 | // will not take part in arb, even though a new dup miss could be | |
401 | // happening at the same time. The new dup miss will show up in | |
402 | // can_leave state the next cycle. | |
403 | // 2. in canleave state and has_dup_miss. Again, if in canleave state | |
404 | // and no dup miss, then thread will not take part in arb even though | |
405 | // a dup miss could be happening in same cycle. The dup miss will | |
406 | // force the state the stay in can_leave and it will set the has_dup | |
407 | // signal next cycle. So the thread will take part in arb next cycle. | |
408 | // 3. In inv_req state. | |
409 | ||
410 | ||
411 | assign csm_valid_req = (req_state & ~(ftu_redirect_lat & ~cmu_has_dup_miss)) | | |
412 | (canleave_state & cmu_has_dup_miss) | | |
413 | (invreq_state); | |
414 | ||
415 | ||
416 | // cmu_cmiss_is_sent | |
417 | // Indicates that a request has been sent. | |
418 | // This signal serves two purposes: | |
419 | // 1. used in conjunction with has_dup_miss in msb_ctl and ifu_ftu to | |
420 | // qualify missbuffer hits. | |
421 | // If a parent thread has not been sent, and it has a redirect, and | |
422 | // it does not have other dup misses outstanding, then an incoming | |
423 | // thread cannot hit on it. | |
424 | // 2. Used by ifu to get out of no_new_miss state. | |
425 | //assign cmu_cmiss_is_sent = lsc_l15_valid | retwait_state | fillwait_state; | |
426 | ||
427 | // wom_valid bit for each thread comes on when the thread is in dupmiss_st or the req | |
428 | // has been sent and thread has not been redirected. | |
429 | // wom_valid is used to qualify bypass for the thread. | |
430 | // Bypass to a thread only if its wom_valid bit is set. | |
431 | // dup WOM bit is not reset if there is redirect and req. is already sent. In this scenario, | |
432 | // bypass is not valid. Hence generating this wom_valid signal to ignore the wom bit. | |
433 | ||
434 | //assign csm_wom_valid = ~null_state & ~reqredirect_state ; | |
435 | ||
436 | assign cmu_null_st = null_state; | |
437 | assign cmu_dupmiss_st = dupmiss_state; | |
438 | assign cmu_req_st = req_state; | |
439 | assign cmu_canleave_st = canleave_state; | |
440 | ||
441 | ||
442 | supply0 vss; | |
443 | supply1 vdd; | |
444 | // fixscan start: | |
445 | assign inv_req_reg_scanin = scan_in ; | |
446 | assign redirect_reg_scanin = inv_req_reg_scanout ; | |
447 | assign null_state_reg_scanin = redirect_reg_scanout ; | |
448 | assign req_state_reg_scanin = null_state_reg_scanout ; | |
449 | assign canleave_state_reg_scanin = req_state_reg_scanout ; | |
450 | assign retwait_state_reg_scanin = canleave_state_reg_scanout; | |
451 | assign fillwait_state_reg_scanin = retwait_state_reg_scanout; | |
452 | assign dupmiss_state_reg_scanin = fillwait_state_reg_scanout; | |
453 | assign invreq_state_reg_scanin = dupmiss_state_reg_scanout; | |
454 | assign scan_out = invreq_state_reg_scanout ; | |
455 | // fixscan end: | |
456 | endmodule | |
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | // any PARAMS parms go into naming of macro | |
464 | ||
465 | module ifu_cmu_csm_ctl_msff_ctl_macro__width_1 ( | |
466 | din, | |
467 | l1clk, | |
468 | scan_in, | |
469 | siclk, | |
470 | soclk, | |
471 | dout, | |
472 | scan_out); | |
473 | wire [0:0] fdin; | |
474 | ||
475 | input [0:0] din; | |
476 | input l1clk; | |
477 | input scan_in; | |
478 | ||
479 | ||
480 | input siclk; | |
481 | input soclk; | |
482 | ||
483 | output [0:0] dout; | |
484 | output scan_out; | |
485 | assign fdin[0:0] = din[0:0]; | |
486 | ||
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | dff #(1) d0_0 ( | |
493 | .l1clk(l1clk), | |
494 | .siclk(siclk), | |
495 | .soclk(soclk), | |
496 | .d(fdin[0:0]), | |
497 | .si(scan_in), | |
498 | .so(scan_out), | |
499 | .q(dout[0:0]) | |
500 | ); | |
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | ||
511 | ||
512 | ||
513 | endmodule | |
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | ||
521 |