projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ifu_ftu_tsm_ctl.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module ifu_ftu_tsm_ctl ( | |
| 36 | l1clk, | |
| 37 | scan_in, | |
| 38 | spc_aclk, | |
| 39 | spc_bclk, | |
| 40 | asi_rd_request, | |
| 41 | asi_wr_request, | |
| 42 | thrx_is_null, | |
| 43 | thrx_is_dupmiss, | |
| 44 | ftp_asi_rd_done, | |
| 45 | ftp_asi_wr_done, | |
| 46 | agc_redirect_bf, | |
| 47 | agc_lsu_no_ic_miss, | |
| 48 | agc_tlu_redirect_bf, | |
| 49 | inv_req_c, | |
| 50 | err_detect_c, | |
| 51 | cmu_inv_req_ack, | |
| 52 | ftu_agc_cmiss_c, | |
| 53 | data_ready, | |
| 54 | cmu_any_data_ready, | |
| 55 | itb_miss_c, | |
| 56 | ftp_room_is_less_t_3, | |
| 57 | tlu_flush_thrx_ifu, | |
| 58 | thrx_go_to_sf_wait, | |
| 59 | itc_demap_next, | |
| 60 | reset_dmiss_bf, | |
| 61 | ftp_reset_fill_wait, | |
| 62 | tsm_fill_rdy0, | |
| 63 | next_thrx_is_ready, | |
| 64 | tsm_no_new_miss, | |
| 65 | tsm_ignore_by_pass, | |
| 66 | tsm_thrx_ifu_quiesce, | |
| 67 | scan_out) ; | |
| 68 | wire siclk; | |
| 69 | wire soclk; | |
| 70 | wire next_reset_wait; | |
| 71 | wire reset_wait_state; | |
| 72 | wire next_reset_wait_; | |
| 73 | wire reset_wait_reg_scanin; | |
| 74 | wire reset_wait_reg_scanout; | |
| 75 | wire reset_wait_state_; | |
| 76 | wire go_to_rmiss_null; | |
| 77 | wire rmiss_wait_state; | |
| 78 | wire dmiss_wait_state; | |
| 79 | wire no_new_miss_state; | |
| 80 | wire can_miss_wait_state; | |
| 81 | wire reset_dmiss_f; | |
| 82 | wire inv_req_ack_ff; | |
| 83 | wire rmiss_null_state; | |
| 84 | wire tsm_ifill_done_bf; | |
| 85 | wire leave_rmiss_null; | |
| 86 | wire next_rmill_null_; | |
| 87 | wire rmiss_null_reg_l_scanin; | |
| 88 | wire rmiss_null_reg_l_scanout; | |
| 89 | wire rmiss_null_state_; | |
| 90 | wire go_to_rmiss_wait; | |
| 91 | wire leave_rmiss_wait; | |
| 92 | wire next_rmiss_wait; | |
| 93 | wire rmiss_wait_reg_scanin; | |
| 94 | wire rmiss_wait_reg_scanout; | |
| 95 | wire go_to_no_new_miss; | |
| 96 | wire leave_no_new_miss; | |
| 97 | wire next_no_new_miss; | |
| 98 | wire no_new_miss_reg_scanin; | |
| 99 | wire no_new_miss_reg_scanout; | |
| 100 | wire tsm_lsu_no_ic_miss_state; | |
| 101 | wire go_to_lsu_ic_miss; | |
| 102 | wire lsu_no_ic_miss_reg_scanin; | |
| 103 | wire lsu_no_ic_miss_reg_scanout; | |
| 104 | wire go_to_lsu_wait; | |
| 105 | wire tsm_lsu_wait_state; | |
| 106 | wire leave_lsu_wait; | |
| 107 | wire next_lsu_wait; | |
| 108 | wire lsu_stops_fetch_reg_scanin; | |
| 109 | wire lsu_stops_fetch_reg_scanout; | |
| 110 | wire go_to_inv_wait; | |
| 111 | wire tsm_inv_wait_state; | |
| 112 | wire leave_inv_wait; | |
| 113 | wire next_inv_wait; | |
| 114 | wire inv_stops_fetch_reg_scanin; | |
| 115 | wire inv_stops_fetch_reg_scanout; | |
| 116 | wire go_to_can_miss_refill; | |
| 117 | wire can_miss_refill_state; | |
| 118 | wire leave_can_miss_refill; | |
| 119 | wire next_can_miss_refill; | |
| 120 | wire can_miss_refill_reg_scanin; | |
| 121 | wire can_miss_refill_reg_scanout; | |
| 122 | wire go_to_can_miss_wait; | |
| 123 | wire leave_can_miss_wait; | |
| 124 | wire next_can_miss_wait; | |
| 125 | wire can_miss_wait_reg_scanin; | |
| 126 | wire can_miss_wait_reg_scanout; | |
| 127 | wire go_to_fill_rdy0; | |
| 128 | wire leave_fill_rdy0; | |
| 129 | wire fill_rdy0_state; | |
| 130 | wire next_fill_rdy0; | |
| 131 | wire fill_rdy0_reg_scanin; | |
| 132 | wire fill_rdy0_reg_scanout; | |
| 133 | wire go_to_asi_rd_wait; | |
| 134 | wire tsm_asi_rd_wait_state; | |
| 135 | wire leave_asi_rd_wait; | |
| 136 | wire next_asi_rd_wait; | |
| 137 | wire asi_rd_stops_fetch_reg_scanin; | |
| 138 | wire asi_rd_stops_fetch_reg_scanout; | |
| 139 | wire go_to_asi_wr_wait; | |
| 140 | wire tsm_asi_wr_wait_state; | |
| 141 | wire leave_asi_wr_wait; | |
| 142 | wire next_asi_wr_wait; | |
| 143 | wire asi_wr_stops_fetch_reg_scanin; | |
| 144 | wire asi_wr_stops_fetch_reg_scanout; | |
| 145 | wire go_to_dmiss_wait; | |
| 146 | wire leave_dmiss_wait; | |
| 147 | wire next_dmiss_wait; | |
| 148 | wire dmiss_wait_reg_scanin; | |
| 149 | wire dmiss_wait_reg_scanout; | |
| 150 | wire reset_dmiss_reg_scanin; | |
| 151 | wire reset_dmiss_reg_scanout; | |
| 152 | wire go_to_fill_wait; | |
| 153 | wire fill_wait_state; | |
| 154 | wire leave_fill_wait; | |
| 155 | wire next_fill_wait; | |
| 156 | wire fill_wait_reg_scanin; | |
| 157 | wire fill_wait_reg_scanout; | |
| 158 | wire go_to_itlb_miss_wait; | |
| 159 | wire itlb_miss_wait_state; | |
| 160 | wire leave_itlb_miss_wait; | |
| 161 | wire next_itlb_miss_wait; | |
| 162 | wire itlb_miss_wait_reg_scanin; | |
| 163 | wire itlb_miss_wait_reg_scanout; | |
| 164 | wire go_to_err_wait; | |
| 165 | wire err_wait_state; | |
| 166 | wire leave_err_wait; | |
| 167 | wire next_err_wait; | |
| 168 | wire err_wait_reg_scanin; | |
| 169 | wire err_wait_reg_scanout; | |
| 170 | wire go_to_no_room_wait; | |
| 171 | wire no_room_wait_state; | |
| 172 | wire leave_no_room_wait; | |
| 173 | wire next_no_room_wait; | |
| 174 | wire no_room_wait_reg_scanin; | |
| 175 | wire no_room_wait_reg_scanout; | |
| 176 | wire go_to_itlb_demap; | |
| 177 | wire leave_itlb_demap; | |
| 178 | wire itlb_demap_state; | |
| 179 | wire next_itlb_demap; | |
| 180 | wire itlb_demap_reg_scanin; | |
| 181 | wire itlb_demap_reg_scanout; | |
| 182 | wire go_to_itlb_write; | |
| 183 | wire leave_itlb_write; | |
| 184 | wire itlb_write_state; | |
| 185 | wire next_itlb_write; | |
| 186 | wire itlb_write_reg_scanin; | |
| 187 | wire itlb_write_reg_scanout; | |
| 188 | wire flush_ifu_reg_scanin; | |
| 189 | wire flush_ifu_reg_scanout; | |
| 190 | wire tlu_flush_thrx_ifu_d; | |
| 191 | wire go_to_tlu_redr; | |
| 192 | wire tsm_tlu_redr_wait_state; | |
| 193 | wire leave_tlu_redr; | |
| 194 | wire next_tlu_redr_wait; | |
| 195 | wire tlu_red_reg_scanin; | |
| 196 | wire tlu_red_reg_scanout; | |
| 197 | wire next_sf_wait; | |
| 198 | wire sf_wait_state; | |
| 199 | wire tlu_sf_reg_scanin; | |
| 200 | wire tlu_sf_reg_scanout; | |
| 201 | wire next_ignore_by_pass; | |
| 202 | wire ignore_by_pass_reg_scanin; | |
| 203 | wire ignore_by_pass_reg_scanout; | |
| 204 | wire next_ifu_quiesce; | |
| 205 | wire no_icmiss_pending_reg_scanin; | |
| 206 | wire no_icmiss_pending_reg_scanout; | |
| 207 | wire ifill_done_reg_scanin; | |
| 208 | wire ifill_done_reg_scanout; | |
| 209 | wire spares_scanin; | |
| 210 | wire spares_scanout; | |
| 211 | ||
| 212 | ||
| 213 | input l1clk; | |
| 214 | input scan_in; | |
| 215 | input spc_aclk; | |
| 216 | input spc_bclk; | |
| 217 | ||
| 218 | input asi_rd_request; | |
| 219 | input asi_wr_request; | |
| 220 | input thrx_is_null; | |
| 221 | input thrx_is_dupmiss; | |
| 222 | input ftp_asi_rd_done; | |
| 223 | input ftp_asi_wr_done; | |
| 224 | input agc_redirect_bf; | |
| 225 | input agc_lsu_no_ic_miss; | |
| 226 | input agc_tlu_redirect_bf; | |
| 227 | input inv_req_c; | |
| 228 | input err_detect_c; | |
| 229 | input cmu_inv_req_ack; | |
| 230 | input ftu_agc_cmiss_c; | |
| 231 | input data_ready; | |
| 232 | input cmu_any_data_ready; | |
| 233 | input itb_miss_c; | |
| 234 | input ftp_room_is_less_t_3; | |
| 235 | input tlu_flush_thrx_ifu ; | |
| 236 | input thrx_go_to_sf_wait ; | |
| 237 | input itc_demap_next; | |
| 238 | input reset_dmiss_bf; | |
| 239 | input ftp_reset_fill_wait; | |
| 240 | // output tsm_ready_hp_bf; | |
| 241 | output tsm_fill_rdy0; | |
| 242 | output next_thrx_is_ready ; | |
| 243 | // output tsm_fill_rdy1; | |
| 244 | output tsm_no_new_miss; | |
| 245 | output tsm_ignore_by_pass; | |
| 246 | output tsm_thrx_ifu_quiesce; | |
| 247 | output scan_out; | |
| 248 | ||
| 249 | // scan renames | |
| 250 | assign siclk = spc_aclk; | |
| 251 | assign soclk = spc_bclk; | |
| 252 | // end scan | |
| 253 | ||
| 254 | //////////////////////////////////////////////////////// | |
| 255 | //////////////////////////////////////////////////////// | |
| 256 | ||
| 257 | ||
| 258 | ||
| 259 | ||
| 260 | //////////////////////////////////////////////////////// | |
| 261 | //////////////////////////////////////////////////////// | |
| 262 | //////////////////////////////////////////////////////// | |
| 263 | // First state machine controls the thread if it // | |
| 264 | // initiated the cache miss. // | |
| 265 | //////////////////////////////////////////////////////// | |
| 266 | // First wait state is to wait the initial trap // | |
| 267 | // redirection from the trap unit. // | |
| 268 | //////////////////////////////////////////////////////// | |
| 269 | assign next_reset_wait = reset_wait_state & ~agc_redirect_bf ; | |
| 270 | assign next_reset_wait_ = ~next_reset_wait ; | |
| 271 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 reset_wait_reg ( | |
| 272 | .scan_in(reset_wait_reg_scanin), | |
| 273 | .scan_out(reset_wait_reg_scanout), | |
| 274 | .l1clk( l1clk ), | |
| 275 | .din (next_reset_wait_), | |
| 276 | .dout (reset_wait_state_), | |
| 277 | .siclk(siclk), | |
| 278 | .soclk(soclk)); | |
| 279 | ||
| 280 | assign reset_wait_state = ~reset_wait_state_ ; | |
| 281 | //////////////////////////////////////////////////////// | |
| 282 | // Real_Miss_Null state // | |
| 283 | // Note: Null state comes up as ONE after reset // | |
| 284 | // There is a case that we get reset_dmiss_bf the // | |
| 285 | // cycle that we trying to go dmiss_state.In that case// | |
| 286 | // we should come to NULL state. // | |
| 287 | //////////////////////////////////////////////////////// | |
| 288 | assign go_to_rmiss_null = ( rmiss_wait_state & thrx_is_null ) | | |
| 289 | // ( rmiss_wait_state & agc_tg_or_v_err_p) | | |
| 290 | ( dmiss_wait_state & (thrx_is_null | agc_redirect_bf)) | | |
| 291 | ( thrx_is_dupmiss & agc_redirect_bf) | | |
| 292 | ( no_new_miss_state & thrx_is_null) | | |
| 293 | ( can_miss_wait_state & thrx_is_null) | | |
| 294 | reset_dmiss_f | | |
| 295 | inv_req_ack_ff | | |
| 296 | rmiss_null_state | | |
| 297 | tsm_ifill_done_bf ; | |
| 298 | assign leave_rmiss_null = ((ftu_agc_cmiss_c | inv_req_c) & ~tsm_ifill_done_bf & ~tsm_no_new_miss) ; | |
| 299 | assign next_rmill_null_ = ~(go_to_rmiss_null & ~leave_rmiss_null) ; | |
| 300 | ||
| 301 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 rmiss_null_reg_l ( | |
| 302 | .scan_in(rmiss_null_reg_l_scanin), | |
| 303 | .scan_out(rmiss_null_reg_l_scanout), | |
| 304 | .l1clk( l1clk ), | |
| 305 | .din (next_rmill_null_), | |
| 306 | .dout (rmiss_null_state_), | |
| 307 | .siclk(siclk), | |
| 308 | .soclk(soclk)); | |
| 309 | ||
| 310 | assign rmiss_null_state = ~rmiss_null_state_ ; | |
| 311 | //////////////////////////////////////////////////////// | |
| 312 | // Real_Miss_Wait state: rmiss_wait_state // | |
| 313 | //////////////////////////////////////////////////////// | |
| 314 | assign go_to_rmiss_wait = (ftu_agc_cmiss_c & rmiss_null_state & ~tsm_no_new_miss) | | |
| 315 | rmiss_wait_state; | |
| 316 | // assign leave_rmiss_wait = (agc_redirect_bf | data_ready | (rmiss_wait_state & thrx_is_null) | thrx_is_dupmiss | agc_tg_or_v_err_p ); | |
| 317 | assign leave_rmiss_wait = (agc_redirect_bf | data_ready | (rmiss_wait_state & thrx_is_null) | thrx_is_dupmiss ) ; // | agc_tg_or_v_err_p ); | |
| 318 | assign next_rmiss_wait = go_to_rmiss_wait & ~leave_rmiss_wait ; | |
| 319 | ||
| 320 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 rmiss_wait_reg ( | |
| 321 | .scan_in(rmiss_wait_reg_scanin), | |
| 322 | .scan_out(rmiss_wait_reg_scanout), | |
| 323 | .l1clk( l1clk ), | |
| 324 | .din (next_rmiss_wait), | |
| 325 | .dout (rmiss_wait_state), | |
| 326 | .siclk(siclk), | |
| 327 | .soclk(soclk)); | |
| 328 | ||
| 329 | //////////////////////////////////////////////////////// | |
| 330 | // No_New_Miss state: no_new_miss_state // | |
| 331 | // NOTE: we do not want to leave no_new_miss_state // | |
| 332 | // even when we go to can_miss_wait_state because it // | |
| 333 | // possible to get flush before the data comes for // | |
| 334 | // the original miss. In that case we simply reset // | |
| 335 | // can_miss_wait_state and we are ready to fetch again// | |
| 336 | //////////////////////////////////////////////////////// | |
| 337 | assign go_to_no_new_miss = (rmiss_wait_state & agc_redirect_bf & ~thrx_is_null & ~thrx_is_dupmiss) | | |
| 338 | no_new_miss_state; | |
| 339 | assign leave_no_new_miss = tsm_ifill_done_bf | thrx_is_null ; | |
| 340 | assign next_no_new_miss = go_to_no_new_miss & ~leave_no_new_miss ; | |
| 341 | ||
| 342 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 no_new_miss_reg ( | |
| 343 | .scan_in(no_new_miss_reg_scanin), | |
| 344 | .scan_out(no_new_miss_reg_scanout), | |
| 345 | .l1clk( l1clk ), | |
| 346 | .din (next_no_new_miss), | |
| 347 | .dout (no_new_miss_state), | |
| 348 | .siclk(siclk), | |
| 349 | .soclk(soclk)); | |
| 350 | ||
| 351 | assign tsm_no_new_miss = no_new_miss_state | tsm_lsu_no_ic_miss_state ; | |
| 352 | ||
| 353 | ||
| 354 | ////////////////////////////////////////////////////////// | |
| 355 | // LSU no new_miss state. LSU needs to delay new misses // | |
| 356 | ////////////////////////////////////////////////////////// | |
| 357 | assign go_to_lsu_ic_miss = agc_lsu_no_ic_miss ; | |
| 358 | ||
| 359 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 lsu_no_ic_miss_reg ( | |
| 360 | .scan_in(lsu_no_ic_miss_reg_scanin), | |
| 361 | .scan_out(lsu_no_ic_miss_reg_scanout), | |
| 362 | .l1clk( l1clk ), | |
| 363 | .din (go_to_lsu_ic_miss), | |
| 364 | .dout (tsm_lsu_no_ic_miss_state), | |
| 365 | .siclk(siclk), | |
| 366 | .soclk(soclk)); | |
| 367 | ||
| 368 | ||
| 369 | ///////////////////////////////////////////////////////// | |
| 370 | // Stop fetch if lsu can not handle new miss and we // | |
| 371 | // detect new miss. // | |
| 372 | ///////////////////////////////////////////////////////// | |
| 373 | assign go_to_lsu_wait = (tsm_lsu_no_ic_miss_state & ftu_agc_cmiss_c) | | |
| 374 | tsm_lsu_wait_state ; | |
| 375 | assign leave_lsu_wait = ~agc_lsu_no_ic_miss ; // | agc_tg_or_v_err_p; | |
| 376 | assign next_lsu_wait = go_to_lsu_wait & ~leave_lsu_wait ; | |
| 377 | ||
| 378 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_2 lsu_stops_fetch_reg ( | |
| 379 | .scan_in(lsu_stops_fetch_reg_scanin), | |
| 380 | .scan_out(lsu_stops_fetch_reg_scanout), | |
| 381 | .l1clk( l1clk ), | |
| 382 | .din ({next_lsu_wait, cmu_inv_req_ack}), | |
| 383 | .dout ({tsm_lsu_wait_state,inv_req_ack_ff}), | |
| 384 | .siclk(siclk), | |
| 385 | .soclk(soclk)); | |
| 386 | ||
| 387 | ///////////////////////////////////////////////////////// | |
| 388 | // Stop fetch if parity eeror is dtetcted and INV is // | |
| 389 | // requested from L2. Wait for inv ack. // | |
| 390 | ///////////////////////////////////////////////////////// | |
| 391 | assign go_to_inv_wait = (inv_req_c & rmiss_null_state & ~tsm_no_new_miss) | | |
| 392 | tsm_inv_wait_state ; | |
| 393 | assign leave_inv_wait = inv_req_ack_ff ; | |
| 394 | assign next_inv_wait = go_to_inv_wait & ~leave_inv_wait ; | |
| 395 | ||
| 396 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 inv_stops_fetch_reg ( | |
| 397 | .scan_in(inv_stops_fetch_reg_scanin), | |
| 398 | .scan_out(inv_stops_fetch_reg_scanout), | |
| 399 | .l1clk( l1clk ), | |
| 400 | .din (next_inv_wait), | |
| 401 | .dout (tsm_inv_wait_state), | |
| 402 | .siclk(siclk), | |
| 403 | .soclk(soclk)); | |
| 404 | ||
| 405 | // Canceled_Miss_refill: can_miss_refill_state // | |
| 406 | //////////////////////////////////////////////////////// | |
| 407 | assign go_to_can_miss_refill = (no_new_miss_state & ftu_agc_cmiss_c & ~thrx_is_null) | | |
| 408 | can_miss_refill_state ; | |
| 409 | assign leave_can_miss_refill = tsm_ifill_done_bf | thrx_is_null ; // | agc_tg_or_v_err_p; | |
| 410 | assign next_can_miss_refill = go_to_can_miss_refill & ~leave_can_miss_refill ; | |
| 411 | ||
| 412 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 can_miss_refill_reg ( | |
| 413 | .scan_in(can_miss_refill_reg_scanin), | |
| 414 | .scan_out(can_miss_refill_reg_scanout), | |
| 415 | .l1clk( l1clk ), | |
| 416 | .din (next_can_miss_refill), | |
| 417 | .dout (can_miss_refill_state), | |
| 418 | .siclk(siclk), | |
| 419 | .soclk(soclk)); | |
| 420 | ||
| 421 | //////////////////////////////////////////////////////// | |
| 422 | // Canceled_Miss_Wait: can_miss_wait_state // | |
| 423 | //////////////////////////////////////////////////////// | |
| 424 | assign go_to_can_miss_wait = (no_new_miss_state & ftu_agc_cmiss_c & ~thrx_is_null) | | |
| 425 | can_miss_wait_state ; | |
| 426 | assign leave_can_miss_wait = tsm_ifill_done_bf | agc_redirect_bf | thrx_is_null ; // | agc_tg_or_v_err_p; | |
| 427 | assign next_can_miss_wait = go_to_can_miss_wait & ~leave_can_miss_wait ; | |
| 428 | ||
| 429 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 can_miss_wait_reg ( | |
| 430 | .scan_in(can_miss_wait_reg_scanin), | |
| 431 | .scan_out(can_miss_wait_reg_scanout), | |
| 432 | .l1clk( l1clk ), | |
| 433 | .din (next_can_miss_wait), | |
| 434 | .dout (can_miss_wait_state), | |
| 435 | .siclk(siclk), | |
| 436 | .soclk(soclk)); | |
| 437 | ||
| 438 | //////////////////////////////////////////////////////// | |
| 439 | // Fill_rdy0 state : // | |
| 440 | //////////////////////////////////////////////////////// | |
| 441 | assign go_to_fill_rdy0 = (data_ready & (rmiss_wait_state | | |
| 442 | no_new_miss_state | can_miss_refill_state)); | |
| 443 | assign leave_fill_rdy0 = fill_rdy0_state ; | |
| 444 | assign next_fill_rdy0 = go_to_fill_rdy0 & ~leave_fill_rdy0 ; | |
| 445 | ||
| 446 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 fill_rdy0_reg ( | |
| 447 | .scan_in(fill_rdy0_reg_scanin), | |
| 448 | .scan_out(fill_rdy0_reg_scanout), | |
| 449 | .l1clk( l1clk ), | |
| 450 | .din (next_fill_rdy0), | |
| 451 | .dout (fill_rdy0_state), | |
| 452 | .siclk(siclk), | |
| 453 | .soclk(soclk)); | |
| 454 | ||
| 455 | //////////////////////////////////////////////////////// | |
| 456 | // Fill_rdy1 state : // | |
| 457 | //////////////////////////////////////////////////////// | |
| 458 | // assign go_to_fill_rdy1 = fill_rdy0_state ; | |
| 459 | // assign leave_fill_rdy1 = fill_rdy1_state ; | |
| 460 | // assign next_fill_rdy1 = go_to_fill_rdy1 & ~leave_fill_rdy1 ; | |
| 461 | ||
| 462 | // msff_ctl_macro fill_rdy1_reg (width=1) ( | |
| 463 | // .scan_in(fill_rdy1_reg_scanin), | |
| 464 | // .scan_out(fill_rdy1_reg_scanout), | |
| 465 | // .l1clk( l1clk ), | |
| 466 | // .din (next_fill_rdy1), | |
| 467 | // .dout (fill_rdy1_state)); | |
| 468 | ||
| 469 | ///////////////////////////////////////////////////////// | |
| 470 | // asi read wait // | |
| 471 | // when asi_request comes stop all threads to gain // | |
| 472 | // access to the arrays. The only thing that may delay// | |
| 473 | // the access is writes to the Icache caused by fill // | |
| 474 | ///////////////////////////////////////////////////////// | |
| 475 | assign go_to_asi_rd_wait = (asi_rd_request ) | | |
| 476 | tsm_asi_rd_wait_state ; | |
| 477 | assign leave_asi_rd_wait = ftp_asi_rd_done ; | |
| 478 | assign next_asi_rd_wait = go_to_asi_rd_wait & ~leave_asi_rd_wait ; | |
| 479 | ||
| 480 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 asi_rd_stops_fetch_reg ( | |
| 481 | .scan_in(asi_rd_stops_fetch_reg_scanin), | |
| 482 | .scan_out(asi_rd_stops_fetch_reg_scanout), | |
| 483 | .l1clk( l1clk ), | |
| 484 | .din (next_asi_rd_wait), | |
| 485 | .dout (tsm_asi_rd_wait_state), | |
| 486 | .siclk(siclk), | |
| 487 | .soclk(soclk)); | |
| 488 | ||
| 489 | ///////////////////////////////////////////////////////// | |
| 490 | // asi write wait // | |
| 491 | // when asi_request comes stop all threads to gain // | |
| 492 | // access to the arrays. The only thing that may delay// | |
| 493 | // the access is writes to the Icache caused by fill // | |
| 494 | ///////////////////////////////////////////////////////// | |
| 495 | assign go_to_asi_wr_wait = (asi_wr_request ) | | |
| 496 | tsm_asi_wr_wait_state ; | |
| 497 | assign leave_asi_wr_wait = ftp_asi_wr_done ; | |
| 498 | assign next_asi_wr_wait = go_to_asi_wr_wait & ~leave_asi_wr_wait ; | |
| 499 | ||
| 500 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 asi_wr_stops_fetch_reg ( | |
| 501 | .scan_in(asi_wr_stops_fetch_reg_scanin), | |
| 502 | .scan_out(asi_wr_stops_fetch_reg_scanout), | |
| 503 | .l1clk( l1clk ), | |
| 504 | .din (next_asi_wr_wait), | |
| 505 | .dout (tsm_asi_wr_wait_state), | |
| 506 | .siclk(siclk), | |
| 507 | .soclk(soclk)); | |
| 508 | ||
| 509 | //////////////////////////////////////////////////////// | |
| 510 | //////////////////////////////////////////////////////// | |
| 511 | //////////////////////////////////////////////////////// | |
| 512 | //////////////////////////////////////////////////////// | |
| 513 | //////////////////////////////////////////////////////// | |
| 514 | // second state machine is activated if the thread is // | |
| 515 | // waiting on a duplicate miss. // | |
| 516 | //////////////////////////////////////////////////////// | |
| 517 | //////////////////////////////////////////////////////// | |
| 518 | //////////////////////////////////////////////////////// | |
| 519 | // Duplicate_Miss_Wait state: dmiss_wait_state // | |
| 520 | //////////////////////////////////////////////////////// | |
| 521 | assign go_to_dmiss_wait = (rmiss_wait_state & thrx_is_dupmiss ) | | |
| 522 | dmiss_wait_state; | |
| 523 | assign leave_dmiss_wait = (agc_redirect_bf | reset_dmiss_f | thrx_is_null); | |
| 524 | assign next_dmiss_wait = go_to_dmiss_wait & ~leave_dmiss_wait ; | |
| 525 | ||
| 526 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 dmiss_wait_reg ( | |
| 527 | .scan_in(dmiss_wait_reg_scanin), | |
| 528 | .scan_out(dmiss_wait_reg_scanout), | |
| 529 | .l1clk( l1clk ), | |
| 530 | .din (next_dmiss_wait), | |
| 531 | .dout (dmiss_wait_state), | |
| 532 | .siclk(siclk), | |
| 533 | .soclk(soclk)); | |
| 534 | ||
| 535 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 reset_dmiss_reg ( | |
| 536 | .scan_in(reset_dmiss_reg_scanin), | |
| 537 | .scan_out(reset_dmiss_reg_scanout), | |
| 538 | .l1clk( l1clk ), | |
| 539 | .din (reset_dmiss_bf), | |
| 540 | .dout (reset_dmiss_f), | |
| 541 | .siclk(siclk), | |
| 542 | .soclk(soclk)); | |
| 543 | ||
| 544 | //////////////////////////////////////////////////////// | |
| 545 | //////////////////////////////////////////////////////// | |
| 546 | //////////////////////////////////////////////////////// | |
| 547 | //////////////////////////////////////////////////////// | |
| 548 | //////////////////////////////////////////////////////// | |
| 549 | // Third state machine is activated if the thread is // | |
| 550 | // waiting on a cache line being filled by an other // | |
| 551 | // thread. // | |
| 552 | //////////////////////////////////////////////////////// | |
| 553 | //////////////////////////////////////////////////////// | |
| 554 | //////////////////////////////////////////////////////// | |
| 555 | // Fill_Wait state: fill_wait_state // | |
| 556 | //////////////////////////////////////////////////////// | |
| 557 | assign go_to_fill_wait = cmu_any_data_ready | fill_wait_state; | |
| 558 | assign leave_fill_wait = ftp_reset_fill_wait & ~cmu_any_data_ready; | |
| 559 | assign next_fill_wait = go_to_fill_wait & ~leave_fill_wait ; | |
| 560 | ||
| 561 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 fill_wait_reg ( | |
| 562 | .scan_in(fill_wait_reg_scanin), | |
| 563 | .scan_out(fill_wait_reg_scanout), | |
| 564 | .l1clk( l1clk ), | |
| 565 | .din (next_fill_wait), | |
| 566 | .dout (fill_wait_state), | |
| 567 | .siclk(siclk), | |
| 568 | .soclk(soclk)); | |
| 569 | ||
| 570 | //////////////////////////////////////////////////////// | |
| 571 | //////////////////////////////////////////////////////// | |
| 572 | //////////////////////////////////////////////////////// | |
| 573 | //////////////////////////////////////////////////////// | |
| 574 | //////////////////////////////////////////////////////// | |
| 575 | // Fourth state machine is activated if the thread is // | |
| 576 | // waiting on a ITLB miss. // | |
| 577 | //////////////////////////////////////////////////////// | |
| 578 | //////////////////////////////////////////////////////// | |
| 579 | //////////////////////////////////////////////////////// | |
| 580 | // Fill_Wait state: itlb_miss_wait_state // | |
| 581 | //////////////////////////////////////////////////////// | |
| 582 | assign go_to_itlb_miss_wait = itb_miss_c | itlb_miss_wait_state; | |
| 583 | assign leave_itlb_miss_wait = agc_redirect_bf ; | |
| 584 | assign next_itlb_miss_wait = go_to_itlb_miss_wait & ~leave_itlb_miss_wait ; | |
| 585 | ||
| 586 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 itlb_miss_wait_reg ( | |
| 587 | .scan_in(itlb_miss_wait_reg_scanin), | |
| 588 | .scan_out(itlb_miss_wait_reg_scanout), | |
| 589 | .l1clk( l1clk ), | |
| 590 | .din (next_itlb_miss_wait), | |
| 591 | .dout (itlb_miss_wait_state), | |
| 592 | .siclk(siclk), | |
| 593 | .soclk(soclk)); | |
| 594 | ||
| 595 | //////////////////////////////////////////////////////// | |
| 596 | //////////////////////////////////////////////////////// | |
| 597 | // err_wait state: err_wait_state // | |
| 598 | //////////////////////////////////////////////////////// | |
| 599 | assign go_to_err_wait = err_detect_c | err_wait_state; | |
| 600 | assign leave_err_wait = agc_redirect_bf ; | |
| 601 | assign next_err_wait = go_to_err_wait & ~leave_err_wait ; | |
| 602 | ||
| 603 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 err_wait_reg ( | |
| 604 | .scan_in(err_wait_reg_scanin), | |
| 605 | .scan_out(err_wait_reg_scanout), | |
| 606 | .l1clk( l1clk ), | |
| 607 | .din (next_err_wait), | |
| 608 | .dout (err_wait_state), | |
| 609 | .siclk(siclk), | |
| 610 | .soclk(soclk)); | |
| 611 | ||
| 612 | //////////////////////////////////////////////////////// | |
| 613 | //////////////////////////////////////////////////////// | |
| 614 | //////////////////////////////////////////////////////// | |
| 615 | //////////////////////////////////////////////////////// | |
| 616 | //////////////////////////////////////////////////////// | |
| 617 | // Fifth state machine is activated if the thread // | |
| 618 | // does not have room for 3 more instructions. // | |
| 619 | //////////////////////////////////////////////////////// | |
| 620 | //////////////////////////////////////////////////////// | |
| 621 | //////////////////////////////////////////////////////// | |
| 622 | //////////////////////////////////////////////////////// | |
| 623 | // Fill_Wait state: no_room_wait_state // | |
| 624 | //////////////////////////////////////////////////////// | |
| 625 | assign go_to_no_room_wait = ftp_room_is_less_t_3 | no_room_wait_state; | |
| 626 | assign leave_no_room_wait = ~ftp_room_is_less_t_3 ; | |
| 627 | assign next_no_room_wait = go_to_no_room_wait & ~leave_no_room_wait ; | |
| 628 | ||
| 629 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 no_room_wait_reg ( | |
| 630 | .scan_in(no_room_wait_reg_scanin), | |
| 631 | .scan_out(no_room_wait_reg_scanout), | |
| 632 | .l1clk( l1clk ), | |
| 633 | .din (next_no_room_wait), | |
| 634 | .dout (no_room_wait_state), | |
| 635 | .siclk(siclk), | |
| 636 | .soclk(soclk)); | |
| 637 | ||
| 638 | //////////////////////////////////////////////////////// | |
| 639 | //////////////////////////////////////////////////////// | |
| 640 | //////////////////////////////////////////////////////// | |
| 641 | //////////////////////////////////////////////////////// | |
| 642 | //////////////////////////////////////////////////////// | |
| 643 | // sixth state machine is activated whenever a ITLB // | |
| 644 | // write is requested by TLU. // | |
| 645 | //////////////////////////////////////////////////////// | |
| 646 | //////////////////////////////////////////////////////// | |
| 647 | //////////////////////////////////////////////////////// | |
| 648 | //////////////////////////////////////////////////////// | |
| 649 | // Itlb_Demap state: itlb_demap_state // | |
| 650 | //////////////////////////////////////////////////////// | |
| 651 | assign go_to_itlb_demap = itc_demap_next ; | |
| 652 | assign leave_itlb_demap = itlb_demap_state ; | |
| 653 | assign next_itlb_demap = go_to_itlb_demap & ~leave_itlb_demap ; | |
| 654 | ||
| 655 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 itlb_demap_reg ( | |
| 656 | .scan_in(itlb_demap_reg_scanin), | |
| 657 | .scan_out(itlb_demap_reg_scanout), | |
| 658 | .l1clk( l1clk ), | |
| 659 | .din (next_itlb_demap), | |
| 660 | .dout (itlb_demap_state), | |
| 661 | .siclk(siclk), | |
| 662 | .soclk(soclk)); | |
| 663 | ||
| 664 | //////////////////////////////////////////////////////// | |
| 665 | // Itlb_write state: itlb_write_state // | |
| 666 | //////////////////////////////////////////////////////// | |
| 667 | assign go_to_itlb_write = itlb_demap_state ; | |
| 668 | assign leave_itlb_write = itlb_write_state ; | |
| 669 | assign next_itlb_write = go_to_itlb_write & ~leave_itlb_write ; | |
| 670 | ||
| 671 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 itlb_write_reg ( | |
| 672 | .scan_in(itlb_write_reg_scanin), | |
| 673 | .scan_out(itlb_write_reg_scanout), | |
| 674 | .l1clk( l1clk ), | |
| 675 | .din (next_itlb_write), | |
| 676 | .dout (itlb_write_state), | |
| 677 | .siclk(siclk), | |
| 678 | .soclk(soclk)); | |
| 679 | ||
| 680 | // assign itlb_miss_write_done = itlb_write_state ; | |
| 681 | ////////////////////////////////////////////////////////// | |
| 682 | // TLU flush causes the thread to wait until TLU redirection | |
| 683 | ///////////////////////////////////////////////////////// | |
| 684 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 flush_ifu_reg ( | |
| 685 | .scan_in(flush_ifu_reg_scanin), | |
| 686 | .scan_out(flush_ifu_reg_scanout), | |
| 687 | .l1clk( l1clk ), | |
| 688 | .din (tlu_flush_thrx_ifu), | |
| 689 | .dout (tlu_flush_thrx_ifu_d), | |
| 690 | .siclk(siclk), | |
| 691 | .soclk(soclk)); | |
| 692 | ||
| 693 | assign go_to_tlu_redr = tlu_flush_thrx_ifu_d | tsm_tlu_redr_wait_state ; | |
| 694 | assign leave_tlu_redr = agc_tlu_redirect_bf ; | |
| 695 | assign next_tlu_redr_wait = go_to_tlu_redr & ~leave_tlu_redr ; | |
| 696 | ||
| 697 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 tlu_red_reg ( | |
| 698 | .scan_in(tlu_red_reg_scanin), | |
| 699 | .scan_out(tlu_red_reg_scanout), | |
| 700 | .l1clk( l1clk ), | |
| 701 | .din (next_tlu_redr_wait), | |
| 702 | .dout (tsm_tlu_redr_wait_state), | |
| 703 | .siclk(siclk), | |
| 704 | .soclk(soclk)); | |
| 705 | ||
| 706 | assign next_sf_wait = (thrx_go_to_sf_wait | sf_wait_state) & ~agc_tlu_redirect_bf & ~ftu_agc_cmiss_c ; | |
| 707 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 tlu_sf_reg ( | |
| 708 | .scan_in(tlu_sf_reg_scanin), | |
| 709 | .scan_out(tlu_sf_reg_scanout), | |
| 710 | .l1clk( l1clk ), | |
| 711 | .din (next_sf_wait), | |
| 712 | .dout (sf_wait_state), | |
| 713 | .siclk(siclk), | |
| 714 | .soclk(soclk)); | |
| 715 | ||
| 716 | //////////////////////////////////////////////////////// | |
| 717 | // Now generate a cumulative Ready for this thread // | |
| 718 | //////////////////////////////////////////////////////// | |
| 719 | assign next_thrx_is_ready = ( ~next_rmiss_wait & ~next_can_miss_wait & ~next_itlb_write & ~next_itlb_miss_wait & ~next_err_wait & | |
| 720 | ~next_dmiss_wait & ~next_fill_wait & ~next_reset_wait & ~next_itlb_demap & ~next_lsu_wait & ~next_sf_wait & | |
| 721 | ~next_inv_wait & ~next_asi_rd_wait & ~next_asi_wr_wait & ~next_itlb_demap & ~next_tlu_redr_wait) ; | |
| 722 | // | next_fill_rdy0 | next_fill_rdy1 ; | |
| 723 | ||
| 724 | // msff_ctl_macro thrx_is_ready_reg (width=1) ( | |
| 725 | // .scan_in(thrx_is_ready_reg_scanin), | |
| 726 | // .scan_out(thrx_is_ready_reg_scanout), | |
| 727 | // .l1clk( l1clk ), | |
| 728 | // .din (next_thrx_is_ready), | |
| 729 | // .dout (thrx_is_ready)); | |
| 730 | ||
| 731 | ||
| 732 | // assign next_ignore_by_pass = (~next_dmiss_wait & ~next_rmiss_wait) | next_can_miss_refill | next_no_new_miss ; | |
| 733 | assign next_ignore_by_pass = (~next_dmiss_wait & ~rmiss_wait_state) | can_miss_refill_state | next_no_new_miss ; | |
| 734 | ||
| 735 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 ignore_by_pass_reg ( | |
| 736 | .scan_in(ignore_by_pass_reg_scanin), | |
| 737 | .scan_out(ignore_by_pass_reg_scanout), | |
| 738 | .l1clk( l1clk ), | |
| 739 | .din (next_ignore_by_pass), | |
| 740 | .dout (tsm_ignore_by_pass), | |
| 741 | .siclk(siclk), | |
| 742 | .soclk(soclk)); | |
| 743 | ||
| 744 | ||
| 745 | // assign tsm_ready_hp_bf = thrx_is_ready ; // & ftp_buffer_is_empty; | |
| 746 | ||
| 747 | assign next_ifu_quiesce = (~rmiss_wait_state & ~dmiss_wait_state & | |
| 748 | ~can_miss_wait_state & ~no_new_miss_state) & (tsm_tlu_redr_wait_state | | |
| 749 | (next_sf_wait & sf_wait_state)) ; | |
| 750 | ||
| 751 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 no_icmiss_pending_reg ( | |
| 752 | .scan_in(no_icmiss_pending_reg_scanin), | |
| 753 | .scan_out(no_icmiss_pending_reg_scanout), | |
| 754 | .l1clk( l1clk ), | |
| 755 | .din (next_ifu_quiesce), | |
| 756 | .dout (tsm_thrx_ifu_quiesce), | |
| 757 | .siclk(siclk), | |
| 758 | .soclk(soclk)); | |
| 759 | ||
| 760 | ///////////////////////////////////////////////////////////////////////////////// | |
| 761 | // assign tsm_ifill_done_bf = leave_fill_rdy0 ; | |
| 762 | // Delay fill done for one cycle so that any fetches still in progress which | |
| 763 | // match the current fill will have a chance to be flagged as duplicate in | |
| 764 | // the CMU. Otherwise we have to compare the current fetch in C (about to | |
| 765 | // miss) to what is being written and if they match kill the miss. | |
| 766 | ///////////////////////////////////////////////////////////////////////////////// | |
| 767 | ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 ifill_done_reg ( | |
| 768 | .scan_in(ifill_done_reg_scanin), | |
| 769 | .scan_out(ifill_done_reg_scanout), | |
| 770 | .l1clk( l1clk ), | |
| 771 | .din (leave_fill_rdy0), | |
| 772 | .dout (tsm_ifill_done_bf), | |
| 773 | .siclk(siclk), | |
| 774 | .soclk(soclk)); | |
| 775 | ||
| 776 | assign tsm_fill_rdy0 = fill_rdy0_state ; | |
| 777 | ||
| 778 | /////////////////////////////////////////////////////////////////////// | |
| 779 | // Spare circuits // | |
| 780 | /////////////////////////////////////////////////////////////////////// | |
| 781 | ifu_ftu_tsm_ctl_spare_ctl_macro__num_1 spares ( | |
| 782 | .scan_in(spares_scanin), | |
| 783 | .scan_out(spares_scanout), | |
| 784 | .l1clk (l1clk), | |
| 785 | .siclk(siclk), | |
| 786 | .soclk(soclk) | |
| 787 | ); | |
| 788 | ||
| 789 | ||
| 790 | ||
| 791 | ||
| 792 | // assign tsm_fill_rdy1 = fill_rdy1_state ; | |
| 793 | supply0 vss; | |
| 794 | supply1 vdd; | |
| 795 | // fixscan start: | |
| 796 | assign reset_wait_reg_scanin = scan_in ; | |
| 797 | assign rmiss_null_reg_l_scanin = reset_wait_reg_scanout ; | |
| 798 | assign rmiss_wait_reg_scanin = rmiss_null_reg_l_scanout ; | |
| 799 | assign no_new_miss_reg_scanin = rmiss_wait_reg_scanout ; | |
| 800 | assign lsu_no_ic_miss_reg_scanin = no_new_miss_reg_scanout ; | |
| 801 | assign lsu_stops_fetch_reg_scanin = lsu_no_ic_miss_reg_scanout; | |
| 802 | assign inv_stops_fetch_reg_scanin = lsu_stops_fetch_reg_scanout; | |
| 803 | assign can_miss_refill_reg_scanin = inv_stops_fetch_reg_scanout; | |
| 804 | assign can_miss_wait_reg_scanin = can_miss_refill_reg_scanout; | |
| 805 | assign fill_rdy0_reg_scanin = can_miss_wait_reg_scanout; | |
| 806 | assign asi_rd_stops_fetch_reg_scanin = fill_rdy0_reg_scanout ; | |
| 807 | assign asi_wr_stops_fetch_reg_scanin = asi_rd_stops_fetch_reg_scanout; | |
| 808 | assign dmiss_wait_reg_scanin = asi_wr_stops_fetch_reg_scanout; | |
| 809 | assign reset_dmiss_reg_scanin = dmiss_wait_reg_scanout ; | |
| 810 | assign fill_wait_reg_scanin = reset_dmiss_reg_scanout ; | |
| 811 | assign itlb_miss_wait_reg_scanin = fill_wait_reg_scanout ; | |
| 812 | assign err_wait_reg_scanin = itlb_miss_wait_reg_scanout; | |
| 813 | assign no_room_wait_reg_scanin = err_wait_reg_scanout ; | |
| 814 | assign itlb_demap_reg_scanin = no_room_wait_reg_scanout ; | |
| 815 | assign itlb_write_reg_scanin = itlb_demap_reg_scanout ; | |
| 816 | assign flush_ifu_reg_scanin = itlb_write_reg_scanout ; | |
| 817 | assign tlu_red_reg_scanin = flush_ifu_reg_scanout ; | |
| 818 | assign tlu_sf_reg_scanin = tlu_red_reg_scanout ; | |
| 819 | assign ignore_by_pass_reg_scanin = tlu_sf_reg_scanout ; | |
| 820 | assign no_icmiss_pending_reg_scanin = ignore_by_pass_reg_scanout; | |
| 821 | assign ifill_done_reg_scanin = no_icmiss_pending_reg_scanout; | |
| 822 | assign spares_scanin = ifill_done_reg_scanout ; | |
| 823 | assign scan_out = spares_scanout ; | |
| 824 | // fixscan end: | |
| 825 | endmodule | |
| 826 | ||
| 827 | ||
| 828 | ||
| 829 | ||
| 830 | ||
| 831 | ||
| 832 | // any PARAMS parms go into naming of macro | |
| 833 | ||
| 834 | module ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 ( | |
| 835 | din, | |
| 836 | l1clk, | |
| 837 | scan_in, | |
| 838 | siclk, | |
| 839 | soclk, | |
| 840 | dout, | |
| 841 | scan_out); | |
| 842 | wire [0:0] fdin; | |
| 843 | ||
| 844 | input [0:0] din; | |
| 845 | input l1clk; | |
| 846 | input scan_in; | |
| 847 | ||
| 848 | ||
| 849 | input siclk; | |
| 850 | input soclk; | |
| 851 | ||
| 852 | output [0:0] dout; | |
| 853 | output scan_out; | |
| 854 | assign fdin[0:0] = din[0:0]; | |
| 855 | ||
| 856 | ||
| 857 | ||
| 858 | ||
| 859 | ||
| 860 | ||
| 861 | dff #(1) d0_0 ( | |
| 862 | .l1clk(l1clk), | |
| 863 | .siclk(siclk), | |
| 864 | .soclk(soclk), | |
| 865 | .d(fdin[0:0]), | |
| 866 | .si(scan_in), | |
| 867 | .so(scan_out), | |
| 868 | .q(dout[0:0]) | |
| 869 | ); | |
| 870 | ||
| 871 | ||
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| 881 | ||
| 882 | endmodule | |
| 883 | ||
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| 885 | ||
| 886 | ||
| 887 | ||
| 888 | ||
| 889 | ||
| 890 | ||
| 891 | ||
| 892 | ||
| 893 | ||
| 894 | ||
| 895 | ||
| 896 | // any PARAMS parms go into naming of macro | |
| 897 | ||
| 898 | module ifu_ftu_tsm_ctl_msff_ctl_macro__width_2 ( | |
| 899 | din, | |
| 900 | l1clk, | |
| 901 | scan_in, | |
| 902 | siclk, | |
| 903 | soclk, | |
| 904 | dout, | |
| 905 | scan_out); | |
| 906 | wire [1:0] fdin; | |
| 907 | wire [0:0] so; | |
| 908 | ||
| 909 | input [1:0] din; | |
| 910 | input l1clk; | |
| 911 | input scan_in; | |
| 912 | ||
| 913 | ||
| 914 | input siclk; | |
| 915 | input soclk; | |
| 916 | ||
| 917 | output [1:0] dout; | |
| 918 | output scan_out; | |
| 919 | assign fdin[1:0] = din[1:0]; | |
| 920 | ||
| 921 | ||
| 922 | ||
| 923 | ||
| 924 | ||
| 925 | ||
| 926 | dff #(2) d0_0 ( | |
| 927 | .l1clk(l1clk), | |
| 928 | .siclk(siclk), | |
| 929 | .soclk(soclk), | |
| 930 | .d(fdin[1:0]), | |
| 931 | .si({scan_in,so[0:0]}), | |
| 932 | .so({so[0:0],scan_out}), | |
| 933 | .q(dout[1:0]) | |
| 934 | ); | |
| 935 | ||
| 936 | ||
| 937 | ||
| 938 | ||
| 939 | ||
| 940 | ||
| 941 | ||
| 942 | ||
| 943 | ||
| 944 | ||
| 945 | ||
| 946 | ||
| 947 | endmodule | |
| 948 | ||
| 949 | ||
| 950 | ||
| 951 | ||
| 952 | ||
| 953 | ||
| 954 | ||
| 955 | ||
| 956 | ||
| 957 | // Description: Spare gate macro for control blocks | |
| 958 | // | |
| 959 | // Param num controls the number of times the macro is added | |
| 960 | // flops=0 can be used to use only combination spare logic | |
| 961 | ||
| 962 | ||
| 963 | module ifu_ftu_tsm_ctl_spare_ctl_macro__num_1 ( | |
| 964 | l1clk, | |
| 965 | scan_in, | |
| 966 | siclk, | |
| 967 | soclk, | |
| 968 | scan_out); | |
| 969 | wire si_0; | |
| 970 | wire so_0; | |
| 971 | wire spare0_flop_unused; | |
| 972 | wire spare0_buf_32x_unused; | |
| 973 | wire spare0_nand3_8x_unused; | |
| 974 | wire spare0_inv_8x_unused; | |
| 975 | wire spare0_aoi22_4x_unused; | |
| 976 | wire spare0_buf_8x_unused; | |
| 977 | wire spare0_oai22_4x_unused; | |
| 978 | wire spare0_inv_16x_unused; | |
| 979 | wire spare0_nand2_16x_unused; | |
| 980 | wire spare0_nor3_4x_unused; | |
| 981 | wire spare0_nand2_8x_unused; | |
| 982 | wire spare0_buf_16x_unused; | |
| 983 | wire spare0_nor2_16x_unused; | |
| 984 | wire spare0_inv_32x_unused; | |
| 985 | ||
| 986 | ||
| 987 | input l1clk; | |
| 988 | input scan_in; | |
| 989 | input siclk; | |
| 990 | input soclk; | |
| 991 | output scan_out; | |
| 992 | ||
| 993 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
| 994 | .siclk(siclk), | |
| 995 | .soclk(soclk), | |
| 996 | .si(si_0), | |
| 997 | .so(so_0), | |
| 998 | .d(1'b0), | |
| 999 | .q(spare0_flop_unused)); | |
| 1000 | assign si_0 = scan_in; | |
| 1001 | ||
| 1002 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
| 1003 | .out(spare0_buf_32x_unused)); | |
| 1004 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
| 1005 | .in1(1'b1), | |
| 1006 | .in2(1'b1), | |
| 1007 | .out(spare0_nand3_8x_unused)); | |
| 1008 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
| 1009 | .out(spare0_inv_8x_unused)); | |
| 1010 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
| 1011 | .in01(1'b1), | |
| 1012 | .in10(1'b1), | |
| 1013 | .in11(1'b1), | |
| 1014 | .out(spare0_aoi22_4x_unused)); | |
| 1015 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
| 1016 | .out(spare0_buf_8x_unused)); | |
| 1017 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
| 1018 | .in01(1'b1), | |
| 1019 | .in10(1'b1), | |
| 1020 | .in11(1'b1), | |
| 1021 | .out(spare0_oai22_4x_unused)); | |
| 1022 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
| 1023 | .out(spare0_inv_16x_unused)); | |
| 1024 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
| 1025 | .in1(1'b1), | |
| 1026 | .out(spare0_nand2_16x_unused)); | |
| 1027 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
| 1028 | .in1(1'b0), | |
| 1029 | .in2(1'b0), | |
| 1030 | .out(spare0_nor3_4x_unused)); | |
| 1031 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
| 1032 | .in1(1'b1), | |
| 1033 | .out(spare0_nand2_8x_unused)); | |
| 1034 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
| 1035 | .out(spare0_buf_16x_unused)); | |
| 1036 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
| 1037 | .in1(1'b0), | |
| 1038 | .out(spare0_nor2_16x_unused)); | |
| 1039 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
| 1040 | .out(spare0_inv_32x_unused)); | |
| 1041 | assign scan_out = so_0; | |
| 1042 | ||
| 1043 | ||
| 1044 | ||
| 1045 | endmodule | |
| 1046 |