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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_asc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_asc_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_scan_en, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | scan_out, | |
43 | asd_p2a_vld, | |
44 | asd_p2a_fast, | |
45 | asd_ring_ctl, | |
46 | asd_ring_asi, | |
47 | asd_ring_addr, | |
48 | lsu_asi_clken, | |
49 | sbc_pid_kill_store_p4_, | |
50 | pic_st_asi_p4, | |
51 | asc_ring_ctl, | |
52 | asc_ring_data, | |
53 | asc_ring_local, | |
54 | asc_ring_fast, | |
55 | asc_wr_p0ctxt, | |
56 | asc_wr_p1ctxt, | |
57 | asc_wr_s0ctxt, | |
58 | asc_wr_s1ctxt, | |
59 | asc_wr_pid, | |
60 | asc_wrasi, | |
61 | asc_pid_ack, | |
62 | lsu_ring_ctl, | |
63 | lsu_ifu_tid_w, | |
64 | lsu_ifu_wr_p0ctxt, | |
65 | lsu_ifu_wr_p1ctxt, | |
66 | lsu_ifu_wr_pid); | |
67 | wire se; | |
68 | wire pce_ov; | |
69 | wire stop; | |
70 | wire siclk; | |
71 | wire soclk; | |
72 | wire l1clk_pm1; | |
73 | wire pid_ackl_c; | |
74 | wire ascl_vld_1f; | |
75 | wire hole_pend_f; | |
76 | wire pid_ackf_c; | |
77 | wire hole_vld_c; | |
78 | wire ascl_vld_c; | |
79 | wire ascl_vld_1_scanin; | |
80 | wire ascl_vld_1_scanout; | |
81 | wire asc_rngl_ctl_c; | |
82 | wire asc_rngf_ctl_c; | |
83 | wire asc_ring_ctl_c; | |
84 | wire pid_ack_scanin; | |
85 | wire pid_ack_scanout; | |
86 | wire rngf_ctl; | |
87 | wire rngl_ctl; | |
88 | wire [3:0] count_c; | |
89 | wire [3:0] count_f; | |
90 | wire hole_count_scanin; | |
91 | wire hole_count_scanout; | |
92 | wire hole_pend_c; | |
93 | wire create_tlb_hole; | |
94 | wire hole_pend_state_scanin; | |
95 | wire hole_pend_state_scanout; | |
96 | wire rngf_unused; | |
97 | wire asi_write; | |
98 | wire asr_write; | |
99 | wire asi_p0ctxt_wr; | |
100 | wire asi_p1ctxt_wr; | |
101 | wire asi_s0ctxt_wr; | |
102 | wire asi_s1ctxt_wr; | |
103 | wire asi_pid_wr; | |
104 | wire wrasi; | |
105 | wire dff_asr_wr_scanin; | |
106 | wire dff_asr_wr_scanout; | |
107 | wire [2:0] asr_wr_tid_2; | |
108 | wire asi_p0ctxt_wr_2; | |
109 | wire asi_p1ctxt_wr_2; | |
110 | wire asi_s0ctxt_wr_2; | |
111 | wire asi_s1ctxt_wr_2; | |
112 | wire asi_pid_wr_2; | |
113 | wire wrasi_2; | |
114 | wire spares_scanin; | |
115 | wire spares_scanout; | |
116 | ||
117 | ||
118 | // globals | |
119 | input l2clk; | |
120 | input scan_in; | |
121 | input tcu_pce_ov; // scan signals | |
122 | input tcu_scan_en; | |
123 | input spc_aclk; | |
124 | input spc_bclk; | |
125 | output scan_out; | |
126 | ||
127 | input asd_p2a_vld; // valid packet from pid | |
128 | input asd_p2a_fast; // packet from pid is destined for fast bus | |
129 | ||
130 | input [63:56] asd_ring_ctl; // Must look for DTLB writes to create hole | |
131 | input [7:0] asd_ring_asi; | |
132 | input [8:3] asd_ring_addr; | |
133 | input lsu_asi_clken; | |
134 | ||
135 | input sbc_pid_kill_store_p4_; | |
136 | input pic_st_asi_p4; | |
137 | ||
138 | output asc_ring_ctl; // ring control to asd | |
139 | output asc_ring_data; // ring data to asd | |
140 | output asc_ring_local; // local ring to asd | |
141 | output asc_ring_fast; // fast ring to asd | |
142 | ||
143 | output [7:0] asc_wr_p0ctxt; | |
144 | output [7:0] asc_wr_p1ctxt; | |
145 | output [7:0] asc_wr_s0ctxt; | |
146 | output [7:0] asc_wr_s1ctxt; | |
147 | output [7:0] asc_wr_pid; | |
148 | output [7:0] asc_wrasi; | |
149 | ||
150 | ||
151 | output asc_pid_ack; // packet acknowledge to pid | |
152 | ||
153 | output lsu_ring_ctl; | |
154 | ||
155 | output [2:0] lsu_ifu_tid_w; | |
156 | output lsu_ifu_wr_p0ctxt; | |
157 | output lsu_ifu_wr_p1ctxt; | |
158 | output lsu_ifu_wr_pid; | |
159 | ||
160 | // scan renames | |
161 | assign se = tcu_scan_en; | |
162 | assign pce_ov = tcu_pce_ov; | |
163 | assign stop = 1'b0; | |
164 | assign siclk = spc_aclk; | |
165 | assign soclk = spc_bclk; | |
166 | // end scan | |
167 | ||
168 | //////////////////////////////////////////////////////// | |
169 | lsu_asc_ctl_l1clkhdr_ctl_macro clkgen | |
170 | ( | |
171 | .l2clk(l2clk), | |
172 | .l1en (lsu_asi_clken ), | |
173 | .l1clk(l1clk_pm1), | |
174 | .pce_ov(pce_ov), | |
175 | .stop(stop), | |
176 | .se(se)); | |
177 | //////////////////////////////////////////////////////// | |
178 | ||
179 | //////////////////////////////////////////////////////// | |
180 | // generate an ack if a valid pid packet received and | |
181 | // not launching the first cycle of a packet on the ring, | |
182 | // and not in middle of a pending hole. | |
183 | ||
184 | // generate a hole packet if a pending hole and | |
185 | // not launching the first cycle of a packet on the ring. | |
186 | ||
187 | assign pid_ackl_c = (asd_p2a_vld & !asd_p2a_fast & !ascl_vld_1f & !hole_pend_f); | |
188 | assign pid_ackf_c = (asd_p2a_vld & asd_p2a_fast & !ascl_vld_1f & !hole_pend_f); | |
189 | ||
190 | // generate a hole every other cycle unless a pid_ack is being sent | |
191 | assign hole_vld_c = ~(pid_ackl_c | pid_ackf_c) & !ascl_vld_1f; | |
192 | ||
193 | // vld_c indicates a ctl pkt. Every other pkt is a control pkt (either a hole or an ack) | |
194 | assign ascl_vld_c = ~ascl_vld_1f; | |
195 | ||
196 | // register the first cycle valid signal | |
197 | lsu_asc_ctl_msff_ctl_macro__width_1 ascl_vld_1 | |
198 | ( | |
199 | .scan_in(ascl_vld_1_scanin), | |
200 | .scan_out(ascl_vld_1_scanout), | |
201 | .l1clk(l1clk_pm1), | |
202 | .din (ascl_vld_c), | |
203 | .dout (ascl_vld_1f), | |
204 | .siclk(siclk), | |
205 | .soclk(soclk) | |
206 | ); | |
207 | ||
208 | assign lsu_ring_ctl = ascl_vld_1f; | |
209 | ||
210 | ||
211 | assign asc_pid_ack = pid_ackl_c | pid_ackf_c; | |
212 | ||
213 | assign asc_rngl_ctl_c = ascl_vld_c & pid_ackl_c; | |
214 | assign asc_rngf_ctl_c = ascl_vld_c & pid_ackf_c; | |
215 | assign asc_ring_ctl_c = ascl_vld_c & (pid_ackf_c | pid_ackl_c); | |
216 | ||
217 | assign asc_ring_ctl = asc_ring_ctl_c; | |
218 | ||
219 | lsu_asc_ctl_msff_ctl_macro__width_3 pid_ack | |
220 | ( | |
221 | .scan_in(pid_ack_scanin), | |
222 | .scan_out(pid_ack_scanout), | |
223 | .l1clk(l1clk_pm1), | |
224 | .din ({asc_ring_ctl_c,asc_rngf_ctl_c,asc_rngl_ctl_c}), | |
225 | .dout ({asc_ring_data ,rngf_ctl, rngl_ctl }), | |
226 | .siclk(siclk), | |
227 | .soclk(soclk) | |
228 | ); | |
229 | ||
230 | assign asc_ring_local = (asc_rngl_ctl_c | rngl_ctl) & (sbc_pid_kill_store_p4_ | ~pic_st_asi_p4); | |
231 | assign asc_ring_fast = (asc_rngf_ctl_c | rngf_ctl) & (sbc_pid_kill_store_p4_ | ~pic_st_asi_p4); | |
232 | ||
233 | ///////////////////////////////////////////////////////////// | |
234 | // HOLE INSERTION | |
235 | ///////////////////////////////////////////////////////////// | |
236 | // Logic to insert hole every 16 cycles. | |
237 | // Duplicated for fast and local rings | |
238 | // 4 bit counter to insert a hole every 16 cycles | |
239 | // This logic exists for local and fast rings | |
240 | assign count_c[3:0] = count_f[3:0] + 4'b1; | |
241 | ||
242 | lsu_asc_ctl_msff_ctl_macro__width_4 hole_count | |
243 | ( | |
244 | .scan_in(hole_count_scanin), | |
245 | .scan_out(hole_count_scanout), | |
246 | .l1clk(l1clk_pm1), | |
247 | .din (count_c[3:0]), | |
248 | .dout (count_f[3:0]), | |
249 | .siclk(siclk), | |
250 | .soclk(soclk) | |
251 | ); | |
252 | ||
253 | // set state to indicate pending hole, clear when hole inserted | |
254 | ||
255 | assign hole_pend_c = ((count_f[3:0] == 4'b0) | hole_pend_f | create_tlb_hole) & !hole_vld_c; | |
256 | ||
257 | lsu_asc_ctl_msff_ctl_macro__width_1 hole_pend_state | |
258 | ( | |
259 | .scan_in(hole_pend_state_scanin), | |
260 | .scan_out(hole_pend_state_scanout), | |
261 | .l1clk(l1clk_pm1), | |
262 | .din (hole_pend_c), | |
263 | .dout (hole_pend_f), | |
264 | .siclk(siclk), | |
265 | .soclk(soclk) | |
266 | ); | |
267 | ||
268 | //////////////////////////////////////////////////////////// | |
269 | // There is a special case in which a hole must be created on the | |
270 | // fast ring. When a write to the DTLB_DATA_IN_REG goes out on the | |
271 | // ring, a hold needs to be created afterwards to ensure that the | |
272 | // bus is free to accomodate the tlb write. (The MMU sends tlb | |
273 | // reload information over the ASI bus.) | |
274 | ||
275 | assign create_tlb_hole = rngf_ctl & // ctl pkt | |
276 | asd_ring_ctl[63] & // valid | |
277 | ~asd_ring_ctl[61] & ~asd_ring_ctl[60] & // type=ASI | |
278 | ~asd_ring_ctl[59] & // write | |
279 | ((asd_ring_asi[7:0] == 8'h5c) | // ASI=DTLB_DATA_IN_REG | |
280 | (asd_ring_asi[7:0] == 8'h5d) | // ASI=DTLB_DATA_ACCESS_REG | |
281 | (asd_ring_asi[7:0] == 8'h5f)); // ASI=DMMU_DEMAP | |
282 | ||
283 | assign rngf_unused = asd_ring_ctl[62]; | |
284 | ||
285 | ||
286 | //////////////////////////////////////////////////////////// | |
287 | // Interface for ASI registers located in the LSU | |
288 | ||
289 | assign asi_write = rngf_ctl & asd_ring_ctl[63] & ~asd_ring_ctl[61] & ~asd_ring_ctl[60] & ~asd_ring_ctl[59]; | |
290 | assign asr_write = rngf_ctl & asd_ring_ctl[63] & ~asd_ring_ctl[61] & asd_ring_ctl[60] & ~asd_ring_ctl[59]; | |
291 | assign asi_p0ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[8:3] == 6'b000001); | |
292 | assign asi_p1ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[7:3] == 5'b00001); | |
293 | assign asi_s0ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[8:3] == 6'b000010); | |
294 | assign asi_s1ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[7:3] == 5'b00010); | |
295 | assign asi_pid_wr = asi_write & (asd_ring_asi[7:0] == 8'h58) & asd_ring_addr[7]; | |
296 | assign wrasi = asr_write & (asd_ring_asi[4:0] == 5'b00011); | |
297 | ||
298 | lsu_asc_ctl_msff_ctl_macro__width_9 dff_asr_wr ( | |
299 | .scan_in(dff_asr_wr_scanin), | |
300 | .scan_out(dff_asr_wr_scanout), | |
301 | .l1clk(l1clk_pm1), | |
302 | .din ({asd_ring_ctl[58:56], asi_p0ctxt_wr, asi_p1ctxt_wr, asi_s0ctxt_wr, asi_s1ctxt_wr, asi_pid_wr, wrasi}), | |
303 | .dout ({asr_wr_tid_2[2:0], asi_p0ctxt_wr_2,asi_p1ctxt_wr_2,asi_s0ctxt_wr_2,asi_s1ctxt_wr_2,asi_pid_wr_2,wrasi_2}), | |
304 | .siclk(siclk), | |
305 | .soclk(soclk) | |
306 | ); | |
307 | ||
308 | assign lsu_ifu_tid_w[2:0] = asr_wr_tid_2[2:0]; | |
309 | assign lsu_ifu_wr_p0ctxt = asi_p0ctxt_wr_2; | |
310 | assign lsu_ifu_wr_p1ctxt = asi_p1ctxt_wr_2; | |
311 | assign lsu_ifu_wr_pid = asi_pid_wr_2; | |
312 | ||
313 | assign asc_wr_p0ctxt[0] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0); | |
314 | assign asc_wr_p0ctxt[1] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1); | |
315 | assign asc_wr_p0ctxt[2] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2); | |
316 | assign asc_wr_p0ctxt[3] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3); | |
317 | assign asc_wr_p0ctxt[4] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4); | |
318 | assign asc_wr_p0ctxt[5] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5); | |
319 | assign asc_wr_p0ctxt[6] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6); | |
320 | assign asc_wr_p0ctxt[7] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7); | |
321 | ||
322 | assign asc_wr_p1ctxt[0] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0); | |
323 | assign asc_wr_p1ctxt[1] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1); | |
324 | assign asc_wr_p1ctxt[2] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2); | |
325 | assign asc_wr_p1ctxt[3] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3); | |
326 | assign asc_wr_p1ctxt[4] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4); | |
327 | assign asc_wr_p1ctxt[5] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5); | |
328 | assign asc_wr_p1ctxt[6] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6); | |
329 | assign asc_wr_p1ctxt[7] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7); | |
330 | ||
331 | assign asc_wr_s0ctxt[0] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0); | |
332 | assign asc_wr_s0ctxt[1] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1); | |
333 | assign asc_wr_s0ctxt[2] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2); | |
334 | assign asc_wr_s0ctxt[3] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3); | |
335 | assign asc_wr_s0ctxt[4] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4); | |
336 | assign asc_wr_s0ctxt[5] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5); | |
337 | assign asc_wr_s0ctxt[6] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6); | |
338 | assign asc_wr_s0ctxt[7] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7); | |
339 | ||
340 | assign asc_wr_s1ctxt[0] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0); | |
341 | assign asc_wr_s1ctxt[1] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1); | |
342 | assign asc_wr_s1ctxt[2] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2); | |
343 | assign asc_wr_s1ctxt[3] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3); | |
344 | assign asc_wr_s1ctxt[4] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4); | |
345 | assign asc_wr_s1ctxt[5] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5); | |
346 | assign asc_wr_s1ctxt[6] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6); | |
347 | assign asc_wr_s1ctxt[7] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7); | |
348 | ||
349 | assign asc_wr_pid[0] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd0); | |
350 | assign asc_wr_pid[1] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd1); | |
351 | assign asc_wr_pid[2] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd2); | |
352 | assign asc_wr_pid[3] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd3); | |
353 | assign asc_wr_pid[4] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd4); | |
354 | assign asc_wr_pid[5] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd5); | |
355 | assign asc_wr_pid[6] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd6); | |
356 | assign asc_wr_pid[7] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd7); | |
357 | ||
358 | assign asc_wrasi[0] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd0); | |
359 | assign asc_wrasi[1] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd1); | |
360 | assign asc_wrasi[2] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd2); | |
361 | assign asc_wrasi[3] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd3); | |
362 | assign asc_wrasi[4] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd4); | |
363 | assign asc_wrasi[5] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd5); | |
364 | assign asc_wrasi[6] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd6); | |
365 | assign asc_wrasi[7] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd7); | |
366 | ||
367 | lsu_asc_ctl_spare_ctl_macro spares ( | |
368 | .scan_in(spares_scanin), | |
369 | .scan_out(spares_scanout), | |
370 | .l1clk (l1clk_pm1), | |
371 | .siclk(siclk), | |
372 | .soclk(soclk) | |
373 | ); | |
374 | ||
375 | supply0 vss; | |
376 | supply1 vdd; | |
377 | // fixscan start: | |
378 | assign ascl_vld_1_scanin = scan_in ; | |
379 | assign pid_ack_scanin = ascl_vld_1_scanout ; | |
380 | assign hole_count_scanin = pid_ack_scanout ; | |
381 | assign hole_pend_state_scanin = hole_count_scanout ; | |
382 | assign dff_asr_wr_scanin = hole_pend_state_scanout ; | |
383 | assign spares_scanin = dff_asr_wr_scanout ; | |
384 | assign scan_out = spares_scanout ; | |
385 | // fixscan end: | |
386 | endmodule | |
387 | ||
388 | ||
389 | ||
390 | ||
391 | ||
392 | ||
393 | ||
394 | // any PARAMS parms go into naming of macro | |
395 | ||
396 | module lsu_asc_ctl_l1clkhdr_ctl_macro ( | |
397 | l2clk, | |
398 | l1en, | |
399 | pce_ov, | |
400 | stop, | |
401 | se, | |
402 | l1clk); | |
403 | ||
404 | ||
405 | input l2clk; | |
406 | input l1en; | |
407 | input pce_ov; | |
408 | input stop; | |
409 | input se; | |
410 | output l1clk; | |
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | cl_sc1_l1hdr_8x c_0 ( | |
417 | ||
418 | ||
419 | .l2clk(l2clk), | |
420 | .pce(l1en), | |
421 | .l1clk(l1clk), | |
422 | .se(se), | |
423 | .pce_ov(pce_ov), | |
424 | .stop(stop) | |
425 | ); | |
426 | ||
427 | ||
428 | ||
429 | endmodule | |
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | ||
439 | ||
440 | ||
441 | ||
442 | ||
443 | // any PARAMS parms go into naming of macro | |
444 | ||
445 | module lsu_asc_ctl_msff_ctl_macro__width_1 ( | |
446 | din, | |
447 | l1clk, | |
448 | scan_in, | |
449 | siclk, | |
450 | soclk, | |
451 | dout, | |
452 | scan_out); | |
453 | wire [0:0] fdin; | |
454 | ||
455 | input [0:0] din; | |
456 | input l1clk; | |
457 | input scan_in; | |
458 | ||
459 | ||
460 | input siclk; | |
461 | input soclk; | |
462 | ||
463 | output [0:0] dout; | |
464 | output scan_out; | |
465 | assign fdin[0:0] = din[0:0]; | |
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | dff #(1) d0_0 ( | |
473 | .l1clk(l1clk), | |
474 | .siclk(siclk), | |
475 | .soclk(soclk), | |
476 | .d(fdin[0:0]), | |
477 | .si(scan_in), | |
478 | .so(scan_out), | |
479 | .q(dout[0:0]) | |
480 | ); | |
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | ||
493 | endmodule | |
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | ||
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | // any PARAMS parms go into naming of macro | |
508 | ||
509 | module lsu_asc_ctl_msff_ctl_macro__width_3 ( | |
510 | din, | |
511 | l1clk, | |
512 | scan_in, | |
513 | siclk, | |
514 | soclk, | |
515 | dout, | |
516 | scan_out); | |
517 | wire [2:0] fdin; | |
518 | wire [1:0] so; | |
519 | ||
520 | input [2:0] din; | |
521 | input l1clk; | |
522 | input scan_in; | |
523 | ||
524 | ||
525 | input siclk; | |
526 | input soclk; | |
527 | ||
528 | output [2:0] dout; | |
529 | output scan_out; | |
530 | assign fdin[2:0] = din[2:0]; | |
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | dff #(3) d0_0 ( | |
538 | .l1clk(l1clk), | |
539 | .siclk(siclk), | |
540 | .soclk(soclk), | |
541 | .d(fdin[2:0]), | |
542 | .si({scan_in,so[1:0]}), | |
543 | .so({so[1:0],scan_out}), | |
544 | .q(dout[2:0]) | |
545 | ); | |
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | endmodule | |
559 | ||
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | // any PARAMS parms go into naming of macro | |
573 | ||
574 | module lsu_asc_ctl_msff_ctl_macro__width_4 ( | |
575 | din, | |
576 | l1clk, | |
577 | scan_in, | |
578 | siclk, | |
579 | soclk, | |
580 | dout, | |
581 | scan_out); | |
582 | wire [3:0] fdin; | |
583 | wire [2:0] so; | |
584 | ||
585 | input [3:0] din; | |
586 | input l1clk; | |
587 | input scan_in; | |
588 | ||
589 | ||
590 | input siclk; | |
591 | input soclk; | |
592 | ||
593 | output [3:0] dout; | |
594 | output scan_out; | |
595 | assign fdin[3:0] = din[3:0]; | |
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | dff #(4) d0_0 ( | |
603 | .l1clk(l1clk), | |
604 | .siclk(siclk), | |
605 | .soclk(soclk), | |
606 | .d(fdin[3:0]), | |
607 | .si({scan_in,so[2:0]}), | |
608 | .so({so[2:0],scan_out}), | |
609 | .q(dout[3:0]) | |
610 | ); | |
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | endmodule | |
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | // any PARAMS parms go into naming of macro | |
638 | ||
639 | module lsu_asc_ctl_msff_ctl_macro__width_9 ( | |
640 | din, | |
641 | l1clk, | |
642 | scan_in, | |
643 | siclk, | |
644 | soclk, | |
645 | dout, | |
646 | scan_out); | |
647 | wire [8:0] fdin; | |
648 | wire [7:0] so; | |
649 | ||
650 | input [8:0] din; | |
651 | input l1clk; | |
652 | input scan_in; | |
653 | ||
654 | ||
655 | input siclk; | |
656 | input soclk; | |
657 | ||
658 | output [8:0] dout; | |
659 | output scan_out; | |
660 | assign fdin[8:0] = din[8:0]; | |
661 | ||
662 | ||
663 | ||
664 | ||
665 | ||
666 | ||
667 | dff #(9) d0_0 ( | |
668 | .l1clk(l1clk), | |
669 | .siclk(siclk), | |
670 | .soclk(soclk), | |
671 | .d(fdin[8:0]), | |
672 | .si({scan_in,so[7:0]}), | |
673 | .so({so[7:0],scan_out}), | |
674 | .q(dout[8:0]) | |
675 | ); | |
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | endmodule | |
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | // Description: Spare gate macro for control blocks | |
699 | // | |
700 | // Param num controls the number of times the macro is added | |
701 | // flops=0 can be used to use only combination spare logic | |
702 | ||
703 | ||
704 | module lsu_asc_ctl_spare_ctl_macro ( | |
705 | l1clk, | |
706 | scan_in, | |
707 | siclk, | |
708 | soclk, | |
709 | scan_out); | |
710 | wire si_0; | |
711 | wire so_0; | |
712 | wire spare0_flop_unused; | |
713 | wire spare0_buf_32x_unused; | |
714 | wire spare0_nand3_8x_unused; | |
715 | wire spare0_inv_8x_unused; | |
716 | wire spare0_aoi22_4x_unused; | |
717 | wire spare0_buf_8x_unused; | |
718 | wire spare0_oai22_4x_unused; | |
719 | wire spare0_inv_16x_unused; | |
720 | wire spare0_nand2_16x_unused; | |
721 | wire spare0_nor3_4x_unused; | |
722 | wire spare0_nand2_8x_unused; | |
723 | wire spare0_buf_16x_unused; | |
724 | wire spare0_nor2_16x_unused; | |
725 | wire spare0_inv_32x_unused; | |
726 | ||
727 | ||
728 | input l1clk; | |
729 | input scan_in; | |
730 | input siclk; | |
731 | input soclk; | |
732 | output scan_out; | |
733 | ||
734 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
735 | .siclk(siclk), | |
736 | .soclk(soclk), | |
737 | .si(si_0), | |
738 | .so(so_0), | |
739 | .d(1'b0), | |
740 | .q(spare0_flop_unused)); | |
741 | assign si_0 = scan_in; | |
742 | ||
743 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
744 | .out(spare0_buf_32x_unused)); | |
745 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
746 | .in1(1'b1), | |
747 | .in2(1'b1), | |
748 | .out(spare0_nand3_8x_unused)); | |
749 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
750 | .out(spare0_inv_8x_unused)); | |
751 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
752 | .in01(1'b1), | |
753 | .in10(1'b1), | |
754 | .in11(1'b1), | |
755 | .out(spare0_aoi22_4x_unused)); | |
756 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
757 | .out(spare0_buf_8x_unused)); | |
758 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
759 | .in01(1'b1), | |
760 | .in10(1'b1), | |
761 | .in11(1'b1), | |
762 | .out(spare0_oai22_4x_unused)); | |
763 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
764 | .out(spare0_inv_16x_unused)); | |
765 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
766 | .in1(1'b1), | |
767 | .out(spare0_nand2_16x_unused)); | |
768 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
769 | .in1(1'b0), | |
770 | .in2(1'b0), | |
771 | .out(spare0_nor3_4x_unused)); | |
772 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
773 | .in1(1'b1), | |
774 | .out(spare0_nand2_8x_unused)); | |
775 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
776 | .out(spare0_buf_16x_unused)); | |
777 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
778 | .in1(1'b0), | |
779 | .out(spare0_nor2_16x_unused)); | |
780 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
781 | .out(spare0_inv_32x_unused)); | |
782 | assign scan_out = so_0; | |
783 | ||
784 | ||
785 | ||
786 | endmodule | |
787 |