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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_red_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_red_ctl ( | |
36 | efu_spc_fuse_data, | |
37 | efu_spc_fuse_dxfer_en, | |
38 | efu_spc_fuse_dclr, | |
39 | io_cmp_sync_en, | |
40 | cmp_io_sync_en, | |
41 | spc_efu_fuse_ddata, | |
42 | spc_efu_fuse_dxfer_en, | |
43 | hdr_sram_rvalue, | |
44 | hdr_sram_rid, | |
45 | hdr_sram_wr_en, | |
46 | hdr_sram_red_clr, | |
47 | sram_hdr_read_data, | |
48 | l2clk, | |
49 | tcu_pce_ov, | |
50 | spc_aclk, | |
51 | spc_bclk, | |
52 | tcu_scan_en, | |
53 | scan_in, | |
54 | scan_out); | |
55 | wire sram_header_instance_scanin; | |
56 | wire sram_header_instance_scanout; | |
57 | wire [3:0] rval_unused; | |
58 | wire [8:0] rid_unused; | |
59 | ||
60 | ||
61 | // EFU to SRAM header | |
62 | input efu_spc_fuse_data; // Efuse to dest data info | |
63 | input efu_spc_fuse_dxfer_en;// Efuse to dest data valid | |
64 | input efu_spc_fuse_dclr; // EFuse to dest clear corresponding redudancy register | |
65 | input io_cmp_sync_en; // (ccu_slow_cmp_sync_en), | |
66 | input cmp_io_sync_en; // (ccu_cmp_slow_sync_en), | |
67 | ||
68 | ||
69 | // SRAM header to EFU | |
70 | output spc_efu_fuse_ddata; // Dest to EFU read data return | |
71 | output spc_efu_fuse_dxfer_en; // Dest to EFU read data return valid | |
72 | ||
73 | // SRAM header to SRAM | |
74 | output [6:0] hdr_sram_rvalue; // Redudancy Value to be written | |
75 | // to SRAM red reg | |
76 | output [1:0] hdr_sram_rid; // Redudancy ID to address SRAM | |
77 | // red reg | |
78 | output hdr_sram_wr_en; // Redudancy register write | |
79 | // enable to write to red reg | |
80 | output hdr_sram_red_clr; // Redudancy register clear | |
81 | // | |
82 | ||
83 | // SRAM to SRAM header | |
84 | input [6:0] sram_hdr_read_data; // Redudancy Read data from SRAM | |
85 | ||
86 | ||
87 | // other common signals | |
88 | input l2clk; | |
89 | input tcu_pce_ov; | |
90 | input spc_aclk; | |
91 | input spc_bclk; | |
92 | input tcu_scan_en; | |
93 | input scan_in; | |
94 | output scan_out; | |
95 | ||
96 | n2_efuhdr1_ctl sram_header_instance | |
97 | ( | |
98 | // All the I/o ports to and from EFU <-> cluster | |
99 | .efu_hdr_write_data (efu_spc_fuse_data), | |
100 | .efu_hdr_xfer_en (efu_spc_fuse_dxfer_en), | |
101 | .io_cmp_sync_en (io_cmp_sync_en), | |
102 | .cmp_io_sync_en (cmp_io_sync_en), | |
103 | .efu_hdr_clr (efu_spc_fuse_dclr), | |
104 | .hdr_efu_read_data (spc_efu_fuse_ddata), | |
105 | .hdr_efu_xfer_en (spc_efu_fuse_dxfer_en), | |
106 | // All other general signals for DFT and clocks | |
107 | .tcu_aclk (spc_aclk), | |
108 | .tcu_bclk (spc_bclk), | |
109 | .tcu_clk_stop (1'b0), | |
110 | .scan_in(sram_header_instance_scanin), | |
111 | .scan_out(sram_header_instance_scanout), | |
112 | .l2clk (l2clk), | |
113 | // All the I/o ports to and from SRAM | |
114 | .sram_hdr_read_data ({4'b0,sram_hdr_read_data[6:0]}), | |
115 | .hdr_sram_rvalue ({rval_unused[3:0],hdr_sram_rvalue[6:0]}), | |
116 | .hdr_sram_rid ({rid_unused[8:0],hdr_sram_rid[1:0]}), | |
117 | .hdr_sram_wr_en (hdr_sram_wr_en), | |
118 | .hdr_sram_red_clr (hdr_sram_red_clr), | |
119 | .tcu_pce_ov(tcu_pce_ov), | |
120 | .tcu_scan_en(tcu_scan_en) | |
121 | ); | |
122 | ||
123 | ||
124 | lsu_red_ctl_spare_ctl_macro__flops_0__num_1 spares (); | |
125 | ||
126 | ||
127 | // fixscan start: | |
128 | assign sram_header_instance_scanin = scan_in ; | |
129 | assign scan_out = sram_header_instance_scanout; | |
130 | // fixscan end: | |
131 | endmodule | |
132 | ||
133 | ||
134 | ||
135 | // any PARAMS parms go into naming of macro | |
136 | ||
137 | module lsu_red_ctl_l1clkhdr_ctl_macro ( | |
138 | l2clk, | |
139 | l1en, | |
140 | pce_ov, | |
141 | stop, | |
142 | se, | |
143 | l1clk); | |
144 | ||
145 | ||
146 | input l2clk; | |
147 | input l1en; | |
148 | input pce_ov; | |
149 | input stop; | |
150 | input se; | |
151 | output l1clk; | |
152 | ||
153 | ||
154 | ||
155 | ||
156 | ||
157 | cl_sc1_l1hdr_8x c_0 ( | |
158 | ||
159 | ||
160 | .l2clk(l2clk), | |
161 | .pce(l1en), | |
162 | .l1clk(l1clk), | |
163 | .se(se), | |
164 | .pce_ov(pce_ov), | |
165 | .stop(stop) | |
166 | ); | |
167 | ||
168 | ||
169 | ||
170 | endmodule | |
171 | ||
172 | ||
173 | ||
174 | ||
175 | ||
176 | ||
177 | ||
178 | ||
179 | ||
180 | ||
181 | ||
182 | ||
183 | ||
184 | // any PARAMS parms go into naming of macro | |
185 | ||
186 | module lsu_red_ctl_msff_ctl_macro__width_1 ( | |
187 | din, | |
188 | l1clk, | |
189 | scan_in, | |
190 | siclk, | |
191 | soclk, | |
192 | dout, | |
193 | scan_out); | |
194 | wire [0:0] fdin; | |
195 | ||
196 | input [0:0] din; | |
197 | input l1clk; | |
198 | input scan_in; | |
199 | ||
200 | ||
201 | input siclk; | |
202 | input soclk; | |
203 | ||
204 | output [0:0] dout; | |
205 | output scan_out; | |
206 | assign fdin[0:0] = din[0:0]; | |
207 | ||
208 | ||
209 | ||
210 | ||
211 | ||
212 | ||
213 | dff #(1) d0_0 ( | |
214 | .l1clk(l1clk), | |
215 | .siclk(siclk), | |
216 | .soclk(soclk), | |
217 | .d(fdin[0:0]), | |
218 | .si(scan_in), | |
219 | .so(scan_out), | |
220 | .q(dout[0:0]) | |
221 | ); | |
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | ||
228 | ||
229 | ||
230 | ||
231 | ||
232 | ||
233 | ||
234 | endmodule | |
235 | ||
236 | ||
237 | ||
238 | ||
239 | ||
240 | ||
241 | ||
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | // any PARAMS parms go into naming of macro | |
249 | ||
250 | module lsu_red_ctl_msff_ctl_macro__en_1__width_4 ( | |
251 | din, | |
252 | en, | |
253 | l1clk, | |
254 | scan_in, | |
255 | siclk, | |
256 | soclk, | |
257 | dout, | |
258 | scan_out); | |
259 | wire [3:0] fdin; | |
260 | wire [2:0] so; | |
261 | ||
262 | input [3:0] din; | |
263 | input en; | |
264 | input l1clk; | |
265 | input scan_in; | |
266 | ||
267 | ||
268 | input siclk; | |
269 | input soclk; | |
270 | ||
271 | output [3:0] dout; | |
272 | output scan_out; | |
273 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | ||
280 | dff #(4) d0_0 ( | |
281 | .l1clk(l1clk), | |
282 | .siclk(siclk), | |
283 | .soclk(soclk), | |
284 | .d(fdin[3:0]), | |
285 | .si({scan_in,so[2:0]}), | |
286 | .so({so[2:0],scan_out}), | |
287 | .q(dout[3:0]) | |
288 | ); | |
289 | ||
290 | ||
291 | ||
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | endmodule | |
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | ||
312 | ||
313 | ||
314 | ||
315 | // any PARAMS parms go into naming of macro | |
316 | ||
317 | module lsu_red_ctl_msff_ctl_macro__en_1__width_22 ( | |
318 | din, | |
319 | en, | |
320 | l1clk, | |
321 | scan_in, | |
322 | siclk, | |
323 | soclk, | |
324 | dout, | |
325 | scan_out); | |
326 | wire [21:0] fdin; | |
327 | wire [20:0] so; | |
328 | ||
329 | input [21:0] din; | |
330 | input en; | |
331 | input l1clk; | |
332 | input scan_in; | |
333 | ||
334 | ||
335 | input siclk; | |
336 | input soclk; | |
337 | ||
338 | output [21:0] dout; | |
339 | output scan_out; | |
340 | assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}}); | |
341 | ||
342 | ||
343 | ||
344 | ||
345 | ||
346 | ||
347 | dff #(22) d0_0 ( | |
348 | .l1clk(l1clk), | |
349 | .siclk(siclk), | |
350 | .soclk(soclk), | |
351 | .d(fdin[21:0]), | |
352 | .si({scan_in,so[20:0]}), | |
353 | .so({so[20:0],scan_out}), | |
354 | .q(dout[21:0]) | |
355 | ); | |
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 | ||
368 | endmodule | |
369 | ||
370 | ||
371 | ||
372 | ||
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | ||
381 | ||
382 | // any PARAMS parms go into naming of macro | |
383 | ||
384 | module lsu_red_ctl_msff_ctl_macro__en_1__width_1 ( | |
385 | din, | |
386 | en, | |
387 | l1clk, | |
388 | scan_in, | |
389 | siclk, | |
390 | soclk, | |
391 | dout, | |
392 | scan_out); | |
393 | wire [0:0] fdin; | |
394 | ||
395 | input [0:0] din; | |
396 | input en; | |
397 | input l1clk; | |
398 | input scan_in; | |
399 | ||
400 | ||
401 | input siclk; | |
402 | input soclk; | |
403 | ||
404 | output [0:0] dout; | |
405 | output scan_out; | |
406 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | dff #(1) d0_0 ( | |
414 | .l1clk(l1clk), | |
415 | .siclk(siclk), | |
416 | .soclk(soclk), | |
417 | .d(fdin[0:0]), | |
418 | .si(scan_in), | |
419 | .so(scan_out), | |
420 | .q(dout[0:0]) | |
421 | ); | |
422 | ||
423 | ||
424 | ||
425 | ||
426 | ||
427 | ||
428 | ||
429 | ||
430 | ||
431 | ||
432 | ||
433 | ||
434 | endmodule | |
435 | ||
436 | ||
437 | ||
438 | ||
439 | ||
440 | ||
441 | ||
442 | ||
443 | ||
444 | ||
445 | ||
446 | ||
447 | ||
448 | // any PARAMS parms go into naming of macro | |
449 | ||
450 | module lsu_red_ctl_msff_ctl_macro__en_1__width_5 ( | |
451 | din, | |
452 | en, | |
453 | l1clk, | |
454 | scan_in, | |
455 | siclk, | |
456 | soclk, | |
457 | dout, | |
458 | scan_out); | |
459 | wire [4:0] fdin; | |
460 | wire [3:0] so; | |
461 | ||
462 | input [4:0] din; | |
463 | input en; | |
464 | input l1clk; | |
465 | input scan_in; | |
466 | ||
467 | ||
468 | input siclk; | |
469 | input soclk; | |
470 | ||
471 | output [4:0] dout; | |
472 | output scan_out; | |
473 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | dff #(5) d0_0 ( | |
481 | .l1clk(l1clk), | |
482 | .siclk(siclk), | |
483 | .soclk(soclk), | |
484 | .d(fdin[4:0]), | |
485 | .si({scan_in,so[3:0]}), | |
486 | .so({so[3:0],scan_out}), | |
487 | .q(dout[4:0]) | |
488 | ); | |
489 | ||
490 | ||
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | ||
501 | endmodule | |
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | ||
511 | // Description: Spare gate macro for control blocks | |
512 | // | |
513 | // Param num controls the number of times the macro is added | |
514 | // flops=0 can be used to use only combination spare logic | |
515 | ||
516 | ||
517 | module lsu_red_ctl_spare_ctl_macro__num_4 ( | |
518 | l1clk, | |
519 | scan_in, | |
520 | siclk, | |
521 | soclk, | |
522 | scan_out); | |
523 | wire si_0; | |
524 | wire so_0; | |
525 | wire spare0_flop_unused; | |
526 | wire spare0_buf_32x_unused; | |
527 | wire spare0_nand3_8x_unused; | |
528 | wire spare0_inv_8x_unused; | |
529 | wire spare0_aoi22_4x_unused; | |
530 | wire spare0_buf_8x_unused; | |
531 | wire spare0_oai22_4x_unused; | |
532 | wire spare0_inv_16x_unused; | |
533 | wire spare0_nand2_16x_unused; | |
534 | wire spare0_nor3_4x_unused; | |
535 | wire spare0_nand2_8x_unused; | |
536 | wire spare0_buf_16x_unused; | |
537 | wire spare0_nor2_16x_unused; | |
538 | wire spare0_inv_32x_unused; | |
539 | wire si_1; | |
540 | wire so_1; | |
541 | wire spare1_flop_unused; | |
542 | wire spare1_buf_32x_unused; | |
543 | wire spare1_nand3_8x_unused; | |
544 | wire spare1_inv_8x_unused; | |
545 | wire spare1_aoi22_4x_unused; | |
546 | wire spare1_buf_8x_unused; | |
547 | wire spare1_oai22_4x_unused; | |
548 | wire spare1_inv_16x_unused; | |
549 | wire spare1_nand2_16x_unused; | |
550 | wire spare1_nor3_4x_unused; | |
551 | wire spare1_nand2_8x_unused; | |
552 | wire spare1_buf_16x_unused; | |
553 | wire spare1_nor2_16x_unused; | |
554 | wire spare1_inv_32x_unused; | |
555 | wire si_2; | |
556 | wire so_2; | |
557 | wire spare2_flop_unused; | |
558 | wire spare2_buf_32x_unused; | |
559 | wire spare2_nand3_8x_unused; | |
560 | wire spare2_inv_8x_unused; | |
561 | wire spare2_aoi22_4x_unused; | |
562 | wire spare2_buf_8x_unused; | |
563 | wire spare2_oai22_4x_unused; | |
564 | wire spare2_inv_16x_unused; | |
565 | wire spare2_nand2_16x_unused; | |
566 | wire spare2_nor3_4x_unused; | |
567 | wire spare2_nand2_8x_unused; | |
568 | wire spare2_buf_16x_unused; | |
569 | wire spare2_nor2_16x_unused; | |
570 | wire spare2_inv_32x_unused; | |
571 | wire si_3; | |
572 | wire so_3; | |
573 | wire spare3_flop_unused; | |
574 | wire spare3_buf_32x_unused; | |
575 | wire spare3_nand3_8x_unused; | |
576 | wire spare3_inv_8x_unused; | |
577 | wire spare3_aoi22_4x_unused; | |
578 | wire spare3_buf_8x_unused; | |
579 | wire spare3_oai22_4x_unused; | |
580 | wire spare3_inv_16x_unused; | |
581 | wire spare3_nand2_16x_unused; | |
582 | wire spare3_nor3_4x_unused; | |
583 | wire spare3_nand2_8x_unused; | |
584 | wire spare3_buf_16x_unused; | |
585 | wire spare3_nor2_16x_unused; | |
586 | wire spare3_inv_32x_unused; | |
587 | ||
588 | ||
589 | input l1clk; | |
590 | input scan_in; | |
591 | input siclk; | |
592 | input soclk; | |
593 | output scan_out; | |
594 | ||
595 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
596 | .siclk(siclk), | |
597 | .soclk(soclk), | |
598 | .si(si_0), | |
599 | .so(so_0), | |
600 | .d(1'b0), | |
601 | .q(spare0_flop_unused)); | |
602 | assign si_0 = scan_in; | |
603 | ||
604 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
605 | .out(spare0_buf_32x_unused)); | |
606 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
607 | .in1(1'b1), | |
608 | .in2(1'b1), | |
609 | .out(spare0_nand3_8x_unused)); | |
610 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
611 | .out(spare0_inv_8x_unused)); | |
612 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
613 | .in01(1'b1), | |
614 | .in10(1'b1), | |
615 | .in11(1'b1), | |
616 | .out(spare0_aoi22_4x_unused)); | |
617 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
618 | .out(spare0_buf_8x_unused)); | |
619 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
620 | .in01(1'b1), | |
621 | .in10(1'b1), | |
622 | .in11(1'b1), | |
623 | .out(spare0_oai22_4x_unused)); | |
624 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
625 | .out(spare0_inv_16x_unused)); | |
626 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
627 | .in1(1'b1), | |
628 | .out(spare0_nand2_16x_unused)); | |
629 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
630 | .in1(1'b0), | |
631 | .in2(1'b0), | |
632 | .out(spare0_nor3_4x_unused)); | |
633 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
634 | .in1(1'b1), | |
635 | .out(spare0_nand2_8x_unused)); | |
636 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
637 | .out(spare0_buf_16x_unused)); | |
638 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
639 | .in1(1'b0), | |
640 | .out(spare0_nor2_16x_unused)); | |
641 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
642 | .out(spare0_inv_32x_unused)); | |
643 | ||
644 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
645 | .siclk(siclk), | |
646 | .soclk(soclk), | |
647 | .si(si_1), | |
648 | .so(so_1), | |
649 | .d(1'b0), | |
650 | .q(spare1_flop_unused)); | |
651 | assign si_1 = so_0; | |
652 | ||
653 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
654 | .out(spare1_buf_32x_unused)); | |
655 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
656 | .in1(1'b1), | |
657 | .in2(1'b1), | |
658 | .out(spare1_nand3_8x_unused)); | |
659 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
660 | .out(spare1_inv_8x_unused)); | |
661 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
662 | .in01(1'b1), | |
663 | .in10(1'b1), | |
664 | .in11(1'b1), | |
665 | .out(spare1_aoi22_4x_unused)); | |
666 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
667 | .out(spare1_buf_8x_unused)); | |
668 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
669 | .in01(1'b1), | |
670 | .in10(1'b1), | |
671 | .in11(1'b1), | |
672 | .out(spare1_oai22_4x_unused)); | |
673 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
674 | .out(spare1_inv_16x_unused)); | |
675 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
676 | .in1(1'b1), | |
677 | .out(spare1_nand2_16x_unused)); | |
678 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
679 | .in1(1'b0), | |
680 | .in2(1'b0), | |
681 | .out(spare1_nor3_4x_unused)); | |
682 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
683 | .in1(1'b1), | |
684 | .out(spare1_nand2_8x_unused)); | |
685 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
686 | .out(spare1_buf_16x_unused)); | |
687 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
688 | .in1(1'b0), | |
689 | .out(spare1_nor2_16x_unused)); | |
690 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
691 | .out(spare1_inv_32x_unused)); | |
692 | ||
693 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
694 | .siclk(siclk), | |
695 | .soclk(soclk), | |
696 | .si(si_2), | |
697 | .so(so_2), | |
698 | .d(1'b0), | |
699 | .q(spare2_flop_unused)); | |
700 | assign si_2 = so_1; | |
701 | ||
702 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
703 | .out(spare2_buf_32x_unused)); | |
704 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
705 | .in1(1'b1), | |
706 | .in2(1'b1), | |
707 | .out(spare2_nand3_8x_unused)); | |
708 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
709 | .out(spare2_inv_8x_unused)); | |
710 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
711 | .in01(1'b1), | |
712 | .in10(1'b1), | |
713 | .in11(1'b1), | |
714 | .out(spare2_aoi22_4x_unused)); | |
715 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
716 | .out(spare2_buf_8x_unused)); | |
717 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
718 | .in01(1'b1), | |
719 | .in10(1'b1), | |
720 | .in11(1'b1), | |
721 | .out(spare2_oai22_4x_unused)); | |
722 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
723 | .out(spare2_inv_16x_unused)); | |
724 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
725 | .in1(1'b1), | |
726 | .out(spare2_nand2_16x_unused)); | |
727 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
728 | .in1(1'b0), | |
729 | .in2(1'b0), | |
730 | .out(spare2_nor3_4x_unused)); | |
731 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
732 | .in1(1'b1), | |
733 | .out(spare2_nand2_8x_unused)); | |
734 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
735 | .out(spare2_buf_16x_unused)); | |
736 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
737 | .in1(1'b0), | |
738 | .out(spare2_nor2_16x_unused)); | |
739 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
740 | .out(spare2_inv_32x_unused)); | |
741 | ||
742 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
743 | .siclk(siclk), | |
744 | .soclk(soclk), | |
745 | .si(si_3), | |
746 | .so(so_3), | |
747 | .d(1'b0), | |
748 | .q(spare3_flop_unused)); | |
749 | assign si_3 = so_2; | |
750 | ||
751 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
752 | .out(spare3_buf_32x_unused)); | |
753 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
754 | .in1(1'b1), | |
755 | .in2(1'b1), | |
756 | .out(spare3_nand3_8x_unused)); | |
757 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
758 | .out(spare3_inv_8x_unused)); | |
759 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
760 | .in01(1'b1), | |
761 | .in10(1'b1), | |
762 | .in11(1'b1), | |
763 | .out(spare3_aoi22_4x_unused)); | |
764 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
765 | .out(spare3_buf_8x_unused)); | |
766 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
767 | .in01(1'b1), | |
768 | .in10(1'b1), | |
769 | .in11(1'b1), | |
770 | .out(spare3_oai22_4x_unused)); | |
771 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
772 | .out(spare3_inv_16x_unused)); | |
773 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
774 | .in1(1'b1), | |
775 | .out(spare3_nand2_16x_unused)); | |
776 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
777 | .in1(1'b0), | |
778 | .in2(1'b0), | |
779 | .out(spare3_nor3_4x_unused)); | |
780 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
781 | .in1(1'b1), | |
782 | .out(spare3_nand2_8x_unused)); | |
783 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
784 | .out(spare3_buf_16x_unused)); | |
785 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
786 | .in1(1'b0), | |
787 | .out(spare3_nor2_16x_unused)); | |
788 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
789 | .out(spare3_inv_32x_unused)); | |
790 | assign scan_out = so_3; | |
791 | ||
792 | ||
793 | ||
794 | endmodule | |
795 | ||
796 | ||
797 | // Description: Spare gate macro for control blocks | |
798 | // | |
799 | // Param num controls the number of times the macro is added | |
800 | // flops=0 can be used to use only combination spare logic | |
801 | ||
802 | ||
803 | module lsu_red_ctl_spare_ctl_macro__flops_0__num_1; | |
804 | wire spare0_buf_32x_unused; | |
805 | wire spare0_nand3_8x_unused; | |
806 | wire spare0_inv_8x_unused; | |
807 | wire spare0_aoi22_4x_unused; | |
808 | wire spare0_buf_8x_unused; | |
809 | wire spare0_oai22_4x_unused; | |
810 | wire spare0_inv_16x_unused; | |
811 | wire spare0_nand2_16x_unused; | |
812 | wire spare0_nor3_4x_unused; | |
813 | wire spare0_nand2_8x_unused; | |
814 | wire spare0_buf_16x_unused; | |
815 | wire spare0_nor2_16x_unused; | |
816 | wire spare0_inv_32x_unused; | |
817 | ||
818 | ||
819 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
820 | .out(spare0_buf_32x_unused)); | |
821 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
822 | .in1(1'b1), | |
823 | .in2(1'b1), | |
824 | .out(spare0_nand3_8x_unused)); | |
825 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
826 | .out(spare0_inv_8x_unused)); | |
827 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
828 | .in01(1'b1), | |
829 | .in10(1'b1), | |
830 | .in11(1'b1), | |
831 | .out(spare0_aoi22_4x_unused)); | |
832 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
833 | .out(spare0_buf_8x_unused)); | |
834 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
835 | .in01(1'b1), | |
836 | .in10(1'b1), | |
837 | .in11(1'b1), | |
838 | .out(spare0_oai22_4x_unused)); | |
839 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
840 | .out(spare0_inv_16x_unused)); | |
841 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
842 | .in1(1'b1), | |
843 | .out(spare0_nand2_16x_unused)); | |
844 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
845 | .in1(1'b0), | |
846 | .in2(1'b0), | |
847 | .out(spare0_nor3_4x_unused)); | |
848 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
849 | .in1(1'b1), | |
850 | .out(spare0_nand2_8x_unused)); | |
851 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
852 | .out(spare0_buf_16x_unused)); | |
853 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
854 | .in1(1'b0), | |
855 | .out(spare0_nor2_16x_unused)); | |
856 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
857 | .out(spare0_inv_32x_unused)); | |
858 | ||
859 | ||
860 | ||
861 | endmodule | |
862 |