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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_sed_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_sed_dp ( | |
36 | data_in, | |
37 | ecc_in, | |
38 | syndrome, | |
39 | cecc_err, | |
40 | uecc_err); | |
41 | wire [66:0] d; | |
42 | wire [7:0] e; | |
43 | wire [36:0] check0_bus; | |
44 | wire check0_4; | |
45 | wire check0_3; | |
46 | wire check0_2; | |
47 | wire check0_1; | |
48 | wire check0_0; | |
49 | wire c0; | |
50 | wire [36:0] check1_bus; | |
51 | wire check1_4; | |
52 | wire check1_3; | |
53 | wire check1_2; | |
54 | wire check1_1; | |
55 | wire check1_0; | |
56 | wire c1; | |
57 | wire [35:0] check2_bus; | |
58 | wire check2_4; | |
59 | wire check2_3; | |
60 | wire check2_2; | |
61 | wire check2_1; | |
62 | wire check2_0; | |
63 | wire c2; | |
64 | wire [34:0] check3_bus; | |
65 | wire check3_4; | |
66 | wire check3_3; | |
67 | wire check3_2; | |
68 | wire check3_1; | |
69 | wire check3_0; | |
70 | wire c3; | |
71 | wire [31:0] check4_bus; | |
72 | wire c4; | |
73 | wire [31:0] check5_bus; | |
74 | wire c5; | |
75 | wire [10:0] check6_bus; | |
76 | wire c6; | |
77 | wire [73:0] check7_bus; | |
78 | wire check7_4; | |
79 | wire check7_3; | |
80 | wire check7_2; | |
81 | wire check7_1; | |
82 | wire check7_0; | |
83 | wire c7; | |
84 | wire [7:7] e_; | |
85 | wire c7_; | |
86 | wire parity_incorrect; | |
87 | wire parity_correct; | |
88 | wire ecc_err_0; | |
89 | wire ecc_err_1; | |
90 | wire ecc_err_2; | |
91 | wire ecc_err; | |
92 | ||
93 | ||
94 | ||
95 | input [66:0] data_in; // Used for generation and checking | |
96 | input [7:0] ecc_in; // Used for checking only | |
97 | ||
98 | output [7:0] syndrome; // Used for generation and checking | |
99 | output cecc_err; // Used for checking only; unused for gen | |
100 | output uecc_err; // Used for checking only; unused for gen | |
101 | ||
102 | ||
103 | ||
104 | ////////////////////////////////////////////////////////////////////////////// | |
105 | ||
106 | // Position Binary | |
107 | // 1 0000001 C0 | |
108 | // 2 0000010 C1 | |
109 | // 3 0000011 D0 | |
110 | // | |
111 | // 4 0000100 C2 | |
112 | // 5 0000101 D1 | |
113 | // 6 0000110 D2 | |
114 | // 7 0000111 D3 | |
115 | // | |
116 | // 8 0001000 C3 | |
117 | // 9 0001001 D4 | |
118 | // 10 0001010 D5 | |
119 | // 11 0001011 D6 | |
120 | // 12 0001100 D7 | |
121 | // ... ... | |
122 | // 15 0001111 D10 | |
123 | // | |
124 | // 16 0010000 C4 | |
125 | // 17 0010001 D11 | |
126 | // ... ... | |
127 | // 20 0010100 D14 | |
128 | // ... ... | |
129 | // 24 0011000 D18 | |
130 | // ... ... | |
131 | // 28 0011100 D22 | |
132 | // ... ... | |
133 | // 31 0011111 D25 | |
134 | // | |
135 | // 32 0100000 C5 | |
136 | // 33 0100001 D26 | |
137 | // ... ... | |
138 | // 36 0100100 D29 | |
139 | // ... ... | |
140 | // 40 0101000 D33 | |
141 | // ... ... | |
142 | // 44 0101100 D37 | |
143 | // ... ... | |
144 | // 48 0110000 D41 | |
145 | // ... ... | |
146 | // 52 0110100 D45 | |
147 | // ... ... | |
148 | // 56 0111000 D49 | |
149 | // ... ... | |
150 | // 60 0111100 D53 | |
151 | // ... ... | |
152 | // 63 0111111 D56 | |
153 | // | |
154 | // 64 1000000 C6 | |
155 | // 65 1000001 D57 | |
156 | // ... ... | |
157 | // 68 1000100 D60 | |
158 | // ... ... | |
159 | // 72 1001000 D64 | |
160 | // 73 1001001 D65 | |
161 | // 74 1001010 D66 | |
162 | // | |
163 | // 75 1001011 C7 | |
164 | ||
165 | assign d[66:0] = | |
166 | data_in[66:0]; | |
167 | assign e[7:0] = | |
168 | ecc_in[7:0]; | |
169 | ||
170 | ||
171 | ||
172 | // All odd positions (LSB of position set) | |
173 | assign check0_bus[36:0] = | |
174 | {d[65], d[63], d[61], d[59], d[57], | |
175 | d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], | |
176 | d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], | |
177 | d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], | |
178 | d[10], d[8], d[6], d[4], | |
179 | d[3], d[1], | |
180 | d[0], | |
181 | e[0]}; | |
182 | ||
183 | mmu_sed_dp_prty_macro__width_8 check0_4_pty ( | |
184 | .din (check0_bus [36:29] ), | |
185 | .dout (check0_4 ) | |
186 | ); | |
187 | ||
188 | mmu_sed_dp_prty_macro__width_8 check0_3_pty ( | |
189 | .din (check0_bus [28:21] ), | |
190 | .dout (check0_3 ) | |
191 | ); | |
192 | ||
193 | mmu_sed_dp_prty_macro__width_8 check0_2_pty ( | |
194 | .din (check0_bus [20:13] ), | |
195 | .dout (check0_2 ) | |
196 | ); | |
197 | ||
198 | mmu_sed_dp_prty_macro__width_8 check0_1_pty ( | |
199 | .din (check0_bus [12:5] ), | |
200 | .dout (check0_1 ) | |
201 | ); | |
202 | ||
203 | mmu_sed_dp_prty_macro__width_8 check0_0_pty ( | |
204 | .din ({check0_bus [4:0], | |
205 | {3 {1'b0}} }), | |
206 | .dout (check0_0 ) | |
207 | ); | |
208 | ||
209 | mmu_sed_dp_prty_macro__width_8 check0_pty ( | |
210 | .din ({check0_4 , | |
211 | check0_3 , | |
212 | check0_2 , | |
213 | check0_1 , | |
214 | check0_0 , | |
215 | {3 {1'b0}} }), | |
216 | .dout (c0 ) | |
217 | ); | |
218 | ||
219 | ||
220 | ||
221 | // All positions with secondmost LSB set | |
222 | assign check1_bus[36:0] = | |
223 | {d[66 ], d[63:62], d[59:58], | |
224 | d[56:55], d[52:51], d[48:47], d[44:43], | |
225 | d[40:39], d[36:35], d[32:31], d[28:27], | |
226 | d[25:24], d[21:20], d[17:16], d[13:12], | |
227 | d[10:9], d[6:5], | |
228 | d[3:2], | |
229 | d[0], | |
230 | e[1]}; | |
231 | ||
232 | mmu_sed_dp_prty_macro__width_8 check1_4_pty ( | |
233 | .din (check1_bus [36:29] ), | |
234 | .dout (check1_4 ) | |
235 | ); | |
236 | ||
237 | mmu_sed_dp_prty_macro__width_8 check1_3_pty ( | |
238 | .din (check1_bus [28:21] ), | |
239 | .dout (check1_3 ) | |
240 | ); | |
241 | ||
242 | mmu_sed_dp_prty_macro__width_8 check1_2_pty ( | |
243 | .din (check1_bus [20:13] ), | |
244 | .dout (check1_2 ) | |
245 | ); | |
246 | ||
247 | mmu_sed_dp_prty_macro__width_8 check1_1_pty ( | |
248 | .din (check1_bus [12:5] ), | |
249 | .dout (check1_1 ) | |
250 | ); | |
251 | ||
252 | mmu_sed_dp_prty_macro__width_8 check1_0_pty ( | |
253 | .din ({check1_bus [4:0], | |
254 | {3 {1'b0}} }), | |
255 | .dout (check1_0 ) | |
256 | ); | |
257 | ||
258 | mmu_sed_dp_prty_macro__width_8 check1_pty ( | |
259 | .din ({check1_0 , | |
260 | check1_1 , | |
261 | check1_2 , | |
262 | check1_3 , | |
263 | check1_4 , | |
264 | {3 {1'b0}} }), | |
265 | .dout (c1 ) | |
266 | ); | |
267 | ||
268 | ||
269 | ||
270 | // All positions with thirdmost LSB set | |
271 | assign check2_bus[35:0] = | |
272 | {d[63:60], | |
273 | d[56:53], d[48:45], d[40:37], d[32:29], | |
274 | d[25:22], d[17:14], | |
275 | d[10:7], | |
276 | d[3:1], | |
277 | e[2]}; | |
278 | ||
279 | mmu_sed_dp_prty_macro__width_8 check2_4_pty ( | |
280 | .din ({1'b0, | |
281 | check2_bus [35:29]}), | |
282 | .dout (check2_4 ) | |
283 | ); | |
284 | ||
285 | mmu_sed_dp_prty_macro__width_8 check2_3_pty ( | |
286 | .din (check2_bus [28:21] ), | |
287 | .dout (check2_3 ) | |
288 | ); | |
289 | ||
290 | mmu_sed_dp_prty_macro__width_8 check2_2_pty ( | |
291 | .din (check2_bus [20:13] ), | |
292 | .dout (check2_2 ) | |
293 | ); | |
294 | ||
295 | mmu_sed_dp_prty_macro__width_8 check2_1_pty ( | |
296 | .din (check2_bus [12:5] ), | |
297 | .dout (check2_1 ) | |
298 | ); | |
299 | ||
300 | mmu_sed_dp_prty_macro__width_8 check2_0_pty ( | |
301 | .din ({check2_bus [4:0], | |
302 | {3 {1'b0}} }), | |
303 | .dout (check2_0 ) | |
304 | ); | |
305 | ||
306 | mmu_sed_dp_prty_macro__width_8 check2_pty ( | |
307 | .din ({check2_0 , | |
308 | check2_1 , | |
309 | check2_2 , | |
310 | check2_3 , | |
311 | check2_4 , | |
312 | {3 {1'b0}} }), | |
313 | .dout (c2 ) | |
314 | ); | |
315 | ||
316 | ||
317 | ||
318 | // All positions with fourthmost LSB set | |
319 | assign check3_bus[34:0] = | |
320 | {d[66:64], | |
321 | d[56:49], d[40:33], | |
322 | d[25:18], | |
323 | d[10:4], | |
324 | e[3]}; | |
325 | ||
326 | mmu_sed_dp_prty_macro__width_8 check3_4_pty ( | |
327 | .din ({{2 {1'b0}} , | |
328 | check3_bus [34:29]}), | |
329 | .dout (check3_4 ) | |
330 | ); | |
331 | ||
332 | mmu_sed_dp_prty_macro__width_8 check3_3_pty ( | |
333 | .din (check3_bus [28:21] ), | |
334 | .dout (check3_3 ) | |
335 | ); | |
336 | ||
337 | mmu_sed_dp_prty_macro__width_8 check3_2_pty ( | |
338 | .din (check3_bus [20:13] ), | |
339 | .dout (check3_2 ) | |
340 | ); | |
341 | ||
342 | mmu_sed_dp_prty_macro__width_8 check3_1_pty ( | |
343 | .din (check3_bus [12:5] ), | |
344 | .dout (check3_1 ) | |
345 | ); | |
346 | ||
347 | mmu_sed_dp_prty_macro__width_8 check3_0_pty ( | |
348 | .din ({check3_bus [4:0], | |
349 | {3 {1'b0}} }), | |
350 | .dout (check3_0 ) | |
351 | ); | |
352 | ||
353 | mmu_sed_dp_prty_macro__width_8 check3_pty ( | |
354 | .din ({check3_0 , | |
355 | check3_1 , | |
356 | check3_2 , | |
357 | check3_3 , | |
358 | check3_4 , | |
359 | {3 {1'b0}} }), | |
360 | .dout (c3 ) | |
361 | ); | |
362 | ||
363 | ||
364 | // All positions with fifthmost LSB set | |
365 | assign check4_bus[31:0] = | |
366 | {d[56:41], | |
367 | d[25:11], | |
368 | e[4]}; | |
369 | ||
370 | mmu_sed_dp_prty_macro__width_32 check4_pty ( | |
371 | .din (check4_bus [31:0] ), | |
372 | .dout (c4 ) | |
373 | ); | |
374 | ||
375 | ||
376 | ||
377 | // All positions with sixthmost LSB set | |
378 | assign check5_bus[31:0] = | |
379 | {d[56:26], | |
380 | e[5]}; | |
381 | ||
382 | mmu_sed_dp_prty_macro__width_32 check5_pty ( | |
383 | .din (check5_bus [31:0] ), | |
384 | .dout (c5 ) | |
385 | ); | |
386 | ||
387 | ||
388 | ||
389 | // All positions with seventhmost LSB set | |
390 | assign check6_bus[10:0] = | |
391 | {d[66:57], | |
392 | e[6]}; | |
393 | ||
394 | mmu_sed_dp_prty_macro__width_16 check6_pty ( | |
395 | .din ({{5 {1'b0}} , | |
396 | check6_bus [10:0]}), | |
397 | .dout (c6 ) | |
398 | ); | |
399 | ||
400 | ||
401 | ||
402 | // Parity of the whole word (including ECC bits) | |
403 | // Then xnor with e[07] to check the parity | |
404 | // (or in this case, xor with e[07] to get miscompare) | |
405 | assign check7_bus[73:0] = | |
406 | {d[66:0], e[6:0]}; | |
407 | ||
408 | mmu_sed_dp_prty_macro__width_8 check7_4_pty ( | |
409 | .din (check7_bus [71:64] ), | |
410 | .dout (check7_4 ) | |
411 | ); | |
412 | ||
413 | mmu_sed_dp_prty_macro__width_16 check7_3_pty ( | |
414 | .din (check7_bus [63:48] ), | |
415 | .dout (check7_3 ) | |
416 | ); | |
417 | ||
418 | mmu_sed_dp_prty_macro__width_16 check7_2_pty ( | |
419 | .din (check7_bus [47:32] ), | |
420 | .dout (check7_2 ) | |
421 | ); | |
422 | ||
423 | mmu_sed_dp_prty_macro__width_16 check7_1_pty ( | |
424 | .din (check7_bus [31:16] ), | |
425 | .dout (check7_1 ) | |
426 | ); | |
427 | ||
428 | mmu_sed_dp_prty_macro__width_16 check7_0_pty ( | |
429 | .din (check7_bus [15:0] ), | |
430 | .dout (check7_0 ) | |
431 | ); | |
432 | ||
433 | mmu_sed_dp_prty_macro__width_8 check7_inv_pty ( | |
434 | .din ({e [7 ], | |
435 | check7_bus [73:72], | |
436 | check7_0 , | |
437 | check7_1 , | |
438 | check7_2 , | |
439 | check7_3 , | |
440 | check7_4 }), | |
441 | .dout (c7 ) | |
442 | ); | |
443 | ||
444 | mmu_sed_dp_inv_macro__width_1 e7_inv ( | |
445 | .din (e [7 ] ), | |
446 | .dout (e_ [7 ] ) | |
447 | ); | |
448 | ||
449 | mmu_sed_dp_prty_macro__width_8 check7_pty ( | |
450 | .din ({e_ [7 ], | |
451 | check7_bus [73:72], | |
452 | check7_0 , | |
453 | check7_1 , | |
454 | check7_2 , | |
455 | check7_3 , | |
456 | check7_4 }), | |
457 | .dout (c7_ ) | |
458 | ); | |
459 | ||
460 | assign parity_incorrect = | |
461 | c7; | |
462 | ||
463 | assign parity_correct = | |
464 | c7_; | |
465 | ||
466 | ||
467 | assign syndrome[7:0] = | |
468 | {c7, c6, c5, c4, c3, c2, c1, c0}; | |
469 | ||
470 | ||
471 | ||
472 | // If the syndrome is zero and overall parity is correct, then no errors | |
473 | ||
474 | // If overall parity is incorrect, then correctable | |
475 | //assign cecc_err = | |
476 | // c7; | |
477 | // If overall parity is correct and the syndrome is nonzero, then uncorrectable | |
478 | //assign uecc_err = | |
479 | // (| ecc_out[06:00]) & ~c7; | |
480 | ||
481 | mmu_sed_dp_nor_macro__ports_3__width_1 ecc_err_2_nor ( | |
482 | .din0 (syndrome [6] ), | |
483 | .din1 (syndrome [5] ), | |
484 | .din2 (syndrome [4] ), | |
485 | .dout (ecc_err_0 ) | |
486 | ); | |
487 | ||
488 | mmu_sed_dp_nor_macro__ports_2__width_1 ecc_err_1_nor ( | |
489 | .din0 (syndrome [3] ), | |
490 | .din1 (syndrome [2] ), | |
491 | .dout (ecc_err_1 ) | |
492 | ); | |
493 | ||
494 | mmu_sed_dp_nor_macro__ports_2__width_1 ecc_err_0_nor ( | |
495 | .din0 (syndrome [1] ), | |
496 | .din1 (syndrome [0] ), | |
497 | .dout (ecc_err_2 ) | |
498 | ); | |
499 | ||
500 | mmu_sed_dp_nand_macro__ports_3__width_1 ecc_err_nand ( | |
501 | .din0 (ecc_err_0 ), | |
502 | .din1 (ecc_err_1 ), | |
503 | .din2 (ecc_err_2 ), | |
504 | .dout (ecc_err ) | |
505 | ); | |
506 | ||
507 | mmu_sed_dp_buff_macro__width_1 cecc_err_buf ( | |
508 | .din (parity_incorrect ), | |
509 | .dout (cecc_err ) | |
510 | ); | |
511 | ||
512 | mmu_sed_dp_and_macro__ports_2__width_1 uecc_err_and ( | |
513 | .din0 (ecc_err ), | |
514 | .din1 (parity_correct ), | |
515 | .dout (uecc_err ) | |
516 | ); | |
517 | ||
518 | ||
519 | supply0 vss; // <- port for ground | |
520 | supply1 vdd; // <- port for power | |
521 | ||
522 | endmodule | |
523 | ||
524 | ||
525 | ||
526 | // | |
527 | // parity macro (even parity) | |
528 | // | |
529 | // | |
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | module mmu_sed_dp_prty_macro__width_8 ( | |
536 | din, | |
537 | dout); | |
538 | input [7:0] din; | |
539 | output dout; | |
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | prty #(8) m0_0 ( | |
548 | .in(din[7:0]), | |
549 | .out(dout) | |
550 | ); | |
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | ||
560 | ||
561 | endmodule | |
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | // | |
568 | // parity macro (even parity) | |
569 | // | |
570 | // | |
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | module mmu_sed_dp_prty_macro__width_32 ( | |
577 | din, | |
578 | dout); | |
579 | input [31:0] din; | |
580 | output dout; | |
581 | ||
582 | ||
583 | ||
584 | ||
585 | ||
586 | ||
587 | ||
588 | prty #(32) m0_0 ( | |
589 | .in(din[31:0]), | |
590 | .out(dout) | |
591 | ); | |
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | endmodule | |
603 | ||
604 | ||
605 | ||
606 | ||
607 | ||
608 | // | |
609 | // parity macro (even parity) | |
610 | // | |
611 | // | |
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | module mmu_sed_dp_prty_macro__width_16 ( | |
618 | din, | |
619 | dout); | |
620 | input [15:0] din; | |
621 | output dout; | |
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | prty #(16) m0_0 ( | |
630 | .in(din[15:0]), | |
631 | .out(dout) | |
632 | ); | |
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | endmodule | |
644 | ||
645 | ||
646 | ||
647 | ||
648 | ||
649 | // | |
650 | // invert macro | |
651 | // | |
652 | // | |
653 | ||
654 | ||
655 | ||
656 | ||
657 | ||
658 | module mmu_sed_dp_inv_macro__width_1 ( | |
659 | din, | |
660 | dout); | |
661 | input [0:0] din; | |
662 | output [0:0] dout; | |
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | ||
669 | inv #(1) d0_0 ( | |
670 | .in(din[0:0]), | |
671 | .out(dout[0:0]) | |
672 | ); | |
673 | ||
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | endmodule | |
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | // | |
689 | // nor macro for ports = 2,3 | |
690 | // | |
691 | // | |
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | module mmu_sed_dp_nor_macro__ports_3__width_1 ( | |
698 | din0, | |
699 | din1, | |
700 | din2, | |
701 | dout); | |
702 | input [0:0] din0; | |
703 | input [0:0] din1; | |
704 | input [0:0] din2; | |
705 | output [0:0] dout; | |
706 | ||
707 | ||
708 | ||
709 | ||
710 | ||
711 | ||
712 | nor3 #(1) d0_0 ( | |
713 | .in0(din0[0:0]), | |
714 | .in1(din1[0:0]), | |
715 | .in2(din2[0:0]), | |
716 | .out(dout[0:0]) | |
717 | ); | |
718 | ||
719 | ||
720 | ||
721 | ||
722 | ||
723 | ||
724 | ||
725 | endmodule | |
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | // | |
732 | // nor macro for ports = 2,3 | |
733 | // | |
734 | // | |
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | module mmu_sed_dp_nor_macro__ports_2__width_1 ( | |
741 | din0, | |
742 | din1, | |
743 | dout); | |
744 | input [0:0] din0; | |
745 | input [0:0] din1; | |
746 | output [0:0] dout; | |
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | ||
753 | nor2 #(1) d0_0 ( | |
754 | .in0(din0[0:0]), | |
755 | .in1(din1[0:0]), | |
756 | .out(dout[0:0]) | |
757 | ); | |
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | ||
764 | ||
765 | endmodule | |
766 | ||
767 | ||
768 | ||
769 | ||
770 | ||
771 | // | |
772 | // nand macro for ports = 2,3,4 | |
773 | // | |
774 | // | |
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | module mmu_sed_dp_nand_macro__ports_3__width_1 ( | |
781 | din0, | |
782 | din1, | |
783 | din2, | |
784 | dout); | |
785 | input [0:0] din0; | |
786 | input [0:0] din1; | |
787 | input [0:0] din2; | |
788 | output [0:0] dout; | |
789 | ||
790 | ||
791 | ||
792 | ||
793 | ||
794 | ||
795 | nand3 #(1) d0_0 ( | |
796 | .in0(din0[0:0]), | |
797 | .in1(din1[0:0]), | |
798 | .in2(din2[0:0]), | |
799 | .out(dout[0:0]) | |
800 | ); | |
801 | ||
802 | ||
803 | ||
804 | ||
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | endmodule | |
811 | ||
812 | ||
813 | ||
814 | ||
815 | ||
816 | // | |
817 | // buff macro | |
818 | // | |
819 | // | |
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | module mmu_sed_dp_buff_macro__width_1 ( | |
826 | din, | |
827 | dout); | |
828 | input [0:0] din; | |
829 | output [0:0] dout; | |
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | buff #(1) d0_0 ( | |
837 | .in(din[0:0]), | |
838 | .out(dout[0:0]) | |
839 | ); | |
840 | ||
841 | ||
842 | ||
843 | ||
844 | ||
845 | ||
846 | ||
847 | ||
848 | endmodule | |
849 | ||
850 | ||
851 | ||
852 | ||
853 | ||
854 | // | |
855 | // and macro for ports = 2,3,4 | |
856 | // | |
857 | // | |
858 | ||
859 | ||
860 | ||
861 | ||
862 | ||
863 | module mmu_sed_dp_and_macro__ports_2__width_1 ( | |
864 | din0, | |
865 | din1, | |
866 | dout); | |
867 | input [0:0] din0; | |
868 | input [0:0] din1; | |
869 | output [0:0] dout; | |
870 | ||
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | and2 #(1) d0_0 ( | |
877 | .in0(din0[0:0]), | |
878 | .in1(din1[0:0]), | |
879 | .out(dout[0:0]) | |
880 | ); | |
881 | ||
882 | ||
883 | ||
884 | ||
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | endmodule | |
891 | ||
892 | ||
893 | ||
894 |