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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_trs_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_trs_ctl ( | |
36 | l1clk, | |
37 | scan_in, | |
38 | spc_aclk, | |
39 | spc_bclk, | |
40 | tsb_hit_hw1, | |
41 | thr_valid_hw3, | |
42 | ra2pahit_hw5, | |
43 | ranotpax_hw5, | |
44 | tsm_waitfortte, | |
45 | ep_miss_hw1, | |
46 | rrindex_bit0, | |
47 | rrindex_bit1, | |
48 | l2_ecc_err_hw1, | |
49 | cfg_ecc_err_m3, | |
50 | rr_ecc_err_hw5, | |
51 | l2_ecc_err_type, | |
52 | cfg_ecc_err_type, | |
53 | rr_ecc_err_type, | |
54 | cfg_ecc_err_index, | |
55 | rr_ecc_err_index, | |
56 | trs_rqv, | |
57 | trs_null_st, | |
58 | trs_waitrr3_st, | |
59 | trs_ecc_err, | |
60 | trs_ep_err, | |
61 | trs_err_type, | |
62 | trs_err_index, | |
63 | trs_eccerr_st, | |
64 | trs_eperr_st, | |
65 | scan_out); | |
66 | wire siclk; | |
67 | wire soclk; | |
68 | wire [1:0] rrindex; | |
69 | wire goto_null_state; | |
70 | wire null_state; | |
71 | wire ignorette_state; | |
72 | wire eperr_state; | |
73 | wire eccerr_state; | |
74 | wire next_null_state; | |
75 | wire next_null_state_; | |
76 | wire null_state_; | |
77 | wire null_state_reg_scanin; | |
78 | wire null_state_reg_scanout; | |
79 | wire goto_validreq_state; | |
80 | wire validreq_state; | |
81 | wire next_validreq_state; | |
82 | wire validreq_state_reg_scanin; | |
83 | wire validreq_state_reg_scanout; | |
84 | wire goto_waitrr2_state; | |
85 | wire next_waitrr2_state; | |
86 | wire waitrr2_state_reg_scanin; | |
87 | wire waitrr2_state_reg_scanout; | |
88 | wire waitrr2_state; | |
89 | wire goto_waitrr3_state; | |
90 | wire next_waitrr3_state; | |
91 | wire waitrr3_state_reg_scanin; | |
92 | wire waitrr3_state_reg_scanout; | |
93 | wire waitrr3_state; | |
94 | wire goto_ignorette_state; | |
95 | wire next_ignorette_state; | |
96 | wire ignorette_state_reg_scanin; | |
97 | wire ignorette_state_reg_scanout; | |
98 | wire goto_eperr_state; | |
99 | wire next_eperr_state; | |
100 | wire eperr_state_reg_scanin; | |
101 | wire eperr_state_reg_scanout; | |
102 | wire goto_eccerr_state; | |
103 | wire next_eccerr_state; | |
104 | wire eccerr_state_reg_scanin; | |
105 | wire eccerr_state_reg_scanout; | |
106 | wire take_l2_err; | |
107 | wire take_cfg_err; | |
108 | wire take_rr_err; | |
109 | wire [2:0] err_type; | |
110 | wire err_type_en; | |
111 | wire [2:0] err_type_in; | |
112 | wire [2:0] new_err_index; | |
113 | wire [2:0] err_index_in; | |
114 | wire err_type_reg_scanin; | |
115 | wire err_type_reg_scanout; | |
116 | wire err_index_reg_scanin; | |
117 | wire err_index_reg_scanout; | |
118 | ||
119 | ||
120 | input l1clk; | |
121 | input scan_in; | |
122 | input spc_aclk; | |
123 | input spc_bclk; | |
124 | ||
125 | input tsb_hit_hw1; | |
126 | input thr_valid_hw3; | |
127 | input ra2pahit_hw5; | |
128 | input ranotpax_hw5; | |
129 | input tsm_waitfortte; | |
130 | ||
131 | input ep_miss_hw1; | |
132 | input rrindex_bit0; | |
133 | input rrindex_bit1; | |
134 | ||
135 | ||
136 | input l2_ecc_err_hw1; | |
137 | input cfg_ecc_err_m3; | |
138 | input rr_ecc_err_hw5; | |
139 | ||
140 | input [1:0] l2_ecc_err_type; | |
141 | input [1:0] cfg_ecc_err_type; | |
142 | input [1:0] rr_ecc_err_type; | |
143 | ||
144 | input [2:0] cfg_ecc_err_index; | |
145 | input [2:0] rr_ecc_err_index; | |
146 | ||
147 | ||
148 | output trs_rqv; | |
149 | output trs_null_st; // indicates that the thread in NULL state. | |
150 | output trs_waitrr3_st; // indicates that the thread in waitrr3 state. | |
151 | output trs_ecc_err; // ecc error signal | |
152 | output trs_ep_err; // ep miss detection | |
153 | output [2:0] trs_err_type; // ecc error type (001=>mra c 010=>mra uc 101=>l2 c 110=>l2 uc 111=>l2 notdata) | |
154 | // thread could be in validreq, readrr, waitrr2, waitrr3 or ignorette states. | |
155 | ||
156 | output [2:0] trs_err_index; // index for mra errors | |
157 | ||
158 | output trs_eccerr_st; | |
159 | output trs_eperr_st; | |
160 | ||
161 | output scan_out; | |
162 | ||
163 | ||
164 | assign siclk = spc_aclk; | |
165 | assign soclk = spc_bclk; | |
166 | ||
167 | ||
168 | ||
169 | assign rrindex[1:0] = {rrindex_bit1, rrindex_bit0}; | |
170 | ||
171 | ||
172 | /////////////////////////////////////////////////// | |
173 | // CASE STATEMENT DESCRIPTION OF TRS MACHINE | |
174 | /////////////////////////////////////////////////// | |
175 | //case(`TRS_STATE) | |
176 | // `NULL_ST: | |
177 | // begin | |
178 | // | |
179 | // if (~tsb_hit_hw1 & ~l2_ecc_err_hw1 & ~cfg_ecc_err_m3 & ~ep_miss_hw1) | |
180 | // next_state = `NULL_ST; | |
181 | // if (tsb_hit_hw1 & ~l2_ecc_err_hw1 & ~cfg_ecc_err_m3 & ~ep_miss_hw1) | |
182 | // next_state = `VALIDREQ_ST; | |
183 | // if (ep_miss_hw1 & l2_ecc_err_hw1 & ~cfg_ecc_err_m3) | |
184 | // next_state = `EPERR_ST; | |
185 | // if (l2_ecc_err_hw1 | cfg_ecc_err_m3) | |
186 | // next_state = `ECCERR_ST; | |
187 | // | |
188 | // end | |
189 | // | |
190 | // `VALIDREQ_ST: | |
191 | // begin | |
192 | // if (~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err & | |
193 | // (~(rrindex[1:0] == 2'b11 & thr_valid_hw3))) | |
194 | // next_state = `VALIDREQ_ST; | |
195 | // if (~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err & | |
196 | // ((rrindex[1:0] == 2'b11 & thr_valid_hw3))) | |
197 | // next_state = `WAITRR2_ST; | |
198 | // if ((ra2pahit_hw5 | ranotpax_hw5) & ~rr_ecc_err) | |
199 | // next_state = `IGNORETTE_ST; | |
200 | // if (rr_ecc_err) | |
201 | // next_state = `ECCERR_ST; | |
202 | // end | |
203 | // | |
204 | // `WAITRR2_ST: | |
205 | // begin | |
206 | // if (~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err) | |
207 | // next_state = `WAITRR3_ST; | |
208 | // if ((ra2pahit_hw5 | ranotpax_hw5) & ~rr_ecc_err) | |
209 | // next_state = `IGNORETTE_ST; | |
210 | // if (rr_ecc_err) | |
211 | // next_state = `ECCERR_ST; | |
212 | // end | |
213 | // | |
214 | // `WAITRR3_ST: | |
215 | // begin | |
216 | // if (~rr_ecc_err) | |
217 | // next_state = `IGNORETTE_ST; | |
218 | // if (rr_ecc_err) | |
219 | // next_state = `ECCERR_ST; | |
220 | // end | |
221 | // | |
222 | // `IGNORETTE_ST: | |
223 | // begin | |
224 | // if (~tsm_waitfortte) | |
225 | // next_state = `NULL_ST; | |
226 | // else | |
227 | // next_state = `IGNORETTE_ST; | |
228 | // end | |
229 | // | |
230 | // `ECCERR_ST: | |
231 | // begin | |
232 | // if (~tsm_waitfortte) | |
233 | // next_state = `NULL_ST; | |
234 | // else | |
235 | // next_state = `ECCERR_ST; | |
236 | // end | |
237 | // | |
238 | // `EPERR_ST: | |
239 | // begin | |
240 | // if (~tsm_waitfortte) | |
241 | // next_state = `NULL_ST; | |
242 | // else | |
243 | // next_state = `EPERR_ST; | |
244 | // end | |
245 | // | |
246 | //endcase // case(`TRS_STATE) | |
247 | ||
248 | // 0in one_hot -var {null_state,validreq_state,waitrr2_state,waitrr3_state,ignorette_state,eccerr_state,eperr_state} | |
249 | ||
250 | ||
251 | ||
252 | /////////////////////////////////////////////////// | |
253 | // Null State (HW1) | |
254 | /////////////////////////////////////////////////// | |
255 | assign goto_null_state = (null_state & ~tsb_hit_hw1 & ~l2_ecc_err_hw1 & ~cfg_ecc_err_m3 & ~ep_miss_hw1) | //if thr_sel then go to specrr) | |
256 | (ignorette_state & ~tsm_waitfortte) | | |
257 | (eperr_state & ~tsm_waitfortte) | | |
258 | (eccerr_state & ~tsm_waitfortte); | |
259 | assign next_null_state = goto_null_state; | |
260 | ||
261 | assign next_null_state_ = ~next_null_state; | |
262 | assign null_state = ~null_state_; | |
263 | ||
264 | mmu_trs_ctl_msff_ctl_macro__width_1 null_state_reg ( | |
265 | .scan_in(null_state_reg_scanin), | |
266 | .scan_out(null_state_reg_scanout), | |
267 | .l1clk(l1clk), | |
268 | .din (next_null_state_), | |
269 | .dout (null_state_), | |
270 | .siclk(siclk), | |
271 | .soclk(soclk) | |
272 | ); | |
273 | ||
274 | /////////////////////////////////////////////////// | |
275 | // Valid Req State (HW2) | |
276 | /////////////////////////////////////////////////// | |
277 | assign goto_validreq_state = (null_state & tsb_hit_hw1 & ~cfg_ecc_err_m3) | //ra2pahit_hw5 cannot happen in null_state | |
278 | (validreq_state & ~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err_hw5 & | |
279 | ~(rrindex[1] & rrindex[0] & thr_valid_hw3)) ; | |
280 | ||
281 | assign next_validreq_state = goto_validreq_state; | |
282 | ||
283 | ||
284 | mmu_trs_ctl_msff_ctl_macro__width_1 validreq_state_reg ( | |
285 | .scan_in(validreq_state_reg_scanin), | |
286 | .scan_out(validreq_state_reg_scanout), | |
287 | .l1clk(l1clk), | |
288 | .din (next_validreq_state), | |
289 | .dout (validreq_state), | |
290 | .siclk(siclk), | |
291 | .soclk(soclk) | |
292 | ); | |
293 | ||
294 | /////////////////////////////////////////////////// | |
295 | // WaitRR2 State (HW4) | |
296 | /////////////////////////////////////////////////// | |
297 | assign goto_waitrr2_state = (validreq_state & ~ra2pahit_hw5 & ~ranotpax_hw5 & rrindex[1] & rrindex[0] & thr_valid_hw3 & ~rr_ecc_err_hw5); | |
298 | assign next_waitrr2_state = goto_waitrr2_state; | |
299 | ||
300 | ||
301 | mmu_trs_ctl_msff_ctl_macro__width_1 waitrr2_state_reg ( | |
302 | .scan_in(waitrr2_state_reg_scanin), | |
303 | .scan_out(waitrr2_state_reg_scanout), | |
304 | .l1clk(l1clk), | |
305 | .din (next_waitrr2_state), | |
306 | .dout (waitrr2_state), | |
307 | .siclk(siclk), | |
308 | .soclk(soclk) | |
309 | ); | |
310 | ||
311 | /////////////////////////////////////////////////// | |
312 | // WaitRR3 State (HW5) | |
313 | /////////////////////////////////////////////////// | |
314 | assign goto_waitrr3_state = (waitrr2_state & ~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err_hw5); | |
315 | assign next_waitrr3_state = goto_waitrr3_state; | |
316 | ||
317 | mmu_trs_ctl_msff_ctl_macro__width_1 waitrr3_state_reg ( | |
318 | .scan_in(waitrr3_state_reg_scanin), | |
319 | .scan_out(waitrr3_state_reg_scanout), | |
320 | .l1clk(l1clk), | |
321 | .din (next_waitrr3_state), | |
322 | .dout (waitrr3_state), | |
323 | .siclk(siclk), | |
324 | .soclk(soclk) | |
325 | ); | |
326 | ||
327 | /////////////////////////////////////////////////// | |
328 | // IgnoreTTE State (HW6) | |
329 | /////////////////////////////////////////////////// | |
330 | assign goto_ignorette_state = ((validreq_state | waitrr2_state ) & (ra2pahit_hw5 | ranotpax_hw5) & ~rr_ecc_err_hw5) | | |
331 | (waitrr3_state & ~rr_ecc_err_hw5) | | |
332 | (ignorette_state & tsm_waitfortte); | |
333 | assign next_ignorette_state = goto_ignorette_state; | |
334 | ||
335 | ||
336 | mmu_trs_ctl_msff_ctl_macro__width_1 ignorette_state_reg ( | |
337 | .scan_in(ignorette_state_reg_scanin), | |
338 | .scan_out(ignorette_state_reg_scanout), | |
339 | .l1clk(l1clk), | |
340 | .din (next_ignorette_state), | |
341 | .dout (ignorette_state), | |
342 | .siclk(siclk), | |
343 | .soclk(soclk) | |
344 | ); | |
345 | ||
346 | /////////////////////////////////////////////////// | |
347 | // EpErr State (HW6) | |
348 | /////////////////////////////////////////////////// | |
349 | assign goto_eperr_state = (null_state & ep_miss_hw1 & ~cfg_ecc_err_m3) | | |
350 | (eperr_state & tsm_waitfortte); | |
351 | assign next_eperr_state = goto_eperr_state; | |
352 | ||
353 | ||
354 | mmu_trs_ctl_msff_ctl_macro__width_1 eperr_state_reg ( | |
355 | .scan_in(eperr_state_reg_scanin), | |
356 | .scan_out(eperr_state_reg_scanout), | |
357 | .l1clk(l1clk), | |
358 | .din (next_eperr_state), | |
359 | .dout (eperr_state), | |
360 | .siclk(siclk), | |
361 | .soclk(soclk) | |
362 | ); | |
363 | ||
364 | /////////////////////////////////////////////////// | |
365 | // EccErr State (HW6) | |
366 | /////////////////////////////////////////////////// | |
367 | assign goto_eccerr_state = (null_state & (l2_ecc_err_hw1 | cfg_ecc_err_m3)) | | |
368 | ((validreq_state | waitrr2_state | waitrr3_state ) & rr_ecc_err_hw5) | | |
369 | (eccerr_state & tsm_waitfortte); | |
370 | assign next_eccerr_state = goto_eccerr_state; | |
371 | ||
372 | ||
373 | mmu_trs_ctl_msff_ctl_macro__width_1 eccerr_state_reg ( | |
374 | .scan_in(eccerr_state_reg_scanin), | |
375 | .scan_out(eccerr_state_reg_scanout), | |
376 | .l1clk(l1clk), | |
377 | .din (next_eccerr_state), | |
378 | .dout (eccerr_state), | |
379 | .siclk(siclk), | |
380 | .soclk(soclk) | |
381 | ); | |
382 | ||
383 | /////////////////////////////////////////////////// | |
384 | // Set the ECC ERROR TYPE | |
385 | // 000 No errors | |
386 | // 110 MRA Correctable | |
387 | // 101 MRA Uncorrectable | |
388 | // 001 L2 correctable | |
389 | // 010 L2 uncorrectable | |
390 | // 011 L2 Not Data | |
391 | // latch the first ecc error and hold it. | |
392 | /////////////////////////////////////////////////// | |
393 | //0in bits_on -var {take_l2_err, take_cfg_err, take_rr_err} -max 1 | |
394 | assign take_l2_err = (null_state & l2_ecc_err_hw1); | |
395 | assign take_cfg_err = (null_state & ~l2_ecc_err_hw1 & cfg_ecc_err_m3); | |
396 | assign take_rr_err = (validreq_state | waitrr2_state | waitrr3_state ) & rr_ecc_err_hw5; | |
397 | ||
398 | assign err_type[1:0] = ({2{take_l2_err}} & l2_ecc_err_type[1:0]) | | |
399 | ({2{take_cfg_err}} & cfg_ecc_err_type[1:0]) | | |
400 | ({2{take_rr_err}} & rr_ecc_err_type[1:0]); | |
401 | ||
402 | assign err_type[2] = (take_cfg_err | take_rr_err) & ~take_l2_err; | |
403 | assign err_type_en = take_l2_err | take_cfg_err | take_rr_err; | |
404 | ||
405 | assign err_type_in[2:0] = ({3{err_type_en}} & err_type[2:0]) | | |
406 | ({3{~err_type_en}} & trs_err_type[2:0]); | |
407 | ||
408 | assign new_err_index[2:0] = ({3{take_cfg_err}} & cfg_ecc_err_index[2:0]) | | |
409 | ({3{take_rr_err}} & rr_ecc_err_index[2:0]); | |
410 | ||
411 | ||
412 | assign err_index_in[2:0] = ({3{err_type_en}} & new_err_index[2:0]) | | |
413 | ({3{~err_type_en}} & trs_err_index[2:0]); | |
414 | ||
415 | ||
416 | mmu_trs_ctl_msff_ctl_macro__width_3 err_type_reg | |
417 | ( | |
418 | .scan_in(err_type_reg_scanin), | |
419 | .scan_out(err_type_reg_scanout), | |
420 | .l1clk(l1clk), | |
421 | .din (err_type_in[2:0]), | |
422 | .dout (trs_err_type[2:0]), | |
423 | .siclk(siclk), | |
424 | .soclk(soclk) | |
425 | ); | |
426 | ||
427 | mmu_trs_ctl_msff_ctl_macro__width_3 err_index_reg | |
428 | ( | |
429 | .scan_in(err_index_reg_scanin), | |
430 | .scan_out(err_index_reg_scanout), | |
431 | .l1clk(l1clk), | |
432 | .din (err_index_in[2:0]), | |
433 | .dout (trs_err_index[2:0]), | |
434 | .siclk(siclk), | |
435 | .soclk(soclk) | |
436 | ); | |
437 | /////////////////////////////////////////////////// | |
438 | // State Machine Outputs | |
439 | /////////////////////////////////////////////////// | |
440 | assign trs_rqv = validreq_state; | |
441 | ||
442 | assign trs_null_st = null_state; | |
443 | assign trs_ecc_err = eccerr_state & ~tsm_waitfortte; | |
444 | assign trs_eccerr_st = eccerr_state; | |
445 | assign trs_waitrr3_st = waitrr3_state; | |
446 | ||
447 | ||
448 | assign trs_ep_err = eperr_state & ~tsm_waitfortte; | |
449 | assign trs_eperr_st = eperr_state; | |
450 | ||
451 | ||
452 | supply0 vss; | |
453 | supply1 vdd; | |
454 | ||
455 | // fixscan start: | |
456 | assign null_state_reg_scanin = scan_in ; | |
457 | assign validreq_state_reg_scanin = null_state_reg_scanout ; | |
458 | assign waitrr2_state_reg_scanin = validreq_state_reg_scanout; | |
459 | assign waitrr3_state_reg_scanin = waitrr2_state_reg_scanout; | |
460 | assign ignorette_state_reg_scanin = waitrr3_state_reg_scanout; | |
461 | assign eperr_state_reg_scanin = ignorette_state_reg_scanout; | |
462 | assign eccerr_state_reg_scanin = eperr_state_reg_scanout ; | |
463 | assign err_type_reg_scanin = eccerr_state_reg_scanout ; | |
464 | assign err_index_reg_scanin = err_type_reg_scanout ; | |
465 | assign scan_out = err_index_reg_scanout ; | |
466 | // fixscan end: | |
467 | endmodule | |
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | // any PARAMS parms go into naming of macro | |
475 | ||
476 | module mmu_trs_ctl_msff_ctl_macro__width_1 ( | |
477 | din, | |
478 | l1clk, | |
479 | scan_in, | |
480 | siclk, | |
481 | soclk, | |
482 | dout, | |
483 | scan_out); | |
484 | wire [0:0] fdin; | |
485 | ||
486 | input [0:0] din; | |
487 | input l1clk; | |
488 | input scan_in; | |
489 | ||
490 | ||
491 | input siclk; | |
492 | input soclk; | |
493 | ||
494 | output [0:0] dout; | |
495 | output scan_out; | |
496 | assign fdin[0:0] = din[0:0]; | |
497 | ||
498 | ||
499 | ||
500 | ||
501 | ||
502 | ||
503 | dff #(1) d0_0 ( | |
504 | .l1clk(l1clk), | |
505 | .siclk(siclk), | |
506 | .soclk(soclk), | |
507 | .d(fdin[0:0]), | |
508 | .si(scan_in), | |
509 | .so(scan_out), | |
510 | .q(dout[0:0]) | |
511 | ); | |
512 | ||
513 | ||
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | ||
521 | ||
522 | ||
523 | ||
524 | endmodule | |
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | // any PARAMS parms go into naming of macro | |
539 | ||
540 | module mmu_trs_ctl_msff_ctl_macro__width_3 ( | |
541 | din, | |
542 | l1clk, | |
543 | scan_in, | |
544 | siclk, | |
545 | soclk, | |
546 | dout, | |
547 | scan_out); | |
548 | wire [2:0] fdin; | |
549 | wire [1:0] so; | |
550 | ||
551 | input [2:0] din; | |
552 | input l1clk; | |
553 | input scan_in; | |
554 | ||
555 | ||
556 | input siclk; | |
557 | input soclk; | |
558 | ||
559 | output [2:0] dout; | |
560 | output scan_out; | |
561 | assign fdin[2:0] = din[2:0]; | |
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | dff #(3) d0_0 ( | |
569 | .l1clk(l1clk), | |
570 | .siclk(siclk), | |
571 | .soclk(soclk), | |
572 | .d(fdin[2:0]), | |
573 | .si({scan_in,so[1:0]}), | |
574 | .so({so[1:0],scan_out}), | |
575 | .q(dout[2:0]) | |
576 | ); | |
577 | ||
578 | ||
579 | ||
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | ||
586 | ||
587 | ||
588 | ||
589 | endmodule | |
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 |