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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmo_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmo_dp ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | ic_dmo_rd_data, | |
42 | lsu_dc_data, | |
43 | dmo_din, | |
44 | dmo_coresel, | |
45 | dmo_icmuxctl, | |
46 | tcu_se_scancollar_out, | |
47 | dmo_dout, | |
48 | scan_out, | |
49 | dmo_coresel_buff); | |
50 | wire pce_ov; | |
51 | wire stop; | |
52 | wire siclk; | |
53 | wire soclk; | |
54 | wire dmo_icmuxctl_buff; | |
55 | wire [35:0] dmo_din_buff; | |
56 | wire dmo_flop_scanin; | |
57 | wire dmo_flop_scanout; | |
58 | wire [35:0] dmo_flop_dout; | |
59 | ||
60 | ||
61 | input l2clk; | |
62 | input scan_in; | |
63 | input tcu_pce_ov; | |
64 | input spc_aclk; | |
65 | input spc_bclk; | |
66 | ||
67 | input [32:0] ic_dmo_rd_data; | |
68 | input [35:0] lsu_dc_data; | |
69 | ||
70 | input [35:0] dmo_din; | |
71 | input dmo_coresel; | |
72 | input dmo_icmuxctl; | |
73 | ||
74 | input tcu_se_scancollar_out; | |
75 | ||
76 | output [35:0] dmo_dout; | |
77 | output scan_out; | |
78 | output dmo_coresel_buff; // for LSU | |
79 | ||
80 | // scan renames | |
81 | assign pce_ov = tcu_pce_ov; | |
82 | assign stop = 1'b0; | |
83 | assign siclk = spc_aclk; | |
84 | assign soclk = spc_bclk; | |
85 | //assign se = tcu_se_scancollar_out; | |
86 | //assign muxtst = tcu_muxtest; | |
87 | //assign test = tcu_dectest; | |
88 | // end scan | |
89 | ||
90 | dmo_dpbuff_macro__rep_1__width_38 dmo_din_buf ( | |
91 | .din ({dmo_coresel, dmo_icmuxctl, dmo_din[35:0]}), | |
92 | .dout({dmo_coresel_buff, dmo_icmuxctl_buff, dmo_din_buff[35:0]}) | |
93 | ); | |
94 | ||
95 | // Flop data from other core and this core | |
96 | dmo_dpmsff_macro__mux_aope__ports_3__stack_64c__width_36 dmo_flop ( | |
97 | .scan_in(dmo_flop_scanin), | |
98 | .scan_out(dmo_flop_scanout), | |
99 | .clk ( l2clk ), | |
100 | .en ( 1'b1 ), | |
101 | .se (tcu_se_scancollar_out ), | |
102 | .din0 ( dmo_din_buff[35:0] ), // other core data | |
103 | // .din0 ( dmo_din[35:0] ), // other core data | |
104 | .din1 ( {3'b0, ic_dmo_rd_data[32:0]} ), // I$ data | |
105 | .din2 ( lsu_dc_data[35:0] ), // D$ data | |
106 | .sel0 ( dmo_coresel_buff ), | |
107 | .sel1 ( dmo_icmuxctl_buff ), | |
108 | .dout( dmo_flop_dout[35:0] ), | |
109 | .siclk(siclk), | |
110 | .soclk(soclk), | |
111 | .pce_ov(pce_ov), | |
112 | .stop(stop)); | |
113 | ||
114 | dmo_dpbuff_macro__dbuff_48x__rep_1__stack_none__width_36 dmo_dout_buf ( | |
115 | .din (dmo_flop_dout[35:0]), | |
116 | .dout(dmo_dout[35:0]) | |
117 | ); | |
118 | ||
119 | ||
120 | ||
121 | // fixscan start: | |
122 | assign dmo_flop_scanin = scan_in ; | |
123 | assign scan_out = dmo_flop_scanout ; | |
124 | // fixscan end: | |
125 | endmodule | |
126 | ||
127 | ||
128 | // | |
129 | // buff macro | |
130 | // | |
131 | // | |
132 | ||
133 | ||
134 | ||
135 | ||
136 | ||
137 | module dmo_dpbuff_macro__rep_1__width_38 ( | |
138 | din, | |
139 | dout); | |
140 | input [37:0] din; | |
141 | output [37:0] dout; | |
142 | ||
143 | ||
144 | ||
145 | ||
146 | ||
147 | ||
148 | buff #(38) d0_0 ( | |
149 | .in(din[37:0]), | |
150 | .out(dout[37:0]) | |
151 | ); | |
152 | ||
153 | ||
154 | ||
155 | ||
156 | ||
157 | ||
158 | ||
159 | ||
160 | endmodule | |
161 | ||
162 | ||
163 | ||
164 | ||
165 | ||
166 | ||
167 | ||
168 | ||
169 | ||
170 | // any PARAMS parms go into naming of macro | |
171 | ||
172 | module dmo_dpmsff_macro__mux_aope__ports_3__stack_64c__width_36 ( | |
173 | din0, | |
174 | din1, | |
175 | din2, | |
176 | sel0, | |
177 | sel1, | |
178 | clk, | |
179 | en, | |
180 | se, | |
181 | scan_in, | |
182 | siclk, | |
183 | soclk, | |
184 | pce_ov, | |
185 | stop, | |
186 | dout, | |
187 | scan_out); | |
188 | wire psel0; | |
189 | wire psel1; | |
190 | wire psel2; | |
191 | wire [35:0] muxout; | |
192 | wire l1clk; | |
193 | wire siclk_out; | |
194 | wire soclk_out; | |
195 | wire [34:0] so; | |
196 | ||
197 | input [35:0] din0; | |
198 | input [35:0] din1; | |
199 | input [35:0] din2; | |
200 | input sel0; | |
201 | input sel1; | |
202 | ||
203 | ||
204 | input clk; | |
205 | input en; | |
206 | input se; | |
207 | input scan_in; | |
208 | input siclk; | |
209 | input soclk; | |
210 | input pce_ov; | |
211 | input stop; | |
212 | ||
213 | ||
214 | ||
215 | output [35:0] dout; | |
216 | ||
217 | ||
218 | output scan_out; | |
219 | ||
220 | ||
221 | ||
222 | ||
223 | cl_dp1_penc3_8x c1_0 ( | |
224 | .test(1'b1), | |
225 | .sel0(sel0), | |
226 | .sel1(sel1), | |
227 | .psel0(psel0), | |
228 | .psel1(psel1), | |
229 | .psel2(psel2) | |
230 | ); | |
231 | ||
232 | mux3s #(36) d1_0 ( | |
233 | .sel0(psel0), | |
234 | .sel1(psel1), | |
235 | .sel2(psel2), | |
236 | .in0(din0[35:0]), | |
237 | .in1(din1[35:0]), | |
238 | .in2(din2[35:0]), | |
239 | .dout(muxout[35:0]) | |
240 | ); | |
241 | cl_dp1_l1hdr_8x c0_0 ( | |
242 | .l2clk(clk), | |
243 | .pce(en), | |
244 | .aclk(siclk), | |
245 | .bclk(soclk), | |
246 | .l1clk(l1clk), | |
247 | .se(se), | |
248 | .pce_ov(pce_ov), | |
249 | .stop(stop), | |
250 | .siclk_out(siclk_out), | |
251 | .soclk_out(soclk_out) | |
252 | ); | |
253 | dff #(36) d0_0 ( | |
254 | .l1clk(l1clk), | |
255 | .siclk(siclk_out), | |
256 | .soclk(soclk_out), | |
257 | .d(muxout[35:0]), | |
258 | .si({scan_in,so[34:0]}), | |
259 | .so({so[34:0],scan_out}), | |
260 | .q(dout[35:0]) | |
261 | ); | |
262 | ||
263 | ||
264 | ||
265 | ||
266 | ||
267 | ||
268 | ||
269 | ||
270 | ||
271 | ||
272 | ||
273 | ||
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | ||
280 | ||
281 | ||
282 | endmodule | |
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | ||
292 | // | |
293 | // buff macro | |
294 | // | |
295 | // | |
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | module dmo_dpbuff_macro__dbuff_48x__rep_1__stack_none__width_36 ( | |
302 | din, | |
303 | dout); | |
304 | input [35:0] din; | |
305 | output [35:0] dout; | |
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | ||
312 | buff #(36) d0_0 ( | |
313 | .in(din[35:0]), | |
314 | .out(dout[35:0]) | |
315 | ); | |
316 | ||
317 | ||
318 | ||
319 | ||
320 | ||
321 | ||
322 | ||
323 | ||
324 | endmodule | |
325 | ||
326 | ||
327 | ||
328 |