Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / spc / tlu / rtl / tlu_cep_dp.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_cep_dp.v
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module tlu_cep_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  lsu_rngf_cdbus, 
  asi_stg1_en, 
  scan_out, 
  cep_wr_data);
wire pce_ov;
wire clk;
wire stop;
wire siclk;
wire soclk;
wire se;
wire bit63_;
wire asi_lat_scanin;
wire asi_lat_scanout;



input 		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input	[63:0] lsu_rngf_cdbus;

input		asi_stg1_en;



output		scan_out;

output 	[63:0]	cep_wr_data;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign clk	= l2clk;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


tlu_cep_dp_inv_macro__left_63__width_1 bit63_inv   (
	.din	(lsu_rngf_cdbus		[63   ]	),
	.dout	(bit63_				)
);

tlu_cep_dp_msff_macro__width_64 asi_lat  (	
	.scan_in(asi_lat_scanin),
	.scan_out(asi_lat_scanout),
	.en	(asi_stg1_en			),
	.din	({bit63_		       ,
		  lsu_rngf_cdbus	[62:0]}),
	.dout	(cep_wr_data		[63:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);



// fixscan start:
assign asi_lat_scanin            = scan_in                  ;
assign scan_out                  = asi_lat_scanout          ;
// fixscan end:
endmodule



//
//   invert macro
//
//





module tlu_cep_dp_inv_macro__left_63__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;






inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);









endmodule









// any PARAMS parms go into naming of macro

module tlu_cep_dp_msff_macro__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;



  output [63:0] dout;


  output scan_out;




cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);




















endmodule