Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / spc / tlu / rtl / tlu_mbd_dp.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tlu_mbd_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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34// ========== Copyright Header End ============================================
35module tlu_mbd_dp (
36 asi_mbd_compare_data,
37 asi_mbd_sel_tsd0,
38 asi_mbd_sel_tsd1,
39 asi_mbd_sel_tic,
40 tic_mbist_data,
41 tsd0_mbist_data,
42 tsd1_mbist_data,
43 tlu_pc_0_prebuf_d,
44 mbd_compare,
45 tlu_pc_0_d);
46wire [31:0] read_data;
47
48
49
50input [7:0] asi_mbd_compare_data;
51input asi_mbd_sel_tsd0;
52input asi_mbd_sel_tsd1;
53input asi_mbd_sel_tic;
54
55input [31:0] tic_mbist_data;
56
57input [31:0] tsd0_mbist_data;
58input [31:0] tsd1_mbist_data;
59
60input [47:2] tlu_pc_0_prebuf_d;
61
62
63
64output mbd_compare;
65
66output [47:2] tlu_pc_0_d;
67
68
69
70//////////////////////////////////////////////////////////////////////
71
72
73
74tlu_mbd_dp_mux_macro__mux_aonpe__ports_3__stack_32r__width_32 read_data_mux (
75 .din0 (tsd0_mbist_data [31:0] ),
76 .din1 (tsd1_mbist_data [31:0] ),
77 .din2 (tic_mbist_data [31:0] ),
78 .sel0 (asi_mbd_sel_tsd0 ),
79 .sel1 (asi_mbd_sel_tsd1 ),
80 .sel2 (asi_mbd_sel_tic ),
81 .dout (read_data [31:0] )
82);
83
84tlu_mbd_dp_cmp_macro__width_32 mbist_cmp (
85 .din0 (read_data [31:0] ),
86 .din1 ({4 {asi_mbd_compare_data [7:0]}}),
87 .dout (mbd_compare )
88
89);
90
91tlu_mbd_dp_buff_macro__dbuff_40x__rep_1__stack_none__width_46 pc_0_d_buf (
92 .din (tlu_pc_0_prebuf_d [47:2] ),
93 .dout (tlu_pc_0_d [47:2] )
94
95);
96
97
98
99
100
101endmodule
102
103
104
105
106// general mux macro for pass-gate and and-or muxes with/wout priority encoders
107// also for pass-gate with decoder
108
109
110
111
112
113// any PARAMS parms go into naming of macro
114
115module tlu_mbd_dp_mux_macro__mux_aonpe__ports_3__stack_32r__width_32 (
116 din0,
117 sel0,
118 din1,
119 sel1,
120 din2,
121 sel2,
122 dout);
123wire buffout0;
124wire buffout1;
125wire buffout2;
126
127 input [31:0] din0;
128 input sel0;
129 input [31:0] din1;
130 input sel1;
131 input [31:0] din2;
132 input sel2;
133 output [31:0] dout;
134
135
136
137
138
139cl_dp1_muxbuff3_8x c0_0 (
140 .in0(sel0),
141 .in1(sel1),
142 .in2(sel2),
143 .out0(buffout0),
144 .out1(buffout1),
145 .out2(buffout2)
146);
147mux3s #(32) d0_0 (
148 .sel0(buffout0),
149 .sel1(buffout1),
150 .sel2(buffout2),
151 .in0(din0[31:0]),
152 .in1(din1[31:0]),
153 .in2(din2[31:0]),
154.dout(dout[31:0])
155);
156
157
158
159
160
161
162
163
164
165
166
167
168
169endmodule
170
171
172//
173// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
174//
175//
176
177
178
179
180
181module tlu_mbd_dp_cmp_macro__width_32 (
182 din0,
183 din1,
184 dout);
185 input [31:0] din0;
186 input [31:0] din1;
187 output dout;
188
189
190
191
192
193
194cmp #(32) m0_0 (
195.in0(din0[31:0]),
196.in1(din1[31:0]),
197.out(dout)
198);
199
200
201
202
203
204
205
206
207
208
209endmodule
210
211
212
213
214
215//
216// buff macro
217//
218//
219
220
221
222
223
224module tlu_mbd_dp_buff_macro__dbuff_40x__rep_1__stack_none__width_46 (
225 din,
226 dout);
227 input [45:0] din;
228 output [45:0] dout;
229
230
231
232
233
234
235buff #(46) d0_0 (
236.in(din[45:0]),
237.out(dout[45:0])
238);
239
240
241
242
243
244
245
246
247endmodule
248
249
250
251