Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu_dbg_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tcu_dbg_ctl ( | |
36 | scan_in, | |
37 | tcu_int_se, | |
38 | tcu_int_aclk, | |
39 | tcu_int_bclk, | |
40 | tcu_int_ce, | |
41 | tcu_pce_ov, | |
42 | l2clk, | |
43 | scan_out, | |
44 | cmp_io_sync_en_local, | |
45 | io_cmp_sync_en_local, | |
46 | cmp_io2x_sync_en_local, | |
47 | spc_hstop_req, | |
48 | spc_sstop_req, | |
49 | spc_tp, | |
50 | reset_event, | |
51 | spc_crstat, | |
52 | spc_crs, | |
53 | spc_ss_comp, | |
54 | doss_stat, | |
55 | tcu_ss_request, | |
56 | ssreq_upd_sync, | |
57 | tcu_ss_mode, | |
58 | tcu_do_mode, | |
59 | dbg1_tcu_soc_hard_stop, | |
60 | dbg1_tcu_soc_asrt_trigout, | |
61 | trigout_pulse, | |
62 | mio_tcu_trigin, | |
63 | cycle_stretch, | |
64 | mbist_clk_stop_req, | |
65 | mbist_clk_stop, | |
66 | jtag_clock_start, | |
67 | jtscan_off, | |
68 | cyc_count, | |
69 | cyc_count_upd_sync, | |
70 | tcudcr_data, | |
71 | tcudcr_upd_sync, | |
72 | decnt_data, | |
73 | decnt_upd_sync, | |
74 | core_sel, | |
75 | core_sel_upd_sync, | |
76 | spc_doss_enab, | |
77 | doss_mode, | |
78 | doss_enab, | |
79 | csmode, | |
80 | csmode_upd_sync, | |
81 | cs_mode, | |
82 | cs_mode_active, | |
83 | jtagclkstop_ov, | |
84 | de_count, | |
85 | cycle_count, | |
86 | tcu_dcr, | |
87 | debug_cycle_counter_stop, | |
88 | clock_domain_data, | |
89 | dbg_upd_clock_domain, | |
90 | tcu_dcr_en, | |
91 | spc_ss_mode, | |
92 | spc_ss_sel, | |
93 | dbg_creg_access, | |
94 | dbg_creg_addr, | |
95 | dbg_creg_data, | |
96 | dbg_creg_wr_en, | |
97 | dbg_creg_addr_en, | |
98 | dbg_creg_data_en, | |
99 | ucb_csr_wr_sync, | |
100 | ucb_csr_addr, | |
101 | ucb_data_out); | |
102 | wire l1en; | |
103 | wire pce_ov; | |
104 | wire stop; | |
105 | wire se; | |
106 | wire siclk; | |
107 | wire soclk; | |
108 | wire l1clk; | |
109 | wire ucb_sel_cycle_count; | |
110 | wire ucb_sel_dcr; | |
111 | wire ucb_sel_trigout; | |
112 | wire ucb_sel_dec; | |
113 | wire ucb_wr_cycle_count; | |
114 | wire ucb_wr_dcr; | |
115 | wire ucb_wr_trigout; | |
116 | wire ucb_wr_dec; | |
117 | wire dbg_cyccnt_reg_scanin; | |
118 | wire dbg_cyccnt_reg_scanout; | |
119 | wire [63:0] next_cycle_count; | |
120 | wire cycle_count_dec; | |
121 | wire xxxrst_count_dec; | |
122 | wire cycxxx_count_dec; | |
123 | wire [63:0] cycxxx_count; | |
124 | wire cycle_count_begin; | |
125 | wire de_count_stop; | |
126 | wire dbg_evnt_hld; | |
127 | wire do_mode_active; | |
128 | wire cycle_count_stop; | |
129 | wire cycrst_count_beg; | |
130 | wire reset_count_stop; | |
131 | wire dbg_tcudcr_reg_scanin; | |
132 | wire dbg_tcudcr_reg_scanout; | |
133 | wire [3:0] next_tcu_dcr; | |
134 | wire sstop_all_spcs; | |
135 | wire dbg_decnt_reg_scanin; | |
136 | wire dbg_decnt_reg_scanout; | |
137 | wire [31:0] next_de_count; | |
138 | wire de_count_dec; | |
139 | wire de_count_begin; | |
140 | wire dbg_event_active; | |
141 | wire soc_hs_active; | |
142 | wire soc_hard_stop; | |
143 | wire trigin_sync; | |
144 | wire spc_hs_active; | |
145 | wire spc_ss_active; | |
146 | wire spc_tp_active; | |
147 | wire dbg1_tcu_soc_asrt_trigout_sync; | |
148 | wire dbg_eventhold_reg_scanin; | |
149 | wire dbg_eventhold_reg_scanout; | |
150 | wire evnt_hld_en; | |
151 | wire [3:0] dbg_event; | |
152 | wire [3:0] dbg_event_hold; | |
153 | wire jtag_clock_start_sync; | |
154 | wire soc_hs_hold; | |
155 | wire spc_tp_hold; | |
156 | wire spc_hs_hold; | |
157 | wire spc_ss_hold; | |
158 | wire dbg_sshold_reg_scanin; | |
159 | wire dbg_sshold_reg_scanout; | |
160 | wire ss_evnt_hld_en; | |
161 | wire [7:0] spc_sstop_din; | |
162 | wire [7:0] ss_hold; | |
163 | wire ss_hold_active; | |
164 | wire [7:0] spc_sstop_qual; | |
165 | wire [7:0] spc_clk_dom; | |
166 | wire cntrs_stopped; | |
167 | wire crstat_ss_vld; | |
168 | wire tcu_dcr_one; | |
169 | wire tcu_dcr_three; | |
170 | wire tcu_dcr_two; | |
171 | wire rst_evnt_trigger; | |
172 | wire rst_evnt_trigger_2nd; | |
173 | wire dbg_trigout_reg_scanin; | |
174 | wire dbg_trigout_reg_scanout; | |
175 | wire trigout; | |
176 | wire trigout_q; | |
177 | wire trigout2; | |
178 | wire trigout2_q; | |
179 | wire trigout_qq; | |
180 | wire trigout2_qq; | |
181 | wire [63:0] core_run; | |
182 | wire [63:0] do_core_run; | |
183 | wire dbg_creg_access_din; | |
184 | wire dbg_creg_ad_enab; | |
185 | wire dbg_creg_wr_enab; | |
186 | wire dbg_cregreq_reg_scanin; | |
187 | wire dbg_cregreq_reg_scanout; | |
188 | wire dbg_creg_ad_enab_q; | |
189 | wire dbg_creg_wr_enab_q; | |
190 | wire dbg_cregreqb_reg_scanin; | |
191 | wire dbg_cregreqb_reg_scanout; | |
192 | wire dbg_creg_ad_enab_qq; | |
193 | wire dbg_creg_wr_enab_qq; | |
194 | wire dbg_creg_access_reg_scanin; | |
195 | wire dbg_creg_access_reg_scanout; | |
196 | wire [63:0] do_park; | |
197 | wire [7:0] spc_dolap_enab; | |
198 | wire [63:0] do_unpark; | |
199 | wire ss_mode_active; | |
200 | wire [7:0] spc_sstep_enab; | |
201 | wire [7:0] singstep_mode; | |
202 | wire dbg_ssupd_reg_scanin; | |
203 | wire dbg_ssupd_reg_scanout; | |
204 | wire ss_request; | |
205 | wire ss_request_pulse; | |
206 | wire [7:0] singstep_request; | |
207 | wire dbg_ssmode_reg_scanin; | |
208 | wire dbg_ssmode_reg_scanout; | |
209 | wire dbg_ssreq_reg_scanin; | |
210 | wire dbg_ssreq_reg_scanout; | |
211 | wire [7:0] disbolap_mode; | |
212 | wire dbg_domode_reg_scanin; | |
213 | wire dbg_domode_reg_scanout; | |
214 | wire dbg_cstep_reg_scanin; | |
215 | wire dbg_cstep_reg_scanout; | |
216 | wire next_cs_mode; | |
217 | wire dbg_sochs_sync_reg_scanin; | |
218 | wire dbg_sochs_sync_reg_scanout; | |
219 | wire sochs_en; | |
220 | wire dbg_trigreq_sync_reg_scanin; | |
221 | wire dbg_trigreq_sync_reg_scanout; | |
222 | wire trigreq_en; | |
223 | wire dbg_trigin_sync_reg_scanin; | |
224 | wire dbg_trigin_sync_reg_scanout; | |
225 | wire mio_tcu_trigin_mission; | |
226 | wire dbg_clkst_sync_reg_scanin; | |
227 | wire dbg_clkst_sync_reg_scanout; | |
228 | ||
229 | ||
230 | // Scan Control | |
231 | input scan_in; | |
232 | input tcu_int_se; | |
233 | input tcu_int_aclk; | |
234 | input tcu_int_bclk; | |
235 | input tcu_int_ce; | |
236 | input tcu_pce_ov; | |
237 | input l2clk; | |
238 | output scan_out; | |
239 | // Synchronizer | |
240 | input cmp_io_sync_en_local; | |
241 | input io_cmp_sync_en_local; | |
242 | input cmp_io2x_sync_en_local; | |
243 | ||
244 | // Debug Event Requests from SPC Cores | |
245 | input [7:0] spc_hstop_req; | |
246 | input [7:0] spc_sstop_req; | |
247 | input [7:0] spc_tp; | |
248 | // End of POR as a Debug Event Request | |
249 | input reset_event; | |
250 | ||
251 | // Core_running Status | |
252 | input [7:0] spc_crstat; | |
253 | input [63:0] spc_crs; | |
254 | input [7:0] spc_ss_comp; // single-step complete | |
255 | ||
256 | // Disable Overlap & Single-Step | |
257 | output [7:0] doss_stat; // to jtag | |
258 | output [7:0] tcu_ss_request; | |
259 | input ssreq_upd_sync; // from jtag | |
260 | output [7:0] tcu_ss_mode; // single-step | |
261 | output [7:0] tcu_do_mode; // Disable Overlap | |
262 | ||
263 | // Hard Stop from SOC | |
264 | input dbg1_tcu_soc_hard_stop; | |
265 | ||
266 | // Watchpoint Trigger | |
267 | input dbg1_tcu_soc_asrt_trigout; | |
268 | output trigout_pulse; // to TRIGOUT package pin | |
269 | ||
270 | // Trigger Input from Pin | |
271 | input mio_tcu_trigin; | |
272 | ||
273 | // Cycle stretch | |
274 | output cycle_stretch; | |
275 | ||
276 | // MBIST Clock Stop | |
277 | input mbist_clk_stop_req; | |
278 | output mbist_clk_stop; | |
279 | ||
280 | // From JTAG | |
281 | input jtag_clock_start; | |
282 | ||
283 | input jtscan_off; | |
284 | input [63:0] cyc_count; | |
285 | input cyc_count_upd_sync; | |
286 | input [3:0] tcudcr_data; | |
287 | input tcudcr_upd_sync; | |
288 | input [31:0] decnt_data; | |
289 | input decnt_upd_sync; | |
290 | input [7:0] core_sel; | |
291 | input core_sel_upd_sync; | |
292 | ||
293 | input [7:0] spc_doss_enab; | |
294 | input [1:0] doss_mode; | |
295 | input [63:0] doss_enab; | |
296 | ||
297 | input csmode; | |
298 | input csmode_upd_sync; | |
299 | output cs_mode; | |
300 | output cs_mode_active; | |
301 | output jtagclkstop_ov; | |
302 | ||
303 | // To JTAG | |
304 | output [31:0] de_count; | |
305 | output [63:0] cycle_count; | |
306 | output [3:0] tcu_dcr; | |
307 | ||
308 | // To Clock Sequencer | |
309 | output debug_cycle_counter_stop; | |
310 | output [23:0] clock_domain_data; | |
311 | output dbg_upd_clock_domain; | |
312 | output tcu_dcr_en; // bit[2] | |
313 | output spc_ss_mode; // soft-stop | |
314 | output [7:0] spc_ss_sel; | |
315 | ||
316 | // To UCB Control | |
317 | output dbg_creg_access; | |
318 | output [39:0] dbg_creg_addr; | |
319 | output [63:0] dbg_creg_data; | |
320 | output dbg_creg_wr_en; | |
321 | output dbg_creg_addr_en; | |
322 | output dbg_creg_data_en; | |
323 | ||
324 | // CSR (mbist_ctl) | |
325 | input ucb_csr_wr_sync; | |
326 | input [5:0] ucb_csr_addr; | |
327 | input [63:0] ucb_data_out; | |
328 | ||
329 | // Scan reassigns | |
330 | assign l1en = tcu_int_ce; // 1'b1; | |
331 | assign pce_ov = tcu_pce_ov; // 1'b1; | |
332 | assign stop = 1'b0; | |
333 | assign se = tcu_int_se; | |
334 | assign siclk = tcu_int_aclk; | |
335 | assign soclk = tcu_int_bclk; | |
336 | // clock header | |
337 | tcu_dbg_ctl_l1clkhdr_ctl_macro dbgctl_clkgen | |
338 | ( | |
339 | .l2clk (l2clk ), | |
340 | .l1clk (l1clk ), | |
341 | .l1en(l1en), | |
342 | .pce_ov(pce_ov), | |
343 | .stop(stop), | |
344 | .se(se) | |
345 | ); | |
346 | ||
347 | assign ucb_sel_cycle_count = (ucb_csr_addr == 6'h20); | |
348 | assign ucb_sel_dcr = (ucb_csr_addr == 6'h21); | |
349 | assign ucb_sel_trigout = (ucb_csr_addr == 6'h22); | |
350 | assign ucb_sel_dec = (ucb_csr_addr == 6'h23); | |
351 | ||
352 | assign ucb_wr_cycle_count = ucb_csr_wr_sync && ucb_sel_cycle_count; | |
353 | assign ucb_wr_dcr = ucb_csr_wr_sync && ucb_sel_dcr; | |
354 | assign ucb_wr_trigout = ucb_csr_wr_sync && ucb_sel_trigout; | |
355 | assign ucb_wr_dec = ucb_csr_wr_sync && ucb_sel_dec; | |
356 | ||
357 | //// Synchronizer Pulse from cluster header | |
358 | // msff_ctl_macro dbg_cmpiosync_reg (width=3) | |
359 | //( | |
360 | // .scan_in(dbg_cmpiosync_reg_scanin), | |
361 | // .scan_out(dbg_cmpiosync_reg_scanout), | |
362 | // .l1clk (l1clk), | |
363 | // .din ({cmp_io_sync_en, io_cmp_sync_en, cmp_io2x_sync_en}), | |
364 | // .dout ({cmp_io_sync_en_local, io_cmp_sync_en_local, cmp_io2x_sync_en_local}) | |
365 | // ); | |
366 | ||
367 | //******************************************************************** | |
368 | // Cycle Counter | |
369 | //******************************************************************** | |
370 | // 64-bit for non-reset event; tcu_dcr[2]==1 ==> 2 32-bit counters | |
371 | // where upper word is cycle counter, lower word is reset counter | |
372 | // When tcu_dcr[2]==0, cycle counter waits until debug events counter | |
373 | // reaches zero | |
374 | ||
375 | tcu_dbg_ctl_msff_ctl_macro__width_64 dbg_cyccnt_reg | |
376 | ( | |
377 | .scan_in(dbg_cyccnt_reg_scanin), | |
378 | .scan_out(dbg_cyccnt_reg_scanout), | |
379 | .l1clk (l1clk), | |
380 | .din (next_cycle_count[63:0]), | |
381 | .dout (cycle_count[63:0]), | |
382 | .siclk(siclk), | |
383 | .soclk(soclk) | |
384 | ); | |
385 | assign next_cycle_count[63:0] = cycle_count_dec ? (cycle_count[63:0] - 64'b1) | |
386 | : xxxrst_count_dec ? (cycle_count[63:0] - 64'b1) | |
387 | : cycxxx_count_dec ? cycxxx_count[63:0] | |
388 | : cyc_count_upd_sync ? cyc_count[63:0] | |
389 | : ucb_wr_cycle_count ? ucb_data_out[63:0] | |
390 | : cycle_count[63:0]; | |
391 | ||
392 | assign cycle_count_begin = ~tcu_dcr_en | |
393 | & ((de_count_stop & dbg_evnt_hld) | do_mode_active | cs_mode | |
394 | | mbist_clk_stop_req); | |
395 | assign cycle_count_dec = cycle_count_begin & ~cycle_count_stop; | |
396 | assign cycle_count_stop = (cycle_count[63:0] == 64'b0); | |
397 | ||
398 | assign cycrst_count_beg = tcu_dcr_en & reset_event; | |
399 | assign xxxrst_count_dec = cycrst_count_beg & ~reset_count_stop; | |
400 | assign cycxxx_count_dec = cycrst_count_beg & reset_count_stop & ~cycle_count_stop; | |
401 | assign reset_count_stop = (cycle_count[31:0] == 32'b0); | |
402 | ||
403 | assign cycxxx_count[63:0] = (cycle_count[63:0] - 64'b1) & 64'hFFFFFFFF00000000; | |
404 | //assign cc_gt_f = |cycle_count[63:4]; | |
405 | ||
406 | //******************************************************************** | |
407 | // TCU DCR: Debug event Control Register | |
408 | //******************************************************************** | |
409 | // 4 bits; [2] makes Cycle Counter operate as Cycle[63:32]/Reset[31:0] | |
410 | // Counter and enables End-of-POR-Sequence as a debug event | |
411 | // bit[3] enables all spc's to be softstopped if any requests a sstop | |
412 | ||
413 | tcu_dbg_ctl_msff_ctl_macro__width_4 dbg_tcudcr_reg | |
414 | ( | |
415 | .scan_in(dbg_tcudcr_reg_scanin), | |
416 | .scan_out(dbg_tcudcr_reg_scanout), | |
417 | .l1clk (l1clk), | |
418 | .din (next_tcu_dcr[3:0]), | |
419 | .dout (tcu_dcr[3:0]), | |
420 | .siclk(siclk), | |
421 | .soclk(soclk) | |
422 | ); | |
423 | assign next_tcu_dcr[3:0] = tcudcr_upd_sync ? tcudcr_data[3:0] | |
424 | : ucb_wr_dcr ? ucb_data_out[3:0] | |
425 | : tcu_dcr[3:0]; | |
426 | ||
427 | assign tcu_dcr_en = tcu_dcr[2]; | |
428 | assign sstop_all_spcs = tcu_dcr[3] & ~tcu_dcr[2]; | |
429 | ||
430 | //******************************************************************** | |
431 | // Debug Events Counter | |
432 | //******************************************************************** | |
433 | // Counts Debug Events: decrements until zero | |
434 | // enabled if tcu_dcr[2]=0 | |
435 | ||
436 | tcu_dbg_ctl_msff_ctl_macro__width_32 dbg_decnt_reg | |
437 | ( | |
438 | .scan_in(dbg_decnt_reg_scanin), | |
439 | .scan_out(dbg_decnt_reg_scanout), | |
440 | .l1clk (l1clk), | |
441 | .din (next_de_count[31:0]), | |
442 | .dout (de_count[31:0]), | |
443 | .siclk(siclk), | |
444 | .soclk(soclk) | |
445 | ); | |
446 | assign next_de_count[31:0] = de_count_dec ? (de_count[31:0] - 32'b1) | |
447 | : decnt_upd_sync ? decnt_data[31:0] | |
448 | : ucb_wr_dec ? ucb_data_out[31:0] | |
449 | : de_count[31:0]; | |
450 | ||
451 | // counter stops after reaching 0 | |
452 | assign de_count_dec = (de_count_begin & dbg_event_active) | |
453 | & ~(de_count_stop); | |
454 | ||
455 | assign de_count_begin = ~tcu_dcr_en; | |
456 | assign de_count_stop = (de_count[31:0] == 32'b0) | tcu_dcr_en; | |
457 | ||
458 | //******************************************************************** | |
459 | // Detect Edge of Any Debug Request and Hold the Request (from spc/soc) | |
460 | //******************************************************************** | |
461 | // Only after all debug events have been counted per de_counter | |
462 | assign soc_hs_active = soc_hard_stop | trigin_sync; | |
463 | assign spc_hs_active = |spc_hstop_req[7:0]; | |
464 | assign spc_ss_active = |spc_sstop_req[7:0]; | |
465 | assign spc_tp_active = |spc_tp[7:0] | dbg1_tcu_soc_asrt_trigout_sync; | |
466 | ||
467 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_4 dbg_eventhold_reg | |
468 | ( | |
469 | .scan_in(dbg_eventhold_reg_scanin), | |
470 | .scan_out(dbg_eventhold_reg_scanout), | |
471 | .l1clk (l1clk), | |
472 | .en (evnt_hld_en), | |
473 | .din (dbg_event[3:0]), | |
474 | .dout (dbg_event_hold[3:0]), | |
475 | .siclk(siclk), | |
476 | .soclk(soclk) | |
477 | ); | |
478 | assign dbg_event[3:0] = {soc_hs_active,spc_tp_active,spc_hs_active,spc_ss_active}; | |
479 | assign dbg_evnt_hld = |dbg_event_hold[3:0]; | |
480 | assign evnt_hld_en = (de_count_stop & ~dbg_evnt_hld) | jtag_clock_start_sync; | |
481 | ||
482 | assign soc_hs_hold = dbg_event_hold[3]; | |
483 | assign spc_tp_hold = dbg_event_hold[2]; | |
484 | assign spc_hs_hold = dbg_event_hold[1]; | |
485 | assign spc_ss_hold = dbg_event_hold[0]; | |
486 | assign dbg_event_active = |dbg_event[3:0]; | |
487 | ||
488 | //******************************************************************** | |
489 | // Detect Edge of Soft Stop Debug Request and Hold It | |
490 | //******************************************************************** | |
491 | // This doubles as core select reg for JTAG | |
492 | ||
493 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_8 dbg_sshold_reg | |
494 | ( | |
495 | .scan_in(dbg_sshold_reg_scanin), | |
496 | .scan_out(dbg_sshold_reg_scanout), | |
497 | .l1clk (l1clk), | |
498 | .en (ss_evnt_hld_en), | |
499 | .din (spc_sstop_din[7:0]), | |
500 | .dout (ss_hold[7:0]), | |
501 | .siclk(siclk), | |
502 | .soclk(soclk) | |
503 | ); | |
504 | assign ss_hold_active = ~(|ss_hold[7:0]) & de_count_stop; | |
505 | assign ss_evnt_hld_en = (ss_hold_active | core_sel_upd_sync) | jtag_clock_start_sync; | |
506 | assign spc_sstop_qual[7:0]= {8{sstop_all_spcs & spc_ss_active}} | spc_sstop_req[7:0]; | |
507 | assign spc_sstop_din[7:0] = core_sel_upd_sync ? core_sel[7:0] : spc_sstop_qual[7:0]; | |
508 | //assign spc_sstop_din[7:0] = core_sel_upd_sync ? core_sel[7:0] : spc_sstop_req[7:0]; | |
509 | ||
510 | //******************************************************************** | |
511 | // Interface to Clock Sequencer | |
512 | //******************************************************************** | |
513 | ||
514 | // Soft Stop - only stop clocks to target SPC cores | |
515 | // Start with SPC0 | |
516 | assign spc_ss_mode = spc_ss_hold; | |
517 | assign spc_ss_sel[7:0] = ss_hold[7:0]; | |
518 | ||
519 | // Hard Stop - stop all clocks, start with target SPC core or SOC0 | |
520 | assign clock_domain_data[23:8] = soc_hs_active ? 16'b1 : 16'b0; | |
521 | assign spc_clk_dom[7:0] = spc_hs_active ? spc_hstop_req[7:0] | |
522 | : spc_ss_active ? 8'b1 // start w/spc0 | |
523 | : 8'b0; | |
524 | ||
525 | assign clock_domain_data[7:0] = spc_clk_dom[7:0]; | |
526 | ||
527 | assign dbg_upd_clock_domain = ~tcu_dcr_en & evnt_hld_en | |
528 | & (soc_hs_active | spc_hs_active | spc_ss_active); | |
529 | //assign dbg_upd_clock_domain = ~tcu_dcr_en & dbg_evnt_hld; | |
530 | assign cntrs_stopped = de_count_stop & cycle_count_stop & ~tcu_dcr_en; | |
531 | ||
532 | assign debug_cycle_counter_stop = cntrs_stopped & ( spc_hs_hold | soc_hs_hold | |
533 | | (spc_ss_hold & crstat_ss_vld)) | |
534 | | (reset_count_stop | |
535 | & reset_event & tcu_dcr_one) | |
536 | | (cycle_count_stop | |
537 | & reset_event & tcu_dcr_three) ; | |
538 | ||
539 | assign mbist_clk_stop = cycle_count_stop & ~tcu_dcr_en & mbist_clk_stop_req; | |
540 | ||
541 | //******************************************************************** | |
542 | // End of Reset Sequence as an Event | |
543 | //******************************************************************** | |
544 | assign tcu_dcr_one = tcu_dcr[2:0]==3'b101; | |
545 | assign tcu_dcr_two = tcu_dcr[2:0]==3'b110; | |
546 | assign tcu_dcr_three = &tcu_dcr[2:0]; | |
547 | ||
548 | assign rst_evnt_trigger = reset_count_stop & tcu_dcr_en & reset_event; | |
549 | assign rst_evnt_trigger_2nd = cycle_count_stop & tcu_dcr_three & reset_event; | |
550 | assign cycle_stretch = reset_count_stop & (tcu_dcr_two | tcu_dcr_three) & reset_event; | |
551 | ||
552 | //******************************************************************** | |
553 | // Trigger Pulse | |
554 | //******************************************************************** | |
555 | // Send pulse to TRIGOUT package pin, in io_clk domain | |
556 | ||
557 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_4 dbg_trigout_reg | |
558 | ( | |
559 | .scan_in(dbg_trigout_reg_scanin), | |
560 | .scan_out(dbg_trigout_reg_scanout), | |
561 | .l1clk (l1clk), | |
562 | .en (cmp_io2x_sync_en_local), | |
563 | .din ({trigout, trigout_q, trigout2, trigout2_q }), | |
564 | .dout ({trigout_q,trigout_qq, trigout2_q, trigout2_qq}), | |
565 | .siclk(siclk), | |
566 | .soclk(soclk) | |
567 | ); | |
568 | ||
569 | assign trigout = ucb_wr_trigout | rst_evnt_trigger | (cntrs_stopped & spc_tp_hold); | |
570 | //| dbg1_tcu_soc_asrt_trigout_sync; | |
571 | assign trigout2 = rst_evnt_trigger_2nd; | |
572 | assign trigout_pulse = (trigout_q & ~trigout_qq) | | |
573 | (trigout2_q & ~trigout2_qq); | |
574 | ||
575 | //******************************************************************** | |
576 | // Core Parking and Run Status Detection | |
577 | //******************************************************************** | |
578 | // Send request to NCU to park targeted SPC Core(s) for Soft-stop or Disable Overlap | |
579 | ||
580 | // Generate data for parking cores for soft stop | |
581 | assign core_run[7:0] = ~ss_hold[0] ? spc_crs[7:0] : 8'b0; | |
582 | assign core_run[15:8] = ~ss_hold[1] ? spc_crs[15:8] : 8'b0; | |
583 | assign core_run[23:16] = ~ss_hold[2] ? spc_crs[23:16] : 8'b0; | |
584 | assign core_run[31:24] = ~ss_hold[3] ? spc_crs[31:24] : 8'b0; | |
585 | assign core_run[39:32] = ~ss_hold[4] ? spc_crs[39:32] : 8'b0; | |
586 | assign core_run[47:40] = ~ss_hold[5] ? spc_crs[47:40] : 8'b0; | |
587 | assign core_run[55:48] = ~ss_hold[6] ? spc_crs[55:48] : 8'b0; | |
588 | assign core_run[63:56] = ~ss_hold[7] ? spc_crs[63:56] : 8'b0; | |
589 | ||
590 | // Generate Core Run Address & Data to send over UCB to NCU; this is to | |
591 | // park cores that should be soft-stopped | |
592 | assign dbg_creg_data[63:0] = spc_ss_hold ? core_run[63:0] : do_core_run[63:0]; | |
593 | assign dbg_creg_addr[39:0] = 40'h9001040050; | |
594 | ||
595 | // Tells ucb to use dbg signals instead of jtag signals | |
596 | assign dbg_creg_access_din = (spc_ss_hold & ~tcu_dcr_en) | do_mode_active; | |
597 | ||
598 | // Send addr/data 'enables' to ucb as one pulse synch'd to io clk domain | |
599 | assign dbg_creg_ad_enab = (spc_ss_hold & ~tcu_dcr_en) | (do_mode_active & cycle_count_dec); // & ~cc_gt_f); | |
600 | assign dbg_creg_wr_enab = (spc_ss_hold & cntrs_stopped) | (do_mode_active & cycle_count_dec); // & ~cc_gt_f); | |
601 | ||
602 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_2 dbg_cregreq_reg | |
603 | ( | |
604 | .scan_in(dbg_cregreq_reg_scanin), | |
605 | .scan_out(dbg_cregreq_reg_scanout), | |
606 | .l1clk (l1clk), | |
607 | .en (cmp_io_sync_en_local), | |
608 | .din ({dbg_creg_ad_enab,dbg_creg_wr_enab}), | |
609 | .dout ({dbg_creg_ad_enab_q,dbg_creg_wr_enab_q}), | |
610 | .siclk(siclk), | |
611 | .soclk(soclk) | |
612 | ); | |
613 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_2 dbg_cregreqb_reg | |
614 | ( | |
615 | .scan_in(dbg_cregreqb_reg_scanin), | |
616 | .scan_out(dbg_cregreqb_reg_scanout), | |
617 | .l1clk (l1clk), | |
618 | .en (cmp_io_sync_en_local), | |
619 | .din ({dbg_creg_ad_enab_q,dbg_creg_wr_enab_q}), | |
620 | .dout ({dbg_creg_ad_enab_qq,dbg_creg_wr_enab_qq}), | |
621 | .siclk(siclk), | |
622 | .soclk(soclk) | |
623 | ); | |
624 | ||
625 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_1 dbg_creg_access_reg ( | |
626 | .scan_in ( dbg_creg_access_reg_scanin ), | |
627 | .scan_out ( dbg_creg_access_reg_scanout ), | |
628 | .l1clk ( l1clk ), | |
629 | .en ( cmp_io_sync_en_local ), | |
630 | .din ( dbg_creg_access_din ), | |
631 | .dout ( dbg_creg_access ), | |
632 | .siclk(siclk), | |
633 | .soclk(soclk)); | |
634 | ||
635 | assign dbg_creg_data_en = dbg_creg_ad_enab_q & ~dbg_creg_ad_enab_qq | |
636 | | (~dbg_creg_ad_enab_q & dbg_creg_ad_enab_qq & do_mode_active); | |
637 | assign dbg_creg_wr_en = dbg_creg_wr_enab_q & ~dbg_creg_wr_enab_qq | |
638 | | (~dbg_creg_wr_enab_q & dbg_creg_wr_enab_qq & do_mode_active); | |
639 | assign dbg_creg_addr_en = dbg_creg_data_en; | |
640 | ||
641 | // This signal is set when targeted cores say they are parked via Core_Run_Status | |
642 | assign crstat_ss_vld = (~ss_hold[0] | (ss_hold[0] & ~spc_crstat[0])) | |
643 | & (~ss_hold[1] | (ss_hold[1] & ~spc_crstat[1])) | |
644 | & (~ss_hold[2] | (ss_hold[2] & ~spc_crstat[2])) | |
645 | & (~ss_hold[3] | (ss_hold[3] & ~spc_crstat[3])) | |
646 | & (~ss_hold[4] | (ss_hold[4] & ~spc_crstat[4])) | |
647 | & (~ss_hold[5] | (ss_hold[5] & ~spc_crstat[5])) | |
648 | & (~ss_hold[6] | (ss_hold[6] & ~spc_crstat[6])) | |
649 | & (~ss_hold[7] | (ss_hold[7] & ~spc_crstat[7])); | |
650 | ||
651 | // Generate data for parking cores for disable overlap | |
652 | ||
653 | assign do_park[7:0] = ~spc_dolap_enab[0] ? spc_crs[7:0] : 8'b0; | |
654 | assign do_park[15:8] = ~spc_dolap_enab[1] ? spc_crs[15:8] : 8'b0; | |
655 | assign do_park[23:16] = ~spc_dolap_enab[2] ? spc_crs[23:16] : 8'b0; | |
656 | assign do_park[31:24] = ~spc_dolap_enab[3] ? spc_crs[31:24] : 8'b0; | |
657 | assign do_park[39:32] = ~spc_dolap_enab[4] ? spc_crs[39:32] : 8'b0; | |
658 | assign do_park[47:40] = ~spc_dolap_enab[5] ? spc_crs[47:40] : 8'b0; | |
659 | assign do_park[55:48] = ~spc_dolap_enab[6] ? spc_crs[55:48] : 8'b0; | |
660 | assign do_park[63:56] = ~spc_dolap_enab[7] ? spc_crs[63:56] : 8'b0; | |
661 | ||
662 | assign do_unpark[7:0] = ~spc_dolap_enab[0] ? spc_crs[7:0] : doss_enab[7:0]; | |
663 | assign do_unpark[15:8] = ~spc_dolap_enab[1] ? spc_crs[15:8] : doss_enab[15:8]; | |
664 | assign do_unpark[23:16] = ~spc_dolap_enab[2] ? spc_crs[23:16] : doss_enab[23:16]; | |
665 | assign do_unpark[31:24] = ~spc_dolap_enab[3] ? spc_crs[31:24] : doss_enab[31:24]; | |
666 | assign do_unpark[39:32] = ~spc_dolap_enab[4] ? spc_crs[39:32] : doss_enab[39:32]; | |
667 | assign do_unpark[47:40] = ~spc_dolap_enab[5] ? spc_crs[47:40] : doss_enab[47:40]; | |
668 | assign do_unpark[55:48] = ~spc_dolap_enab[6] ? spc_crs[55:48] : doss_enab[55:48]; | |
669 | assign do_unpark[63:56] = ~spc_dolap_enab[7] ? spc_crs[63:56] : doss_enab[63:56]; | |
670 | ||
671 | assign do_core_run[63:0] = cycle_count_stop ? do_park[63:0]: do_unpark[63:0]; | |
672 | ||
673 | //******************************************************************** | |
674 | // Single Step Mode | |
675 | //******************************************************************** | |
676 | // Detect when all physical cores that should be in single-step mode | |
677 | // become parked & send a tcu_ss_mode signal to those cores; only update | |
678 | // when core becomes parked; single step does not stop clocks to cores | |
679 | ||
680 | assign ss_mode_active = &doss_mode[1:0]; | |
681 | ||
682 | assign spc_sstep_enab[7:0] = spc_doss_enab[7:0] & {8{ss_mode_active}}; | |
683 | ||
684 | assign singstep_mode[0] = ~spc_crstat[0] ? spc_sstep_enab[0] : tcu_ss_mode[0]; | |
685 | assign singstep_mode[1] = ~spc_crstat[1] ? spc_sstep_enab[1] : tcu_ss_mode[1]; | |
686 | assign singstep_mode[2] = ~spc_crstat[2] ? spc_sstep_enab[2] : tcu_ss_mode[2]; | |
687 | assign singstep_mode[3] = ~spc_crstat[3] ? spc_sstep_enab[3] : tcu_ss_mode[3]; | |
688 | assign singstep_mode[4] = ~spc_crstat[4] ? spc_sstep_enab[4] : tcu_ss_mode[4]; | |
689 | assign singstep_mode[5] = ~spc_crstat[5] ? spc_sstep_enab[5] : tcu_ss_mode[5]; | |
690 | assign singstep_mode[6] = ~spc_crstat[6] ? spc_sstep_enab[6] : tcu_ss_mode[6]; | |
691 | assign singstep_mode[7] = ~spc_crstat[7] ? spc_sstep_enab[7] : tcu_ss_mode[7]; | |
692 | ||
693 | // Create single-step request pulses to target SPC cores | |
694 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_1 dbg_ssupd_reg | |
695 | ( | |
696 | .scan_in(dbg_ssupd_reg_scanin), | |
697 | .scan_out(dbg_ssupd_reg_scanout), | |
698 | .l1clk (l1clk), | |
699 | .en (ss_mode_active), | |
700 | .din (ssreq_upd_sync), | |
701 | .dout (ss_request), | |
702 | .siclk(siclk), | |
703 | .soclk(soclk) | |
704 | ); | |
705 | ||
706 | assign ss_request_pulse = ~ss_request & ssreq_upd_sync; | |
707 | ||
708 | assign singstep_request[7:0] = singstep_mode[7:0] & {8{ss_request_pulse}}; | |
709 | ||
710 | // Outputs to SPC Cores for Single Step | |
711 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_8 dbg_ssmode_reg | |
712 | ( | |
713 | .scan_in(dbg_ssmode_reg_scanin), | |
714 | .scan_out(dbg_ssmode_reg_scanout), | |
715 | .l1clk (l1clk), | |
716 | .en (io_cmp_sync_en_local), | |
717 | .din (singstep_mode[7:0]), | |
718 | .dout (tcu_ss_mode[7:0]), | |
719 | .siclk(siclk), | |
720 | .soclk(soclk) | |
721 | ); | |
722 | tcu_dbg_ctl_msff_ctl_macro__width_8 dbg_ssreq_reg | |
723 | ( | |
724 | .scan_in(dbg_ssreq_reg_scanin), | |
725 | .scan_out(dbg_ssreq_reg_scanout), | |
726 | .l1clk (l1clk), | |
727 | .din (singstep_request[7:0]), | |
728 | .dout (tcu_ss_request[7:0]), | |
729 | .siclk(siclk), | |
730 | .soclk(soclk) | |
731 | ); | |
732 | ||
733 | //******************************************************************** | |
734 | // Disable Overlap Mode | |
735 | //******************************************************************** | |
736 | // disable overlap does not stop clocks to cores | |
737 | assign do_mode_active = doss_mode[1] & ~doss_mode[0]; | |
738 | ||
739 | assign spc_dolap_enab[7:0] = spc_doss_enab[7:0] & {8{do_mode_active}}; | |
740 | ||
741 | assign disbolap_mode[0] = ~spc_crstat[0] ? spc_dolap_enab[0] : tcu_do_mode[0]; | |
742 | assign disbolap_mode[1] = ~spc_crstat[1] ? spc_dolap_enab[1] : tcu_do_mode[1]; | |
743 | assign disbolap_mode[2] = ~spc_crstat[2] ? spc_dolap_enab[2] : tcu_do_mode[2]; | |
744 | assign disbolap_mode[3] = ~spc_crstat[3] ? spc_dolap_enab[3] : tcu_do_mode[3]; | |
745 | assign disbolap_mode[4] = ~spc_crstat[4] ? spc_dolap_enab[4] : tcu_do_mode[4]; | |
746 | assign disbolap_mode[5] = ~spc_crstat[5] ? spc_dolap_enab[5] : tcu_do_mode[5]; | |
747 | assign disbolap_mode[6] = ~spc_crstat[6] ? spc_dolap_enab[6] : tcu_do_mode[6]; | |
748 | assign disbolap_mode[7] = ~spc_crstat[7] ? spc_dolap_enab[7] : tcu_do_mode[7]; | |
749 | ||
750 | // Outputs to SPC Cores for Disable Overlap | |
751 | tcu_dbg_ctl_msff_ctl_macro__clr__1__en_1__width_8 dbg_domode_reg | |
752 | ( | |
753 | .scan_in(dbg_domode_reg_scanin), | |
754 | .scan_out(dbg_domode_reg_scanout), | |
755 | .l1clk (l1clk), | |
756 | .en (io_cmp_sync_en_local), | |
757 | .clr_ (do_mode_active), | |
758 | .din (disbolap_mode[7:0]), | |
759 | .dout (tcu_do_mode[7:0]), | |
760 | .siclk(siclk), | |
761 | .soclk(soclk) | |
762 | ); | |
763 | ||
764 | // Single-step complete status back to JTAG; spc_ss_comp is spc_single-step_complete | |
765 | // Also Disable Overlap Running Status when enabled and counter is done and parked | |
766 | assign doss_stat[0] = (singstep_mode[0] & spc_ss_comp[0]) | (spc_dolap_enab[0] & ~cycle_count_dec & ~spc_crstat[0]); | |
767 | assign doss_stat[1] = (singstep_mode[1] & spc_ss_comp[1]) | (spc_dolap_enab[1] & ~cycle_count_dec & ~spc_crstat[1]); | |
768 | assign doss_stat[2] = (singstep_mode[2] & spc_ss_comp[2]) | (spc_dolap_enab[2] & ~cycle_count_dec & ~spc_crstat[2]); | |
769 | assign doss_stat[3] = (singstep_mode[3] & spc_ss_comp[3]) | (spc_dolap_enab[3] & ~cycle_count_dec & ~spc_crstat[3]); | |
770 | assign doss_stat[4] = (singstep_mode[4] & spc_ss_comp[4]) | (spc_dolap_enab[4] & ~cycle_count_dec & ~spc_crstat[4]); | |
771 | assign doss_stat[5] = (singstep_mode[5] & spc_ss_comp[5]) | (spc_dolap_enab[5] & ~cycle_count_dec & ~spc_crstat[5]); | |
772 | assign doss_stat[6] = (singstep_mode[6] & spc_ss_comp[6]) | (spc_dolap_enab[6] & ~cycle_count_dec & ~spc_crstat[6]); | |
773 | assign doss_stat[7] = (singstep_mode[7] & spc_ss_comp[7]) | (spc_dolap_enab[7] & ~cycle_count_dec & ~spc_crstat[7]); | |
774 | ||
775 | //******************************************************************** | |
776 | // Cycle Step Mode | |
777 | //******************************************************************** | |
778 | tcu_dbg_ctl_msff_ctl_macro__width_1 dbg_cstep_reg | |
779 | ( | |
780 | .scan_in(dbg_cstep_reg_scanin), | |
781 | .scan_out(dbg_cstep_reg_scanout), | |
782 | .l1clk (l1clk), | |
783 | .din (next_cs_mode), | |
784 | .dout (cs_mode), | |
785 | .siclk(siclk), | |
786 | .soclk(soclk) | |
787 | ); | |
788 | ||
789 | assign next_cs_mode = csmode_upd_sync ? csmode | |
790 | : cs_mode; | |
791 | ||
792 | assign cs_mode_active = cycle_count_stop & cs_mode; | |
793 | assign jtagclkstop_ov = ~cycle_count_stop & cs_mode; // overrides jtag clk stop | |
794 | ||
795 | //******************************************************************** | |
796 | // SOC Hard Stop | |
797 | //******************************************************************** | |
798 | // In io_clk domain, synchronize to cmp | |
799 | ||
800 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_1 dbg_sochs_sync_reg | |
801 | ( | |
802 | .scan_in(dbg_sochs_sync_reg_scanin), | |
803 | .scan_out(dbg_sochs_sync_reg_scanout), | |
804 | .l1clk (l1clk), | |
805 | .en (sochs_en), | |
806 | .din (dbg1_tcu_soc_hard_stop), | |
807 | .dout (soc_hard_stop), | |
808 | .siclk(siclk), | |
809 | .soclk(soclk) | |
810 | ); | |
811 | assign sochs_en = io_cmp_sync_en_local & jtscan_off; | |
812 | ||
813 | //******************************************************************** | |
814 | // DBG Generated Trigger Pulse Request | |
815 | //******************************************************************** | |
816 | // From io2x_clk domain, receive with io2x sync enable | |
817 | tcu_dbg_ctl_msff_ctl_macro__en_1__width_1 dbg_trigreq_sync_reg | |
818 | ( | |
819 | .scan_in(dbg_trigreq_sync_reg_scanin), | |
820 | .scan_out(dbg_trigreq_sync_reg_scanout), | |
821 | .l1clk (l1clk), | |
822 | .en (trigreq_en), | |
823 | .din (dbg1_tcu_soc_asrt_trigout), | |
824 | .dout (dbg1_tcu_soc_asrt_trigout_sync), | |
825 | .siclk(siclk), | |
826 | .soclk(soclk) | |
827 | ); | |
828 | assign trigreq_en = io_cmp_sync_en_local & jtscan_off; | |
829 | ||
830 | //******************************************************************** | |
831 | // Trigger In Request from Pins | |
832 | //******************************************************************** | |
833 | // Incoming from MIO, asynchronous | |
834 | cl_sc1_clksyncff_4x dbg_trigin_sync_reg | |
835 | ( | |
836 | .si (dbg_trigin_sync_reg_scanin), | |
837 | .so (dbg_trigin_sync_reg_scanout), | |
838 | .l1clk (l1clk), | |
839 | .d (mio_tcu_trigin_mission), | |
840 | .q (trigin_sync), | |
841 | .siclk(siclk), | |
842 | .soclk(soclk) | |
843 | ); | |
844 | // once it's set, hold the trigger_in and kick off a hard clock stop | |
845 | // - treat as a pulse, it will get held in other logic | |
846 | assign mio_tcu_trigin_mission = mio_tcu_trigin & jtscan_off; | |
847 | ||
848 | // ******************************************************************** | |
849 | // Synchronizer for JTAG Clock Start, from instr_clock_start | |
850 | // ******************************************************************** | |
851 | // This is so a jtag clock start instruction can turn off the debug event | |
852 | // that is active, thus restarting clocks | |
853 | cl_sc1_clksyncff_4x dbg_clkst_sync_reg | |
854 | (.si (dbg_clkst_sync_reg_scanin), | |
855 | .so (dbg_clkst_sync_reg_scanout), | |
856 | .l1clk (l1clk), | |
857 | .d (jtag_clock_start), | |
858 | .q (jtag_clock_start_sync), | |
859 | .siclk(siclk), | |
860 | .soclk(soclk) | |
861 | ); | |
862 | ||
863 | // fixscan start: | |
864 | //assign dbg_cmpiosync_reg_scanin = scan_in ; | |
865 | //assign dbg_cyccnt_reg_scanin = dbg_cmpiosync_reg_scanout; | |
866 | assign dbg_cyccnt_reg_scanin = scan_in ; | |
867 | assign dbg_tcudcr_reg_scanin = dbg_cyccnt_reg_scanout ; | |
868 | assign dbg_decnt_reg_scanin = dbg_tcudcr_reg_scanout ; | |
869 | assign dbg_eventhold_reg_scanin = dbg_decnt_reg_scanout ; | |
870 | assign dbg_sshold_reg_scanin = dbg_eventhold_reg_scanout; | |
871 | assign dbg_trigout_reg_scanin = dbg_sshold_reg_scanout ; | |
872 | assign dbg_cregreq_reg_scanin = dbg_trigout_reg_scanout ; | |
873 | assign dbg_cregreqb_reg_scanin = dbg_cregreq_reg_scanout ; | |
874 | assign dbg_creg_access_reg_scanin = dbg_cregreqb_reg_scanout; | |
875 | assign dbg_ssupd_reg_scanin = dbg_creg_access_reg_scanout; | |
876 | assign dbg_ssmode_reg_scanin = dbg_ssupd_reg_scanout ; | |
877 | assign dbg_ssreq_reg_scanin = dbg_ssmode_reg_scanout ; | |
878 | assign dbg_domode_reg_scanin = dbg_ssreq_reg_scanout ; | |
879 | assign dbg_cstep_reg_scanin = dbg_domode_reg_scanout ; | |
880 | assign dbg_sochs_sync_reg_scanin = dbg_cstep_reg_scanout ; | |
881 | assign dbg_trigreq_sync_reg_scanin = dbg_sochs_sync_reg_scanout; | |
882 | assign dbg_trigin_sync_reg_scanin = dbg_trigreq_sync_reg_scanout; | |
883 | assign dbg_clkst_sync_reg_scanin = dbg_trigin_sync_reg_scanout; | |
884 | assign scan_out = dbg_clkst_sync_reg_scanout; | |
885 | // fixscan end: | |
886 | endmodule | |
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | // any PARAMS parms go into naming of macro | |
894 | ||
895 | module tcu_dbg_ctl_l1clkhdr_ctl_macro ( | |
896 | l2clk, | |
897 | l1en, | |
898 | pce_ov, | |
899 | stop, | |
900 | se, | |
901 | l1clk); | |
902 | ||
903 | ||
904 | input l2clk; | |
905 | input l1en; | |
906 | input pce_ov; | |
907 | input stop; | |
908 | input se; | |
909 | output l1clk; | |
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | cl_sc1_l1hdr_8x c_0 ( | |
916 | ||
917 | ||
918 | .l2clk(l2clk), | |
919 | .pce(l1en), | |
920 | .l1clk(l1clk), | |
921 | .se(se), | |
922 | .pce_ov(pce_ov), | |
923 | .stop(stop) | |
924 | ); | |
925 | ||
926 | ||
927 | ||
928 | endmodule | |
929 | ||
930 | ||
931 | ||
932 | ||
933 | ||
934 | ||
935 | ||
936 | ||
937 | ||
938 | ||
939 | ||
940 | ||
941 | ||
942 | // any PARAMS parms go into naming of macro | |
943 | ||
944 | module tcu_dbg_ctl_msff_ctl_macro__width_64 ( | |
945 | din, | |
946 | l1clk, | |
947 | scan_in, | |
948 | siclk, | |
949 | soclk, | |
950 | dout, | |
951 | scan_out); | |
952 | wire [63:0] fdin; | |
953 | wire [62:0] so; | |
954 | ||
955 | input [63:0] din; | |
956 | input l1clk; | |
957 | input scan_in; | |
958 | ||
959 | ||
960 | input siclk; | |
961 | input soclk; | |
962 | ||
963 | output [63:0] dout; | |
964 | output scan_out; | |
965 | assign fdin[63:0] = din[63:0]; | |
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | dff #(64) d0_0 ( | |
973 | .l1clk(l1clk), | |
974 | .siclk(siclk), | |
975 | .soclk(soclk), | |
976 | .d(fdin[63:0]), | |
977 | .si({scan_in,so[62:0]}), | |
978 | .so({so[62:0],scan_out}), | |
979 | .q(dout[63:0]) | |
980 | ); | |
981 | ||
982 | ||
983 | ||
984 | ||
985 | ||
986 | ||
987 | ||
988 | ||
989 | ||
990 | ||
991 | ||
992 | ||
993 | endmodule | |
994 | ||
995 | ||
996 | ||
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | // any PARAMS parms go into naming of macro | |
1008 | ||
1009 | module tcu_dbg_ctl_msff_ctl_macro__width_4 ( | |
1010 | din, | |
1011 | l1clk, | |
1012 | scan_in, | |
1013 | siclk, | |
1014 | soclk, | |
1015 | dout, | |
1016 | scan_out); | |
1017 | wire [3:0] fdin; | |
1018 | wire [2:0] so; | |
1019 | ||
1020 | input [3:0] din; | |
1021 | input l1clk; | |
1022 | input scan_in; | |
1023 | ||
1024 | ||
1025 | input siclk; | |
1026 | input soclk; | |
1027 | ||
1028 | output [3:0] dout; | |
1029 | output scan_out; | |
1030 | assign fdin[3:0] = din[3:0]; | |
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | ||
1036 | ||
1037 | dff #(4) d0_0 ( | |
1038 | .l1clk(l1clk), | |
1039 | .siclk(siclk), | |
1040 | .soclk(soclk), | |
1041 | .d(fdin[3:0]), | |
1042 | .si({scan_in,so[2:0]}), | |
1043 | .so({so[2:0],scan_out}), | |
1044 | .q(dout[3:0]) | |
1045 | ); | |
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | ||
1057 | ||
1058 | endmodule | |
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | // any PARAMS parms go into naming of macro | |
1073 | ||
1074 | module tcu_dbg_ctl_msff_ctl_macro__width_32 ( | |
1075 | din, | |
1076 | l1clk, | |
1077 | scan_in, | |
1078 | siclk, | |
1079 | soclk, | |
1080 | dout, | |
1081 | scan_out); | |
1082 | wire [31:0] fdin; | |
1083 | wire [30:0] so; | |
1084 | ||
1085 | input [31:0] din; | |
1086 | input l1clk; | |
1087 | input scan_in; | |
1088 | ||
1089 | ||
1090 | input siclk; | |
1091 | input soclk; | |
1092 | ||
1093 | output [31:0] dout; | |
1094 | output scan_out; | |
1095 | assign fdin[31:0] = din[31:0]; | |
1096 | ||
1097 | ||
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | dff #(32) d0_0 ( | |
1103 | .l1clk(l1clk), | |
1104 | .siclk(siclk), | |
1105 | .soclk(soclk), | |
1106 | .d(fdin[31:0]), | |
1107 | .si({scan_in,so[30:0]}), | |
1108 | .so({so[30:0],scan_out}), | |
1109 | .q(dout[31:0]) | |
1110 | ); | |
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | ||
1120 | ||
1121 | ||
1122 | ||
1123 | endmodule | |
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | // any PARAMS parms go into naming of macro | |
1138 | ||
1139 | module tcu_dbg_ctl_msff_ctl_macro__en_1__width_4 ( | |
1140 | din, | |
1141 | en, | |
1142 | l1clk, | |
1143 | scan_in, | |
1144 | siclk, | |
1145 | soclk, | |
1146 | dout, | |
1147 | scan_out); | |
1148 | wire [3:0] fdin; | |
1149 | wire [2:0] so; | |
1150 | ||
1151 | input [3:0] din; | |
1152 | input en; | |
1153 | input l1clk; | |
1154 | input scan_in; | |
1155 | ||
1156 | ||
1157 | input siclk; | |
1158 | input soclk; | |
1159 | ||
1160 | output [3:0] dout; | |
1161 | output scan_out; | |
1162 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | dff #(4) d0_0 ( | |
1170 | .l1clk(l1clk), | |
1171 | .siclk(siclk), | |
1172 | .soclk(soclk), | |
1173 | .d(fdin[3:0]), | |
1174 | .si({scan_in,so[2:0]}), | |
1175 | .so({so[2:0],scan_out}), | |
1176 | .q(dout[3:0]) | |
1177 | ); | |
1178 | ||
1179 | ||
1180 | ||
1181 | ||
1182 | ||
1183 | ||
1184 | ||
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | endmodule | |
1191 | ||
1192 | ||
1193 | ||
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | // any PARAMS parms go into naming of macro | |
1205 | ||
1206 | module tcu_dbg_ctl_msff_ctl_macro__en_1__width_8 ( | |
1207 | din, | |
1208 | en, | |
1209 | l1clk, | |
1210 | scan_in, | |
1211 | siclk, | |
1212 | soclk, | |
1213 | dout, | |
1214 | scan_out); | |
1215 | wire [7:0] fdin; | |
1216 | wire [6:0] so; | |
1217 | ||
1218 | input [7:0] din; | |
1219 | input en; | |
1220 | input l1clk; | |
1221 | input scan_in; | |
1222 | ||
1223 | ||
1224 | input siclk; | |
1225 | input soclk; | |
1226 | ||
1227 | output [7:0] dout; | |
1228 | output scan_out; | |
1229 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | ||
1236 | dff #(8) d0_0 ( | |
1237 | .l1clk(l1clk), | |
1238 | .siclk(siclk), | |
1239 | .soclk(soclk), | |
1240 | .d(fdin[7:0]), | |
1241 | .si({scan_in,so[6:0]}), | |
1242 | .so({so[6:0],scan_out}), | |
1243 | .q(dout[7:0]) | |
1244 | ); | |
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | ||
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | ||
1257 | endmodule | |
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | // any PARAMS parms go into naming of macro | |
1272 | ||
1273 | module tcu_dbg_ctl_msff_ctl_macro__en_1__width_2 ( | |
1274 | din, | |
1275 | en, | |
1276 | l1clk, | |
1277 | scan_in, | |
1278 | siclk, | |
1279 | soclk, | |
1280 | dout, | |
1281 | scan_out); | |
1282 | wire [1:0] fdin; | |
1283 | wire [0:0] so; | |
1284 | ||
1285 | input [1:0] din; | |
1286 | input en; | |
1287 | input l1clk; | |
1288 | input scan_in; | |
1289 | ||
1290 | ||
1291 | input siclk; | |
1292 | input soclk; | |
1293 | ||
1294 | output [1:0] dout; | |
1295 | output scan_out; | |
1296 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
1297 | ||
1298 | ||
1299 | ||
1300 | ||
1301 | ||
1302 | ||
1303 | dff #(2) d0_0 ( | |
1304 | .l1clk(l1clk), | |
1305 | .siclk(siclk), | |
1306 | .soclk(soclk), | |
1307 | .d(fdin[1:0]), | |
1308 | .si({scan_in,so[0:0]}), | |
1309 | .so({so[0:0],scan_out}), | |
1310 | .q(dout[1:0]) | |
1311 | ); | |
1312 | ||
1313 | ||
1314 | ||
1315 | ||
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | endmodule | |
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | // any PARAMS parms go into naming of macro | |
1339 | ||
1340 | module tcu_dbg_ctl_msff_ctl_macro__en_1__width_1 ( | |
1341 | din, | |
1342 | en, | |
1343 | l1clk, | |
1344 | scan_in, | |
1345 | siclk, | |
1346 | soclk, | |
1347 | dout, | |
1348 | scan_out); | |
1349 | wire [0:0] fdin; | |
1350 | ||
1351 | input [0:0] din; | |
1352 | input en; | |
1353 | input l1clk; | |
1354 | input scan_in; | |
1355 | ||
1356 | ||
1357 | input siclk; | |
1358 | input soclk; | |
1359 | ||
1360 | output [0:0] dout; | |
1361 | output scan_out; | |
1362 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | dff #(1) d0_0 ( | |
1370 | .l1clk(l1clk), | |
1371 | .siclk(siclk), | |
1372 | .soclk(soclk), | |
1373 | .d(fdin[0:0]), | |
1374 | .si(scan_in), | |
1375 | .so(scan_out), | |
1376 | .q(dout[0:0]) | |
1377 | ); | |
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | ||
1389 | ||
1390 | endmodule | |
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | // any PARAMS parms go into naming of macro | |
1405 | ||
1406 | module tcu_dbg_ctl_msff_ctl_macro__width_8 ( | |
1407 | din, | |
1408 | l1clk, | |
1409 | scan_in, | |
1410 | siclk, | |
1411 | soclk, | |
1412 | dout, | |
1413 | scan_out); | |
1414 | wire [7:0] fdin; | |
1415 | wire [6:0] so; | |
1416 | ||
1417 | input [7:0] din; | |
1418 | input l1clk; | |
1419 | input scan_in; | |
1420 | ||
1421 | ||
1422 | input siclk; | |
1423 | input soclk; | |
1424 | ||
1425 | output [7:0] dout; | |
1426 | output scan_out; | |
1427 | assign fdin[7:0] = din[7:0]; | |
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | dff #(8) d0_0 ( | |
1435 | .l1clk(l1clk), | |
1436 | .siclk(siclk), | |
1437 | .soclk(soclk), | |
1438 | .d(fdin[7:0]), | |
1439 | .si({scan_in,so[6:0]}), | |
1440 | .so({so[6:0],scan_out}), | |
1441 | .q(dout[7:0]) | |
1442 | ); | |
1443 | ||
1444 | ||
1445 | ||
1446 | ||
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | endmodule | |
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | // any PARAMS parms go into naming of macro | |
1470 | ||
1471 | module tcu_dbg_ctl_msff_ctl_macro__clr__1__en_1__width_8 ( | |
1472 | din, | |
1473 | en, | |
1474 | clr_, | |
1475 | l1clk, | |
1476 | scan_in, | |
1477 | siclk, | |
1478 | soclk, | |
1479 | dout, | |
1480 | scan_out); | |
1481 | wire [7:0] fdin; | |
1482 | wire [6:0] so; | |
1483 | ||
1484 | input [7:0] din; | |
1485 | input en; | |
1486 | input clr_; | |
1487 | input l1clk; | |
1488 | input scan_in; | |
1489 | ||
1490 | ||
1491 | input siclk; | |
1492 | input soclk; | |
1493 | ||
1494 | output [7:0] dout; | |
1495 | output scan_out; | |
1496 | assign fdin[7:0] = (din[7:0] & {8{en}} & ~{8{(~clr_)}}) | (dout[7:0] & ~{8{en}} & ~{8{(~clr_)}}); | |
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | dff #(8) d0_0 ( | |
1504 | .l1clk(l1clk), | |
1505 | .siclk(siclk), | |
1506 | .soclk(soclk), | |
1507 | .d(fdin[7:0]), | |
1508 | .si({scan_in,so[6:0]}), | |
1509 | .so({so[6:0],scan_out}), | |
1510 | .q(dout[7:0]) | |
1511 | ); | |
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | endmodule | |
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | // any PARAMS parms go into naming of macro | |
1539 | ||
1540 | module tcu_dbg_ctl_msff_ctl_macro__width_1 ( | |
1541 | din, | |
1542 | l1clk, | |
1543 | scan_in, | |
1544 | siclk, | |
1545 | soclk, | |
1546 | dout, | |
1547 | scan_out); | |
1548 | wire [0:0] fdin; | |
1549 | ||
1550 | input [0:0] din; | |
1551 | input l1clk; | |
1552 | input scan_in; | |
1553 | ||
1554 | ||
1555 | input siclk; | |
1556 | input soclk; | |
1557 | ||
1558 | output [0:0] dout; | |
1559 | output scan_out; | |
1560 | assign fdin[0:0] = din[0:0]; | |
1561 | ||
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | ||
1567 | dff #(1) d0_0 ( | |
1568 | .l1clk(l1clk), | |
1569 | .siclk(siclk), | |
1570 | .soclk(soclk), | |
1571 | .d(fdin[0:0]), | |
1572 | .si(scan_in), | |
1573 | .so(scan_out), | |
1574 | .q(dout[0:0]) | |
1575 | ); | |
1576 | ||
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | endmodule | |
1589 | ||
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | ||
1596 |