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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu_regs_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define CNT_ADDR_HI 14 | |
36 | `define CNT_ADDR_LO 12 | |
37 | `define IAB_ADDR_HI 11 | |
38 | `define IAB_ADDR_LO 9 | |
39 | `define DAB_ADDR_HI 8 | |
40 | `define DAB_ADDR_LO 6 | |
41 | `define EXT_ADDR_HI 5 | |
42 | `define EXT_ADDR_LO 3 | |
43 | `define AE_ADDR_HI 2 | |
44 | `define AE_ADDR_LO 0 | |
45 | ||
46 | //debug event codes | |
47 | `define WATCH_POINT 2'b00 | |
48 | `define HARD_STOP 2'b01 | |
49 | `define SOFT_STOP 2'b10 | |
50 | `define START_COUNT 2'b11 | |
51 | ||
52 | //debug event status bit location | |
53 | `define CNT 4 | |
54 | `define IAB 3 | |
55 | `define DAB 2 | |
56 | `define EXT 1 | |
57 | `define AE 0 | |
58 | ||
59 | // UCB defines, copied from Niagara iop/include/sys.h or iop.h | |
60 | `define UCB_BUF_HI 11 // (2) buffer ID | |
61 | `define UCB_BUF_LO 10 | |
62 | `define UCB_THR_HI 9 // (6) cpu/thread ID | |
63 | `define UCB_THR_LO 4 | |
64 | `define UCB_DATA_HI 127 // (64) data | |
65 | `define UCB_DATA_LO 64 | |
66 | `define UCB_PKT_HI 3 // (4) packet type | |
67 | `define UCB_PKT_LO 0 | |
68 | `define UCB_READ_ACK 4'b0001 | |
69 | `define UCB_READ_REQ 4'b0100 // req types | |
70 | `define UCB_WRITE_ACK 4'b0010 | |
71 | `define UCB_WRITE_REQ 4'b0101 | |
72 | `define UCB_SIZE_HI 14 // (3) request size | |
73 | `define UCB_SIZE_LO 12 | |
74 | `define UCB_BID_TAP 2'b01 | |
75 | `define UCB_ADDR_HI 54 // (40) bit address | |
76 | `define UCB_ADDR_LO 15 | |
77 | `define PCX_SZ_8B 3'b011 // encoding for 8B access | |
78 | ||
79 | // MBIST Defines | |
80 | `define NUM_TOTAL_MBIST_M1 47 | |
81 | `define NUM_TOTAL_MBIST 48 | |
82 | ||
83 | `define NUM_TOTAL_LBIST 8 | |
84 | `define NUM_TOTAL_LBIST_M1 7 | |
85 | ||
86 | `define MBIST_IDLE 4'd0 | |
87 | `define POR_CLR_DF 4'd1 | |
88 | `define POR_START 4'd2 | |
89 | `define POR_CLR_START 4'd3 | |
90 | `define POR_END_WAIT 4'd4 | |
91 | `define WMR_DUMMY 4'd5 | |
92 | `define WMR_CLR_DF 4'd6 | |
93 | `define WMR_START 4'd7 | |
94 | `define WMR_CLR_START 4'd8 | |
95 | `define WMR_END_WAIT 4'd9 | |
96 | `define BISX_CLR_DF 4'd10 | |
97 | `define BISX_START 4'd11 | |
98 | `define BISX_CLR_START 4'd12 | |
99 | ||
100 | ||
101 | module tcu_regs_ctl ( | |
102 | debug_event_stop, | |
103 | l2clk, | |
104 | tcu_int_aclk, | |
105 | tcu_int_bclk, | |
106 | tcu_int_se, | |
107 | tcu_int_ce, | |
108 | tcu_int_ce_to_ucb, | |
109 | tcu_int_ce_ucb, | |
110 | tcu_pce_ov, | |
111 | ac_test_mode, | |
112 | cmp_io_sync_en, | |
113 | io_cmp_sync_en, | |
114 | cmp_io2x_sync_en, | |
115 | ac_trans_test_counter_start, | |
116 | jtag_clock_start, | |
117 | clock_domain, | |
118 | clock_domain_upd, | |
119 | core_sel, | |
120 | core_sel_upd, | |
121 | decnt_data, | |
122 | decnt_upd, | |
123 | de_count, | |
124 | cyc_count, | |
125 | cyc_count_upd, | |
126 | cycle_count, | |
127 | tcudcr_data, | |
128 | tcudcr_upd, | |
129 | tcu_dcr, | |
130 | dossen, | |
131 | dossen_upd, | |
132 | doss_enab, | |
133 | dossmode, | |
134 | dossmode_upd, | |
135 | doss_mode, | |
136 | ssreq_upd, | |
137 | csmode, | |
138 | csmode_upd, | |
139 | cs_mode, | |
140 | cs_mode_active, | |
141 | jtagclkstop_ov, | |
142 | jtag_ser_scan_q, | |
143 | jtag_mt_enable, | |
144 | jtag_test_protect, | |
145 | flush_test_protect, | |
146 | tcu_tp_sync_2io, | |
147 | mt_mode_sync, | |
148 | rst_tcu_dbr_gen, | |
149 | tcu_dbr_gateoff, | |
150 | cycle_stretch_to_mbc, | |
151 | spc_crs, | |
152 | doss_stat, | |
153 | dbg1_tcu_soc_hard_stop, | |
154 | spc0_hardstop_request, | |
155 | spc1_hardstop_request, | |
156 | spc2_hardstop_request, | |
157 | spc3_hardstop_request, | |
158 | spc4_hardstop_request, | |
159 | spc5_hardstop_request, | |
160 | spc6_hardstop_request, | |
161 | spc7_hardstop_request, | |
162 | clk_stop_ac_trans_counter_initiated, | |
163 | debug_reg_hard_stop_domain_1st, | |
164 | debug_cycle_counter_stop_to_mbc, | |
165 | spc0_ss_complete, | |
166 | spc1_ss_complete, | |
167 | spc2_ss_complete, | |
168 | spc3_ss_complete, | |
169 | spc4_ss_complete, | |
170 | spc5_ss_complete, | |
171 | spc6_ss_complete, | |
172 | spc7_ss_complete, | |
173 | tcu_ss_request, | |
174 | tcu_do_mode, | |
175 | tcu_ss_mode, | |
176 | spc0_softstop_request, | |
177 | spc1_softstop_request, | |
178 | spc2_softstop_request, | |
179 | spc3_softstop_request, | |
180 | spc4_softstop_request, | |
181 | spc5_softstop_request, | |
182 | spc6_softstop_request, | |
183 | spc7_softstop_request, | |
184 | spc0_ncu_core_running_status, | |
185 | spc1_ncu_core_running_status, | |
186 | spc2_ncu_core_running_status, | |
187 | spc3_ncu_core_running_status, | |
188 | spc4_ncu_core_running_status, | |
189 | spc5_ncu_core_running_status, | |
190 | spc6_ncu_core_running_status, | |
191 | spc7_ncu_core_running_status, | |
192 | spc0_trigger_pulse, | |
193 | spc1_trigger_pulse, | |
194 | spc2_trigger_pulse, | |
195 | spc3_trigger_pulse, | |
196 | spc4_trigger_pulse, | |
197 | spc5_trigger_pulse, | |
198 | spc6_trigger_pulse, | |
199 | spc7_trigger_pulse, | |
200 | dbg_creg_access, | |
201 | dbg_creg_addr, | |
202 | dbg_creg_data, | |
203 | dbg_creg_wr_en, | |
204 | dbg_creg_addr_en, | |
205 | dbg_creg_data_en, | |
206 | spc_ss_mode, | |
207 | spc_ss_sel, | |
208 | dbg1_tcu_soc_asrt_trigout, | |
209 | tcu_mio_trigout, | |
210 | mio_tcu_trigin, | |
211 | tcu_rst_flush_stop_ack, | |
212 | wmr_two, | |
213 | mbist_clk_stop_req, | |
214 | mbist_clk_stop_to_mbc, | |
215 | scan_in, | |
216 | scan_out, | |
217 | l2data_upd, | |
218 | l2addr_upd, | |
219 | l2rti, | |
220 | instr_l2_wr, | |
221 | instr_l2_rd, | |
222 | sio_tcu_data, | |
223 | sio_tcu_vld, | |
224 | l2access, | |
225 | tcu_sii_data, | |
226 | tcu_sii_vld, | |
227 | l2rddata, | |
228 | l2_read_vld, | |
229 | ucb_csr_wr, | |
230 | ucb_csr_addr, | |
231 | ucb_data_out); | |
232 | wire l1en; | |
233 | wire pce_ov; | |
234 | wire stop; | |
235 | wire se; | |
236 | wire siclk; | |
237 | wire soclk; | |
238 | wire l1clk; | |
239 | wire tcuregs_cmpiosync_reg_scanin; | |
240 | wire tcuregs_cmpiosync_reg_scanout; | |
241 | wire io_cmp_sync_en_local; | |
242 | wire cmp_io_sync_en_local; | |
243 | wire cmp_io2x_sync_en_local; | |
244 | wire ucb_csr_wr_sync_reg_scanin; | |
245 | wire ucb_csr_wr_sync_reg_scanout; | |
246 | wire ucb_csr_wr_sync; | |
247 | wire ac_test_muxed_clk_qual; | |
248 | wire ac_trans_test_counter_stop; | |
249 | wire tcuregs_ttcounter_reg_scanin; | |
250 | wire tcuregs_ttcounter_reg_scanout; | |
251 | wire [7:0] tt_count; | |
252 | wire [7:0] tt_count_dout; | |
253 | wire tt_start_d; | |
254 | wire tcuregs_ttstart_reg_scanin; | |
255 | wire tcuregs_ttstart_reg_scanout; | |
256 | wire ucb_wr_clk_domain; | |
257 | wire ff_debug_event_hard_stop_scanin; | |
258 | wire ff_debug_event_hard_stop_scanout; | |
259 | wire [23:0] clk_stop_domain; | |
260 | wire clock_domain_upd_sync; | |
261 | wire dbg_upd_clock_domain; | |
262 | wire [23:0] clock_domain_data; | |
263 | wire rst_upd_clock_domain; | |
264 | wire reset_event; | |
265 | wire tcu_dcr_en; | |
266 | wire clk_stop_dom_zero; | |
267 | wire rstend_reg_scanin; | |
268 | wire rstend_reg_scanout; | |
269 | wire rst_event; | |
270 | wire end_of_reset; | |
271 | wire wmr_two_d; | |
272 | wire [5:0] spc_hs_req_stg_din; | |
273 | wire spc7_hstop_req; | |
274 | wire spc6_hstop_req; | |
275 | wire spc5_hstop_req; | |
276 | wire spc4_hstop_req; | |
277 | wire spc3_hstop_req; | |
278 | wire spc1_hstop_req; | |
279 | wire spc_hs_req_stg_reg_scanin; | |
280 | wire spc_hs_req_stg_reg_scanout; | |
281 | wire [5:0] spc_hs_req_stg; | |
282 | wire [7:0] spc_hs_req; | |
283 | wire spc2_hstop_req; | |
284 | wire spc0_hstop_req; | |
285 | wire spchsreq_reg_scanin; | |
286 | wire spchsreq_reg_scanout; | |
287 | wire spchsreq_en; | |
288 | wire [7:0] spc_hstop_req; | |
289 | wire jtscan_off; | |
290 | wire dossen_reg_scanin; | |
291 | wire dossen_reg_scanout; | |
292 | wire [63:0] next_doss_enab; | |
293 | wire dossen_upd_sync; | |
294 | wire spc0_doss_enab; | |
295 | wire spc1_doss_enab; | |
296 | wire spc2_doss_enab; | |
297 | wire spc3_doss_enab; | |
298 | wire spc4_doss_enab; | |
299 | wire spc5_doss_enab; | |
300 | wire spc6_doss_enab; | |
301 | wire spc7_doss_enab; | |
302 | wire [7:0] spc_doss_enab; | |
303 | wire dossmode_reg_scanin; | |
304 | wire dossmode_reg_scanout; | |
305 | wire [1:0] next_doss_mode; | |
306 | wire dossmode_upd_sync; | |
307 | wire [5:0] spc_ss_complete_stg_din; | |
308 | wire spc_ss_complete_stg_reg_scanin; | |
309 | wire spc_ss_complete_stg_reg_scanout; | |
310 | wire [5:0] spc_ss_complete_stg; | |
311 | wire [7:0] spc_ss_complete; | |
312 | wire spcsscomp_reg_scanin; | |
313 | wire spcsscomp_reg_scanout; | |
314 | wire spc_ss_en; | |
315 | wire [7:0] spc_ss_comp_hld; | |
316 | wire [7:0] spc_ss_comp; | |
317 | wire [7:0] spc_ss_comp_din; | |
318 | wire [5:0] spc_ss_req_stg_din; | |
319 | wire spc7_sstop_req; | |
320 | wire spc6_sstop_req; | |
321 | wire spc5_sstop_req; | |
322 | wire spc4_sstop_req; | |
323 | wire spc3_sstop_req; | |
324 | wire spc1_sstop_req; | |
325 | wire spc_ss_req_stg_reg_scanin; | |
326 | wire spc_ss_req_stg_reg_scanout; | |
327 | wire [5:0] spc_ss_req_stg; | |
328 | wire [7:0] spc_ss_req; | |
329 | wire spc2_sstop_req; | |
330 | wire spc0_sstop_req; | |
331 | wire spcssreq_reg_scanin; | |
332 | wire spcssreq_reg_scanout; | |
333 | wire spcssreq_en; | |
334 | wire [7:0] spc_sstop_req; | |
335 | wire [63:0] spc_crunstat; | |
336 | wire spcrstat_reg_scanin; | |
337 | wire spcrstat_reg_scanout; | |
338 | wire spccrs_en; | |
339 | wire spc0_crunstat; | |
340 | wire spc1_crunstat; | |
341 | wire spc2_crunstat; | |
342 | wire spc3_crunstat; | |
343 | wire spc4_crunstat; | |
344 | wire spc5_crunstat; | |
345 | wire spc6_crunstat; | |
346 | wire spc7_crunstat; | |
347 | wire [7:0] spc_crstat; | |
348 | wire [5:0] spc_tp_req_stg_din; | |
349 | wire spc7_tp_req; | |
350 | wire spc6_tp_req; | |
351 | wire spc5_tp_req; | |
352 | wire spc4_tp_req; | |
353 | wire spc3_tp_req; | |
354 | wire spc1_tp_req; | |
355 | wire spc_tp_req_stg_reg_scanin; | |
356 | wire spc_tp_req_stg_reg_scanout; | |
357 | wire [5:0] spc_tp_req_stg; | |
358 | wire [7:0] spc_tp_req; | |
359 | wire spc2_tp_req; | |
360 | wire spc0_tp_req; | |
361 | wire spctp_reg_scanin; | |
362 | wire spctp_reg_scanout; | |
363 | wire spctpreq_en; | |
364 | wire [7:0] spc_tp; | |
365 | wire trigout_pulse; | |
366 | wire clkdomain_upd_sync_reg_scanin; | |
367 | wire clkdomain_upd_sync_reg_scanout; | |
368 | wire coresel_upd_sync_reg_scanin; | |
369 | wire coresel_upd_sync_reg_scanout; | |
370 | wire core_sel_upd_sync; | |
371 | wire decnt_upd_sync_reg_scanin; | |
372 | wire decnt_upd_sync_reg_scanout; | |
373 | wire decnt_upd_sync; | |
374 | wire cyccnt_upd_sync_reg_scanin; | |
375 | wire cyccnt_upd_sync_reg_scanout; | |
376 | wire cyc_count_upd_sync; | |
377 | wire tcudcr_upd_sync_reg_scanin; | |
378 | wire tcudcr_upd_sync_reg_scanout; | |
379 | wire tcudcr_upd_sync; | |
380 | wire dossen_upd_sync_reg_scanin; | |
381 | wire dossen_upd_sync_reg_scanout; | |
382 | wire dossmode_upd_sync_reg_scanin; | |
383 | wire dossmode_upd_sync_reg_scanout; | |
384 | wire ssreq_upd_sync_reg_scanin; | |
385 | wire ssreq_upd_sync_reg_scanout; | |
386 | wire ssreq_upd_sync; | |
387 | wire csmode_upd_sync_reg_scanin; | |
388 | wire csmode_upd_sync_reg_scanout; | |
389 | wire csmode_upd_sync; | |
390 | wire jtagserscan_sync_reg_scanin; | |
391 | wire jtagserscan_sync_reg_scanout; | |
392 | wire jtag_ser_scan_sync; | |
393 | wire testprotect_sync_reg_scanin; | |
394 | wire testprotect_sync_reg_scanout; | |
395 | wire jtag_test_protect_sync; | |
396 | wire test_protect; | |
397 | wire dbr_gateoff; | |
398 | wire testprotect_reg_scanin; | |
399 | wire testprotect_reg_scanout; | |
400 | wire test_protect_en; | |
401 | wire test_protect_sync_to_io; | |
402 | wire mt_mode; | |
403 | wire tcuregs_mtmode_syncreg_scanin; | |
404 | wire tcuregs_mtmode_syncreg_scanout; | |
405 | wire jtagclkstop_ov_d; | |
406 | wire tcu_dbg_ctl_scan_in; | |
407 | wire tcu_dbg_ctl_scan_out; | |
408 | wire tcuregs_l2dataupd_syncreg_scanin; | |
409 | wire tcuregs_l2dataupd_syncreg_scanout; | |
410 | wire l2data_upd_sync; | |
411 | wire tcuregs_l2addrupd_syncreg_scanin; | |
412 | wire tcuregs_l2addrupd_syncreg_scanout; | |
413 | wire l2addr_upd_sync; | |
414 | wire tcuregs_l2rti_syncreg_scanin; | |
415 | wire tcuregs_l2rti_syncreg_scanout; | |
416 | wire l2rti_sync; | |
417 | wire tcuregs_l2rd_syncreg_scanin; | |
418 | wire tcuregs_l2rd_syncreg_scanout; | |
419 | wire instr_l2_rd_sync; | |
420 | wire tcuregs_l2wr_syncreg_scanin; | |
421 | wire tcuregs_l2wr_syncreg_scanout; | |
422 | wire instr_l2_wr_sync; | |
423 | wire tcuregs_l2data_reg_scanin; | |
424 | wire tcuregs_l2data_reg_scanout; | |
425 | wire [63:0] next_l2data_reg; | |
426 | wire [63:0] l2data_reg; | |
427 | wire l2wrdata_shift; | |
428 | wire l2rddata_shift; | |
429 | wire l2addr_shift; | |
430 | wire l2_read_start; | |
431 | wire l2cnt_done; | |
432 | wire tcuregs_l2addr_reg_scanin; | |
433 | wire tcuregs_l2addr_reg_scanout; | |
434 | wire [63:0] next_l2addr_reg; | |
435 | wire [63:0] l2addr_reg; | |
436 | wire tcu_sii_data_din; | |
437 | wire tcuregs_tcu_sii_data_reg_scanin; | |
438 | wire tcuregs_tcu_sii_data_reg_scanout; | |
439 | wire [6:0] l2cnt; | |
440 | wire tcuregs_l2rti_reg_scanin; | |
441 | wire tcuregs_l2rti_reg_scanout; | |
442 | wire l2rti_dly; | |
443 | wire tcu_sii_vld_din; | |
444 | wire tcuregs_tcu_sii_vld_reg_scanin; | |
445 | wire tcuregs_tcu_sii_vld_reg_scanout; | |
446 | wire tcuregs_l2siovld_reg_scanin; | |
447 | wire tcuregs_l2siovld_reg_scanout; | |
448 | wire tcuregs_l2cntr_reg_scanin; | |
449 | wire tcuregs_l2cntr_reg_scanout; | |
450 | wire l2cnt_clr_; | |
451 | wire [6:0] new_l2cnt; | |
452 | wire l2cnt_en; | |
453 | wire l2cnt_max; | |
454 | wire spare_flops_scanin; | |
455 | wire spare_flops_scanout; | |
456 | wire [8:0] spare_flops_d; | |
457 | wire [8:0] spare_flops_q; | |
458 | wire spare6_flop_d; | |
459 | wire spare4_flop_d; | |
460 | wire [8:0] spare_flops_unused; | |
461 | wire spare6_flop_q; | |
462 | wire spare4_flop_q; | |
463 | ||
464 | output debug_event_stop; assign debug_event_stop = 1'b0; // to be removed | |
465 | input l2clk; | |
466 | input tcu_int_aclk; | |
467 | input tcu_int_bclk; | |
468 | input tcu_int_se; | |
469 | input tcu_int_ce; | |
470 | input tcu_int_ce_to_ucb; // for timing ECO A | |
471 | output tcu_int_ce_ucb; // for timing ECO A | |
472 | input tcu_pce_ov; | |
473 | //input io_test_mode; | |
474 | //input io_ac_test_mode; | |
475 | input ac_test_mode; | |
476 | input cmp_io_sync_en; | |
477 | input io_cmp_sync_en; | |
478 | input cmp_io2x_sync_en; | |
479 | input ac_trans_test_counter_start; | |
480 | ||
481 | // from JTAG | |
482 | input jtag_clock_start; | |
483 | ||
484 | input [23:0] clock_domain; | |
485 | input clock_domain_upd; | |
486 | input [7:0] core_sel; | |
487 | input core_sel_upd; | |
488 | ||
489 | input [31:0] decnt_data; | |
490 | input decnt_upd; | |
491 | output [31:0] de_count; | |
492 | ||
493 | input [63:0] cyc_count; | |
494 | input cyc_count_upd; | |
495 | output [63:0] cycle_count; | |
496 | ||
497 | input [3:0] tcudcr_data; | |
498 | input tcudcr_upd; | |
499 | output [3:0] tcu_dcr; | |
500 | ||
501 | input [63:0] dossen; | |
502 | input dossen_upd; | |
503 | output [63:0] doss_enab; | |
504 | ||
505 | input [1:0] dossmode; | |
506 | input dossmode_upd; | |
507 | output [1:0] doss_mode; | |
508 | ||
509 | input ssreq_upd; | |
510 | ||
511 | input csmode; | |
512 | input csmode_upd; | |
513 | output cs_mode; | |
514 | output cs_mode_active; | |
515 | output jtagclkstop_ov; | |
516 | ||
517 | // test protect goes to live blocks to gate off | |
518 | // unwanted activity during test modes and scan flush | |
519 | input jtag_ser_scan_q; // during jtag scan // ECO yyyyyy | |
520 | input jtag_mt_enable; // during macrotest | |
521 | input jtag_test_protect; // when set via jtag | |
522 | input flush_test_protect; // during scan flush | |
523 | output tcu_tp_sync_2io; | |
524 | output mt_mode_sync; // synchronized macrotest mode signal | |
525 | // and during debug reset to block outputs of blocks | |
526 | // that can interfere with debug reset | |
527 | input rst_tcu_dbr_gen; // during debug reset | |
528 | output tcu_dbr_gateoff; | |
529 | ||
530 | // Cycle Stretch | |
531 | output cycle_stretch_to_mbc; // ECO D | |
532 | ||
533 | // To JTAG | |
534 | output [63:0] spc_crs; // core_run status | |
535 | output [7:0] doss_stat; | |
536 | ||
537 | // Hard Stop from SOC | |
538 | input dbg1_tcu_soc_hard_stop; | |
539 | ||
540 | // Debug Event Requests from SPC Cores | |
541 | input spc0_hardstop_request; | |
542 | input spc1_hardstop_request; | |
543 | input spc2_hardstop_request; | |
544 | input spc3_hardstop_request; | |
545 | input spc4_hardstop_request; | |
546 | input spc5_hardstop_request; | |
547 | input spc6_hardstop_request; | |
548 | input spc7_hardstop_request; | |
549 | ||
550 | output clk_stop_ac_trans_counter_initiated; | |
551 | output [23:0] debug_reg_hard_stop_domain_1st; | |
552 | output debug_cycle_counter_stop_to_mbc; // ECO C | |
553 | ||
554 | input spc0_ss_complete; | |
555 | input spc1_ss_complete; | |
556 | input spc2_ss_complete; | |
557 | input spc3_ss_complete; | |
558 | input spc4_ss_complete; | |
559 | input spc5_ss_complete; | |
560 | input spc6_ss_complete; | |
561 | input spc7_ss_complete; | |
562 | ||
563 | // To SPC Cores: Single Step and Disable Overlap | |
564 | output [7:0] tcu_ss_request; // pulse | |
565 | output [7:0] tcu_do_mode; | |
566 | output [7:0] tcu_ss_mode; | |
567 | ||
568 | input spc0_softstop_request; | |
569 | input spc1_softstop_request; | |
570 | input spc2_softstop_request; | |
571 | input spc3_softstop_request; | |
572 | input spc4_softstop_request; | |
573 | input spc5_softstop_request; | |
574 | input spc6_softstop_request; | |
575 | input spc7_softstop_request; | |
576 | ||
577 | input [7:0] spc0_ncu_core_running_status; | |
578 | input [7:0] spc1_ncu_core_running_status; | |
579 | input [7:0] spc2_ncu_core_running_status; | |
580 | input [7:0] spc3_ncu_core_running_status; | |
581 | input [7:0] spc4_ncu_core_running_status; | |
582 | input [7:0] spc5_ncu_core_running_status; | |
583 | input [7:0] spc6_ncu_core_running_status; | |
584 | input [7:0] spc7_ncu_core_running_status; | |
585 | ||
586 | input spc0_trigger_pulse; | |
587 | input spc1_trigger_pulse; | |
588 | input spc2_trigger_pulse; | |
589 | input spc3_trigger_pulse; | |
590 | input spc4_trigger_pulse; | |
591 | input spc5_trigger_pulse; | |
592 | input spc6_trigger_pulse; | |
593 | input spc7_trigger_pulse; | |
594 | ||
595 | // Interface to UCB Control for parking cores | |
596 | output dbg_creg_access; | |
597 | output [39:0] dbg_creg_addr; | |
598 | output [63:0] dbg_creg_data; | |
599 | output dbg_creg_wr_en; | |
600 | output dbg_creg_addr_en; | |
601 | output dbg_creg_data_en; | |
602 | ||
603 | output spc_ss_mode; | |
604 | output [7:0] spc_ss_sel; | |
605 | ||
606 | // Watchpoint Trigger | |
607 | input dbg1_tcu_soc_asrt_trigout; | |
608 | output tcu_mio_trigout; // to TRIGOUT package pin | |
609 | ||
610 | // Trigger Input from Pin | |
611 | input mio_tcu_trigin; | |
612 | ||
613 | // End of Power-on Reset as a Debug Event | |
614 | input tcu_rst_flush_stop_ack; | |
615 | input wmr_two; | |
616 | ||
617 | // MBIST Clock Stop | |
618 | input mbist_clk_stop_req; | |
619 | output mbist_clk_stop_to_mbc; // ECO C | |
620 | ||
621 | //scan | |
622 | input scan_in; | |
623 | output scan_out; | |
624 | ||
625 | // SIU Interface (L2 Access) | |
626 | input l2data_upd; | |
627 | input l2addr_upd; | |
628 | input l2rti; | |
629 | input instr_l2_wr; | |
630 | input instr_l2_rd; | |
631 | input sio_tcu_data; | |
632 | input sio_tcu_vld; | |
633 | input [64:0] l2access; // bit 0 is ignored | |
634 | output tcu_sii_data; | |
635 | output tcu_sii_vld; | |
636 | output [63:0] l2rddata; | |
637 | output l2_read_vld; | |
638 | ||
639 | // CSR (mbist_ctl) | |
640 | input ucb_csr_wr; | |
641 | input [5:0] ucb_csr_addr; | |
642 | input [63:0] ucb_data_out; | |
643 | ||
644 | // Scan reassigns | |
645 | assign l1en = tcu_int_ce; // 1'b1; | |
646 | assign pce_ov = tcu_pce_ov; // 1'b1; | |
647 | assign stop = 1'b0; | |
648 | assign se = tcu_int_se; | |
649 | assign siclk = tcu_int_aclk; | |
650 | assign soclk = tcu_int_bclk; | |
651 | ||
652 | //create clock headers | |
653 | tcu_regs_ctl_l1clkhdr_ctl_macro regs_clkgen | |
654 | ( | |
655 | .l2clk (l2clk), | |
656 | .l1clk (l1clk), | |
657 | .l1en(l1en), | |
658 | .pce_ov(pce_ov), | |
659 | .stop(stop), | |
660 | .se(se) | |
661 | ); | |
662 | ||
663 | // Synchronizer Pulse from cluster header | |
664 | tcu_regs_ctl_msff_ctl_macro__width_3 tcuregs_cmpiosync_reg | |
665 | ( | |
666 | .scan_in(tcuregs_cmpiosync_reg_scanin), | |
667 | .scan_out(tcuregs_cmpiosync_reg_scanout), | |
668 | .l1clk (l1clk), | |
669 | .din ({io_cmp_sync_en , cmp_io_sync_en , cmp_io2x_sync_en}), | |
670 | .dout ({io_cmp_sync_en_local, cmp_io_sync_en_local, cmp_io2x_sync_en_local}), | |
671 | .siclk(siclk), | |
672 | .soclk(soclk) | |
673 | ); | |
674 | ||
675 | // Sync UCB CSR write signal and then pass it to dbg_ctl | |
676 | tcu_regs_ctl_msff_ctl_macro__en_1__width_1 ucb_csr_wr_sync_reg ( | |
677 | .scan_in ( ucb_csr_wr_sync_reg_scanin ), | |
678 | .scan_out ( ucb_csr_wr_sync_reg_scanout ), | |
679 | .l1clk ( l1clk ), | |
680 | .en ( io_cmp_sync_en_local ), | |
681 | .din ( ucb_csr_wr ), | |
682 | .dout ( ucb_csr_wr_sync ), | |
683 | .siclk(siclk), | |
684 | .soclk(soclk)); | |
685 | ||
686 | //******************************************************************** | |
687 | // Transition Test Control | |
688 | //******************************************************************** | |
689 | //assign ac_test_mode = io_test_mode & io_ac_test_mode; | |
690 | ||
691 | //need to qualify muxed clock with de-assertion of a clock stop | |
692 | assign ac_test_muxed_clk_qual = ac_test_mode & | |
693 | ac_trans_test_counter_start & | |
694 | ~ac_trans_test_counter_stop; | |
695 | ||
696 | //ac trans test counter only 8 bits wide, ac tests not that long | |
697 | //msff_ctl_macro ff_counter_ac_trans_clk_stop (width=8,en=1) ( | |
698 | tcu_regs_ctl_msff_ctl_macro__en_1__width_8 tcuregs_ttcounter_reg ( | |
699 | .scan_in(tcuregs_ttcounter_reg_scanin), | |
700 | .scan_out(tcuregs_ttcounter_reg_scanout), | |
701 | .din (tt_count[7:0]), | |
702 | .dout (tt_count_dout[7:0]), | |
703 | .en (ac_test_muxed_clk_qual), | |
704 | .l1clk (l1clk), | |
705 | .siclk(siclk), | |
706 | .soclk(soclk)); //ac_test_muxed_clk)); | |
707 | ||
708 | ||
709 | assign tt_count[7:0] = tt_count_dout[7:0] - 8'b1; | |
710 | ||
711 | assign ac_trans_test_counter_stop = | |
712 | ac_test_mode & | |
713 | (tt_count_dout[7:0] == 8'h0) & | |
714 | tt_start_d; //ac_trans_test_counter_start; | |
715 | ||
716 | //means clk stop initiated by counter stop | |
717 | assign clk_stop_ac_trans_counter_initiated = ac_trans_test_counter_stop; | |
718 | ||
719 | // Flop start of ac transition test to break timing loop | |
720 | tcu_regs_ctl_msff_ctl_macro__width_1 tcuregs_ttstart_reg ( | |
721 | .scan_in(tcuregs_ttstart_reg_scanin), | |
722 | .scan_out(tcuregs_ttstart_reg_scanout), | |
723 | .din (ac_trans_test_counter_start), | |
724 | .dout (tt_start_d), | |
725 | .l1clk (l1clk), | |
726 | .siclk(siclk), | |
727 | .soclk(soclk)); | |
728 | ||
729 | //******************************************************************** | |
730 | // Clock Domain Register | |
731 | //******************************************************************** | |
732 | assign ucb_wr_clk_domain = ucb_csr_wr_sync && ucb_csr_addr == 6'h25; | |
733 | ||
734 | //debug event hard stop clk register | |
735 | tcu_regs_ctl_msff_ctl_macro__width_24 ff_debug_event_hard_stop ( | |
736 | .scan_in(ff_debug_event_hard_stop_scanin), | |
737 | .scan_out(ff_debug_event_hard_stop_scanout), | |
738 | .din(clk_stop_domain[23:0]), //debug_reg_hard_stop_domain_1st[16:0]), | |
739 | .dout(debug_reg_hard_stop_domain_1st[23:0]), | |
740 | .l1clk(l1clk), | |
741 | .siclk(siclk), | |
742 | .soclk(soclk)); | |
743 | ||
744 | // from JTAG | |
745 | assign clk_stop_domain[23:0] = clock_domain_upd_sync ? clock_domain[23:0] | |
746 | : dbg_upd_clock_domain ? clock_domain_data[23:0] | |
747 | : rst_upd_clock_domain ? 24'h1 | |
748 | : ucb_wr_clk_domain ? ucb_data_out[23:0] | |
749 | : debug_reg_hard_stop_domain_1st[23:0]; | |
750 | assign rst_upd_clock_domain = reset_event & tcu_dcr_en & clk_stop_dom_zero; | |
751 | assign clk_stop_dom_zero = ~(|debug_reg_hard_stop_domain_1st[23:0]); | |
752 | ||
753 | //******************************************************************** | |
754 | // Debug Control | |
755 | //******************************************************************** | |
756 | ||
757 | //******************************************************************** | |
758 | // Create a debug event when Power-on reset sequence ends | |
759 | //******************************************************************** | |
760 | // For use with TCU DCR - only enabled when tcu_dcr[2] active | |
761 | tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_2 rstend_reg | |
762 | ( | |
763 | .scan_in(rstend_reg_scanin), | |
764 | .scan_out(rstend_reg_scanout), | |
765 | .l1clk (l1clk), | |
766 | .clr (~tcu_dcr_en), | |
767 | .en (~rst_event), | |
768 | .din ({wmr_two, end_of_reset}), | |
769 | .dout ({wmr_two_d, rst_event}), | |
770 | .siclk(siclk), | |
771 | .soclk(soclk) | |
772 | ); | |
773 | ||
774 | assign end_of_reset = wmr_two_d & tcu_rst_flush_stop_ack; | |
775 | assign reset_event = rst_event; | |
776 | ||
777 | //******************************************************************** | |
778 | // Hard Stop - SPC request for Hard Clock Stop | |
779 | //******************************************************************** | |
780 | assign spc_hs_req_stg_din = {spc7_hstop_req, spc6_hstop_req, spc5_hstop_req, | |
781 | spc4_hstop_req, spc3_hstop_req, spc1_hstop_req}; | |
782 | ||
783 | tcu_regs_ctl_msff_ctl_macro__width_6 spc_hs_req_stg_reg ( | |
784 | .scan_in ( spc_hs_req_stg_reg_scanin ), | |
785 | .scan_out ( spc_hs_req_stg_reg_scanout ), | |
786 | .l1clk ( l1clk ), | |
787 | .din ( spc_hs_req_stg_din[5:0] ), | |
788 | .dout ( spc_hs_req_stg[5:0] ), | |
789 | .siclk(siclk), | |
790 | .soclk(soclk)); | |
791 | ||
792 | assign spc_hs_req[7:0] = {spc_hs_req_stg[5:1], | |
793 | spc2_hstop_req, | |
794 | spc_hs_req_stg[0], | |
795 | spc0_hstop_req}; | |
796 | ||
797 | tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_8 spchsreq_reg | |
798 | ( | |
799 | .scan_in(spchsreq_reg_scanin), | |
800 | .scan_out(spchsreq_reg_scanout), | |
801 | .l1clk (l1clk), | |
802 | .clr (tcu_dcr_en), | |
803 | .en (spchsreq_en), | |
804 | .din (spc_hs_req[7:0]), | |
805 | .dout (spc_hstop_req[7:0]), | |
806 | .siclk(siclk), | |
807 | .soclk(soclk) | |
808 | ); | |
809 | assign spchsreq_en = jtscan_off; | |
810 | ||
811 | assign spc0_hstop_req = spc0_hardstop_request; //|spc0_hardstop_request[7:0]; | |
812 | assign spc1_hstop_req = spc1_hardstop_request; //|spc1_hardstop_request[7:0]; | |
813 | assign spc2_hstop_req = spc2_hardstop_request; //|spc2_hardstop_request[7:0]; | |
814 | assign spc3_hstop_req = spc3_hardstop_request; //|spc3_hardstop_request[7:0]; | |
815 | assign spc4_hstop_req = spc4_hardstop_request; //|spc4_hardstop_request[7:0]; | |
816 | assign spc5_hstop_req = spc5_hardstop_request; //|spc5_hardstop_request[7:0]; | |
817 | assign spc6_hstop_req = spc6_hardstop_request; //|spc6_hardstop_request[7:0]; | |
818 | assign spc7_hstop_req = spc7_hardstop_request; //|spc7_hardstop_request[7:0]; | |
819 | ||
820 | //******************************************************************** | |
821 | // Disable Overlap and Single Step Enable Register | |
822 | //******************************************************************** | |
823 | ||
824 | tcu_regs_ctl_msff_ctl_macro__width_64 dossen_reg | |
825 | ( | |
826 | .scan_in(dossen_reg_scanin), | |
827 | .scan_out(dossen_reg_scanout), | |
828 | .l1clk (l1clk), | |
829 | .din (next_doss_enab[63:0]), | |
830 | .dout (doss_enab[63:0]), | |
831 | .siclk(siclk), | |
832 | .soclk(soclk) | |
833 | ); | |
834 | ||
835 | assign next_doss_enab[63:0] = dossen_upd_sync ? dossen[63:0] | |
836 | : doss_enab[63:0]; | |
837 | ||
838 | assign spc0_doss_enab = |doss_enab[7:0]; | |
839 | assign spc1_doss_enab = |doss_enab[15:8]; | |
840 | assign spc2_doss_enab = |doss_enab[23:16]; | |
841 | assign spc3_doss_enab = |doss_enab[31:24]; | |
842 | assign spc4_doss_enab = |doss_enab[39:32]; | |
843 | assign spc5_doss_enab = |doss_enab[47:40]; | |
844 | assign spc6_doss_enab = |doss_enab[55:48]; | |
845 | assign spc7_doss_enab = |doss_enab[63:56]; | |
846 | ||
847 | assign spc_doss_enab[7:0] = {spc7_doss_enab,spc6_doss_enab, | |
848 | spc5_doss_enab,spc4_doss_enab, | |
849 | spc3_doss_enab,spc2_doss_enab, | |
850 | spc1_doss_enab,spc0_doss_enab}; | |
851 | ||
852 | //******************************************************************** | |
853 | // Disable Overlap Mode Register | |
854 | //******************************************************************** | |
855 | ||
856 | tcu_regs_ctl_msff_ctl_macro__en_1__width_2 dossmode_reg | |
857 | ( | |
858 | .scan_in(dossmode_reg_scanin), | |
859 | .scan_out(dossmode_reg_scanout), | |
860 | .l1clk (l1clk), | |
861 | .en (cmp_io_sync_en_local), | |
862 | .din (next_doss_mode[1:0]), | |
863 | .dout (doss_mode[1:0]), | |
864 | .siclk(siclk), | |
865 | .soclk(soclk) | |
866 | ); | |
867 | ||
868 | assign next_doss_mode[1:0] = dossmode_upd_sync ? dossmode[1:0] | |
869 | : doss_mode[1:0]; | |
870 | ||
871 | //******************************************************************** | |
872 | // Single Step Complete - SPC acknowledgement that its single-step is complete | |
873 | //******************************************************************** | |
874 | ||
875 | // Staging Flops | |
876 | assign spc_ss_complete_stg_din = {spc7_ss_complete, spc6_ss_complete, spc5_ss_complete, | |
877 | spc4_ss_complete, spc3_ss_complete, spc1_ss_complete}; | |
878 | ||
879 | tcu_regs_ctl_msff_ctl_macro__width_6 spc_ss_complete_stg_reg ( | |
880 | .scan_in ( spc_ss_complete_stg_reg_scanin ), | |
881 | .scan_out ( spc_ss_complete_stg_reg_scanout ), | |
882 | .l1clk ( l1clk ), | |
883 | .din ( spc_ss_complete_stg_din[5:0] ), | |
884 | .dout ( spc_ss_complete_stg[5:0] ), | |
885 | .siclk(siclk), | |
886 | .soclk(soclk)); | |
887 | ||
888 | assign spc_ss_complete[7:0] = {spc_ss_complete_stg[5:1], | |
889 | spc2_ss_complete, | |
890 | spc_ss_complete_stg[0], | |
891 | spc0_ss_complete}; | |
892 | ||
893 | tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_8 spcsscomp_reg | |
894 | ( | |
895 | .scan_in(spcsscomp_reg_scanin), | |
896 | .scan_out(spcsscomp_reg_scanout), | |
897 | .l1clk (l1clk), | |
898 | .clr (~spc_ss_en), | |
899 | .en (spc_ss_en), | |
900 | .din (spc_ss_comp_hld[7:0]), | |
901 | .dout (spc_ss_comp[7:0]), | |
902 | .siclk(siclk), | |
903 | .soclk(soclk) | |
904 | ); | |
905 | // ss_complete from SPC's is a pulse, but need to hold until cleared | |
906 | assign spc_ss_comp_din[7:0] = spc_ss_complete[7:0] & ~tcu_ss_request[7:0]; | |
907 | assign spc_ss_comp_hld[7:0] = spc_ss_comp_din[7:0] | spc_ss_comp[7:0]; | |
908 | assign spc_ss_en = doss_mode[1] & doss_mode[0] & jtscan_off; | |
909 | ||
910 | //******************************************************************** | |
911 | // Soft Stop - SPC request for Soft Clock Stop | |
912 | //******************************************************************** | |
913 | assign spc_ss_req_stg_din = {spc7_sstop_req, spc6_sstop_req, spc5_sstop_req, | |
914 | spc4_sstop_req, spc3_sstop_req, spc1_sstop_req}; | |
915 | ||
916 | tcu_regs_ctl_msff_ctl_macro__width_6 spc_ss_req_stg_reg ( | |
917 | .scan_in ( spc_ss_req_stg_reg_scanin ), | |
918 | .scan_out ( spc_ss_req_stg_reg_scanout ), | |
919 | .l1clk ( l1clk ), | |
920 | .din ( spc_ss_req_stg_din[5:0] ), | |
921 | .dout ( spc_ss_req_stg[5:0] ), | |
922 | .siclk(siclk), | |
923 | .soclk(soclk)); | |
924 | ||
925 | assign spc_ss_req[7:0] = {spc_ss_req_stg[5:1], | |
926 | spc2_sstop_req, | |
927 | spc_ss_req_stg[0], | |
928 | spc0_sstop_req}; | |
929 | ||
930 | tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_8 spcssreq_reg | |
931 | ( | |
932 | .scan_in(spcssreq_reg_scanin), | |
933 | .scan_out(spcssreq_reg_scanout), | |
934 | .l1clk (l1clk), | |
935 | .clr (tcu_dcr_en), | |
936 | .en (spcssreq_en), | |
937 | .din (spc_ss_req[7:0]), | |
938 | .dout (spc_sstop_req[7:0]), | |
939 | .siclk(siclk), | |
940 | .soclk(soclk) | |
941 | ); | |
942 | assign spcssreq_en = jtscan_off; | |
943 | ||
944 | assign spc0_sstop_req = spc0_softstop_request; //|spc0_softstop_request[7:0]; | |
945 | assign spc1_sstop_req = spc1_softstop_request; //|spc1_softstop_request[7:0]; | |
946 | assign spc2_sstop_req = spc2_softstop_request; //|spc2_softstop_request[7:0]; | |
947 | assign spc3_sstop_req = spc3_softstop_request; //|spc3_softstop_request[7:0]; | |
948 | assign spc4_sstop_req = spc4_softstop_request; //|spc4_softstop_request[7:0]; | |
949 | assign spc5_sstop_req = spc5_softstop_request; //|spc5_softstop_request[7:0]; | |
950 | assign spc6_sstop_req = spc6_softstop_request; //|spc6_softstop_request[7:0]; | |
951 | assign spc7_sstop_req = spc7_softstop_request; //|spc7_softstop_request[7:0]; | |
952 | ||
953 | //******************************************************************** | |
954 | // Core Running Status - SPC status: parked or running | |
955 | //******************************************************************** | |
956 | assign spc_crunstat[63:0] = {spc7_ncu_core_running_status[7:0], | |
957 | spc6_ncu_core_running_status[7:0], | |
958 | spc5_ncu_core_running_status[7:0], | |
959 | spc4_ncu_core_running_status[7:0], | |
960 | spc3_ncu_core_running_status[7:0], | |
961 | spc2_ncu_core_running_status[7:0], | |
962 | spc1_ncu_core_running_status[7:0], | |
963 | spc0_ncu_core_running_status[7:0]}; | |
964 | ||
965 | tcu_regs_ctl_msff_ctl_macro__en_1__width_64 spcrstat_reg | |
966 | ( | |
967 | .scan_in(spcrstat_reg_scanin), | |
968 | .scan_out(spcrstat_reg_scanout), | |
969 | .l1clk (l1clk), | |
970 | .en (spccrs_en), | |
971 | .din (spc_crunstat[63:0]), | |
972 | .dout (spc_crs[63:0]), | |
973 | .siclk(siclk), | |
974 | .soclk(soclk) | |
975 | ); | |
976 | assign spccrs_en = jtscan_off & cmp_io_sync_en_local; | |
977 | ||
978 | assign spc0_crunstat = |spc_crs[7:0]; | |
979 | assign spc1_crunstat = |spc_crs[15:8]; | |
980 | assign spc2_crunstat = |spc_crs[23:16]; | |
981 | assign spc3_crunstat = |spc_crs[31:24]; | |
982 | assign spc4_crunstat = |spc_crs[39:32]; | |
983 | assign spc5_crunstat = |spc_crs[47:40]; | |
984 | assign spc6_crunstat = |spc_crs[55:48]; | |
985 | assign spc7_crunstat = |spc_crs[63:56]; | |
986 | ||
987 | assign spc_crstat[7:0] = {spc7_crunstat,spc6_crunstat, | |
988 | spc5_crunstat,spc4_crunstat, | |
989 | spc3_crunstat,spc2_crunstat, | |
990 | spc1_crunstat,spc0_crunstat}; | |
991 | ||
992 | //******************************************************************** | |
993 | // Trigger Pulse - SPC request to pulse Watchpoint (TRIGOUT) pin | |
994 | //******************************************************************** | |
995 | assign spc_tp_req_stg_din = {spc7_tp_req, spc6_tp_req, spc5_tp_req, | |
996 | spc4_tp_req, spc3_tp_req, spc1_tp_req}; | |
997 | ||
998 | tcu_regs_ctl_msff_ctl_macro__width_6 spc_tp_req_stg_reg ( | |
999 | .scan_in ( spc_tp_req_stg_reg_scanin ), | |
1000 | .scan_out ( spc_tp_req_stg_reg_scanout ), | |
1001 | .l1clk ( l1clk ), | |
1002 | .din ( spc_tp_req_stg_din[5:0] ), | |
1003 | .dout ( spc_tp_req_stg[5:0] ), | |
1004 | .siclk(siclk), | |
1005 | .soclk(soclk)); | |
1006 | ||
1007 | assign spc_tp_req[7:0] = {spc_tp_req_stg[5:1], | |
1008 | spc2_tp_req, | |
1009 | spc_tp_req_stg[0], | |
1010 | spc0_tp_req}; | |
1011 | ||
1012 | tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_8 spctp_reg | |
1013 | ( | |
1014 | .scan_in(spctp_reg_scanin), | |
1015 | .scan_out(spctp_reg_scanout), | |
1016 | .l1clk (l1clk), | |
1017 | .clr (tcu_dcr_en), | |
1018 | .en (spctpreq_en), | |
1019 | .din (spc_tp_req[7:0]), | |
1020 | .dout (spc_tp[7:0]), | |
1021 | .siclk(siclk), | |
1022 | .soclk(soclk) | |
1023 | ); | |
1024 | assign spctpreq_en = jtscan_off; | |
1025 | ||
1026 | assign spc0_tp_req = spc0_trigger_pulse; //|spc0_trigger_pulse[7:0]; | |
1027 | assign spc1_tp_req = spc1_trigger_pulse; //|spc1_trigger_pulse[7:0]; | |
1028 | assign spc2_tp_req = spc2_trigger_pulse; //|spc2_trigger_pulse[7:0]; | |
1029 | assign spc3_tp_req = spc3_trigger_pulse; //|spc3_trigger_pulse[7:0]; | |
1030 | assign spc4_tp_req = spc4_trigger_pulse; //|spc4_trigger_pulse[7:0]; | |
1031 | assign spc5_tp_req = spc5_trigger_pulse; //|spc5_trigger_pulse[7:0]; | |
1032 | assign spc6_tp_req = spc6_trigger_pulse; //|spc6_trigger_pulse[7:0]; | |
1033 | assign spc7_tp_req = spc7_trigger_pulse; //|spc7_trigger_pulse[7:0]; | |
1034 | ||
1035 | assign tcu_mio_trigout = trigout_pulse; // from dbg_ctl | |
1036 | ||
1037 | ||
1038 | //******************************************************************** | |
1039 | // Synchronizers for Updates from JTAG (TCK Clock Domain) | |
1040 | //******************************************************************** | |
1041 | ||
1042 | cl_sc1_clksyncff_4x clkdomain_upd_sync_reg | |
1043 | ( .si (clkdomain_upd_sync_reg_scanin), | |
1044 | .so (clkdomain_upd_sync_reg_scanout), | |
1045 | .l1clk (l1clk), | |
1046 | .d (clock_domain_upd), | |
1047 | .q (clock_domain_upd_sync), | |
1048 | .siclk(siclk), | |
1049 | .soclk(soclk) | |
1050 | ); | |
1051 | ||
1052 | cl_sc1_clksyncff_4x coresel_upd_sync_reg | |
1053 | ( .si (coresel_upd_sync_reg_scanin), | |
1054 | .so (coresel_upd_sync_reg_scanout), | |
1055 | .l1clk (l1clk), | |
1056 | .d (core_sel_upd), | |
1057 | .q (core_sel_upd_sync), | |
1058 | .siclk(siclk), | |
1059 | .soclk(soclk) | |
1060 | ); | |
1061 | ||
1062 | cl_sc1_clksyncff_4x decnt_upd_sync_reg | |
1063 | ( .si (decnt_upd_sync_reg_scanin), | |
1064 | .so (decnt_upd_sync_reg_scanout), | |
1065 | .l1clk (l1clk), | |
1066 | .d (decnt_upd), | |
1067 | .q (decnt_upd_sync), | |
1068 | .siclk(siclk), | |
1069 | .soclk(soclk) | |
1070 | ); | |
1071 | ||
1072 | cl_sc1_clksyncff_4x cyccnt_upd_sync_reg | |
1073 | ( .si (cyccnt_upd_sync_reg_scanin), | |
1074 | .so (cyccnt_upd_sync_reg_scanout), | |
1075 | .l1clk (l1clk), | |
1076 | .d (cyc_count_upd), | |
1077 | .q (cyc_count_upd_sync), | |
1078 | .siclk(siclk), | |
1079 | .soclk(soclk) | |
1080 | ); | |
1081 | ||
1082 | cl_sc1_clksyncff_4x tcudcr_upd_sync_reg | |
1083 | ( .si (tcudcr_upd_sync_reg_scanin), | |
1084 | .so (tcudcr_upd_sync_reg_scanout), | |
1085 | .l1clk (l1clk), | |
1086 | .d (tcudcr_upd), | |
1087 | .q (tcudcr_upd_sync), | |
1088 | .siclk(siclk), | |
1089 | .soclk(soclk) | |
1090 | ); | |
1091 | ||
1092 | cl_sc1_clksyncff_4x dossen_upd_sync_reg | |
1093 | ( .si (dossen_upd_sync_reg_scanin), | |
1094 | .so (dossen_upd_sync_reg_scanout), | |
1095 | .l1clk (l1clk), | |
1096 | .d (dossen_upd), | |
1097 | .q (dossen_upd_sync), | |
1098 | .siclk(siclk), | |
1099 | .soclk(soclk) | |
1100 | ); | |
1101 | ||
1102 | cl_sc1_clksyncff_4x dossmode_upd_sync_reg | |
1103 | ( .si (dossmode_upd_sync_reg_scanin), | |
1104 | .so (dossmode_upd_sync_reg_scanout), | |
1105 | .l1clk (l1clk), | |
1106 | .d (dossmode_upd), | |
1107 | .q (dossmode_upd_sync), | |
1108 | .siclk(siclk), | |
1109 | .soclk(soclk) | |
1110 | ); | |
1111 | ||
1112 | cl_sc1_clksyncff_4x ssreq_upd_sync_reg | |
1113 | ( .si (ssreq_upd_sync_reg_scanin), | |
1114 | .so (ssreq_upd_sync_reg_scanout), | |
1115 | .l1clk (l1clk), | |
1116 | .d (ssreq_upd), | |
1117 | .q (ssreq_upd_sync), | |
1118 | .siclk(siclk), | |
1119 | .soclk(soclk) | |
1120 | ); | |
1121 | ||
1122 | cl_sc1_clksyncff_4x csmode_upd_sync_reg | |
1123 | ( .si (csmode_upd_sync_reg_scanin), | |
1124 | .so (csmode_upd_sync_reg_scanout), | |
1125 | .l1clk (l1clk), | |
1126 | .d (csmode_upd), | |
1127 | .q (csmode_upd_sync), | |
1128 | .siclk(siclk), | |
1129 | .soclk(soclk) | |
1130 | ); | |
1131 | ||
1132 | // Test Protect mode to block inputs to TCU | |
1133 | cl_sc1_clksyncff_4x jtagserscan_sync_reg | |
1134 | ( .si (jtagserscan_sync_reg_scanin), | |
1135 | .so (jtagserscan_sync_reg_scanout), | |
1136 | .l1clk (l1clk), | |
1137 | .d (jtag_ser_scan_q), // ECO yyyyyy | |
1138 | .q (jtag_ser_scan_sync), | |
1139 | .siclk(siclk), | |
1140 | .soclk(soclk) | |
1141 | ); | |
1142 | cl_sc1_clksyncff_4x testprotect_sync_reg | |
1143 | ( .si (testprotect_sync_reg_scanin), | |
1144 | .so (testprotect_sync_reg_scanout), | |
1145 | .l1clk (l1clk), | |
1146 | .d (jtag_test_protect), | |
1147 | .q (jtag_test_protect_sync), | |
1148 | .siclk(siclk), | |
1149 | .soclk(soclk) | |
1150 | ); | |
1151 | assign test_protect = jtag_test_protect_sync | flush_test_protect; | |
1152 | assign dbr_gateoff = rst_tcu_dbr_gen & flush_test_protect; | |
1153 | tcu_regs_ctl_msff_ctl_macro__en_1__width_2 testprotect_reg | |
1154 | ( .scan_in(testprotect_reg_scanin), | |
1155 | .scan_out(testprotect_reg_scanout), | |
1156 | .l1clk (l1clk), | |
1157 | .en (test_protect_en), | |
1158 | .din ({test_protect, dbr_gateoff }), | |
1159 | .dout ({test_protect_sync_to_io, tcu_dbr_gateoff }), | |
1160 | .siclk(siclk), | |
1161 | .soclk(soclk) | |
1162 | ); | |
1163 | // block inputs when jtag scan or mbist, lbist when desired | |
1164 | // or when jtag serial scan, block tcu inputs; also goes to RST, CCU, DMU, PEU | |
1165 | assign mt_mode = jtag_mt_enable; | |
1166 | assign test_protect_en = cmp_io_sync_en_local & ~ac_test_mode & ~mt_mode_sync; | |
1167 | assign jtscan_off = ~tcu_tp_sync_2io & ~jtag_ser_scan_sync; | |
1168 | assign tcu_tp_sync_2io = ac_test_mode | test_protect_sync_to_io; | |
1169 | ||
1170 | // to synchronize mt_mode, just in case | |
1171 | cl_sc1_clksyncff_4x tcuregs_mtmode_syncreg ( | |
1172 | .si ( tcuregs_mtmode_syncreg_scanin ), | |
1173 | .so ( tcuregs_mtmode_syncreg_scanout ), | |
1174 | .l1clk ( l1clk ), | |
1175 | .d ( mt_mode ), | |
1176 | .q ( mt_mode_sync ), | |
1177 | .siclk(siclk), | |
1178 | .soclk(soclk)); | |
1179 | ||
1180 | ||
1181 | //******************************************************************** | |
1182 | // Instantiate Debug Sub-Block | |
1183 | //******************************************************************** | |
1184 | ||
1185 | tcu_dbg_ctl dbg_ctl | |
1186 | ( | |
1187 | .jtagclkstop_ov (jtagclkstop_ov_d), // ECO B | |
1188 | .debug_cycle_counter_stop (debug_cycle_counter_stop_to_mbc), // ECO C | |
1189 | .cycle_stretch (cycle_stretch_to_mbc), // ECO D | |
1190 | .mbist_clk_stop (mbist_clk_stop_to_mbc), // ECO C | |
1191 | .scan_in (tcu_dbg_ctl_scan_in), | |
1192 | .scan_out (tcu_dbg_ctl_scan_out), | |
1193 | .tcu_int_se(tcu_int_se), | |
1194 | .tcu_int_aclk(tcu_int_aclk), | |
1195 | .tcu_int_bclk(tcu_int_bclk), | |
1196 | .tcu_int_ce(tcu_int_ce), | |
1197 | .tcu_pce_ov(tcu_pce_ov), | |
1198 | .l2clk(l2clk), | |
1199 | .cmp_io_sync_en_local(cmp_io_sync_en_local), | |
1200 | .io_cmp_sync_en_local(io_cmp_sync_en_local), | |
1201 | .cmp_io2x_sync_en_local(cmp_io2x_sync_en_local), | |
1202 | .spc_hstop_req(spc_hstop_req[7:0]), | |
1203 | .spc_sstop_req(spc_sstop_req[7:0]), | |
1204 | .spc_tp(spc_tp[7:0]), | |
1205 | .reset_event(reset_event), | |
1206 | .spc_crstat(spc_crstat[7:0]), | |
1207 | .spc_crs(spc_crs[63:0]), | |
1208 | .spc_ss_comp(spc_ss_comp[7:0]), | |
1209 | .doss_stat(doss_stat[7:0]), | |
1210 | .tcu_ss_request(tcu_ss_request[7:0]), | |
1211 | .ssreq_upd_sync(ssreq_upd_sync), | |
1212 | .tcu_ss_mode(tcu_ss_mode[7:0]), | |
1213 | .tcu_do_mode(tcu_do_mode[7:0]), | |
1214 | .dbg1_tcu_soc_hard_stop(dbg1_tcu_soc_hard_stop), | |
1215 | .dbg1_tcu_soc_asrt_trigout(dbg1_tcu_soc_asrt_trigout), | |
1216 | .trigout_pulse(trigout_pulse), | |
1217 | .mio_tcu_trigin(mio_tcu_trigin), | |
1218 | .mbist_clk_stop_req(mbist_clk_stop_req), | |
1219 | .jtag_clock_start(jtag_clock_start), | |
1220 | .jtscan_off(jtscan_off), | |
1221 | .cyc_count(cyc_count[63:0]), | |
1222 | .cyc_count_upd_sync(cyc_count_upd_sync), | |
1223 | .tcudcr_data(tcudcr_data[3:0]), | |
1224 | .tcudcr_upd_sync(tcudcr_upd_sync), | |
1225 | .decnt_data(decnt_data[31:0]), | |
1226 | .decnt_upd_sync(decnt_upd_sync), | |
1227 | .core_sel(core_sel[7:0]), | |
1228 | .core_sel_upd_sync(core_sel_upd_sync), | |
1229 | .spc_doss_enab(spc_doss_enab[7:0]), | |
1230 | .doss_mode(doss_mode[1:0]), | |
1231 | .doss_enab(doss_enab[63:0]), | |
1232 | .csmode(csmode), | |
1233 | .csmode_upd_sync(csmode_upd_sync), | |
1234 | .cs_mode(cs_mode), | |
1235 | .cs_mode_active(cs_mode_active), | |
1236 | .de_count(de_count[31:0]), | |
1237 | .cycle_count(cycle_count[63:0]), | |
1238 | .tcu_dcr(tcu_dcr[3:0]), | |
1239 | .clock_domain_data(clock_domain_data[23:0]), | |
1240 | .dbg_upd_clock_domain(dbg_upd_clock_domain), | |
1241 | .tcu_dcr_en(tcu_dcr_en), | |
1242 | .spc_ss_mode(spc_ss_mode), | |
1243 | .spc_ss_sel(spc_ss_sel[7:0]), | |
1244 | .dbg_creg_access(dbg_creg_access), | |
1245 | .dbg_creg_addr(dbg_creg_addr[39:0]), | |
1246 | .dbg_creg_data(dbg_creg_data[63:0]), | |
1247 | .dbg_creg_wr_en(dbg_creg_wr_en), | |
1248 | .dbg_creg_addr_en(dbg_creg_addr_en), | |
1249 | .dbg_creg_data_en(dbg_creg_data_en), | |
1250 | .ucb_csr_wr_sync(ucb_csr_wr_sync), | |
1251 | .ucb_csr_addr(ucb_csr_addr[5:0]), | |
1252 | .ucb_data_out(ucb_data_out[63:0]) | |
1253 | ); | |
1254 | ||
1255 | ||
1256 | //============================================================ | |
1257 | // Following is for L2 Access via SIU, using JTAG | |
1258 | //============================================================ | |
1259 | ||
1260 | // these synchronizers for L2 access via SIU | |
1261 | cl_sc1_clksyncff_4x tcuregs_l2dataupd_syncreg ( | |
1262 | .si ( tcuregs_l2dataupd_syncreg_scanin ), | |
1263 | .so ( tcuregs_l2dataupd_syncreg_scanout ), | |
1264 | .l1clk ( l1clk ), | |
1265 | .d ( l2data_upd ), | |
1266 | .q ( l2data_upd_sync ), | |
1267 | .siclk(siclk), | |
1268 | .soclk(soclk)); | |
1269 | ||
1270 | cl_sc1_clksyncff_4x tcuregs_l2addrupd_syncreg ( | |
1271 | .si ( tcuregs_l2addrupd_syncreg_scanin ), | |
1272 | .so ( tcuregs_l2addrupd_syncreg_scanout ), | |
1273 | .l1clk ( l1clk ), | |
1274 | .d ( l2addr_upd ), | |
1275 | .q ( l2addr_upd_sync ), | |
1276 | .siclk(siclk), | |
1277 | .soclk(soclk)); | |
1278 | ||
1279 | cl_sc1_clksyncff_4x tcuregs_l2vld_syncreg ( | |
1280 | .si ( tcuregs_l2rti_syncreg_scanin ), | |
1281 | .so ( tcuregs_l2rti_syncreg_scanout ), | |
1282 | .l1clk ( l1clk ), | |
1283 | .d ( l2rti ), | |
1284 | .q ( l2rti_sync ), | |
1285 | .siclk(siclk), | |
1286 | .soclk(soclk)); | |
1287 | ||
1288 | cl_sc1_clksyncff_4x tcuregs_l2rd_syncreg ( | |
1289 | .si ( tcuregs_l2rd_syncreg_scanin ), | |
1290 | .so ( tcuregs_l2rd_syncreg_scanout ), | |
1291 | .l1clk ( l1clk ), | |
1292 | .d ( instr_l2_rd ), | |
1293 | .q ( instr_l2_rd_sync ), | |
1294 | .siclk(siclk), | |
1295 | .soclk(soclk)); | |
1296 | ||
1297 | cl_sc1_clksyncff_4x tcuregs_l2wr_syncreg ( | |
1298 | .si ( tcuregs_l2wr_syncreg_scanin ), | |
1299 | .so ( tcuregs_l2wr_syncreg_scanout ), | |
1300 | .l1clk ( l1clk ), | |
1301 | .d ( instr_l2_wr ), | |
1302 | .q ( instr_l2_wr_sync ), | |
1303 | .siclk(siclk), | |
1304 | .soclk(soclk)); | |
1305 | ||
1306 | ||
1307 | //============================================================ | |
1308 | // L2 Write/Read Data Register - for L2 access via SIU; this is PAYLOAD | |
1309 | // - during l2_WRITE, it sends data to L2 | |
1310 | // - during l2_READ, it is an input and receives data from L2 | |
1311 | //============================================================ | |
1312 | // Comes from shift register in JTAG, enable is synchronzed to cmp clock | |
1313 | ||
1314 | tcu_regs_ctl_msff_ctl_macro__width_64 tcuregs_l2data_reg ( | |
1315 | .scan_in ( tcuregs_l2data_reg_scanin ), | |
1316 | .scan_out ( tcuregs_l2data_reg_scanout ), | |
1317 | .l1clk ( l1clk ), | |
1318 | .din ( next_l2data_reg[63:0] ), | |
1319 | .dout ( l2data_reg[63:0] ), | |
1320 | .siclk(siclk), | |
1321 | .soclk(soclk)); | |
1322 | ||
1323 | assign next_l2data_reg[63:0] = l2wrdata_shift ? | |
1324 | {1'b0, l2data_reg[63:1]} : | |
1325 | l2data_upd_sync ? | |
1326 | l2access[64:1] : | |
1327 | l2rddata_shift ? | |
1328 | {sio_tcu_data,l2data_reg[63:1]} : | |
1329 | l2data_reg[63:0]; | |
1330 | ||
1331 | assign l2rddata[63:0] = l2data_reg[63:0]; | |
1332 | ||
1333 | assign l2wrdata_shift = instr_l2_wr_sync & l2rti_sync & ~l2addr_shift; | |
1334 | assign l2rddata_shift = instr_l2_rd_sync & (l2_read_start | sio_tcu_vld) & ~l2cnt_done; | |
1335 | ||
1336 | //============================================================ | |
1337 | // L2 Write/Read Address Register - for L2 access via SIU; this is HEADER | |
1338 | //============================================================ | |
1339 | // Comes from shift register in JTAG, enable is synchronzed to cmp clock | |
1340 | ||
1341 | tcu_regs_ctl_msff_ctl_macro__width_64 tcuregs_l2addr_reg ( | |
1342 | .scan_in ( tcuregs_l2addr_reg_scanin ), | |
1343 | .scan_out ( tcuregs_l2addr_reg_scanout ), | |
1344 | .l1clk ( l1clk ), | |
1345 | .din ( next_l2addr_reg[63:0] ), | |
1346 | .dout ( l2addr_reg[63:0] ), | |
1347 | .siclk(siclk), | |
1348 | .soclk(soclk)); | |
1349 | ||
1350 | assign next_l2addr_reg[63:0] = l2addr_shift ? | |
1351 | {1'b0, l2addr_reg[63:1]} : | |
1352 | l2addr_upd_sync ? | |
1353 | l2access[64:1] : | |
1354 | l2addr_reg[63:0]; | |
1355 | ||
1356 | assign tcu_sii_data_din = l2wrdata_shift ? | |
1357 | l2data_reg[0] : | |
1358 | l2addr_shift ? | |
1359 | l2addr_reg[0] : | |
1360 | 1'b0; | |
1361 | ||
1362 | tcu_regs_ctl_msff_ctl_macro__width_1 tcuregs_tcu_sii_data_reg ( | |
1363 | .scan_in ( tcuregs_tcu_sii_data_reg_scanin ), | |
1364 | .scan_out ( tcuregs_tcu_sii_data_reg_scanout ), | |
1365 | .l1clk ( l1clk ), | |
1366 | .din ( tcu_sii_data_din ), | |
1367 | .dout ( tcu_sii_data ), | |
1368 | .siclk(siclk), | |
1369 | .soclk(soclk)); | |
1370 | ||
1371 | ||
1372 | assign l2addr_shift = (instr_l2_wr_sync | instr_l2_rd_sync) & l2rti_sync & ~l2cnt[6]; | |
1373 | ||
1374 | //============================================================ | |
1375 | // L2 Access - Generate VALID pulse & catch sio_tcu_vld for L2 Read | |
1376 | //============================================================ | |
1377 | tcu_regs_ctl_msff_ctl_macro__width_1 tcuregs_l2rti_reg ( | |
1378 | .scan_in ( tcuregs_l2rti_reg_scanin ), | |
1379 | .scan_out ( tcuregs_l2rti_reg_scanout ), | |
1380 | .l1clk ( l1clk ), | |
1381 | .din ( l2rti_sync ), | |
1382 | .dout ( l2rti_dly ), | |
1383 | .siclk(siclk), | |
1384 | .soclk(soclk)); | |
1385 | ||
1386 | assign tcu_sii_vld_din = (l2rti_sync & ~l2rti_dly & (instr_l2_wr_sync | instr_l2_rd_sync)) | |
1387 | | (instr_l2_wr_sync & (l2cnt[6:0] == 7'b1000000)); | |
1388 | ||
1389 | tcu_regs_ctl_msff_ctl_macro__width_1 tcuregs_tcu_sii_vld_reg ( | |
1390 | .scan_in ( tcuregs_tcu_sii_vld_reg_scanin ), | |
1391 | .scan_out ( tcuregs_tcu_sii_vld_reg_scanout ), | |
1392 | .l1clk ( l1clk ), | |
1393 | .din ( tcu_sii_vld_din ), | |
1394 | .dout ( tcu_sii_vld ), | |
1395 | .siclk(siclk), | |
1396 | .soclk(soclk)); | |
1397 | ||
1398 | ||
1399 | tcu_regs_ctl_msff_ctl_macro__clr__1__en_1__width_1 tcuregs_l2siovld_reg ( | |
1400 | .scan_in ( tcuregs_l2siovld_reg_scanin ), | |
1401 | .scan_out ( tcuregs_l2siovld_reg_scanout ), | |
1402 | .l1clk ( l1clk ), | |
1403 | .en ( sio_tcu_vld ), | |
1404 | .clr_ ( instr_l2_rd_sync ), | |
1405 | .din ( instr_l2_rd_sync ), //(l2rti_dly), | |
1406 | .dout ( l2_read_start ), | |
1407 | .siclk(siclk), | |
1408 | .soclk(soclk)); | |
1409 | ||
1410 | //============================================================ | |
1411 | // L2 Access - Counter to track number of shifts | |
1412 | //============================================================ | |
1413 | tcu_regs_ctl_msff_ctl_macro__clr__1__width_7 tcuregs_l2cntr_reg ( | |
1414 | .scan_in ( tcuregs_l2cntr_reg_scanin ), | |
1415 | .scan_out ( tcuregs_l2cntr_reg_scanout ), | |
1416 | .l1clk ( l1clk ), | |
1417 | .clr_ ( l2cnt_clr_ ), | |
1418 | .din ( new_l2cnt[6:0] ), | |
1419 | .dout ( l2cnt[6:0] ), | |
1420 | .siclk(siclk), | |
1421 | .soclk(soclk)); | |
1422 | ||
1423 | assign new_l2cnt[6:0] = l2cnt_en ? (l2cnt[6:0] + 7'b0000001) : l2cnt[6:0]; | |
1424 | assign l2cnt_clr_ = (instr_l2_wr_sync | instr_l2_rd_sync); | |
1425 | assign l2cnt_en = (instr_l2_wr_sync & l2rti_sync & ~l2cnt_done) | (l2rddata_shift); | |
1426 | //| (instr_l2_rd & l2rti_sync & l2rddata_shift); | |
1427 | assign l2cnt_max = &l2cnt[6:0]; | |
1428 | assign l2cnt_done = (instr_l2_rd_sync & l2cnt[6]) | (instr_l2_wr_sync & l2cnt_max); | |
1429 | assign l2_read_vld = instr_l2_rd_sync & l2cnt_done; | |
1430 | ||
1431 | // ---------------------------------------------------------------------- | |
1432 | // Removed for ECO to make flops visible in SunV | |
1433 | //spare_ctl_macro spare (num=9) ( | |
1434 | // .l1clk ( l1clk ), | |
1435 | // .scan_in ( spare_scanin ), | |
1436 | // .scan_out ( spare_scanout )); | |
1437 | ||
1438 | // Added for ECO to make flops visible | |
1439 | ||
1440 | // - this is an expansion of spare_ctl_macro with just the gates | |
1441 | tcu_regs_ctl_spare_ctl_macro__flops_0__num_9 spare_gates ( | |
1442 | ); | |
1443 | ||
1444 | tcu_regs_ctl_msff_ctl_macro__scanreverse_1__width_9 spare_flops ( | |
1445 | .scan_in(spare_flops_scanin), | |
1446 | .scan_out(spare_flops_scanout), | |
1447 | .l1clk(l1clk), | |
1448 | .din (spare_flops_d[8:0]), | |
1449 | .dout (spare_flops_q[8:0]), | |
1450 | .siclk(siclk), | |
1451 | .soclk(soclk) | |
1452 | ); | |
1453 | ||
1454 | assign spare_flops_d[8] = 1'b0; | |
1455 | assign spare_flops_d[7] = 1'b0; | |
1456 | assign spare_flops_d[6] = spare6_flop_d; | |
1457 | assign spare_flops_d[5] = 1'b0; | |
1458 | assign spare_flops_d[4] = spare4_flop_d; | |
1459 | assign spare_flops_d[3] = 1'b0; | |
1460 | assign spare_flops_d[2] = 1'b0; | |
1461 | assign spare_flops_d[1] = 1'b0; | |
1462 | assign spare_flops_d[0] = 1'b0; | |
1463 | ||
1464 | assign spare_flops_unused[8] = spare_flops_q[8]; | |
1465 | assign spare_flops_unused[7] = spare_flops_q[7]; | |
1466 | assign spare6_flop_q = spare_flops_q[6]; | |
1467 | assign spare_flops_unused[5] = spare_flops_q[5]; | |
1468 | assign spare4_flop_q = spare_flops_q[4]; | |
1469 | assign spare_flops_unused[3] = spare_flops_q[3]; | |
1470 | assign spare_flops_unused[2] = spare_flops_q[2]; | |
1471 | assign spare_flops_unused[1] = spare_flops_q[1]; | |
1472 | assign spare_flops_unused[0] = spare_flops_q[0]; | |
1473 | ||
1474 | assign spare4_flop_d = tcu_int_ce_to_ucb; // ECO A | |
1475 | assign tcu_int_ce_ucb = spare4_flop_q & ~ac_test_mode; // ECO A | |
1476 | ||
1477 | assign spare6_flop_d = jtagclkstop_ov_d; // ECO B | |
1478 | assign jtagclkstop_ov = spare6_flop_q; // ECO B | |
1479 | ||
1480 | // ---------------------------------------------------------------------- | |
1481 | ||
1482 | // fixscan start: | |
1483 | assign tcuregs_ttcounter_reg_scanin = scan_in ; | |
1484 | assign tcuregs_ttstart_reg_scanin = tcuregs_ttcounter_reg_scanout; | |
1485 | assign tcuregs_cmpiosync_reg_scanin = tcuregs_ttstart_reg_scanout; //tcuregs_ttcounter_reg_scanout; | |
1486 | assign ucb_csr_wr_sync_reg_scanin = tcuregs_cmpiosync_reg_scanout; | |
1487 | assign ff_debug_event_hard_stop_scanin = ucb_csr_wr_sync_reg_scanout; | |
1488 | assign rstend_reg_scanin = ff_debug_event_hard_stop_scanout; | |
1489 | assign spc_hs_req_stg_reg_scanin = rstend_reg_scanout; | |
1490 | assign spchsreq_reg_scanin = spc_hs_req_stg_reg_scanout; | |
1491 | assign tcu_dbg_ctl_scan_in = spchsreq_reg_scanout; | |
1492 | assign dossen_reg_scanin = tcu_dbg_ctl_scan_out; | |
1493 | assign dossmode_reg_scanin = dossen_reg_scanout; | |
1494 | assign spc_ss_complete_stg_reg_scanin = dossmode_reg_scanout; | |
1495 | assign spcsscomp_reg_scanin = spc_ss_complete_stg_reg_scanout; | |
1496 | assign spc_ss_req_stg_reg_scanin = spcsscomp_reg_scanout; | |
1497 | assign spcssreq_reg_scanin = spc_ss_req_stg_reg_scanout; | |
1498 | assign spcrstat_reg_scanin = spcssreq_reg_scanout; | |
1499 | assign spc_tp_req_stg_reg_scanin = spcrstat_reg_scanout; | |
1500 | assign spctp_reg_scanin = spc_tp_req_stg_reg_scanout; | |
1501 | assign clkdomain_upd_sync_reg_scanin = spctp_reg_scanout; | |
1502 | assign coresel_upd_sync_reg_scanin = clkdomain_upd_sync_reg_scanout; | |
1503 | assign decnt_upd_sync_reg_scanin = coresel_upd_sync_reg_scanout; | |
1504 | assign cyccnt_upd_sync_reg_scanin = decnt_upd_sync_reg_scanout; | |
1505 | assign tcudcr_upd_sync_reg_scanin = cyccnt_upd_sync_reg_scanout; | |
1506 | assign dossen_upd_sync_reg_scanin = tcudcr_upd_sync_reg_scanout; | |
1507 | assign dossmode_upd_sync_reg_scanin = dossen_upd_sync_reg_scanout; | |
1508 | assign ssreq_upd_sync_reg_scanin = dossmode_upd_sync_reg_scanout; | |
1509 | assign csmode_upd_sync_reg_scanin = ssreq_upd_sync_reg_scanout; | |
1510 | assign jtagserscan_sync_reg_scanin = csmode_upd_sync_reg_scanout; | |
1511 | assign testprotect_sync_reg_scanin = jtagserscan_sync_reg_scanout; | |
1512 | assign testprotect_reg_scanin = testprotect_sync_reg_scanout; | |
1513 | assign tcuregs_mtmode_syncreg_scanin = testprotect_reg_scanout; | |
1514 | assign tcuregs_l2dataupd_syncreg_scanin = tcuregs_mtmode_syncreg_scanout; | |
1515 | assign tcuregs_l2addrupd_syncreg_scanin = tcuregs_l2dataupd_syncreg_scanout; | |
1516 | assign tcuregs_l2rti_syncreg_scanin = tcuregs_l2addrupd_syncreg_scanout; | |
1517 | assign tcuregs_l2rd_syncreg_scanin = tcuregs_l2rti_syncreg_scanout; | |
1518 | assign tcuregs_l2wr_syncreg_scanin = tcuregs_l2rd_syncreg_scanout; | |
1519 | assign tcuregs_l2data_reg_scanin = tcuregs_l2wr_syncreg_scanout; | |
1520 | assign tcuregs_l2addr_reg_scanin = tcuregs_l2data_reg_scanout; | |
1521 | assign tcuregs_tcu_sii_data_reg_scanin = tcuregs_l2addr_reg_scanout; | |
1522 | assign tcuregs_l2rti_reg_scanin = tcuregs_tcu_sii_data_reg_scanout; | |
1523 | assign tcuregs_tcu_sii_vld_reg_scanin = tcuregs_l2rti_reg_scanout; | |
1524 | assign tcuregs_l2siovld_reg_scanin = tcuregs_tcu_sii_vld_reg_scanout; | |
1525 | assign tcuregs_l2cntr_reg_scanin = tcuregs_l2siovld_reg_scanout; | |
1526 | assign spare_flops_scanin = tcuregs_l2cntr_reg_scanout; | |
1527 | assign scan_out = spare_flops_scanout; | |
1528 | // fixscan end: | |
1529 | ||
1530 | endmodule | |
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | // any PARAMS parms go into naming of macro | |
1538 | ||
1539 | module tcu_regs_ctl_l1clkhdr_ctl_macro ( | |
1540 | l2clk, | |
1541 | l1en, | |
1542 | pce_ov, | |
1543 | stop, | |
1544 | se, | |
1545 | l1clk); | |
1546 | ||
1547 | ||
1548 | input l2clk; | |
1549 | input l1en; | |
1550 | input pce_ov; | |
1551 | input stop; | |
1552 | input se; | |
1553 | output l1clk; | |
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | ||
1559 | cl_sc1_l1hdr_8x c_0 ( | |
1560 | ||
1561 | ||
1562 | .l2clk(l2clk), | |
1563 | .pce(l1en), | |
1564 | .l1clk(l1clk), | |
1565 | .se(se), | |
1566 | .pce_ov(pce_ov), | |
1567 | .stop(stop) | |
1568 | ); | |
1569 | ||
1570 | ||
1571 | ||
1572 | endmodule | |
1573 | ||
1574 | ||
1575 | ||
1576 | ||
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | // any PARAMS parms go into naming of macro | |
1587 | ||
1588 | module tcu_regs_ctl_msff_ctl_macro__width_3 ( | |
1589 | din, | |
1590 | l1clk, | |
1591 | scan_in, | |
1592 | siclk, | |
1593 | soclk, | |
1594 | dout, | |
1595 | scan_out); | |
1596 | wire [2:0] fdin; | |
1597 | wire [1:0] so; | |
1598 | ||
1599 | input [2:0] din; | |
1600 | input l1clk; | |
1601 | input scan_in; | |
1602 | ||
1603 | ||
1604 | input siclk; | |
1605 | input soclk; | |
1606 | ||
1607 | output [2:0] dout; | |
1608 | output scan_out; | |
1609 | assign fdin[2:0] = din[2:0]; | |
1610 | ||
1611 | ||
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | dff #(3) d0_0 ( | |
1617 | .l1clk(l1clk), | |
1618 | .siclk(siclk), | |
1619 | .soclk(soclk), | |
1620 | .d(fdin[2:0]), | |
1621 | .si({scan_in,so[1:0]}), | |
1622 | .so({so[1:0],scan_out}), | |
1623 | .q(dout[2:0]) | |
1624 | ); | |
1625 | ||
1626 | ||
1627 | ||
1628 | ||
1629 | ||
1630 | ||
1631 | ||
1632 | ||
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | endmodule | |
1638 | ||
1639 | ||
1640 | ||
1641 | ||
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | // any PARAMS parms go into naming of macro | |
1652 | ||
1653 | module tcu_regs_ctl_msff_ctl_macro__en_1__width_1 ( | |
1654 | din, | |
1655 | en, | |
1656 | l1clk, | |
1657 | scan_in, | |
1658 | siclk, | |
1659 | soclk, | |
1660 | dout, | |
1661 | scan_out); | |
1662 | wire [0:0] fdin; | |
1663 | ||
1664 | input [0:0] din; | |
1665 | input en; | |
1666 | input l1clk; | |
1667 | input scan_in; | |
1668 | ||
1669 | ||
1670 | input siclk; | |
1671 | input soclk; | |
1672 | ||
1673 | output [0:0] dout; | |
1674 | output scan_out; | |
1675 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | dff #(1) d0_0 ( | |
1683 | .l1clk(l1clk), | |
1684 | .siclk(siclk), | |
1685 | .soclk(soclk), | |
1686 | .d(fdin[0:0]), | |
1687 | .si(scan_in), | |
1688 | .so(scan_out), | |
1689 | .q(dout[0:0]) | |
1690 | ); | |
1691 | ||
1692 | ||
1693 | ||
1694 | ||
1695 | ||
1696 | ||
1697 | ||
1698 | ||
1699 | ||
1700 | ||
1701 | ||
1702 | ||
1703 | endmodule | |
1704 | ||
1705 | ||
1706 | ||
1707 | ||
1708 | ||
1709 | ||
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | ||
1716 | ||
1717 | // any PARAMS parms go into naming of macro | |
1718 | ||
1719 | module tcu_regs_ctl_msff_ctl_macro__en_1__width_8 ( | |
1720 | din, | |
1721 | en, | |
1722 | l1clk, | |
1723 | scan_in, | |
1724 | siclk, | |
1725 | soclk, | |
1726 | dout, | |
1727 | scan_out); | |
1728 | wire [7:0] fdin; | |
1729 | wire [6:0] so; | |
1730 | ||
1731 | input [7:0] din; | |
1732 | input en; | |
1733 | input l1clk; | |
1734 | input scan_in; | |
1735 | ||
1736 | ||
1737 | input siclk; | |
1738 | input soclk; | |
1739 | ||
1740 | output [7:0] dout; | |
1741 | output scan_out; | |
1742 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
1743 | ||
1744 | ||
1745 | ||
1746 | ||
1747 | ||
1748 | ||
1749 | dff #(8) d0_0 ( | |
1750 | .l1clk(l1clk), | |
1751 | .siclk(siclk), | |
1752 | .soclk(soclk), | |
1753 | .d(fdin[7:0]), | |
1754 | .si({scan_in,so[6:0]}), | |
1755 | .so({so[6:0],scan_out}), | |
1756 | .q(dout[7:0]) | |
1757 | ); | |
1758 | ||
1759 | ||
1760 | ||
1761 | ||
1762 | ||
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | ||
1770 | endmodule | |
1771 | ||
1772 | ||
1773 | ||
1774 | ||
1775 | ||
1776 | ||
1777 | ||
1778 | ||
1779 | ||
1780 | ||
1781 | ||
1782 | ||
1783 | ||
1784 | // any PARAMS parms go into naming of macro | |
1785 | ||
1786 | module tcu_regs_ctl_msff_ctl_macro__width_1 ( | |
1787 | din, | |
1788 | l1clk, | |
1789 | scan_in, | |
1790 | siclk, | |
1791 | soclk, | |
1792 | dout, | |
1793 | scan_out); | |
1794 | wire [0:0] fdin; | |
1795 | ||
1796 | input [0:0] din; | |
1797 | input l1clk; | |
1798 | input scan_in; | |
1799 | ||
1800 | ||
1801 | input siclk; | |
1802 | input soclk; | |
1803 | ||
1804 | output [0:0] dout; | |
1805 | output scan_out; | |
1806 | assign fdin[0:0] = din[0:0]; | |
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | dff #(1) d0_0 ( | |
1814 | .l1clk(l1clk), | |
1815 | .siclk(siclk), | |
1816 | .soclk(soclk), | |
1817 | .d(fdin[0:0]), | |
1818 | .si(scan_in), | |
1819 | .so(scan_out), | |
1820 | .q(dout[0:0]) | |
1821 | ); | |
1822 | ||
1823 | ||
1824 | ||
1825 | ||
1826 | ||
1827 | ||
1828 | ||
1829 | ||
1830 | ||
1831 | ||
1832 | ||
1833 | ||
1834 | endmodule | |
1835 | ||
1836 | ||
1837 | ||
1838 | ||
1839 | ||
1840 | ||
1841 | ||
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | ||
1847 | ||
1848 | // any PARAMS parms go into naming of macro | |
1849 | ||
1850 | module tcu_regs_ctl_msff_ctl_macro__width_24 ( | |
1851 | din, | |
1852 | l1clk, | |
1853 | scan_in, | |
1854 | siclk, | |
1855 | soclk, | |
1856 | dout, | |
1857 | scan_out); | |
1858 | wire [23:0] fdin; | |
1859 | wire [22:0] so; | |
1860 | ||
1861 | input [23:0] din; | |
1862 | input l1clk; | |
1863 | input scan_in; | |
1864 | ||
1865 | ||
1866 | input siclk; | |
1867 | input soclk; | |
1868 | ||
1869 | output [23:0] dout; | |
1870 | output scan_out; | |
1871 | assign fdin[23:0] = din[23:0]; | |
1872 | ||
1873 | ||
1874 | ||
1875 | ||
1876 | ||
1877 | ||
1878 | dff #(24) d0_0 ( | |
1879 | .l1clk(l1clk), | |
1880 | .siclk(siclk), | |
1881 | .soclk(soclk), | |
1882 | .d(fdin[23:0]), | |
1883 | .si({scan_in,so[22:0]}), | |
1884 | .so({so[22:0],scan_out}), | |
1885 | .q(dout[23:0]) | |
1886 | ); | |
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | ||
1896 | ||
1897 | ||
1898 | ||
1899 | endmodule | |
1900 | ||
1901 | ||
1902 | ||
1903 | ||
1904 | ||
1905 | ||
1906 | ||
1907 | ||
1908 | ||
1909 | ||
1910 | ||
1911 | ||
1912 | ||
1913 | // any PARAMS parms go into naming of macro | |
1914 | ||
1915 | module tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_2 ( | |
1916 | din, | |
1917 | en, | |
1918 | clr, | |
1919 | l1clk, | |
1920 | scan_in, | |
1921 | siclk, | |
1922 | soclk, | |
1923 | dout, | |
1924 | scan_out); | |
1925 | wire [1:0] fdin; | |
1926 | wire [0:0] so; | |
1927 | ||
1928 | input [1:0] din; | |
1929 | input en; | |
1930 | input clr; | |
1931 | input l1clk; | |
1932 | input scan_in; | |
1933 | ||
1934 | ||
1935 | input siclk; | |
1936 | input soclk; | |
1937 | ||
1938 | output [1:0] dout; | |
1939 | output scan_out; | |
1940 | assign fdin[1:0] = (din[1:0] & {2{en}} & ~{2{clr}}) | (dout[1:0] & ~{2{en}} & ~{2{clr}}); | |
1941 | ||
1942 | ||
1943 | ||
1944 | ||
1945 | ||
1946 | ||
1947 | dff #(2) d0_0 ( | |
1948 | .l1clk(l1clk), | |
1949 | .siclk(siclk), | |
1950 | .soclk(soclk), | |
1951 | .d(fdin[1:0]), | |
1952 | .si({scan_in,so[0:0]}), | |
1953 | .so({so[0:0],scan_out}), | |
1954 | .q(dout[1:0]) | |
1955 | ); | |
1956 | ||
1957 | ||
1958 | ||
1959 | ||
1960 | ||
1961 | ||
1962 | ||
1963 | ||
1964 | ||
1965 | ||
1966 | ||
1967 | ||
1968 | endmodule | |
1969 | ||
1970 | ||
1971 | ||
1972 | ||
1973 | ||
1974 | ||
1975 | ||
1976 | ||
1977 | ||
1978 | ||
1979 | ||
1980 | ||
1981 | ||
1982 | // any PARAMS parms go into naming of macro | |
1983 | ||
1984 | module tcu_regs_ctl_msff_ctl_macro__width_6 ( | |
1985 | din, | |
1986 | l1clk, | |
1987 | scan_in, | |
1988 | siclk, | |
1989 | soclk, | |
1990 | dout, | |
1991 | scan_out); | |
1992 | wire [5:0] fdin; | |
1993 | wire [4:0] so; | |
1994 | ||
1995 | input [5:0] din; | |
1996 | input l1clk; | |
1997 | input scan_in; | |
1998 | ||
1999 | ||
2000 | input siclk; | |
2001 | input soclk; | |
2002 | ||
2003 | output [5:0] dout; | |
2004 | output scan_out; | |
2005 | assign fdin[5:0] = din[5:0]; | |
2006 | ||
2007 | ||
2008 | ||
2009 | ||
2010 | ||
2011 | ||
2012 | dff #(6) d0_0 ( | |
2013 | .l1clk(l1clk), | |
2014 | .siclk(siclk), | |
2015 | .soclk(soclk), | |
2016 | .d(fdin[5:0]), | |
2017 | .si({scan_in,so[4:0]}), | |
2018 | .so({so[4:0],scan_out}), | |
2019 | .q(dout[5:0]) | |
2020 | ); | |
2021 | ||
2022 | ||
2023 | ||
2024 | ||
2025 | ||
2026 | ||
2027 | ||
2028 | ||
2029 | ||
2030 | ||
2031 | ||
2032 | ||
2033 | endmodule | |
2034 | ||
2035 | ||
2036 | ||
2037 | ||
2038 | ||
2039 | ||
2040 | ||
2041 | ||
2042 | ||
2043 | ||
2044 | ||
2045 | ||
2046 | ||
2047 | // any PARAMS parms go into naming of macro | |
2048 | ||
2049 | module tcu_regs_ctl_msff_ctl_macro__clr_1__en_1__width_8 ( | |
2050 | din, | |
2051 | en, | |
2052 | clr, | |
2053 | l1clk, | |
2054 | scan_in, | |
2055 | siclk, | |
2056 | soclk, | |
2057 | dout, | |
2058 | scan_out); | |
2059 | wire [7:0] fdin; | |
2060 | wire [6:0] so; | |
2061 | ||
2062 | input [7:0] din; | |
2063 | input en; | |
2064 | input clr; | |
2065 | input l1clk; | |
2066 | input scan_in; | |
2067 | ||
2068 | ||
2069 | input siclk; | |
2070 | input soclk; | |
2071 | ||
2072 | output [7:0] dout; | |
2073 | output scan_out; | |
2074 | assign fdin[7:0] = (din[7:0] & {8{en}} & ~{8{clr}}) | (dout[7:0] & ~{8{en}} & ~{8{clr}}); | |
2075 | ||
2076 | ||
2077 | ||
2078 | ||
2079 | ||
2080 | ||
2081 | dff #(8) d0_0 ( | |
2082 | .l1clk(l1clk), | |
2083 | .siclk(siclk), | |
2084 | .soclk(soclk), | |
2085 | .d(fdin[7:0]), | |
2086 | .si({scan_in,so[6:0]}), | |
2087 | .so({so[6:0],scan_out}), | |
2088 | .q(dout[7:0]) | |
2089 | ); | |
2090 | ||
2091 | ||
2092 | ||
2093 | ||
2094 | ||
2095 | ||
2096 | ||
2097 | ||
2098 | ||
2099 | ||
2100 | ||
2101 | ||
2102 | endmodule | |
2103 | ||
2104 | ||
2105 | ||
2106 | ||
2107 | ||
2108 | ||
2109 | ||
2110 | ||
2111 | ||
2112 | ||
2113 | ||
2114 | ||
2115 | ||
2116 | // any PARAMS parms go into naming of macro | |
2117 | ||
2118 | module tcu_regs_ctl_msff_ctl_macro__width_64 ( | |
2119 | din, | |
2120 | l1clk, | |
2121 | scan_in, | |
2122 | siclk, | |
2123 | soclk, | |
2124 | dout, | |
2125 | scan_out); | |
2126 | wire [63:0] fdin; | |
2127 | wire [62:0] so; | |
2128 | ||
2129 | input [63:0] din; | |
2130 | input l1clk; | |
2131 | input scan_in; | |
2132 | ||
2133 | ||
2134 | input siclk; | |
2135 | input soclk; | |
2136 | ||
2137 | output [63:0] dout; | |
2138 | output scan_out; | |
2139 | assign fdin[63:0] = din[63:0]; | |
2140 | ||
2141 | ||
2142 | ||
2143 | ||
2144 | ||
2145 | ||
2146 | dff #(64) d0_0 ( | |
2147 | .l1clk(l1clk), | |
2148 | .siclk(siclk), | |
2149 | .soclk(soclk), | |
2150 | .d(fdin[63:0]), | |
2151 | .si({scan_in,so[62:0]}), | |
2152 | .so({so[62:0],scan_out}), | |
2153 | .q(dout[63:0]) | |
2154 | ); | |
2155 | ||
2156 | ||
2157 | ||
2158 | ||
2159 | ||
2160 | ||
2161 | ||
2162 | ||
2163 | ||
2164 | ||
2165 | ||
2166 | ||
2167 | endmodule | |
2168 | ||
2169 | ||
2170 | ||
2171 | ||
2172 | ||
2173 | ||
2174 | ||
2175 | ||
2176 | ||
2177 | ||
2178 | ||
2179 | ||
2180 | ||
2181 | // any PARAMS parms go into naming of macro | |
2182 | ||
2183 | module tcu_regs_ctl_msff_ctl_macro__en_1__width_2 ( | |
2184 | din, | |
2185 | en, | |
2186 | l1clk, | |
2187 | scan_in, | |
2188 | siclk, | |
2189 | soclk, | |
2190 | dout, | |
2191 | scan_out); | |
2192 | wire [1:0] fdin; | |
2193 | wire [0:0] so; | |
2194 | ||
2195 | input [1:0] din; | |
2196 | input en; | |
2197 | input l1clk; | |
2198 | input scan_in; | |
2199 | ||
2200 | ||
2201 | input siclk; | |
2202 | input soclk; | |
2203 | ||
2204 | output [1:0] dout; | |
2205 | output scan_out; | |
2206 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
2207 | ||
2208 | ||
2209 | ||
2210 | ||
2211 | ||
2212 | ||
2213 | dff #(2) d0_0 ( | |
2214 | .l1clk(l1clk), | |
2215 | .siclk(siclk), | |
2216 | .soclk(soclk), | |
2217 | .d(fdin[1:0]), | |
2218 | .si({scan_in,so[0:0]}), | |
2219 | .so({so[0:0],scan_out}), | |
2220 | .q(dout[1:0]) | |
2221 | ); | |
2222 | ||
2223 | ||
2224 | ||
2225 | ||
2226 | ||
2227 | ||
2228 | ||
2229 | ||
2230 | ||
2231 | ||
2232 | ||
2233 | ||
2234 | endmodule | |
2235 | ||
2236 | ||
2237 | ||
2238 | ||
2239 | ||
2240 | ||
2241 | ||
2242 | ||
2243 | ||
2244 | ||
2245 | ||
2246 | ||
2247 | ||
2248 | // any PARAMS parms go into naming of macro | |
2249 | ||
2250 | module tcu_regs_ctl_msff_ctl_macro__en_1__width_64 ( | |
2251 | din, | |
2252 | en, | |
2253 | l1clk, | |
2254 | scan_in, | |
2255 | siclk, | |
2256 | soclk, | |
2257 | dout, | |
2258 | scan_out); | |
2259 | wire [63:0] fdin; | |
2260 | wire [62:0] so; | |
2261 | ||
2262 | input [63:0] din; | |
2263 | input en; | |
2264 | input l1clk; | |
2265 | input scan_in; | |
2266 | ||
2267 | ||
2268 | input siclk; | |
2269 | input soclk; | |
2270 | ||
2271 | output [63:0] dout; | |
2272 | output scan_out; | |
2273 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); | |
2274 | ||
2275 | ||
2276 | ||
2277 | ||
2278 | ||
2279 | ||
2280 | dff #(64) d0_0 ( | |
2281 | .l1clk(l1clk), | |
2282 | .siclk(siclk), | |
2283 | .soclk(soclk), | |
2284 | .d(fdin[63:0]), | |
2285 | .si({scan_in,so[62:0]}), | |
2286 | .so({so[62:0],scan_out}), | |
2287 | .q(dout[63:0]) | |
2288 | ); | |
2289 | ||
2290 | ||
2291 | ||
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | ||
2297 | ||
2298 | ||
2299 | ||
2300 | ||
2301 | endmodule | |
2302 | ||
2303 | ||
2304 | ||
2305 | ||
2306 | ||
2307 | // any PARAMS parms go into naming of macro | |
2308 | ||
2309 | module tcu_regs_ctl_msff_ctl_macro__width_4 ( | |
2310 | din, | |
2311 | l1clk, | |
2312 | scan_in, | |
2313 | siclk, | |
2314 | soclk, | |
2315 | dout, | |
2316 | scan_out); | |
2317 | wire [3:0] fdin; | |
2318 | wire [2:0] so; | |
2319 | ||
2320 | input [3:0] din; | |
2321 | input l1clk; | |
2322 | input scan_in; | |
2323 | ||
2324 | ||
2325 | input siclk; | |
2326 | input soclk; | |
2327 | ||
2328 | output [3:0] dout; | |
2329 | output scan_out; | |
2330 | assign fdin[3:0] = din[3:0]; | |
2331 | ||
2332 | ||
2333 | ||
2334 | ||
2335 | ||
2336 | ||
2337 | dff #(4) d0_0 ( | |
2338 | .l1clk(l1clk), | |
2339 | .siclk(siclk), | |
2340 | .soclk(soclk), | |
2341 | .d(fdin[3:0]), | |
2342 | .si({scan_in,so[2:0]}), | |
2343 | .so({so[2:0],scan_out}), | |
2344 | .q(dout[3:0]) | |
2345 | ); | |
2346 | ||
2347 | ||
2348 | ||
2349 | ||
2350 | ||
2351 | ||
2352 | ||
2353 | ||
2354 | ||
2355 | ||
2356 | ||
2357 | ||
2358 | endmodule | |
2359 | ||
2360 | ||
2361 | ||
2362 | ||
2363 | ||
2364 | ||
2365 | ||
2366 | ||
2367 | ||
2368 | ||
2369 | ||
2370 | ||
2371 | ||
2372 | // any PARAMS parms go into naming of macro | |
2373 | ||
2374 | module tcu_regs_ctl_msff_ctl_macro__width_32 ( | |
2375 | din, | |
2376 | l1clk, | |
2377 | scan_in, | |
2378 | siclk, | |
2379 | soclk, | |
2380 | dout, | |
2381 | scan_out); | |
2382 | wire [31:0] fdin; | |
2383 | wire [30:0] so; | |
2384 | ||
2385 | input [31:0] din; | |
2386 | input l1clk; | |
2387 | input scan_in; | |
2388 | ||
2389 | ||
2390 | input siclk; | |
2391 | input soclk; | |
2392 | ||
2393 | output [31:0] dout; | |
2394 | output scan_out; | |
2395 | assign fdin[31:0] = din[31:0]; | |
2396 | ||
2397 | ||
2398 | ||
2399 | ||
2400 | ||
2401 | ||
2402 | dff #(32) d0_0 ( | |
2403 | .l1clk(l1clk), | |
2404 | .siclk(siclk), | |
2405 | .soclk(soclk), | |
2406 | .d(fdin[31:0]), | |
2407 | .si({scan_in,so[30:0]}), | |
2408 | .so({so[30:0],scan_out}), | |
2409 | .q(dout[31:0]) | |
2410 | ); | |
2411 | ||
2412 | ||
2413 | ||
2414 | ||
2415 | ||
2416 | ||
2417 | ||
2418 | ||
2419 | ||
2420 | ||
2421 | ||
2422 | ||
2423 | endmodule | |
2424 | ||
2425 | ||
2426 | ||
2427 | ||
2428 | ||
2429 | ||
2430 | ||
2431 | ||
2432 | ||
2433 | ||
2434 | ||
2435 | ||
2436 | ||
2437 | // any PARAMS parms go into naming of macro | |
2438 | ||
2439 | module tcu_regs_ctl_msff_ctl_macro__en_1__width_4 ( | |
2440 | din, | |
2441 | en, | |
2442 | l1clk, | |
2443 | scan_in, | |
2444 | siclk, | |
2445 | soclk, | |
2446 | dout, | |
2447 | scan_out); | |
2448 | wire [3:0] fdin; | |
2449 | wire [2:0] so; | |
2450 | ||
2451 | input [3:0] din; | |
2452 | input en; | |
2453 | input l1clk; | |
2454 | input scan_in; | |
2455 | ||
2456 | ||
2457 | input siclk; | |
2458 | input soclk; | |
2459 | ||
2460 | output [3:0] dout; | |
2461 | output scan_out; | |
2462 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
2463 | ||
2464 | ||
2465 | ||
2466 | ||
2467 | ||
2468 | ||
2469 | dff #(4) d0_0 ( | |
2470 | .l1clk(l1clk), | |
2471 | .siclk(siclk), | |
2472 | .soclk(soclk), | |
2473 | .d(fdin[3:0]), | |
2474 | .si({scan_in,so[2:0]}), | |
2475 | .so({so[2:0],scan_out}), | |
2476 | .q(dout[3:0]) | |
2477 | ); | |
2478 | ||
2479 | ||
2480 | ||
2481 | ||
2482 | ||
2483 | ||
2484 | ||
2485 | ||
2486 | ||
2487 | ||
2488 | ||
2489 | ||
2490 | endmodule | |
2491 | ||
2492 | ||
2493 | ||
2494 | ||
2495 | ||
2496 | ||
2497 | ||
2498 | ||
2499 | ||
2500 | ||
2501 | ||
2502 | ||
2503 | ||
2504 | // any PARAMS parms go into naming of macro | |
2505 | ||
2506 | module tcu_regs_ctl_msff_ctl_macro__width_8 ( | |
2507 | din, | |
2508 | l1clk, | |
2509 | scan_in, | |
2510 | siclk, | |
2511 | soclk, | |
2512 | dout, | |
2513 | scan_out); | |
2514 | wire [7:0] fdin; | |
2515 | wire [6:0] so; | |
2516 | ||
2517 | input [7:0] din; | |
2518 | input l1clk; | |
2519 | input scan_in; | |
2520 | ||
2521 | ||
2522 | input siclk; | |
2523 | input soclk; | |
2524 | ||
2525 | output [7:0] dout; | |
2526 | output scan_out; | |
2527 | assign fdin[7:0] = din[7:0]; | |
2528 | ||
2529 | ||
2530 | ||
2531 | ||
2532 | ||
2533 | ||
2534 | dff #(8) d0_0 ( | |
2535 | .l1clk(l1clk), | |
2536 | .siclk(siclk), | |
2537 | .soclk(soclk), | |
2538 | .d(fdin[7:0]), | |
2539 | .si({scan_in,so[6:0]}), | |
2540 | .so({so[6:0],scan_out}), | |
2541 | .q(dout[7:0]) | |
2542 | ); | |
2543 | ||
2544 | ||
2545 | ||
2546 | ||
2547 | ||
2548 | ||
2549 | ||
2550 | ||
2551 | ||
2552 | ||
2553 | ||
2554 | ||
2555 | endmodule | |
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | ||
2562 | ||
2563 | ||
2564 | ||
2565 | ||
2566 | ||
2567 | ||
2568 | ||
2569 | // any PARAMS parms go into naming of macro | |
2570 | ||
2571 | module tcu_regs_ctl_msff_ctl_macro__clr__1__en_1__width_8 ( | |
2572 | din, | |
2573 | en, | |
2574 | clr_, | |
2575 | l1clk, | |
2576 | scan_in, | |
2577 | siclk, | |
2578 | soclk, | |
2579 | dout, | |
2580 | scan_out); | |
2581 | wire [7:0] fdin; | |
2582 | wire [6:0] so; | |
2583 | ||
2584 | input [7:0] din; | |
2585 | input en; | |
2586 | input clr_; | |
2587 | input l1clk; | |
2588 | input scan_in; | |
2589 | ||
2590 | ||
2591 | input siclk; | |
2592 | input soclk; | |
2593 | ||
2594 | output [7:0] dout; | |
2595 | output scan_out; | |
2596 | assign fdin[7:0] = (din[7:0] & {8{en}} & ~{8{(~clr_)}}) | (dout[7:0] & ~{8{en}} & ~{8{(~clr_)}}); | |
2597 | ||
2598 | ||
2599 | ||
2600 | ||
2601 | ||
2602 | ||
2603 | dff #(8) d0_0 ( | |
2604 | .l1clk(l1clk), | |
2605 | .siclk(siclk), | |
2606 | .soclk(soclk), | |
2607 | .d(fdin[7:0]), | |
2608 | .si({scan_in,so[6:0]}), | |
2609 | .so({so[6:0],scan_out}), | |
2610 | .q(dout[7:0]) | |
2611 | ); | |
2612 | ||
2613 | ||
2614 | ||
2615 | ||
2616 | ||
2617 | ||
2618 | ||
2619 | ||
2620 | ||
2621 | ||
2622 | ||
2623 | ||
2624 | endmodule | |
2625 | ||
2626 | ||
2627 | ||
2628 | ||
2629 | ||
2630 | ||
2631 | ||
2632 | ||
2633 | ||
2634 | ||
2635 | ||
2636 | ||
2637 | ||
2638 | // any PARAMS parms go into naming of macro | |
2639 | ||
2640 | module tcu_regs_ctl_msff_ctl_macro__clr__1__en_1__width_1 ( | |
2641 | din, | |
2642 | en, | |
2643 | clr_, | |
2644 | l1clk, | |
2645 | scan_in, | |
2646 | siclk, | |
2647 | soclk, | |
2648 | dout, | |
2649 | scan_out); | |
2650 | wire [0:0] fdin; | |
2651 | ||
2652 | input [0:0] din; | |
2653 | input en; | |
2654 | input clr_; | |
2655 | input l1clk; | |
2656 | input scan_in; | |
2657 | ||
2658 | ||
2659 | input siclk; | |
2660 | input soclk; | |
2661 | ||
2662 | output [0:0] dout; | |
2663 | output scan_out; | |
2664 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{(~clr_)}}) | (dout[0:0] & ~{1{en}} & ~{1{(~clr_)}}); | |
2665 | ||
2666 | ||
2667 | ||
2668 | ||
2669 | ||
2670 | ||
2671 | dff #(1) d0_0 ( | |
2672 | .l1clk(l1clk), | |
2673 | .siclk(siclk), | |
2674 | .soclk(soclk), | |
2675 | .d(fdin[0:0]), | |
2676 | .si(scan_in), | |
2677 | .so(scan_out), | |
2678 | .q(dout[0:0]) | |
2679 | ); | |
2680 | ||
2681 | ||
2682 | ||
2683 | ||
2684 | ||
2685 | ||
2686 | ||
2687 | ||
2688 | ||
2689 | ||
2690 | ||
2691 | ||
2692 | endmodule | |
2693 | ||
2694 | ||
2695 | ||
2696 | ||
2697 | ||
2698 | ||
2699 | ||
2700 | ||
2701 | ||
2702 | ||
2703 | ||
2704 | ||
2705 | ||
2706 | // any PARAMS parms go into naming of macro | |
2707 | ||
2708 | module tcu_regs_ctl_msff_ctl_macro__clr__1__width_7 ( | |
2709 | din, | |
2710 | clr_, | |
2711 | l1clk, | |
2712 | scan_in, | |
2713 | siclk, | |
2714 | soclk, | |
2715 | dout, | |
2716 | scan_out); | |
2717 | wire [6:0] fdin; | |
2718 | wire [5:0] so; | |
2719 | ||
2720 | input [6:0] din; | |
2721 | input clr_; | |
2722 | input l1clk; | |
2723 | input scan_in; | |
2724 | ||
2725 | ||
2726 | input siclk; | |
2727 | input soclk; | |
2728 | ||
2729 | output [6:0] dout; | |
2730 | output scan_out; | |
2731 | assign fdin[6:0] = din[6:0] & ~{7{(~clr_)}}; | |
2732 | ||
2733 | ||
2734 | ||
2735 | ||
2736 | ||
2737 | ||
2738 | dff #(7) d0_0 ( | |
2739 | .l1clk(l1clk), | |
2740 | .siclk(siclk), | |
2741 | .soclk(soclk), | |
2742 | .d(fdin[6:0]), | |
2743 | .si({scan_in,so[5:0]}), | |
2744 | .so({so[5:0],scan_out}), | |
2745 | .q(dout[6:0]) | |
2746 | ); | |
2747 | ||
2748 | ||
2749 | ||
2750 | ||
2751 | ||
2752 | ||
2753 | ||
2754 | ||
2755 | ||
2756 | ||
2757 | ||
2758 | ||
2759 | endmodule | |
2760 | ||
2761 | ||
2762 | ||
2763 | ||
2764 | ||
2765 | ||
2766 | ||
2767 | ||
2768 | ||
2769 | // Description: Spare gate macro for control blocks | |
2770 | // | |
2771 | // Param num controls the number of times the macro is added | |
2772 | // flops=0 can be used to use only combination spare logic | |
2773 | ||
2774 | ||
2775 | module tcu_regs_ctl_spare_ctl_macro__flops_0__num_9; | |
2776 | wire spare0_buf_32x_unused; | |
2777 | wire spare0_nand3_8x_unused; | |
2778 | wire spare0_inv_8x_unused; | |
2779 | wire spare0_aoi22_4x_unused; | |
2780 | wire spare0_buf_8x_unused; | |
2781 | wire spare0_oai22_4x_unused; | |
2782 | wire spare0_inv_16x_unused; | |
2783 | wire spare0_nand2_16x_unused; | |
2784 | wire spare0_nor3_4x_unused; | |
2785 | wire spare0_nand2_8x_unused; | |
2786 | wire spare0_buf_16x_unused; | |
2787 | wire spare0_nor2_16x_unused; | |
2788 | wire spare0_inv_32x_unused; | |
2789 | wire spare1_buf_32x_unused; | |
2790 | wire spare1_nand3_8x_unused; | |
2791 | wire spare1_inv_8x_unused; | |
2792 | wire spare1_aoi22_4x_unused; | |
2793 | wire spare1_buf_8x_unused; | |
2794 | wire spare1_oai22_4x_unused; | |
2795 | wire spare1_inv_16x_unused; | |
2796 | wire spare1_nand2_16x_unused; | |
2797 | wire spare1_nor3_4x_unused; | |
2798 | wire spare1_nand2_8x_unused; | |
2799 | wire spare1_buf_16x_unused; | |
2800 | wire spare1_nor2_16x_unused; | |
2801 | wire spare1_inv_32x_unused; | |
2802 | wire spare2_buf_32x_unused; | |
2803 | wire spare2_nand3_8x_unused; | |
2804 | wire spare2_inv_8x_unused; | |
2805 | wire spare2_aoi22_4x_unused; | |
2806 | wire spare2_buf_8x_unused; | |
2807 | wire spare2_oai22_4x_unused; | |
2808 | wire spare2_inv_16x_unused; | |
2809 | wire spare2_nand2_16x_unused; | |
2810 | wire spare2_nor3_4x_unused; | |
2811 | wire spare2_nand2_8x_unused; | |
2812 | wire spare2_buf_16x_unused; | |
2813 | wire spare2_nor2_16x_unused; | |
2814 | wire spare2_inv_32x_unused; | |
2815 | wire spare3_buf_32x_unused; | |
2816 | wire spare3_nand3_8x_unused; | |
2817 | wire spare3_inv_8x_unused; | |
2818 | wire spare3_aoi22_4x_unused; | |
2819 | wire spare3_buf_8x_unused; | |
2820 | wire spare3_oai22_4x_unused; | |
2821 | wire spare3_inv_16x_unused; | |
2822 | wire spare3_nand2_16x_unused; | |
2823 | wire spare3_nor3_4x_unused; | |
2824 | wire spare3_nand2_8x_unused; | |
2825 | wire spare3_buf_16x_unused; | |
2826 | wire spare3_nor2_16x_unused; | |
2827 | wire spare3_inv_32x_unused; | |
2828 | wire spare4_buf_32x_unused; | |
2829 | wire spare4_nand3_8x_unused; | |
2830 | wire spare4_inv_8x_unused; | |
2831 | wire spare4_aoi22_4x_unused; | |
2832 | wire spare4_buf_8x_unused; | |
2833 | wire spare4_oai22_4x_unused; | |
2834 | wire spare4_inv_16x_unused; | |
2835 | wire spare4_nand2_16x_unused; | |
2836 | wire spare4_nor3_4x_unused; | |
2837 | wire spare4_nand2_8x_unused; | |
2838 | wire spare4_buf_16x_unused; | |
2839 | wire spare4_nor2_16x_unused; | |
2840 | wire spare4_inv_32x_unused; | |
2841 | wire spare5_buf_32x_unused; | |
2842 | wire spare5_nand3_8x_unused; | |
2843 | wire spare5_inv_8x_unused; | |
2844 | wire spare5_aoi22_4x_unused; | |
2845 | wire spare5_buf_8x_unused; | |
2846 | wire spare5_oai22_4x_unused; | |
2847 | wire spare5_inv_16x_unused; | |
2848 | wire spare5_nand2_16x_unused; | |
2849 | wire spare5_nor3_4x_unused; | |
2850 | wire spare5_nand2_8x_unused; | |
2851 | wire spare5_buf_16x_unused; | |
2852 | wire spare5_nor2_16x_unused; | |
2853 | wire spare5_inv_32x_unused; | |
2854 | wire spare6_buf_32x_unused; | |
2855 | wire spare6_nand3_8x_unused; | |
2856 | wire spare6_inv_8x_unused; | |
2857 | wire spare6_aoi22_4x_unused; | |
2858 | wire spare6_buf_8x_unused; | |
2859 | wire spare6_oai22_4x_unused; | |
2860 | wire spare6_inv_16x_unused; | |
2861 | wire spare6_nand2_16x_unused; | |
2862 | wire spare6_nor3_4x_unused; | |
2863 | wire spare6_nand2_8x_unused; | |
2864 | wire spare6_buf_16x_unused; | |
2865 | wire spare6_nor2_16x_unused; | |
2866 | wire spare6_inv_32x_unused; | |
2867 | wire spare7_buf_32x_unused; | |
2868 | wire spare7_nand3_8x_unused; | |
2869 | wire spare7_inv_8x_unused; | |
2870 | wire spare7_aoi22_4x_unused; | |
2871 | wire spare7_buf_8x_unused; | |
2872 | wire spare7_oai22_4x_unused; | |
2873 | wire spare7_inv_16x_unused; | |
2874 | wire spare7_nand2_16x_unused; | |
2875 | wire spare7_nor3_4x_unused; | |
2876 | wire spare7_nand2_8x_unused; | |
2877 | wire spare7_buf_16x_unused; | |
2878 | wire spare7_nor2_16x_unused; | |
2879 | wire spare7_inv_32x_unused; | |
2880 | wire spare8_buf_32x_unused; | |
2881 | wire spare8_nand3_8x_unused; | |
2882 | wire spare8_inv_8x_unused; | |
2883 | wire spare8_aoi22_4x_unused; | |
2884 | wire spare8_buf_8x_unused; | |
2885 | wire spare8_oai22_4x_unused; | |
2886 | wire spare8_inv_16x_unused; | |
2887 | wire spare8_nand2_16x_unused; | |
2888 | wire spare8_nor3_4x_unused; | |
2889 | wire spare8_nand2_8x_unused; | |
2890 | wire spare8_buf_16x_unused; | |
2891 | wire spare8_nor2_16x_unused; | |
2892 | wire spare8_inv_32x_unused; | |
2893 | ||
2894 | ||
2895 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
2896 | .out(spare0_buf_32x_unused)); | |
2897 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
2898 | .in1(1'b1), | |
2899 | .in2(1'b1), | |
2900 | .out(spare0_nand3_8x_unused)); | |
2901 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
2902 | .out(spare0_inv_8x_unused)); | |
2903 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
2904 | .in01(1'b1), | |
2905 | .in10(1'b1), | |
2906 | .in11(1'b1), | |
2907 | .out(spare0_aoi22_4x_unused)); | |
2908 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
2909 | .out(spare0_buf_8x_unused)); | |
2910 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
2911 | .in01(1'b1), | |
2912 | .in10(1'b1), | |
2913 | .in11(1'b1), | |
2914 | .out(spare0_oai22_4x_unused)); | |
2915 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
2916 | .out(spare0_inv_16x_unused)); | |
2917 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
2918 | .in1(1'b1), | |
2919 | .out(spare0_nand2_16x_unused)); | |
2920 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
2921 | .in1(1'b0), | |
2922 | .in2(1'b0), | |
2923 | .out(spare0_nor3_4x_unused)); | |
2924 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
2925 | .in1(1'b1), | |
2926 | .out(spare0_nand2_8x_unused)); | |
2927 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
2928 | .out(spare0_buf_16x_unused)); | |
2929 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
2930 | .in1(1'b0), | |
2931 | .out(spare0_nor2_16x_unused)); | |
2932 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
2933 | .out(spare0_inv_32x_unused)); | |
2934 | ||
2935 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
2936 | .out(spare1_buf_32x_unused)); | |
2937 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
2938 | .in1(1'b1), | |
2939 | .in2(1'b1), | |
2940 | .out(spare1_nand3_8x_unused)); | |
2941 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
2942 | .out(spare1_inv_8x_unused)); | |
2943 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
2944 | .in01(1'b1), | |
2945 | .in10(1'b1), | |
2946 | .in11(1'b1), | |
2947 | .out(spare1_aoi22_4x_unused)); | |
2948 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
2949 | .out(spare1_buf_8x_unused)); | |
2950 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
2951 | .in01(1'b1), | |
2952 | .in10(1'b1), | |
2953 | .in11(1'b1), | |
2954 | .out(spare1_oai22_4x_unused)); | |
2955 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
2956 | .out(spare1_inv_16x_unused)); | |
2957 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
2958 | .in1(1'b1), | |
2959 | .out(spare1_nand2_16x_unused)); | |
2960 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
2961 | .in1(1'b0), | |
2962 | .in2(1'b0), | |
2963 | .out(spare1_nor3_4x_unused)); | |
2964 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
2965 | .in1(1'b1), | |
2966 | .out(spare1_nand2_8x_unused)); | |
2967 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
2968 | .out(spare1_buf_16x_unused)); | |
2969 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
2970 | .in1(1'b0), | |
2971 | .out(spare1_nor2_16x_unused)); | |
2972 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
2973 | .out(spare1_inv_32x_unused)); | |
2974 | ||
2975 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
2976 | .out(spare2_buf_32x_unused)); | |
2977 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
2978 | .in1(1'b1), | |
2979 | .in2(1'b1), | |
2980 | .out(spare2_nand3_8x_unused)); | |
2981 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
2982 | .out(spare2_inv_8x_unused)); | |
2983 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
2984 | .in01(1'b1), | |
2985 | .in10(1'b1), | |
2986 | .in11(1'b1), | |
2987 | .out(spare2_aoi22_4x_unused)); | |
2988 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
2989 | .out(spare2_buf_8x_unused)); | |
2990 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
2991 | .in01(1'b1), | |
2992 | .in10(1'b1), | |
2993 | .in11(1'b1), | |
2994 | .out(spare2_oai22_4x_unused)); | |
2995 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
2996 | .out(spare2_inv_16x_unused)); | |
2997 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
2998 | .in1(1'b1), | |
2999 | .out(spare2_nand2_16x_unused)); | |
3000 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
3001 | .in1(1'b0), | |
3002 | .in2(1'b0), | |
3003 | .out(spare2_nor3_4x_unused)); | |
3004 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
3005 | .in1(1'b1), | |
3006 | .out(spare2_nand2_8x_unused)); | |
3007 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
3008 | .out(spare2_buf_16x_unused)); | |
3009 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
3010 | .in1(1'b0), | |
3011 | .out(spare2_nor2_16x_unused)); | |
3012 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
3013 | .out(spare2_inv_32x_unused)); | |
3014 | ||
3015 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
3016 | .out(spare3_buf_32x_unused)); | |
3017 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
3018 | .in1(1'b1), | |
3019 | .in2(1'b1), | |
3020 | .out(spare3_nand3_8x_unused)); | |
3021 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
3022 | .out(spare3_inv_8x_unused)); | |
3023 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
3024 | .in01(1'b1), | |
3025 | .in10(1'b1), | |
3026 | .in11(1'b1), | |
3027 | .out(spare3_aoi22_4x_unused)); | |
3028 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
3029 | .out(spare3_buf_8x_unused)); | |
3030 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
3031 | .in01(1'b1), | |
3032 | .in10(1'b1), | |
3033 | .in11(1'b1), | |
3034 | .out(spare3_oai22_4x_unused)); | |
3035 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
3036 | .out(spare3_inv_16x_unused)); | |
3037 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
3038 | .in1(1'b1), | |
3039 | .out(spare3_nand2_16x_unused)); | |
3040 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
3041 | .in1(1'b0), | |
3042 | .in2(1'b0), | |
3043 | .out(spare3_nor3_4x_unused)); | |
3044 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
3045 | .in1(1'b1), | |
3046 | .out(spare3_nand2_8x_unused)); | |
3047 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
3048 | .out(spare3_buf_16x_unused)); | |
3049 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
3050 | .in1(1'b0), | |
3051 | .out(spare3_nor2_16x_unused)); | |
3052 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
3053 | .out(spare3_inv_32x_unused)); | |
3054 | ||
3055 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
3056 | .out(spare4_buf_32x_unused)); | |
3057 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
3058 | .in1(1'b1), | |
3059 | .in2(1'b1), | |
3060 | .out(spare4_nand3_8x_unused)); | |
3061 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
3062 | .out(spare4_inv_8x_unused)); | |
3063 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
3064 | .in01(1'b1), | |
3065 | .in10(1'b1), | |
3066 | .in11(1'b1), | |
3067 | .out(spare4_aoi22_4x_unused)); | |
3068 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
3069 | .out(spare4_buf_8x_unused)); | |
3070 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
3071 | .in01(1'b1), | |
3072 | .in10(1'b1), | |
3073 | .in11(1'b1), | |
3074 | .out(spare4_oai22_4x_unused)); | |
3075 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
3076 | .out(spare4_inv_16x_unused)); | |
3077 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
3078 | .in1(1'b1), | |
3079 | .out(spare4_nand2_16x_unused)); | |
3080 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
3081 | .in1(1'b0), | |
3082 | .in2(1'b0), | |
3083 | .out(spare4_nor3_4x_unused)); | |
3084 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
3085 | .in1(1'b1), | |
3086 | .out(spare4_nand2_8x_unused)); | |
3087 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
3088 | .out(spare4_buf_16x_unused)); | |
3089 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
3090 | .in1(1'b0), | |
3091 | .out(spare4_nor2_16x_unused)); | |
3092 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
3093 | .out(spare4_inv_32x_unused)); | |
3094 | ||
3095 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
3096 | .out(spare5_buf_32x_unused)); | |
3097 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
3098 | .in1(1'b1), | |
3099 | .in2(1'b1), | |
3100 | .out(spare5_nand3_8x_unused)); | |
3101 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
3102 | .out(spare5_inv_8x_unused)); | |
3103 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
3104 | .in01(1'b1), | |
3105 | .in10(1'b1), | |
3106 | .in11(1'b1), | |
3107 | .out(spare5_aoi22_4x_unused)); | |
3108 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
3109 | .out(spare5_buf_8x_unused)); | |
3110 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
3111 | .in01(1'b1), | |
3112 | .in10(1'b1), | |
3113 | .in11(1'b1), | |
3114 | .out(spare5_oai22_4x_unused)); | |
3115 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
3116 | .out(spare5_inv_16x_unused)); | |
3117 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
3118 | .in1(1'b1), | |
3119 | .out(spare5_nand2_16x_unused)); | |
3120 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
3121 | .in1(1'b0), | |
3122 | .in2(1'b0), | |
3123 | .out(spare5_nor3_4x_unused)); | |
3124 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
3125 | .in1(1'b1), | |
3126 | .out(spare5_nand2_8x_unused)); | |
3127 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
3128 | .out(spare5_buf_16x_unused)); | |
3129 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
3130 | .in1(1'b0), | |
3131 | .out(spare5_nor2_16x_unused)); | |
3132 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
3133 | .out(spare5_inv_32x_unused)); | |
3134 | ||
3135 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
3136 | .out(spare6_buf_32x_unused)); | |
3137 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
3138 | .in1(1'b1), | |
3139 | .in2(1'b1), | |
3140 | .out(spare6_nand3_8x_unused)); | |
3141 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
3142 | .out(spare6_inv_8x_unused)); | |
3143 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
3144 | .in01(1'b1), | |
3145 | .in10(1'b1), | |
3146 | .in11(1'b1), | |
3147 | .out(spare6_aoi22_4x_unused)); | |
3148 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
3149 | .out(spare6_buf_8x_unused)); | |
3150 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
3151 | .in01(1'b1), | |
3152 | .in10(1'b1), | |
3153 | .in11(1'b1), | |
3154 | .out(spare6_oai22_4x_unused)); | |
3155 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
3156 | .out(spare6_inv_16x_unused)); | |
3157 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
3158 | .in1(1'b1), | |
3159 | .out(spare6_nand2_16x_unused)); | |
3160 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
3161 | .in1(1'b0), | |
3162 | .in2(1'b0), | |
3163 | .out(spare6_nor3_4x_unused)); | |
3164 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
3165 | .in1(1'b1), | |
3166 | .out(spare6_nand2_8x_unused)); | |
3167 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
3168 | .out(spare6_buf_16x_unused)); | |
3169 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
3170 | .in1(1'b0), | |
3171 | .out(spare6_nor2_16x_unused)); | |
3172 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
3173 | .out(spare6_inv_32x_unused)); | |
3174 | ||
3175 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), | |
3176 | .out(spare7_buf_32x_unused)); | |
3177 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), | |
3178 | .in1(1'b1), | |
3179 | .in2(1'b1), | |
3180 | .out(spare7_nand3_8x_unused)); | |
3181 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), | |
3182 | .out(spare7_inv_8x_unused)); | |
3183 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), | |
3184 | .in01(1'b1), | |
3185 | .in10(1'b1), | |
3186 | .in11(1'b1), | |
3187 | .out(spare7_aoi22_4x_unused)); | |
3188 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), | |
3189 | .out(spare7_buf_8x_unused)); | |
3190 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), | |
3191 | .in01(1'b1), | |
3192 | .in10(1'b1), | |
3193 | .in11(1'b1), | |
3194 | .out(spare7_oai22_4x_unused)); | |
3195 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), | |
3196 | .out(spare7_inv_16x_unused)); | |
3197 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), | |
3198 | .in1(1'b1), | |
3199 | .out(spare7_nand2_16x_unused)); | |
3200 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), | |
3201 | .in1(1'b0), | |
3202 | .in2(1'b0), | |
3203 | .out(spare7_nor3_4x_unused)); | |
3204 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), | |
3205 | .in1(1'b1), | |
3206 | .out(spare7_nand2_8x_unused)); | |
3207 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), | |
3208 | .out(spare7_buf_16x_unused)); | |
3209 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), | |
3210 | .in1(1'b0), | |
3211 | .out(spare7_nor2_16x_unused)); | |
3212 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), | |
3213 | .out(spare7_inv_32x_unused)); | |
3214 | ||
3215 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), | |
3216 | .out(spare8_buf_32x_unused)); | |
3217 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), | |
3218 | .in1(1'b1), | |
3219 | .in2(1'b1), | |
3220 | .out(spare8_nand3_8x_unused)); | |
3221 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), | |
3222 | .out(spare8_inv_8x_unused)); | |
3223 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), | |
3224 | .in01(1'b1), | |
3225 | .in10(1'b1), | |
3226 | .in11(1'b1), | |
3227 | .out(spare8_aoi22_4x_unused)); | |
3228 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), | |
3229 | .out(spare8_buf_8x_unused)); | |
3230 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), | |
3231 | .in01(1'b1), | |
3232 | .in10(1'b1), | |
3233 | .in11(1'b1), | |
3234 | .out(spare8_oai22_4x_unused)); | |
3235 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), | |
3236 | .out(spare8_inv_16x_unused)); | |
3237 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), | |
3238 | .in1(1'b1), | |
3239 | .out(spare8_nand2_16x_unused)); | |
3240 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), | |
3241 | .in1(1'b0), | |
3242 | .in2(1'b0), | |
3243 | .out(spare8_nor3_4x_unused)); | |
3244 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), | |
3245 | .in1(1'b1), | |
3246 | .out(spare8_nand2_8x_unused)); | |
3247 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), | |
3248 | .out(spare8_buf_16x_unused)); | |
3249 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), | |
3250 | .in1(1'b0), | |
3251 | .out(spare8_nor2_16x_unused)); | |
3252 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), | |
3253 | .out(spare8_inv_32x_unused)); | |
3254 | ||
3255 | ||
3256 | ||
3257 | endmodule | |
3258 | ||
3259 | ||
3260 | ||
3261 | ||
3262 | ||
3263 | ||
3264 | // any PARAMS parms go into naming of macro | |
3265 | ||
3266 | module tcu_regs_ctl_msff_ctl_macro__scanreverse_1__width_9 ( | |
3267 | din, | |
3268 | l1clk, | |
3269 | scan_in, | |
3270 | siclk, | |
3271 | soclk, | |
3272 | dout, | |
3273 | scan_out); | |
3274 | wire [8:0] fdin; | |
3275 | wire [0:7] so; | |
3276 | ||
3277 | input [8:0] din; | |
3278 | input l1clk; | |
3279 | input scan_in; | |
3280 | ||
3281 | ||
3282 | input siclk; | |
3283 | input soclk; | |
3284 | ||
3285 | output [8:0] dout; | |
3286 | output scan_out; | |
3287 | assign fdin[8:0] = din[8:0]; | |
3288 | ||
3289 | ||
3290 | ||
3291 | ||
3292 | ||
3293 | ||
3294 | dff #(9) d0_0 ( | |
3295 | .l1clk(l1clk), | |
3296 | .siclk(siclk), | |
3297 | .soclk(soclk), | |
3298 | .d(fdin[8:0]), | |
3299 | .si({so[0:7],scan_in}), | |
3300 | .so({scan_out,so[0:7]}), | |
3301 | .q(dout[8:0]) | |
3302 | ); | |
3303 | ||
3304 | ||
3305 | ||
3306 | ||
3307 | ||
3308 | ||
3309 | ||
3310 | ||
3311 | ||
3312 | ||
3313 | ||
3314 | ||
3315 | endmodule | |
3316 | ||
3317 | ||
3318 | ||
3319 | ||
3320 | ||
3321 | ||
3322 | ||
3323 |