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86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu_sigmux_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tcu_sigmux_ctl ( | |
36 | mio_ext_cmp_clk, | |
37 | mio_ext_dr_clk, | |
38 | tcu_ccu_ext_dr_clk, | |
39 | tcu_ccu_ext_cmp_clk, | |
40 | tcu_ccu_clk_stop, | |
41 | tcu_ccu_io_clk_stop, | |
42 | tcu_rst_clk_stop, | |
43 | tcu_rst_io_clk_stop, | |
44 | mbist_clk_stop, | |
45 | tck_clk_tree, | |
46 | mio_tcu_peu_clk_ext, | |
47 | tcu_peu_clk_ext, | |
48 | mio_tcu_niu_clk_ext, | |
49 | mac_125rx_test_clk, | |
50 | mac_125tx_test_clk, | |
51 | mac_156rx_test_clk, | |
52 | mac_156tx_test_clk, | |
53 | mac_312rx_test_clk, | |
54 | mac_312tx_test_clk, | |
55 | mio_tcu_pll_cmp_bypass, | |
56 | mio_tcu_divider_bypass, | |
57 | tcu_div_bypass, | |
58 | cmp_io_sync_en, | |
59 | io_cmp_sync_en, | |
60 | cmp_dr_sync_en, | |
61 | tcu_peu_testmode, | |
62 | tcu_mac_testmode, | |
63 | tcu_spc0_test_mode, | |
64 | tcu_spc1_test_mode, | |
65 | tcu_spc2_test_mode, | |
66 | tcu_spc3_test_mode, | |
67 | tcu_spc4_test_mode, | |
68 | tcu_spc5_test_mode, | |
69 | tcu_spc6_test_mode, | |
70 | tcu_spc7_test_mode, | |
71 | tcu_rst_scan_mode, | |
72 | tcu_atpg_mode, | |
73 | tcu_mcu_testmode, | |
74 | io_aclk, | |
75 | io_bclk, | |
76 | l2clk, | |
77 | io_tdi, | |
78 | io_scan_in, | |
79 | spc0_tcu_scan_in, | |
80 | spc1_tcu_scan_in, | |
81 | spc2_tcu_scan_in, | |
82 | spc3_tcu_scan_in, | |
83 | spc4_tcu_scan_in, | |
84 | spc5_tcu_scan_in, | |
85 | spc6_tcu_scan_in, | |
86 | spc7_tcu_scan_in, | |
87 | soca_tcu_scan_in, | |
88 | socb_tcu_scan_in, | |
89 | socc_tcu_scan_in, | |
90 | socd_tcu_scan_in, | |
91 | soce_tcu_scan_in, | |
92 | socf_tcu_scan_in, | |
93 | socg_tcu_scan_in, | |
94 | soch_tcu_scan_in, | |
95 | soc0_tcu_scan_in, | |
96 | soc1_tcu_scan_in, | |
97 | soc2_tcu_scan_in, | |
98 | soc3_tcu_scan_in, | |
99 | soc4_tcu_scan_in, | |
100 | soc5_tcu_scan_in, | |
101 | soc6_tcu_scan_in, | |
102 | peu_tcu_scan_in, | |
103 | ccu_tcu_scan_in, | |
104 | jtag_sbs_scan_in, | |
105 | mio_tcu_bs_scan_out, | |
106 | io_test_mode, | |
107 | jtag_ser_scan_q, | |
108 | io_scan_en, | |
109 | clk_stop_ac_trans_counter_initiated, | |
110 | io_ac_test_mode, | |
111 | io_ac_testtrig, | |
112 | ac_test_mode, | |
113 | debug_reg_hard_stop_domain_1st, | |
114 | debug_cycle_counter_stop, | |
115 | debug_event_stop, | |
116 | spc_ss_mode, | |
117 | spc_ss_sel, | |
118 | instr_sstop_csmode, | |
119 | tcu_scan_chain, | |
120 | POR_, | |
121 | jtag_clk_stop_req, | |
122 | jtagclkstop_ov, | |
123 | rst_tcu_flush_init_req, | |
124 | rst_tcu_flush_stop_req, | |
125 | rst_tcu_asicflush_stop_req, | |
126 | rst_wmr_protect, | |
127 | rst_tcu_dbr_gen, | |
128 | tcu_rst_flush_init_ack, | |
129 | tcu_rst_flush_stop_ack, | |
130 | tcu_rst_asicflush_stop_ack, | |
131 | tcu_rst_efu_done, | |
132 | flush_test_protect, | |
133 | tcu_test_protect_cmp, | |
134 | jtag_sck_byp, | |
135 | tcu_sck_bypass, | |
136 | jtag_por_enable, | |
137 | jtag_por_status, | |
138 | jtag_efu_clear_instr, | |
139 | jtag_efu_rvclr, | |
140 | tcu_efu_read_start, | |
141 | tcu_efu_rvclr, | |
142 | jt_scan_in, | |
143 | jt_scan_en, | |
144 | jt_scan_aclk, | |
145 | jt_scan_bclk, | |
146 | ser_scan_out, | |
147 | chain_select, | |
148 | sel_chain, | |
149 | tcu_spc_lbist_start, | |
150 | tap_spc0_mb_aclk, | |
151 | tap_spc0_mb_bclk, | |
152 | tap_spc0_mb_scan_en, | |
153 | tap_spc0_mb_clk_stop, | |
154 | tap_spc1_mb_aclk, | |
155 | tap_spc1_mb_bclk, | |
156 | tap_spc1_mb_scan_en, | |
157 | tap_spc1_mb_clk_stop, | |
158 | tap_spc2_mb_aclk, | |
159 | tap_spc2_mb_bclk, | |
160 | tap_spc2_mb_scan_en, | |
161 | tap_spc2_mb_clk_stop, | |
162 | tap_spc3_mb_aclk, | |
163 | tap_spc3_mb_bclk, | |
164 | tap_spc3_mb_scan_en, | |
165 | tap_spc3_mb_clk_stop, | |
166 | tap_spc4_mb_aclk, | |
167 | tap_spc4_mb_bclk, | |
168 | tap_spc4_mb_scan_en, | |
169 | tap_spc4_mb_clk_stop, | |
170 | tap_spc5_mb_aclk, | |
171 | tap_spc5_mb_bclk, | |
172 | tap_spc5_mb_scan_en, | |
173 | tap_spc5_mb_clk_stop, | |
174 | tap_spc6_mb_aclk, | |
175 | tap_spc6_mb_bclk, | |
176 | tap_spc6_mb_scan_en, | |
177 | tap_spc6_mb_clk_stop, | |
178 | tap_spc7_mb_aclk, | |
179 | tap_spc7_mb_bclk, | |
180 | tap_spc7_mb_scan_en, | |
181 | tap_spc7_mb_clk_stop, | |
182 | scan_in, | |
183 | scan_out, | |
184 | tcu_dectest, | |
185 | tcu_muxtest, | |
186 | tcu_jtag_flush_req, | |
187 | tcu_jtag_flush_dly_req, | |
188 | tcu_aclk, | |
189 | tcu_bclk, | |
190 | tcu_scan_en, | |
191 | jtag_mt_enable, | |
192 | tcu_spc0_aclk, | |
193 | tcu_spc0_bclk, | |
194 | tcu_spc0_scan_en, | |
195 | tcu_spc0_se_scancollar_in, | |
196 | tcu_spc0_se_scancollar_out, | |
197 | tcu_spc0_array_wr_inhibit, | |
198 | tcu_spc1_aclk, | |
199 | tcu_spc1_bclk, | |
200 | tcu_spc1_scan_en, | |
201 | tcu_spc1_se_scancollar_in, | |
202 | tcu_spc1_se_scancollar_out, | |
203 | tcu_spc1_array_wr_inhibit, | |
204 | tcu_spc2_aclk, | |
205 | tcu_spc2_bclk, | |
206 | tcu_spc2_scan_en, | |
207 | tcu_spc2_se_scancollar_in, | |
208 | tcu_spc2_se_scancollar_out, | |
209 | tcu_spc2_array_wr_inhibit, | |
210 | tcu_spc3_aclk, | |
211 | tcu_spc3_bclk, | |
212 | tcu_spc3_scan_en, | |
213 | tcu_spc3_se_scancollar_in, | |
214 | tcu_spc3_se_scancollar_out, | |
215 | tcu_spc3_array_wr_inhibit, | |
216 | tcu_spc4_aclk, | |
217 | tcu_spc4_bclk, | |
218 | tcu_spc4_scan_en, | |
219 | tcu_spc4_se_scancollar_in, | |
220 | tcu_spc4_se_scancollar_out, | |
221 | tcu_spc4_array_wr_inhibit, | |
222 | tcu_spc5_aclk, | |
223 | tcu_spc5_bclk, | |
224 | tcu_spc5_scan_en, | |
225 | tcu_spc5_se_scancollar_in, | |
226 | tcu_spc5_se_scancollar_out, | |
227 | tcu_spc5_array_wr_inhibit, | |
228 | tcu_spc6_aclk, | |
229 | tcu_spc6_bclk, | |
230 | tcu_spc6_scan_en, | |
231 | tcu_spc6_se_scancollar_in, | |
232 | tcu_spc6_se_scancollar_out, | |
233 | tcu_spc6_array_wr_inhibit, | |
234 | tcu_spc7_aclk, | |
235 | tcu_spc7_bclk, | |
236 | tcu_spc7_scan_en, | |
237 | tcu_spc7_se_scancollar_in, | |
238 | tcu_spc7_se_scancollar_out, | |
239 | tcu_spc7_array_wr_inhibit, | |
240 | tcu_asic_aclk, | |
241 | tcu_asic_bclk, | |
242 | tcu_asic_scan_en, | |
243 | tcu_asic_se_scancollar_in, | |
244 | tcu_asic_se_scancollar_out, | |
245 | tcu_asic_array_wr_inhibit, | |
246 | tcu_int_se, | |
247 | tcu_jtag_se, | |
248 | tcu_int_aclk, | |
249 | tcu_int_bclk, | |
250 | tcu_int_ce, | |
251 | tcu_int_ce_to_ucb, | |
252 | tcu_int_pce_ov, | |
253 | tcu_jtag_aclk, | |
254 | tcu_spc0_scan_out, | |
255 | tcu_spc1_scan_out, | |
256 | tcu_spc2_scan_out, | |
257 | tcu_spc3_scan_out, | |
258 | tcu_spc4_scan_out, | |
259 | tcu_spc5_scan_out, | |
260 | tcu_spc6_scan_out, | |
261 | tcu_spc7_scan_out, | |
262 | tcu_soca_scan_out, | |
263 | tcu_socb_scan_out, | |
264 | tcu_socc_scan_out, | |
265 | tcu_socd_scan_out, | |
266 | tcu_soce_scan_out, | |
267 | tcu_socf_scan_out, | |
268 | tcu_socg_scan_out, | |
269 | tcu_soch_scan_out, | |
270 | tcu_soc0_scan_out, | |
271 | tcu_soc1_scan_out, | |
272 | tcu_soc2_scan_out, | |
273 | tcu_soc3_scan_out, | |
274 | tcu_soc4_scan_out, | |
275 | tcu_soc5_scan_out, | |
276 | tcu_soc6_scan_out, | |
277 | tcu_peu_scan_out, | |
278 | tcu_rst_scan_out, | |
279 | tcu_sbs_scan_in, | |
280 | tcu_pins_scan_out, | |
281 | pre_spc0_clk_stop, | |
282 | pre_spc1_clk_stop, | |
283 | pre_spc2_clk_stop, | |
284 | pre_spc3_clk_stop, | |
285 | pre_spc4_clk_stop, | |
286 | pre_spc5_clk_stop, | |
287 | pre_spc6_clk_stop, | |
288 | pre_spc7_clk_stop, | |
289 | pre_bnk0_clk_stop, | |
290 | pre_l2t0_clk_stop, | |
291 | pre_bnk1_clk_stop, | |
292 | pre_l2t1_clk_stop, | |
293 | pre_bnk2_clk_stop, | |
294 | pre_l2t2_clk_stop, | |
295 | pre_bnk3_clk_stop, | |
296 | pre_l2t3_clk_stop, | |
297 | pre_bnk4_clk_stop, | |
298 | pre_l2t4_clk_stop, | |
299 | pre_bnk5_clk_stop, | |
300 | pre_l2t5_clk_stop, | |
301 | pre_bnk6_clk_stop, | |
302 | pre_l2t6_clk_stop, | |
303 | pre_bnk7_clk_stop, | |
304 | pre_l2t7_clk_stop, | |
305 | pre_mcu0_clk_stop, | |
306 | pre_mcu0_io_clk_stop, | |
307 | pre_mcu0_dr_clk_stop, | |
308 | pre_mcu0_fbd_clk_stop, | |
309 | pre_mcu1_clk_stop, | |
310 | pre_mcu1_io_clk_stop, | |
311 | pre_mcu1_dr_clk_stop, | |
312 | pre_mcu1_fbd_clk_stop, | |
313 | pre_mcu2_clk_stop, | |
314 | pre_mcu2_io_clk_stop, | |
315 | pre_mcu2_dr_clk_stop, | |
316 | pre_mcu2_fbd_clk_stop, | |
317 | pre_mcu3_clk_stop, | |
318 | pre_mcu3_io_clk_stop, | |
319 | pre_mcu3_dr_clk_stop, | |
320 | pre_mcu3_fbd_clk_stop, | |
321 | pre_soc0_clk_stop, | |
322 | pre_soc0_io_clk_stop, | |
323 | pre_soc1_io_clk_stop, | |
324 | pre_soc2_io_clk_stop, | |
325 | pre_soc3_clk_stop, | |
326 | pre_soc3_io_clk_stop, | |
327 | tcu_pce_ov, | |
328 | ac_trans_test_counter_start, | |
329 | spc0_tcu_mbist_scan_in, | |
330 | tap_spc0_mb_scan_out, | |
331 | tcu_spc0_mb_scan_out, | |
332 | spc0_tap_mb_scan_in, | |
333 | spc1_tcu_mbist_scan_in, | |
334 | tap_spc1_mb_scan_out, | |
335 | tcu_spc1_mb_scan_out, | |
336 | spc1_tap_mb_scan_in, | |
337 | spc2_tcu_mbist_scan_in, | |
338 | tap_spc2_mb_scan_out, | |
339 | tcu_spc2_mb_scan_out, | |
340 | spc2_tap_mb_scan_in, | |
341 | spc3_tcu_mbist_scan_in, | |
342 | tap_spc3_mb_scan_out, | |
343 | tcu_spc3_mb_scan_out, | |
344 | spc3_tap_mb_scan_in, | |
345 | spc4_tcu_mbist_scan_in, | |
346 | tap_spc4_mb_scan_out, | |
347 | tcu_spc4_mb_scan_out, | |
348 | spc4_tap_mb_scan_in, | |
349 | spc5_tcu_mbist_scan_in, | |
350 | tap_spc5_mb_scan_out, | |
351 | tcu_spc5_mb_scan_out, | |
352 | spc5_tap_mb_scan_in, | |
353 | spc6_tcu_mbist_scan_in, | |
354 | tap_spc6_mb_scan_out, | |
355 | tcu_spc6_mb_scan_out, | |
356 | spc6_tap_mb_scan_in, | |
357 | spc7_tcu_mbist_scan_in, | |
358 | tap_spc7_mb_scan_out, | |
359 | tcu_spc7_mb_scan_out, | |
360 | spc7_tap_mb_scan_in, | |
361 | tcu_sii_mbist_scan_in, | |
362 | tcu_sio_mbist_scan_in, | |
363 | tcu_ncu_mbist_scan_in, | |
364 | tcu_mcu0_mbist_scan_in, | |
365 | tcu_mcu1_mbist_scan_in, | |
366 | tcu_mcu2_mbist_scan_in, | |
367 | tcu_mcu3_mbist_scan_in, | |
368 | tcu_l2b0_mbist_scan_in, | |
369 | tcu_l2b1_mbist_scan_in, | |
370 | tcu_l2b2_mbist_scan_in, | |
371 | tcu_l2b3_mbist_scan_in, | |
372 | tcu_l2b4_mbist_scan_in, | |
373 | tcu_l2b5_mbist_scan_in, | |
374 | tcu_l2b6_mbist_scan_in, | |
375 | tcu_l2b7_mbist_scan_in, | |
376 | tcu_l2t0_mbist_scan_in, | |
377 | tcu_l2t1_mbist_scan_in, | |
378 | tcu_l2t2_mbist_scan_in, | |
379 | tcu_l2t3_mbist_scan_in, | |
380 | tcu_l2t4_mbist_scan_in, | |
381 | tcu_l2t5_mbist_scan_in, | |
382 | tcu_l2t6_mbist_scan_in, | |
383 | tcu_l2t7_mbist_scan_in, | |
384 | tcu_dmu_mbist_scan_in, | |
385 | tcu_peu_mbist_scan_in, | |
386 | rdp_rdmc_mbist_scan_in, | |
387 | rtx_mbist_scan_in, | |
388 | tds_mbist_scan_in, | |
389 | sii_tcu_mbist_scan_out, | |
390 | sio_tcu_mbist_scan_out, | |
391 | ncu_tcu_mbist_scan_out, | |
392 | mcu0_tcu_mbist_scan_out, | |
393 | mcu1_tcu_mbist_scan_out, | |
394 | mcu2_tcu_mbist_scan_out, | |
395 | mcu3_tcu_mbist_scan_out, | |
396 | l2b0_tcu_mbist_scan_out, | |
397 | l2b1_tcu_mbist_scan_out, | |
398 | l2b2_tcu_mbist_scan_out, | |
399 | l2b3_tcu_mbist_scan_out, | |
400 | l2b4_tcu_mbist_scan_out, | |
401 | l2b5_tcu_mbist_scan_out, | |
402 | l2b6_tcu_mbist_scan_out, | |
403 | l2b7_tcu_mbist_scan_out, | |
404 | l2t0_tcu_mbist_scan_out, | |
405 | l2t1_tcu_mbist_scan_out, | |
406 | l2t2_tcu_mbist_scan_out, | |
407 | l2t3_tcu_mbist_scan_out, | |
408 | l2t4_tcu_mbist_scan_out, | |
409 | l2t5_tcu_mbist_scan_out, | |
410 | l2t6_tcu_mbist_scan_out, | |
411 | l2t7_tcu_mbist_scan_out, | |
412 | dmu_tcu_mbist_scan_out, | |
413 | peu_tcu_mbist_scan_out, | |
414 | rdp_rdmc_mbist_scan_out, | |
415 | rtx_mbist_scan_out, | |
416 | tds_mbist_scan_out, | |
417 | spc0_tcu_lbist_scan_out, | |
418 | spc1_tcu_lbist_scan_out, | |
419 | spc2_tcu_lbist_scan_out, | |
420 | spc3_tcu_lbist_scan_out, | |
421 | spc4_tcu_lbist_scan_out, | |
422 | spc5_tcu_lbist_scan_out, | |
423 | spc6_tcu_lbist_scan_out, | |
424 | spc7_tcu_lbist_scan_out, | |
425 | tcu_spc_lbist_scan_in, | |
426 | spc0_tcu_shscan_scan_in, | |
427 | spc1_tcu_shscan_scan_in, | |
428 | spc2_tcu_shscan_scan_in, | |
429 | spc3_tcu_shscan_scan_in, | |
430 | spc4_tcu_shscan_scan_in, | |
431 | spc5_tcu_shscan_scan_in, | |
432 | spc6_tcu_shscan_scan_in, | |
433 | spc7_tcu_shscan_scan_in, | |
434 | tcu_spc0_shscan_scan_out, | |
435 | tcu_spc1_shscan_scan_out, | |
436 | tcu_spc2_shscan_scan_out, | |
437 | tcu_spc3_shscan_scan_out, | |
438 | tcu_spc4_shscan_scan_out, | |
439 | tcu_spc5_shscan_scan_out, | |
440 | tcu_spc6_shscan_scan_out, | |
441 | tcu_spc7_shscan_scan_out, | |
442 | tap_spc0_shscan_scan_out, | |
443 | spc7_tap_shscan_scan_in, | |
444 | jtag_spc_shscanid, | |
445 | tcu_spc_shscanid, | |
446 | jtag_spc0_shscan_clk_stop, | |
447 | jtag_spc1_shscan_clk_stop, | |
448 | jtag_spc2_shscan_clk_stop, | |
449 | jtag_spc3_shscan_clk_stop, | |
450 | jtag_spc4_shscan_clk_stop, | |
451 | jtag_spc5_shscan_clk_stop, | |
452 | jtag_spc6_shscan_clk_stop, | |
453 | jtag_spc7_shscan_clk_stop, | |
454 | tcu_spc0_shscan_clk_stop, | |
455 | tcu_spc1_shscan_clk_stop, | |
456 | tcu_spc2_shscan_clk_stop, | |
457 | tcu_spc3_shscan_clk_stop, | |
458 | tcu_spc4_shscan_clk_stop, | |
459 | tcu_spc5_shscan_clk_stop, | |
460 | tcu_spc6_shscan_clk_stop, | |
461 | tcu_spc7_shscan_clk_stop, | |
462 | jtag_spc_shscan_pce_ov, | |
463 | tcu_spc_shscan_pce_ov, | |
464 | jtag_l2t0_shscan_clk_stop, | |
465 | jtag_l2t1_shscan_clk_stop, | |
466 | jtag_l2t2_shscan_clk_stop, | |
467 | jtag_l2t3_shscan_clk_stop, | |
468 | jtag_l2t4_shscan_clk_stop, | |
469 | jtag_l2t5_shscan_clk_stop, | |
470 | jtag_l2t6_shscan_clk_stop, | |
471 | jtag_l2t7_shscan_clk_stop, | |
472 | jtag_l2t_shscan_pce_ov, | |
473 | tcu_l2t0_shscan_clk_stop, | |
474 | tcu_l2t1_shscan_clk_stop, | |
475 | tcu_l2t2_shscan_clk_stop, | |
476 | tcu_l2t3_shscan_clk_stop, | |
477 | tcu_l2t4_shscan_clk_stop, | |
478 | tcu_l2t5_shscan_clk_stop, | |
479 | tcu_l2t6_shscan_clk_stop, | |
480 | tcu_l2t7_shscan_clk_stop, | |
481 | tcu_l2t_shscan_pce_ov, | |
482 | core_avail, | |
483 | ncu_spc0_core_enable_status, | |
484 | ncu_spc1_core_enable_status, | |
485 | ncu_spc2_core_enable_status, | |
486 | ncu_spc3_core_enable_status, | |
487 | ncu_spc4_core_enable_status, | |
488 | ncu_spc5_core_enable_status, | |
489 | ncu_spc6_core_enable_status, | |
490 | ncu_spc7_core_enable_status, | |
491 | bank_avail, | |
492 | ncu_spc_pm, | |
493 | ncu_spc_ba01, | |
494 | ncu_spc_ba23, | |
495 | ncu_spc_ba45, | |
496 | ncu_spc_ba67, | |
497 | tcu_se_scancollar_in, | |
498 | tcu_se_scancollar_out, | |
499 | tcu_array_bypass, | |
500 | tcu_array_wr_inhibit, | |
501 | jtag_upd_cntdly, | |
502 | jtag_cntdly_data, | |
503 | csdel_data, | |
504 | clkseq_stop, | |
505 | clkseq_strt, | |
506 | cycle_stretch, | |
507 | tcu_ccu_clk_stretch, | |
508 | tcu_ccu_mux_sel, | |
509 | wmr_two, | |
510 | start_bisx_por, | |
511 | start_bisx_wmr, | |
512 | stop_bisx_wmr, | |
513 | instr_mbist_diag, | |
514 | soc_mbist_aclk, | |
515 | soc_mbist_bclk, | |
516 | soc_mbist_scan_en, | |
517 | soc0_mbist_clk_stop, | |
518 | mcu0_mbist_clk_stop, | |
519 | mcu1_mbist_clk_stop, | |
520 | mcu2_mbist_clk_stop, | |
521 | mcu3_mbist_clk_stop, | |
522 | l2b0_mbist_clk_stop, | |
523 | l2b1_mbist_clk_stop, | |
524 | l2b2_mbist_clk_stop, | |
525 | l2b3_mbist_clk_stop, | |
526 | l2b4_mbist_clk_stop, | |
527 | l2b5_mbist_clk_stop, | |
528 | l2b6_mbist_clk_stop, | |
529 | l2b7_mbist_clk_stop, | |
530 | l2t0_mbist_clk_stop, | |
531 | l2t1_mbist_clk_stop, | |
532 | l2t2_mbist_clk_stop, | |
533 | l2t3_mbist_clk_stop, | |
534 | l2t4_mbist_clk_stop, | |
535 | l2t5_mbist_clk_stop, | |
536 | l2t6_mbist_clk_stop, | |
537 | l2t7_mbist_clk_stop, | |
538 | dmu_mbist_clk_stop, | |
539 | peu_mbist_clk_stop, | |
540 | rdp_mbist_clk_stop, | |
541 | rtx_mbist_clk_stop, | |
542 | tds_mbist_clk_stop, | |
543 | tcu_srd_atpgse, | |
544 | tcu_srd_atpgd, | |
545 | tcu_mio_scan_out31, | |
546 | tcu_srd_atpgmode, | |
547 | mio_tcu_scan_in31, | |
548 | srd_tcu_atpgq, | |
549 | l2t0_tcu_shscan_scan_out, | |
550 | l2t1_tcu_shscan_scan_out, | |
551 | l2t2_tcu_shscan_scan_out, | |
552 | l2t3_tcu_shscan_scan_out, | |
553 | l2t4_tcu_shscan_scan_out, | |
554 | l2t5_tcu_shscan_scan_out, | |
555 | l2t6_tcu_shscan_scan_out, | |
556 | l2t7_tcu_shscan_scan_out, | |
557 | tcu_l2t0_shscan_scan_in, | |
558 | tcu_l2t1_shscan_scan_in, | |
559 | tcu_l2t2_shscan_scan_in, | |
560 | tcu_l2t3_shscan_scan_in, | |
561 | tcu_l2t4_shscan_scan_in, | |
562 | tcu_l2t5_shscan_scan_in, | |
563 | tcu_l2t6_shscan_scan_in, | |
564 | tcu_l2t7_shscan_scan_in, | |
565 | ucb_csr_wr, | |
566 | ucb_csr_addr, | |
567 | ucb_data_out); | |
568 | wire l1en; | |
569 | wire pce_ov; | |
570 | wire stop; | |
571 | wire se; | |
572 | wire siclk; | |
573 | wire soclk; | |
574 | wire l1clk; | |
575 | wire ucb_csr_wr_sync_reg_scanin; | |
576 | wire ucb_csr_wr_sync_reg_scanout; | |
577 | wire io_cmp_sync_en_local; | |
578 | wire ucb_csr_wr_sync; | |
579 | wire ucb_sel_clkstp_delay; | |
580 | wire ucb_wr_clkstp_delay; | |
581 | wire por_one; | |
582 | wire int_flush_d6; | |
583 | wire ac_tt_trigger_fr; | |
584 | wire test_mode_block; | |
585 | wire test_mode_gated; | |
586 | wire pin_aclk; | |
587 | wire pin_bclk; | |
588 | wire pin_scan_en; | |
589 | wire jt_scan_spc0; | |
590 | wire jt_scan_spc1; | |
591 | wire jt_scan_spc2; | |
592 | wire jt_scan_spc3; | |
593 | wire jt_scan_spc4; | |
594 | wire jt_scan_spc5; | |
595 | wire jt_scan_spc6; | |
596 | wire jt_scan_spc7; | |
597 | wire por_two; | |
598 | wire jt_scan_mtmode; | |
599 | wire pll_bypass; | |
600 | wire spc0_stopped; | |
601 | wire spc1_stopped; | |
602 | wire spc2_stopped; | |
603 | wire spc3_stopped; | |
604 | wire spc4_stopped; | |
605 | wire spc5_stopped; | |
606 | wire spc6_stopped; | |
607 | wire spc7_stopped; | |
608 | wire bnk0_stopped; | |
609 | wire l2t0_stopped; | |
610 | wire bnk1_stopped; | |
611 | wire l2t1_stopped; | |
612 | wire bnk2_stopped; | |
613 | wire l2t2_stopped; | |
614 | wire bnk3_stopped; | |
615 | wire l2t3_stopped; | |
616 | wire bnk4_stopped; | |
617 | wire l2t4_stopped; | |
618 | wire bnk5_stopped; | |
619 | wire l2t5_stopped; | |
620 | wire bnk6_stopped; | |
621 | wire l2t6_stopped; | |
622 | wire bnk7_stopped; | |
623 | wire l2t7_stopped; | |
624 | wire mcu0_stopped_tt; | |
625 | wire mcu1_stopped_tt; | |
626 | wire mcu2_stopped_tt; | |
627 | wire mcu3_stopped_tt; | |
628 | wire soc0_stopped_tt; | |
629 | wire soc1_stopped_tt; | |
630 | wire soc2_stopped_tt; | |
631 | wire soc3_stopped_tt; | |
632 | wire tt_cmp_mode; | |
633 | wire tt_io_clk; | |
634 | wire tt_io_mode; | |
635 | wire tt_dr_mode; | |
636 | wire [1:0] pre_tcu_spc0_scan_out; | |
637 | wire [1:0] pre_tcu_spc1_scan_out; | |
638 | wire [1:0] pre_tcu_spc2_scan_out; | |
639 | wire [1:0] pre_tcu_spc3_scan_out; | |
640 | wire [1:0] pre_tcu_spc4_scan_out; | |
641 | wire [1:0] pre_tcu_spc5_scan_out; | |
642 | wire [1:0] pre_tcu_spc6_scan_out; | |
643 | wire [1:0] pre_tcu_spc7_scan_out; | |
644 | wire pre_tcu_soca_scan_out; | |
645 | wire pre_tcu_socb_scan_out; | |
646 | wire pre_tcu_socc_scan_out; | |
647 | wire pre_tcu_socd_scan_out; | |
648 | wire pre_tcu_soce_scan_out; | |
649 | wire pre_tcu_socf_scan_out; | |
650 | wire pre_tcu_socg_scan_out; | |
651 | wire pre_tcu_soch_scan_out; | |
652 | wire pre_tcu_soc0_scan_out; | |
653 | wire pre_tcu_soc1_scan_out; | |
654 | wire pre_tcu_soc2_scan_out; | |
655 | wire pre_tcu_soc3_scan_out; | |
656 | wire pre_tcu_soc4_scan_out; | |
657 | wire pre_tcu_soc5_scan_out; | |
658 | wire pre_tcu_soc6_scan_out; | |
659 | wire jt_scan; | |
660 | wire miobscan_or_peu_scan; | |
661 | wire tcu_int_nfse; | |
662 | wire tcu_int_nfce; | |
663 | wire nf_l1clk; | |
664 | wire rst_flush_req; | |
665 | wire flush_tcu; | |
666 | wire rst_tcu_flush_init_req_hold; | |
667 | wire rst_tcu_flush_stop_req_hold; | |
668 | wire fr_l1clk; | |
669 | wire ok_to_flush; | |
670 | wire cntstop_equal_max_q; | |
671 | wire flush_q0; | |
672 | wire flush; | |
673 | wire tcusig_foncnt_nf_reg_scanin; | |
674 | wire tcusig_foncnt_nf_reg_scanout; | |
675 | wire tcu_int_nfaclk; | |
676 | wire tcu_int_nfbclk; | |
677 | wire clear_flush_on_counter; | |
678 | wire [6:0] flush_oncnt_din; | |
679 | wire [6:0] flush_oncnt; | |
680 | wire flush_on_24; | |
681 | wire flush_on_48; | |
682 | wire flush_on_72; | |
683 | wire flush_on_96; | |
684 | wire tcusig_foffcnt_nf_reg_scanin; | |
685 | wire tcusig_foffcnt_nf_reg_scanout; | |
686 | wire clear_flush_off_counter; | |
687 | wire [6:0] flush_offcnt_din; | |
688 | wire [6:0] flush_offcnt; | |
689 | wire flush_off_24; | |
690 | wire flush_off_48; | |
691 | wire flush_off_72; | |
692 | wire flush_off_96; | |
693 | wire tcusig_fq24_nf_reg_scanin; | |
694 | wire tcusig_fq24_nf_reg_scanout; | |
695 | wire enable_flush_q24_delay; | |
696 | wire flush_q24; | |
697 | wire tcusig_fq48_nf_reg_scanin; | |
698 | wire tcusig_fq48_nf_reg_scanout; | |
699 | wire enable_flush_q48_delay; | |
700 | wire flush_q48; | |
701 | wire tcusig_fq72_nf_reg_scanin; | |
702 | wire tcusig_fq72_nf_reg_scanout; | |
703 | wire enable_flush_q72_delay; | |
704 | wire flush_q72; | |
705 | wire tcusig_fq96_nf_reg_scanin; | |
706 | wire tcusig_fq96_nf_reg_scanout; | |
707 | wire enable_flush_q96_delay; | |
708 | wire flush_q96; | |
709 | wire flush_off; | |
710 | wire flush_go; | |
711 | wire flush_start; | |
712 | wire tcusig_cstopq48_nf_reg_scanin; | |
713 | wire tcusig_cstopq48_nf_reg_scanout; | |
714 | wire enable_cstop_q48_delay; | |
715 | wire clk_stop_loops_all_off; | |
716 | wire clk_stop_loops_all_off_q48; | |
717 | wire clk_stop_loops_all_off_q128; | |
718 | wire tcusig_flushdly_reg_scanin; | |
719 | wire tcusig_flushdly_reg_scanout; | |
720 | wire cntstart; | |
721 | wire clk_stop_loops_all_on; | |
722 | wire cntstop_equal_max; | |
723 | wire tcusig_fireq_reg_scanin; | |
724 | wire tcusig_fireq_reg_scanout; | |
725 | wire fireq; | |
726 | wire tcusig_fsreq_reg_scanin; | |
727 | wire tcusig_fsreq_reg_scanout; | |
728 | wire int_flush_d12; | |
729 | wire tcusig_rstsm_nf_reg_scanin; | |
730 | wire tcusig_rstsm_nf_reg_scanout; | |
731 | wire [1:0] rst_sm_new; | |
732 | wire [1:0] rst_sm_dout; | |
733 | wire [1:0] rst_sm; | |
734 | wire wmr_one; | |
735 | wire tcusig_fiack_reg_scanin; | |
736 | wire tcusig_fiack_reg_scanout; | |
737 | wire tcu_rst_flush_init_ack_int; | |
738 | wire tcu_rst_flush_init_ack_pre; | |
739 | wire flush_clk_stop_active; | |
740 | wire tcusig_tcuf_nf_reg_scanin; | |
741 | wire tcusig_tcuf_nf_reg_scanout; | |
742 | wire flush_tcu_req; | |
743 | wire flush_tcu_req_hld; | |
744 | wire tcusig_tcuasicf_nf_reg_scanin; | |
745 | wire tcusig_tcuasicf_nf_reg_scanout; | |
746 | wire asicflush_tcu; | |
747 | wire asicflush_tcu_req; | |
748 | wire asicflush_tcu_req_hld; | |
749 | wire tcusig_intflush_nf_reg_scanin; | |
750 | wire tcusig_intflush_nf_reg_scanout; | |
751 | wire int_flush; | |
752 | wire int_flush_d; | |
753 | wire int_flush_d2; | |
754 | wire int_flush_d3; | |
755 | wire int_flush_d4; | |
756 | wire int_flush_d5; | |
757 | wire int_flush_d7; | |
758 | wire int_flush_d8; | |
759 | wire int_flush_d9; | |
760 | wire int_flush_d10; | |
761 | wire int_flush_d11; | |
762 | wire tcusig_efctl_reg_scanin; | |
763 | wire tcusig_efctl_reg_scanout; | |
764 | wire efctl_clear; | |
765 | wire [5:0] efctl_din; | |
766 | wire [5:0] efctl_dout; | |
767 | wire efu_clr_ok; | |
768 | wire efctl_hold; | |
769 | wire tcusig_efcnt_reg_scanin; | |
770 | wire tcusig_efcnt_reg_scanout; | |
771 | wire efcnt_clear; | |
772 | wire [14:0] efcnt_din; | |
773 | wire [14:0] efcnt_dout; | |
774 | wire efcnt_pre_hold; | |
775 | wire efcnt_hold; | |
776 | wire jtag_efu_clear_instr_sync; | |
777 | wire efu_done_int; | |
778 | wire jtag_por_active; | |
779 | wire strt_cnt_clr_; | |
780 | wire hard_stop_via_reg_din; | |
781 | wire clock_stop_active; | |
782 | wire hard_stop_via_reg; | |
783 | wire coreavail_clk_stop_active; | |
784 | wire jtag_clk_stop_active; | |
785 | wire debug_stop_req; | |
786 | wire stop_req; | |
787 | wire jtmb_clk_stop; | |
788 | wire tcusig_clkstopviareg_reg_scanin; | |
789 | wire tcusig_clkstopviareg_reg_scanout; | |
790 | wire clk_stop_loops_off; | |
791 | wire tcusig_jtagclkstop_reg_scanin; | |
792 | wire tcusig_jtagclkstop_reg_scanout; | |
793 | wire jtag_clk_stop_clear_; | |
794 | wire jtag_clk_stop; | |
795 | wire tcusig_flushclkstop_reg_scanin; | |
796 | wire tcusig_flushclkstop_reg_scanout; | |
797 | wire flush_clk_stop_in; | |
798 | wire flush_clk_stop_active_l; | |
799 | wire flush_clk_stop; | |
800 | wire flush_clear_; | |
801 | wire tcusig_warmrp_reg_scanin; | |
802 | wire tcusig_warmrp_reg_scanout; | |
803 | wire rst_wmr_protect_d; | |
804 | wire rst_wmr_protect_d2; | |
805 | wire rst_wmr_protect_sync; | |
806 | wire tcusig_coreavailclkstop_reg_scanin; | |
807 | wire tcusig_coreavailclkstop_reg_scanout; | |
808 | wire coreavail_clear; | |
809 | wire coreavail_clk_stop; | |
810 | wire coreavail_clk_stop_active_dout; | |
811 | wire core_avail_qualified; | |
812 | wire [7:0] core_avail_pre_hold; | |
813 | wire [7:0] bank_avail_pre_hold; | |
814 | wire [7:0] core_avail_pre_hold_l; | |
815 | wire [7:0] bank_avail_pre_hold_l; | |
816 | wire tcusig_ca_reg_scanin; | |
817 | wire tcusig_ca_reg_scanout; | |
818 | wire ca_enable; | |
819 | wire [7:0] bank_avail_hold_l; | |
820 | wire [7:0] core_avail_hold_l; | |
821 | wire [7:0] core_avail_hold; | |
822 | wire [7:0] bank_avail_hold; | |
823 | wire ca_hold; | |
824 | wire all_cores_available; | |
825 | wire [7:0] spc_avail; | |
826 | wire [7:0] l2bnk_avail; | |
827 | wire ces_enable; | |
828 | wire tcusig_coreavailclear_reg_scanin; | |
829 | wire tcusig_coreavailclear_reg_scanout; | |
830 | wire mcu3_clk_stop_loop; | |
831 | wire coreavail_clear_dout; | |
832 | wire tcusig_enstat_reg_scanin; | |
833 | wire tcusig_enstat_reg_scanout; | |
834 | wire enstat_en; | |
835 | wire ncu_spc7_core_enable_status_io; | |
836 | wire ncu_spc6_core_enable_status_io; | |
837 | wire ncu_spc5_core_enable_status_io; | |
838 | wire ncu_spc4_core_enable_status_io; | |
839 | wire ncu_spc3_core_enable_status_io; | |
840 | wire ncu_spc2_core_enable_status_io; | |
841 | wire ncu_spc1_core_enable_status_io; | |
842 | wire ncu_spc0_core_enable_status_io; | |
843 | wire ncu_spc_pm_io; | |
844 | wire ncu_spc_ba67_io; | |
845 | wire ncu_spc_ba45_io; | |
846 | wire ncu_spc_ba23_io; | |
847 | wire ncu_spc_ba01_io; | |
848 | wire ncu_ba67; | |
849 | wire ncu_ba45; | |
850 | wire ncu_ba23; | |
851 | wire ncu_ba01; | |
852 | wire [11:0] core_en_status; | |
853 | wire core_enstat_qual_l; | |
854 | wire core_enstat_qual; | |
855 | wire tcusig_cesq_reg_scanin; | |
856 | wire tcusig_cesq_reg_scanout; | |
857 | wire core_enstat_qual_dly; | |
858 | wire [11:0] core_en_status_pre_hold; | |
859 | wire tcusig_ces_reg_scanin; | |
860 | wire tcusig_ces_reg_scanout; | |
861 | wire [11:0] core_en_status_hold_l; | |
862 | wire [11:0] core_en_status_hold; | |
863 | wire mcu3_avail_hold; | |
864 | wire mcu2_avail_hold; | |
865 | wire mcu1_avail_hold; | |
866 | wire mcu0_avail_hold; | |
867 | wire clk_stop_seq_scanin; | |
868 | wire clk_stop_seq_scanout; | |
869 | wire cntstop; | |
870 | wire [6:0] cntstop_dout; | |
871 | wire [6:0] cntdly_dout; | |
872 | wire cntstart_equal_max; | |
873 | wire [6:0] cntstart_dout; | |
874 | wire [6:0] cntstop_din; | |
875 | wire [6:0] cntstart_din; | |
876 | wire tcusig_cntdly_reg_scanin; | |
877 | wire tcusig_cntdly_reg_scanout; | |
878 | wire [6:0] cntdly_din_l; | |
879 | wire [6:0] cntdly_dout_l; | |
880 | wire [6:0] cntdly_din; | |
881 | wire jtag_upd_cntdly_sync; | |
882 | wire tcusig_cntstop_reg_scanin; | |
883 | wire tcusig_cntstop_reg_scanout; | |
884 | wire stop_cnt_en; | |
885 | wire tcusig_cntstart_reg_scanin; | |
886 | wire tcusig_cntstart_reg_scanout; | |
887 | wire strt_cnt_en; | |
888 | wire tcusig_ssmode_reg_scanin; | |
889 | wire tcusig_ssmode_reg_scanout; | |
890 | wire ssmode_en; | |
891 | wire ss_req; | |
892 | wire ss_mode; | |
893 | wire core_sel_reg_nonzero; | |
894 | wire instr_sstop_csmode_sync; | |
895 | wire tcusig_sssel_reg_scanin; | |
896 | wire tcusig_sssel_reg_scanout; | |
897 | wire sssel_en; | |
898 | wire [7:0] spc_ss_sel_d; | |
899 | wire [7:0] spc_ss_sel_qual; | |
900 | wire spc0_clk_stop_cavail; | |
901 | wire spc0_clk_stop_loop; | |
902 | wire spc0_clk_stop_prepresync; | |
903 | wire spc0_clk_stop_presync; | |
904 | wire spc0_clk_stop_sync; | |
905 | wire spc1_clk_stop_cavail; | |
906 | wire spc1_clk_stop_loop; | |
907 | wire spc1_clk_stop_prepresync; | |
908 | wire spc1_clk_stop_presync; | |
909 | wire spc1_clk_stop_sync; | |
910 | wire spc2_clk_stop_cavail; | |
911 | wire spc2_clk_stop_loop; | |
912 | wire spc2_clk_stop_prepresync; | |
913 | wire spc2_clk_stop_presync; | |
914 | wire spc2_clk_stop_sync; | |
915 | wire spc3_clk_stop_cavail; | |
916 | wire spc3_clk_stop_loop; | |
917 | wire spc3_clk_stop_prepresync; | |
918 | wire spc3_clk_stop_presync; | |
919 | wire spc3_clk_stop_sync; | |
920 | wire spc4_clk_stop_cavail; | |
921 | wire spc4_clk_stop_loop; | |
922 | wire spc4_clk_stop_prepresync; | |
923 | wire spc4_clk_stop_presync; | |
924 | wire spc4_clk_stop_sync; | |
925 | wire spc5_clk_stop_cavail; | |
926 | wire spc5_clk_stop_loop; | |
927 | wire spc5_clk_stop_prepresync; | |
928 | wire spc5_clk_stop_presync; | |
929 | wire spc5_clk_stop_sync; | |
930 | wire spc6_clk_stop_cavail; | |
931 | wire spc6_clk_stop_loop; | |
932 | wire spc6_clk_stop_prepresync; | |
933 | wire spc6_clk_stop_presync; | |
934 | wire spc6_clk_stop_sync; | |
935 | wire spc7_clk_stop_cavail; | |
936 | wire spc7_clk_stop_loop; | |
937 | wire spc7_clk_stop_prepresync; | |
938 | wire spc7_clk_stop_presync; | |
939 | wire spc7_clk_stop_sync; | |
940 | wire bnk0_clk_stop_cavail; | |
941 | wire bnk0_clk_stop_loop; | |
942 | wire bnk0_clk_stop_prepresync; | |
943 | wire bnk0_clk_stop_presync; | |
944 | wire bnk0_clk_stop_sync; | |
945 | wire l2t0_clk_stop_prepresync; | |
946 | wire l2t0_clk_stop_presync; | |
947 | wire l2t0_clk_stop_sync; | |
948 | wire bnk1_clk_stop_cavail; | |
949 | wire bnk1_clk_stop_loop; | |
950 | wire bnk1_clk_stop_prepresync; | |
951 | wire bnk1_clk_stop_presync; | |
952 | wire bnk1_clk_stop_sync; | |
953 | wire l2t1_clk_stop_prepresync; | |
954 | wire l2t1_clk_stop_presync; | |
955 | wire l2t1_clk_stop_sync; | |
956 | wire bnk2_clk_stop_cavail; | |
957 | wire bnk2_clk_stop_loop; | |
958 | wire bnk2_clk_stop_prepresync; | |
959 | wire bnk2_clk_stop_presync; | |
960 | wire bnk2_clk_stop_sync; | |
961 | wire l2t2_clk_stop_prepresync; | |
962 | wire l2t2_clk_stop_presync; | |
963 | wire l2t2_clk_stop_sync; | |
964 | wire bnk3_clk_stop_cavail; | |
965 | wire bnk3_clk_stop_loop; | |
966 | wire bnk3_clk_stop_prepresync; | |
967 | wire bnk3_clk_stop_presync; | |
968 | wire bnk3_clk_stop_sync; | |
969 | wire l2t3_clk_stop_prepresync; | |
970 | wire l2t3_clk_stop_presync; | |
971 | wire l2t3_clk_stop_sync; | |
972 | wire bnk4_clk_stop_cavail; | |
973 | wire bnk4_clk_stop_loop; | |
974 | wire bnk4_clk_stop_prepresync; | |
975 | wire bnk4_clk_stop_presync; | |
976 | wire bnk4_clk_stop_sync; | |
977 | wire l2t4_clk_stop_prepresync; | |
978 | wire l2t4_clk_stop_presync; | |
979 | wire l2t4_clk_stop_sync; | |
980 | wire bnk5_clk_stop_cavail; | |
981 | wire bnk5_clk_stop_loop; | |
982 | wire bnk5_clk_stop_prepresync; | |
983 | wire bnk5_clk_stop_presync; | |
984 | wire bnk5_clk_stop_sync; | |
985 | wire l2t5_clk_stop_prepresync; | |
986 | wire l2t5_clk_stop_presync; | |
987 | wire l2t5_clk_stop_sync; | |
988 | wire bnk6_clk_stop_cavail; | |
989 | wire bnk6_clk_stop_loop; | |
990 | wire bnk6_clk_stop_prepresync; | |
991 | wire bnk6_clk_stop_presync; | |
992 | wire bnk6_clk_stop_sync; | |
993 | wire l2t6_clk_stop_prepresync; | |
994 | wire l2t6_clk_stop_presync; | |
995 | wire l2t6_clk_stop_sync; | |
996 | wire bnk7_clk_stop_cavail; | |
997 | wire bnk7_clk_stop_loop; | |
998 | wire bnk7_clk_stop_prepresync; | |
999 | wire bnk7_clk_stop_presync; | |
1000 | wire bnk7_clk_stop_sync; | |
1001 | wire l2t7_clk_stop_prepresync; | |
1002 | wire l2t7_clk_stop_presync; | |
1003 | wire l2t7_clk_stop_sync; | |
1004 | wire mcu0_clk_stop_cavail; | |
1005 | wire mcu0_clk_stop_loop; | |
1006 | wire mcu0_clk_stop_prepresync; | |
1007 | wire mcu0_clk_stop_presync; | |
1008 | wire mcu0_clk_stop_sync; | |
1009 | wire mcu1_clk_stop_cavail; | |
1010 | wire mcu1_clk_stop_loop; | |
1011 | wire mcu1_clk_stop_prepresync; | |
1012 | wire mcu1_clk_stop_presync; | |
1013 | wire mcu1_clk_stop_sync; | |
1014 | wire mcu2_clk_stop_cavail; | |
1015 | wire mcu2_clk_stop_loop; | |
1016 | wire mcu2_clk_stop_prepresync; | |
1017 | wire mcu2_clk_stop_presync; | |
1018 | wire mcu2_clk_stop_sync; | |
1019 | wire mcu3_clk_stop_cavail; | |
1020 | wire mcu3_clk_stop_prepresync; | |
1021 | wire mcu3_clk_stop_presync; | |
1022 | wire mcu3_clk_stop_sync; | |
1023 | wire soc0_clk_stop_presync; | |
1024 | wire soc0_clk_stop_sync; | |
1025 | wire soc0_clk_stop_loop; | |
1026 | wire soc1_clk_stop_presync; | |
1027 | wire soc1_clk_stop_sync; | |
1028 | wire soc1_clk_stop_loop; | |
1029 | wire soc2_clk_stop_presync; | |
1030 | wire soc2_clk_stop_sync; | |
1031 | wire soc2_clk_stop_loop; | |
1032 | wire soc3_clk_stop_presync; | |
1033 | wire soc3_clk_stop_sync; | |
1034 | wire soc3_clk_stop_loop; | |
1035 | wire io_ac_tt_trigger; | |
1036 | wire tt_hold; | |
1037 | wire ac_tt_trigger; | |
1038 | wire sync_ff_ac_tt_trigger_fr_scanout_unused; | |
1039 | wire sync_ff_ac_tt_trigger_scanin; | |
1040 | wire sync_ff_ac_tt_trigger_scanout; | |
1041 | wire ac_tt_trigger_fr_sync_unused; | |
1042 | wire spc0_clk_stop; | |
1043 | wire spc0_clk_stop_q; | |
1044 | wire spc1_clk_stop; | |
1045 | wire spc1_clk_stop_q; | |
1046 | wire spc2_clk_stop; | |
1047 | wire spc2_clk_stop_q; | |
1048 | wire spc3_clk_stop; | |
1049 | wire spc3_clk_stop_q; | |
1050 | wire spc4_clk_stop; | |
1051 | wire spc4_clk_stop_q; | |
1052 | wire spc5_clk_stop; | |
1053 | wire spc5_clk_stop_q; | |
1054 | wire spc6_clk_stop; | |
1055 | wire spc6_clk_stop_q; | |
1056 | wire spc7_clk_stop; | |
1057 | wire spc7_clk_stop_q; | |
1058 | wire bnk0_clk_stop; | |
1059 | wire bnk0_clk_stop_q; | |
1060 | wire l2t0_clk_stop; | |
1061 | wire bnk1_clk_stop; | |
1062 | wire bnk1_clk_stop_q; | |
1063 | wire l2t1_clk_stop; | |
1064 | wire bnk2_clk_stop; | |
1065 | wire bnk2_clk_stop_q; | |
1066 | wire l2t2_clk_stop; | |
1067 | wire bnk3_clk_stop; | |
1068 | wire bnk3_clk_stop_q; | |
1069 | wire l2t3_clk_stop; | |
1070 | wire bnk4_clk_stop; | |
1071 | wire bnk4_clk_stop_q; | |
1072 | wire l2t4_clk_stop; | |
1073 | wire bnk5_clk_stop; | |
1074 | wire bnk5_clk_stop_q; | |
1075 | wire l2t5_clk_stop; | |
1076 | wire bnk6_clk_stop; | |
1077 | wire bnk6_clk_stop_q; | |
1078 | wire l2t6_clk_stop; | |
1079 | wire bnk7_clk_stop; | |
1080 | wire bnk7_clk_stop_q; | |
1081 | wire l2t7_clk_stop; | |
1082 | wire mcu0_clk_stop; | |
1083 | wire mcu0_clk_stop_q; | |
1084 | wire mcu1_clk_stop; | |
1085 | wire mcu1_clk_stop_q; | |
1086 | wire mcu2_clk_stop; | |
1087 | wire mcu2_clk_stop_q; | |
1088 | wire mcu3_clk_stop; | |
1089 | wire mcu3_clk_stop_q; | |
1090 | wire sync_ff_clk_stop_spc0_0_scanin; | |
1091 | wire sync_ff_clk_stop_spc0_0_scanout; | |
1092 | wire spc0_clk_stop_sync_l; | |
1093 | wire sync_ff_clk_stop_spc0_1_scanin; | |
1094 | wire sync_ff_clk_stop_spc0_1_scanout; | |
1095 | wire spc0_stopped_l; | |
1096 | wire sync_ff_clk_stop_spc1_0_scanin; | |
1097 | wire sync_ff_clk_stop_spc1_0_scanout; | |
1098 | wire spc1_clk_stop_sync_l; | |
1099 | wire sync_ff_clk_stop_spc1_1_scanin; | |
1100 | wire sync_ff_clk_stop_spc1_1_scanout; | |
1101 | wire spc1_stopped_l; | |
1102 | wire sync_ff_clk_stop_spc2_0_scanin; | |
1103 | wire sync_ff_clk_stop_spc2_0_scanout; | |
1104 | wire spc2_clk_stop_sync_l; | |
1105 | wire sync_ff_clk_stop_spc2_1_scanin; | |
1106 | wire sync_ff_clk_stop_spc2_1_scanout; | |
1107 | wire spc2_stopped_l; | |
1108 | wire sync_ff_clk_stop_spc3_0_scanin; | |
1109 | wire sync_ff_clk_stop_spc3_0_scanout; | |
1110 | wire spc3_clk_stop_sync_l; | |
1111 | wire sync_ff_clk_stop_spc3_1_scanin; | |
1112 | wire sync_ff_clk_stop_spc3_1_scanout; | |
1113 | wire spc3_stopped_l; | |
1114 | wire sync_ff_clk_stop_spc4_0_scanin; | |
1115 | wire sync_ff_clk_stop_spc4_0_scanout; | |
1116 | wire spc4_clk_stop_sync_l; | |
1117 | wire sync_ff_clk_stop_spc4_1_scanin; | |
1118 | wire sync_ff_clk_stop_spc4_1_scanout; | |
1119 | wire spc4_stopped_l; | |
1120 | wire sync_ff_clk_stop_spc5_0_scanin; | |
1121 | wire sync_ff_clk_stop_spc5_0_scanout; | |
1122 | wire spc5_clk_stop_sync_l; | |
1123 | wire sync_ff_clk_stop_spc5_1_scanin; | |
1124 | wire sync_ff_clk_stop_spc5_1_scanout; | |
1125 | wire spc5_stopped_l; | |
1126 | wire sync_ff_clk_stop_spc6_0_scanin; | |
1127 | wire sync_ff_clk_stop_spc6_0_scanout; | |
1128 | wire spc6_clk_stop_sync_l; | |
1129 | wire sync_ff_clk_stop_spc6_1_scanin; | |
1130 | wire sync_ff_clk_stop_spc6_1_scanout; | |
1131 | wire spc6_stopped_l; | |
1132 | wire sync_ff_clk_stop_spc7_0_scanin; | |
1133 | wire sync_ff_clk_stop_spc7_0_scanout; | |
1134 | wire spc7_clk_stop_sync_l; | |
1135 | wire sync_ff_clk_stop_spc7_1_scanin; | |
1136 | wire sync_ff_clk_stop_spc7_1_scanout; | |
1137 | wire spc7_stopped_l; | |
1138 | wire sync_ff_clk_stop_bnk0_0_scanin; | |
1139 | wire sync_ff_clk_stop_bnk0_0_scanout; | |
1140 | wire bnk0_clk_stop_sync_l; | |
1141 | wire sync_ff_clk_stop_bnk0_1_scanin; | |
1142 | wire sync_ff_clk_stop_bnk0_1_scanout; | |
1143 | wire bnk0_stopped_l; | |
1144 | wire sync_ff_clk_stop_l2t0_0_scanin; | |
1145 | wire sync_ff_clk_stop_l2t0_0_scanout; | |
1146 | wire l2t0_clk_stop_sync_l; | |
1147 | wire sync_ff_clk_stop_l2t0_1_scanin; | |
1148 | wire sync_ff_clk_stop_l2t0_1_scanout; | |
1149 | wire l2t0_stopped_l; | |
1150 | wire sync_ff_clk_stop_bnk1_0_scanin; | |
1151 | wire sync_ff_clk_stop_bnk1_0_scanout; | |
1152 | wire bnk1_clk_stop_sync_l; | |
1153 | wire sync_ff_clk_stop_bnk1_1_scanin; | |
1154 | wire sync_ff_clk_stop_bnk1_1_scanout; | |
1155 | wire bnk1_stopped_l; | |
1156 | wire sync_ff_clk_stop_l2t1_0_scanin; | |
1157 | wire sync_ff_clk_stop_l2t1_0_scanout; | |
1158 | wire l2t1_clk_stop_sync_l; | |
1159 | wire sync_ff_clk_stop_l2t1_1_scanin; | |
1160 | wire sync_ff_clk_stop_l2t1_1_scanout; | |
1161 | wire l2t1_stopped_l; | |
1162 | wire sync_ff_clk_stop_bnk2_0_scanin; | |
1163 | wire sync_ff_clk_stop_bnk2_0_scanout; | |
1164 | wire bnk2_clk_stop_sync_l; | |
1165 | wire sync_ff_clk_stop_bnk2_1_scanin; | |
1166 | wire sync_ff_clk_stop_bnk2_1_scanout; | |
1167 | wire bnk2_stopped_l; | |
1168 | wire sync_ff_clk_stop_l2t2_0_scanin; | |
1169 | wire sync_ff_clk_stop_l2t2_0_scanout; | |
1170 | wire l2t2_clk_stop_sync_l; | |
1171 | wire sync_ff_clk_stop_l2t2_1_scanin; | |
1172 | wire sync_ff_clk_stop_l2t2_1_scanout; | |
1173 | wire l2t2_stopped_l; | |
1174 | wire sync_ff_clk_stop_bnk3_0_scanin; | |
1175 | wire sync_ff_clk_stop_bnk3_0_scanout; | |
1176 | wire bnk3_clk_stop_sync_l; | |
1177 | wire sync_ff_clk_stop_bnk3_1_scanin; | |
1178 | wire sync_ff_clk_stop_bnk3_1_scanout; | |
1179 | wire bnk3_stopped_l; | |
1180 | wire sync_ff_clk_stop_l2t3_0_scanin; | |
1181 | wire sync_ff_clk_stop_l2t3_0_scanout; | |
1182 | wire l2t3_clk_stop_sync_l; | |
1183 | wire sync_ff_clk_stop_l2t3_1_scanin; | |
1184 | wire sync_ff_clk_stop_l2t3_1_scanout; | |
1185 | wire l2t3_stopped_l; | |
1186 | wire sync_ff_clk_stop_bnk4_0_scanin; | |
1187 | wire sync_ff_clk_stop_bnk4_0_scanout; | |
1188 | wire bnk4_clk_stop_sync_l; | |
1189 | wire sync_ff_clk_stop_bnk4_1_scanin; | |
1190 | wire sync_ff_clk_stop_bnk4_1_scanout; | |
1191 | wire bnk4_stopped_l; | |
1192 | wire sync_ff_clk_stop_l2t4_0_scanin; | |
1193 | wire sync_ff_clk_stop_l2t4_0_scanout; | |
1194 | wire l2t4_clk_stop_sync_l; | |
1195 | wire sync_ff_clk_stop_l2t4_1_scanin; | |
1196 | wire sync_ff_clk_stop_l2t4_1_scanout; | |
1197 | wire l2t4_stopped_l; | |
1198 | wire sync_ff_clk_stop_bnk5_0_scanin; | |
1199 | wire sync_ff_clk_stop_bnk5_0_scanout; | |
1200 | wire bnk5_clk_stop_sync_l; | |
1201 | wire sync_ff_clk_stop_bnk5_1_scanin; | |
1202 | wire sync_ff_clk_stop_bnk5_1_scanout; | |
1203 | wire bnk5_stopped_l; | |
1204 | wire sync_ff_clk_stop_l2t5_0_scanin; | |
1205 | wire sync_ff_clk_stop_l2t5_0_scanout; | |
1206 | wire l2t5_clk_stop_sync_l; | |
1207 | wire sync_ff_clk_stop_l2t5_1_scanin; | |
1208 | wire sync_ff_clk_stop_l2t5_1_scanout; | |
1209 | wire l2t5_stopped_l; | |
1210 | wire sync_ff_clk_stop_bnk6_0_scanin; | |
1211 | wire sync_ff_clk_stop_bnk6_0_scanout; | |
1212 | wire bnk6_clk_stop_sync_l; | |
1213 | wire sync_ff_clk_stop_bnk6_1_scanin; | |
1214 | wire sync_ff_clk_stop_bnk6_1_scanout; | |
1215 | wire bnk6_stopped_l; | |
1216 | wire sync_ff_clk_stop_l2t6_0_scanin; | |
1217 | wire sync_ff_clk_stop_l2t6_0_scanout; | |
1218 | wire l2t6_clk_stop_sync_l; | |
1219 | wire sync_ff_clk_stop_l2t6_1_scanin; | |
1220 | wire sync_ff_clk_stop_l2t6_1_scanout; | |
1221 | wire l2t6_stopped_l; | |
1222 | wire sync_ff_clk_stop_bnk7_0_scanin; | |
1223 | wire sync_ff_clk_stop_bnk7_0_scanout; | |
1224 | wire bnk7_clk_stop_sync_l; | |
1225 | wire sync_ff_clk_stop_bnk7_1_scanin; | |
1226 | wire sync_ff_clk_stop_bnk7_1_scanout; | |
1227 | wire bnk7_stopped_l; | |
1228 | wire sync_ff_clk_stop_l2t7_0_scanin; | |
1229 | wire sync_ff_clk_stop_l2t7_0_scanout; | |
1230 | wire l2t7_clk_stop_sync_l; | |
1231 | wire sync_ff_clk_stop_l2t7_1_scanin; | |
1232 | wire sync_ff_clk_stop_l2t7_1_scanout; | |
1233 | wire l2t7_stopped_l; | |
1234 | wire sync_ff_clk_stop_mcu0_0_scanin; | |
1235 | wire sync_ff_clk_stop_mcu0_0_scanout; | |
1236 | wire mcu0_clk_stop_sync_l; | |
1237 | wire sync_ff_clk_stop_mcu0_1_scanin; | |
1238 | wire sync_ff_clk_stop_mcu0_1_scanout; | |
1239 | wire mcu0_cmp_clk_stop_l; | |
1240 | wire mcu0_stopped_l; | |
1241 | wire sync_ff_ioclk_stop_mcu0_1_scanin; | |
1242 | wire sync_ff_ioclk_stop_mcu0_1_scanout; | |
1243 | wire cmp_io_sync_en_local; | |
1244 | wire mcu0_io_clk_stop_l; | |
1245 | wire mcu0_io_stopped_l; | |
1246 | wire sync_ff_drclk_stop_mcu0_1_scanin; | |
1247 | wire sync_ff_drclk_stop_mcu0_1_scanout; | |
1248 | wire mcu0_dr_clk_stop_l; | |
1249 | wire mcu0_dr_stopped_l; | |
1250 | wire mcu0_stopped; | |
1251 | wire mcu0_io_stopped; | |
1252 | wire mcu0_dr_stopped; | |
1253 | wire sync_ff_clk_stop_mcu1_0_scanin; | |
1254 | wire sync_ff_clk_stop_mcu1_0_scanout; | |
1255 | wire mcu1_clk_stop_sync_l; | |
1256 | wire sync_ff_clk_stop_mcu1_1_scanin; | |
1257 | wire sync_ff_clk_stop_mcu1_1_scanout; | |
1258 | wire mcu1_cmp_clk_stop_l; | |
1259 | wire mcu1_stopped_l; | |
1260 | wire sync_ff_ioclk_stop_mcu1_1_scanin; | |
1261 | wire sync_ff_ioclk_stop_mcu1_1_scanout; | |
1262 | wire mcu1_io_clk_stop_l; | |
1263 | wire mcu1_io_stopped_l; | |
1264 | wire sync_ff_drclk_stop_mcu1_1_scanin; | |
1265 | wire sync_ff_drclk_stop_mcu1_1_scanout; | |
1266 | wire mcu1_dr_clk_stop_l; | |
1267 | wire mcu1_dr_stopped_l; | |
1268 | wire mcu1_stopped; | |
1269 | wire mcu1_io_stopped; | |
1270 | wire mcu1_dr_stopped; | |
1271 | wire sync_ff_clk_stop_mcu2_0_scanin; | |
1272 | wire sync_ff_clk_stop_mcu2_0_scanout; | |
1273 | wire mcu2_clk_stop_sync_l; | |
1274 | wire sync_ff_clk_stop_mcu2_1_scanin; | |
1275 | wire sync_ff_clk_stop_mcu2_1_scanout; | |
1276 | wire mcu2_cmp_clk_stop_l; | |
1277 | wire mcu2_stopped_l; | |
1278 | wire sync_ff_ioclk_stop_mcu2_1_scanin; | |
1279 | wire sync_ff_ioclk_stop_mcu2_1_scanout; | |
1280 | wire mcu2_io_clk_stop_l; | |
1281 | wire mcu2_io_stopped_l; | |
1282 | wire sync_ff_drclk_stop_mcu2_1_scanin; | |
1283 | wire sync_ff_drclk_stop_mcu2_1_scanout; | |
1284 | wire mcu2_dr_clk_stop_l; | |
1285 | wire mcu2_dr_stopped_l; | |
1286 | wire mcu2_stopped; | |
1287 | wire mcu2_io_stopped; | |
1288 | wire mcu2_dr_stopped; | |
1289 | wire sync_ff_clk_stop_mcu3_0_scanin; | |
1290 | wire sync_ff_clk_stop_mcu3_0_scanout; | |
1291 | wire mcu3_clk_stop_sync_l; | |
1292 | wire sync_ff_clk_stop_mcu3_1_scanin; | |
1293 | wire sync_ff_clk_stop_mcu3_1_scanout; | |
1294 | wire mcu3_cmp_clk_stop_l; | |
1295 | wire mcu3_stopped_l; | |
1296 | wire sync_ff_ioclk_stop_mcu3_1_scanin; | |
1297 | wire sync_ff_ioclk_stop_mcu3_1_scanout; | |
1298 | wire mcu3_io_clk_stop_l; | |
1299 | wire mcu3_io_stopped_l; | |
1300 | wire sync_ff_drclk_stop_mcu3_1_scanin; | |
1301 | wire sync_ff_drclk_stop_mcu3_1_scanout; | |
1302 | wire mcu3_dr_clk_stop_l; | |
1303 | wire mcu3_dr_stopped_l; | |
1304 | wire mcu3_stopped; | |
1305 | wire mcu3_io_stopped; | |
1306 | wire mcu3_dr_stopped; | |
1307 | wire sync_ff_clk_stop_soc0_0_scanin; | |
1308 | wire sync_ff_clk_stop_soc0_0_scanout; | |
1309 | wire soc0_clk_stop_sync_l; | |
1310 | wire soc0_clk_stop; | |
1311 | wire sync_ff_clk_stop_soc0_1_scanin; | |
1312 | wire sync_ff_clk_stop_soc0_1_scanout; | |
1313 | wire soc0_cmp_clk_stop_l; | |
1314 | wire soc0_stopped_l; | |
1315 | wire sync_ff_ioclk_stop_soc0_1_scanin; | |
1316 | wire sync_ff_ioclk_stop_soc0_1_scanout; | |
1317 | wire soc0_io_clk_stop_l; | |
1318 | wire soc0_io_stopped_l; | |
1319 | wire soc0_stopped; | |
1320 | wire soc0_io_stopped; | |
1321 | wire sync_ff_clk_stop_soc1_0_scanin; | |
1322 | wire sync_ff_clk_stop_soc1_0_scanout; | |
1323 | wire soc1_clk_stop_sync_l; | |
1324 | wire soc1_clk_stop; | |
1325 | wire sync_ff_ioclk_stop_soc1_1_scanin; | |
1326 | wire sync_ff_ioclk_stop_soc1_1_scanout; | |
1327 | wire soc1_io_clk_stop_l; | |
1328 | wire soc1_io_stopped_l; | |
1329 | wire soc1_io_stopped; | |
1330 | wire sync_ff_clk_stop_soc2_0_scanin; | |
1331 | wire sync_ff_clk_stop_soc2_0_scanout; | |
1332 | wire soc2_clk_stop_sync_l; | |
1333 | wire soc2_clk_stop; | |
1334 | wire sync_ff_ioclk_stop_soc2_1_scanin; | |
1335 | wire sync_ff_ioclk_stop_soc2_1_scanout; | |
1336 | wire soc2_io_clk_stop_l; | |
1337 | wire soc2_io_stopped_l; | |
1338 | wire soc2_io_stopped; | |
1339 | wire sync_ff_clk_stop_soc3_0_scanin; | |
1340 | wire sync_ff_clk_stop_soc3_0_scanout; | |
1341 | wire soc3_clk_stop_sync_l; | |
1342 | wire soc3_clk_stop; | |
1343 | wire sync_ff_clk_stop_soc3_1_scanin; | |
1344 | wire sync_ff_clk_stop_soc3_1_scanout; | |
1345 | wire soc3_cmp_clk_stop_l; | |
1346 | wire soc3_stopped_l; | |
1347 | wire sync_ff_ioclk_stop_soc3_1_scanin; | |
1348 | wire sync_ff_ioclk_stop_soc3_1_scanout; | |
1349 | wire soc3_io_clk_stop_l; | |
1350 | wire soc3_io_stopped_l; | |
1351 | wire soc3_stopped; | |
1352 | wire soc3_io_stopped; | |
1353 | wire tcusig_ttclksel_reg_scanin; | |
1354 | wire tcusig_ttclksel_reg_scanout; | |
1355 | wire tap_spc0_mb_clk_stop_sync; | |
1356 | wire tap_spc1_mb_clk_stop_sync; | |
1357 | wire tap_spc2_mb_clk_stop_sync; | |
1358 | wire tap_spc3_mb_clk_stop_sync; | |
1359 | wire tap_spc4_mb_clk_stop_sync; | |
1360 | wire tap_spc5_mb_clk_stop_sync; | |
1361 | wire tap_spc6_mb_clk_stop_sync; | |
1362 | wire tap_spc7_mb_clk_stop_sync; | |
1363 | wire l2b0_mbist_clk_stop_sync; | |
1364 | wire l2t0_mbist_clk_stop_sync; | |
1365 | wire l2b1_mbist_clk_stop_sync; | |
1366 | wire l2t1_mbist_clk_stop_sync; | |
1367 | wire l2b2_mbist_clk_stop_sync; | |
1368 | wire l2t2_mbist_clk_stop_sync; | |
1369 | wire l2b3_mbist_clk_stop_sync; | |
1370 | wire l2t3_mbist_clk_stop_sync; | |
1371 | wire l2b4_mbist_clk_stop_sync; | |
1372 | wire l2t4_mbist_clk_stop_sync; | |
1373 | wire l2b5_mbist_clk_stop_sync; | |
1374 | wire l2t5_mbist_clk_stop_sync; | |
1375 | wire l2b6_mbist_clk_stop_sync; | |
1376 | wire l2t6_mbist_clk_stop_sync; | |
1377 | wire l2b7_mbist_clk_stop_sync; | |
1378 | wire l2t7_mbist_clk_stop_sync; | |
1379 | wire mcu0_mbist_clk_stop_sync; | |
1380 | wire mcu1_mbist_clk_stop_sync; | |
1381 | wire mcu2_mbist_clk_stop_sync; | |
1382 | wire mcu3_mbist_clk_stop_sync; | |
1383 | wire soc0_mbist_clk_stop_sync; | |
1384 | wire asic_stop_en; | |
1385 | wire asic_por_stop; | |
1386 | wire rdp_mbist_clk_stop_sync; | |
1387 | wire rtx_mbist_clk_stop_sync; | |
1388 | wire tds_mbist_clk_stop_sync; | |
1389 | wire dmu_mbist_clk_stop_sync; | |
1390 | wire peu_mbist_clk_stop_sync; | |
1391 | wire spc0_mb_scan_out; | |
1392 | wire flush_drive_0; | |
1393 | wire ser_scan_spc0_ch0; | |
1394 | wire spc1_mb_scan_out; | |
1395 | wire ser_scan_spc1_ch0; | |
1396 | wire byp_spc0_ch1_so; | |
1397 | wire spc2_mb_scan_out; | |
1398 | wire ser_scan_spc2_ch0; | |
1399 | wire byp_spc1_ch1_so; | |
1400 | wire spc3_mb_scan_out; | |
1401 | wire ser_scan_spc3_ch0; | |
1402 | wire byp_spc2_ch1_so; | |
1403 | wire spc4_mb_scan_out; | |
1404 | wire ser_scan_spc4_ch0; | |
1405 | wire byp_spc3_ch1_so; | |
1406 | wire spc5_mb_scan_out; | |
1407 | wire ser_scan_spc5_ch0; | |
1408 | wire byp_spc4_ch1_so; | |
1409 | wire spc6_mb_scan_out; | |
1410 | wire ser_scan_spc6_ch0; | |
1411 | wire byp_spc5_ch1_so; | |
1412 | wire spc7_mb_scan_out; | |
1413 | wire ser_scan_spc7_ch0; | |
1414 | wire byp_spc6_ch1_so; | |
1415 | wire not_flush_and_io_tdi; | |
1416 | wire spc0_shscan_scan_out; | |
1417 | wire ser_scan_spc0_ch1; | |
1418 | wire byp_spc0_tcu_shscan_scan_in; | |
1419 | wire byp_spc0_ch0_so; | |
1420 | wire spc1_shscan_scan_out; | |
1421 | wire ser_scan_spc1_ch1; | |
1422 | wire byp_spc1_tcu_shscan_scan_in; | |
1423 | wire byp_spc1_ch0_so; | |
1424 | wire spc2_shscan_scan_out; | |
1425 | wire ser_scan_spc2_ch1; | |
1426 | wire byp_spc2_tcu_shscan_scan_in; | |
1427 | wire byp_spc2_ch0_so; | |
1428 | wire spc3_shscan_scan_out; | |
1429 | wire ser_scan_spc3_ch1; | |
1430 | wire byp_spc3_tcu_shscan_scan_in; | |
1431 | wire byp_spc3_ch0_so; | |
1432 | wire spc4_shscan_scan_out; | |
1433 | wire ser_scan_spc4_ch1; | |
1434 | wire byp_spc4_tcu_shscan_scan_in; | |
1435 | wire byp_spc4_ch0_so; | |
1436 | wire spc5_shscan_scan_out; | |
1437 | wire ser_scan_spc5_ch1; | |
1438 | wire byp_spc5_tcu_shscan_scan_in; | |
1439 | wire byp_spc5_ch0_so; | |
1440 | wire spc6_shscan_scan_out; | |
1441 | wire ser_scan_spc6_ch1; | |
1442 | wire byp_spc6_tcu_shscan_scan_in; | |
1443 | wire byp_spc6_ch0_so; | |
1444 | wire spc7_shscan_scan_out; | |
1445 | wire ser_scan_spc7_ch1; | |
1446 | wire byp_spc7_tcu_shscan_scan_in; | |
1447 | wire byp_spc7_ch0_so; | |
1448 | wire byp_spc7_ch1_so; | |
1449 | wire byp_soca_so; | |
1450 | wire byp_socb_so; | |
1451 | wire byp_socc_so; | |
1452 | wire byp_socd_so; | |
1453 | wire byp_soce_so; | |
1454 | wire byp_socf_so; | |
1455 | wire byp_socg_so; | |
1456 | wire byp_soch_so; | |
1457 | wire byp_soc0_so; | |
1458 | wire byp_soc1_so; | |
1459 | wire byp_soc2_so; | |
1460 | wire byp_soc3_so; | |
1461 | wire byp_soc4_so; | |
1462 | wire byp_soc5_so; | |
1463 | wire sel_spc0_chains; | |
1464 | wire sel_spc1_chains; | |
1465 | wire sel_spc2_chains; | |
1466 | wire sel_spc3_chains; | |
1467 | wire sel_spc4_chains; | |
1468 | wire sel_spc5_chains; | |
1469 | wire sel_spc6_chains; | |
1470 | wire sel_spc7_chains; | |
1471 | wire byp_spc0_ch0; | |
1472 | wire byp_spc0_ch1; | |
1473 | wire byp_spc1_ch0; | |
1474 | wire byp_spc1_ch1; | |
1475 | wire byp_spc2_ch0; | |
1476 | wire byp_spc2_ch1; | |
1477 | wire byp_spc3_ch0; | |
1478 | wire byp_spc3_ch1; | |
1479 | wire byp_spc4_ch0; | |
1480 | wire byp_spc4_ch1; | |
1481 | wire byp_spc5_ch0; | |
1482 | wire byp_spc5_ch1; | |
1483 | wire byp_spc6_ch0; | |
1484 | wire byp_spc6_ch1; | |
1485 | wire byp_spc7_ch0; | |
1486 | wire byp_spc7_ch1; | |
1487 | wire byp_soca; | |
1488 | wire byp_socb; | |
1489 | wire byp_socc; | |
1490 | wire byp_socd; | |
1491 | wire byp_soce; | |
1492 | wire byp_socf; | |
1493 | wire byp_socg; | |
1494 | wire byp_soch; | |
1495 | wire byp_soc0; | |
1496 | wire byp_soc1; | |
1497 | wire byp_soc2; | |
1498 | wire byp_soc3; | |
1499 | wire byp_soc4; | |
1500 | wire byp_soc5; | |
1501 | wire byp_soc6; | |
1502 | wire byp_soc6_so; | |
1503 | wire mt_mode; | |
1504 | wire sel_only_spc_scan; | |
1505 | wire fm_scan_en; | |
1506 | wire flush_mode; | |
1507 | wire fm_aclk; | |
1508 | wire fm_bclk; | |
1509 | wire atpg_dectest; | |
1510 | wire atpg_muxtest; | |
1511 | wire sel_spc0; | |
1512 | wire sel_spc1; | |
1513 | wire sel_spc2; | |
1514 | wire sel_spc3; | |
1515 | wire sel_spc4; | |
1516 | wire sel_spc5; | |
1517 | wire sel_spc6; | |
1518 | wire sel_spc7; | |
1519 | wire jt_spc0_scan_en; | |
1520 | wire jt_spc1_scan_en; | |
1521 | wire jt_spc2_scan_en; | |
1522 | wire jt_spc3_scan_en; | |
1523 | wire jt_spc4_scan_en; | |
1524 | wire jt_spc5_scan_en; | |
1525 | wire jt_spc6_scan_en; | |
1526 | wire jt_spc7_scan_en; | |
1527 | wire fm_asic_scan_en; | |
1528 | wire jt_spc0_aclk; | |
1529 | wire jt_spc1_aclk; | |
1530 | wire jt_spc2_aclk; | |
1531 | wire jt_spc3_aclk; | |
1532 | wire jt_spc4_aclk; | |
1533 | wire jt_spc5_aclk; | |
1534 | wire jt_spc6_aclk; | |
1535 | wire jt_spc7_aclk; | |
1536 | wire jt_spc0_bclk; | |
1537 | wire jt_spc1_bclk; | |
1538 | wire jt_spc2_bclk; | |
1539 | wire jt_spc3_bclk; | |
1540 | wire jt_spc4_bclk; | |
1541 | wire jt_spc5_bclk; | |
1542 | wire jt_spc6_bclk; | |
1543 | wire jt_spc7_bclk; | |
1544 | wire atpg_pce_ov; | |
1545 | wire int_scan_in; | |
1546 | wire jtag_clk_stop_req_sync; | |
1547 | wire serdes_ac_mode_1; | |
1548 | wire serdes_ac_mode_0; | |
1549 | wire tcusig_srdacmode_reg_scanin; | |
1550 | wire tcusig_srdacmode_reg_scanout; | |
1551 | wire tcusig_cmpdrsync_reg_scanin; | |
1552 | wire tcusig_cmpdrsync_reg_scanout; | |
1553 | wire cmp_dr_sync_en_local_unused; | |
1554 | wire tcusig_pceov_reg_scanin; | |
1555 | wire tcusig_pceov_reg_scanout; | |
1556 | wire tcusig_ccu_clk_stop_reg_scanin; | |
1557 | wire tcusig_ccu_clk_stop_reg_scanout; | |
1558 | wire tcu_ccu_clk_stop_din; | |
1559 | wire tcu_ccu_clk_stop_dout; | |
1560 | wire tcusig_ccu_io_clk_stop_reg_scanin; | |
1561 | wire tcusig_ccu_io_clk_stop_reg_scanout; | |
1562 | wire tcu_ccu_io_clk_stop_din; | |
1563 | wire tcu_ccu_io_clk_stop_dout; | |
1564 | wire tcusig_rst_clk_stop_reg_scanin; | |
1565 | wire tcusig_rst_clk_stop_reg_scanout; | |
1566 | wire tcu_rst_clk_stop_din; | |
1567 | wire tcu_rst_clk_stop_dout; | |
1568 | wire tcusig_rst_io_clk_stop_reg_scanin; | |
1569 | wire tcusig_rst_io_clk_stop_reg_scanout; | |
1570 | wire tcu_rst_io_clk_stop_din; | |
1571 | wire tcu_rst_io_clk_stop_dout; | |
1572 | wire sync_ff_jtagporacc_scanin; | |
1573 | wire sync_ff_jtagporacc_scanout; | |
1574 | wire jtag_por_enable_sync; | |
1575 | wire sync_ff_sckbyp_scanin; | |
1576 | wire sync_ff_sckbyp_scanout; | |
1577 | wire jtag_sck_byp_sync; | |
1578 | wire pre_sck_bypass; | |
1579 | wire tcusig_sck_reg_scanin; | |
1580 | wire tcusig_sck_reg_scanout; | |
1581 | wire tap_spc7_mb_cs_sync_reg_scanin; | |
1582 | wire tap_spc7_mb_cs_sync_reg_scanout; | |
1583 | wire tap_spc6_mb_cs_sync_reg_scanin; | |
1584 | wire tap_spc6_mb_cs_sync_reg_scanout; | |
1585 | wire tap_spc5_mb_cs_sync_reg_scanin; | |
1586 | wire tap_spc5_mb_cs_sync_reg_scanout; | |
1587 | wire tap_spc4_mb_cs_sync_reg_scanin; | |
1588 | wire tap_spc4_mb_cs_sync_reg_scanout; | |
1589 | wire tap_spc3_mb_cs_sync_reg_scanin; | |
1590 | wire tap_spc3_mb_cs_sync_reg_scanout; | |
1591 | wire tap_spc2_mb_cs_sync_reg_scanin; | |
1592 | wire tap_spc2_mb_cs_sync_reg_scanout; | |
1593 | wire tap_spc1_mb_cs_sync_reg_scanin; | |
1594 | wire tap_spc1_mb_cs_sync_reg_scanout; | |
1595 | wire tap_spc0_mb_cs_sync_reg_scanin; | |
1596 | wire tap_spc0_mb_cs_sync_reg_scanout; | |
1597 | wire l2t7_mbist_cs_sync_reg_scanin; | |
1598 | wire l2t7_mbist_cs_sync_reg_scanout; | |
1599 | wire l2t6_mbist_cs_sync_reg_scanin; | |
1600 | wire l2t6_mbist_cs_sync_reg_scanout; | |
1601 | wire l2t5_mbist_cs_sync_reg_scanin; | |
1602 | wire l2t5_mbist_cs_sync_reg_scanout; | |
1603 | wire l2t4_mbist_cs_sync_reg_scanin; | |
1604 | wire l2t4_mbist_cs_sync_reg_scanout; | |
1605 | wire l2t3_mbist_cs_sync_reg_scanin; | |
1606 | wire l2t3_mbist_cs_sync_reg_scanout; | |
1607 | wire l2t2_mbist_cs_sync_reg_scanin; | |
1608 | wire l2t2_mbist_cs_sync_reg_scanout; | |
1609 | wire l2t1_mbist_cs_sync_reg_scanin; | |
1610 | wire l2t1_mbist_cs_sync_reg_scanout; | |
1611 | wire l2t0_mbist_cs_sync_reg_scanin; | |
1612 | wire l2t0_mbist_cs_sync_reg_scanout; | |
1613 | wire l2b7_mbist_cs_sync_reg_scanin; | |
1614 | wire l2b7_mbist_cs_sync_reg_scanout; | |
1615 | wire l2b6_mbist_cs_sync_reg_scanin; | |
1616 | wire l2b6_mbist_cs_sync_reg_scanout; | |
1617 | wire l2b5_mbist_cs_sync_reg_scanin; | |
1618 | wire l2b5_mbist_cs_sync_reg_scanout; | |
1619 | wire l2b4_mbist_cs_sync_reg_scanin; | |
1620 | wire l2b4_mbist_cs_sync_reg_scanout; | |
1621 | wire l2b3_mbist_cs_sync_reg_scanin; | |
1622 | wire l2b3_mbist_cs_sync_reg_scanout; | |
1623 | wire l2b2_mbist_cs_sync_reg_scanin; | |
1624 | wire l2b2_mbist_cs_sync_reg_scanout; | |
1625 | wire l2b1_mbist_cs_sync_reg_scanin; | |
1626 | wire l2b1_mbist_cs_sync_reg_scanout; | |
1627 | wire l2b0_mbist_cs_sync_reg_scanin; | |
1628 | wire l2b0_mbist_cs_sync_reg_scanout; | |
1629 | wire soc0_mbist_cs_sync_reg_scanin; | |
1630 | wire soc0_mbist_cs_sync_reg_scanout; | |
1631 | wire mcu3_mbist_cs_sync_reg_scanin; | |
1632 | wire mcu3_mbist_cs_sync_reg_scanout; | |
1633 | wire mcu2_mbist_cs_sync_reg_scanin; | |
1634 | wire mcu2_mbist_cs_sync_reg_scanout; | |
1635 | wire mcu1_mbist_cs_sync_reg_scanin; | |
1636 | wire mcu1_mbist_cs_sync_reg_scanout; | |
1637 | wire mcu0_mbist_cs_sync_reg_scanin; | |
1638 | wire mcu0_mbist_cs_sync_reg_scanout; | |
1639 | wire dmu_mbist_cs_sync_reg_scanin; | |
1640 | wire dmu_mbist_cs_sync_reg_scanout; | |
1641 | wire peu_mbist_cs_sync_reg_scanin; | |
1642 | wire peu_mbist_cs_sync_reg_scanout; | |
1643 | wire rdp_mbist_cs_sync_reg_scanin; | |
1644 | wire rdp_mbist_cs_sync_reg_scanout; | |
1645 | wire rtx_mbist_cs_sync_reg_scanin; | |
1646 | wire rtx_mbist_cs_sync_reg_scanout; | |
1647 | wire tds_mbist_cs_sync_reg_scanin; | |
1648 | wire tds_mbist_cs_sync_reg_scanout; | |
1649 | wire jtag_spc7_ss_cs_sync_reg_scanin; | |
1650 | wire jtag_spc7_ss_cs_sync_reg_scanout; | |
1651 | wire jtag_spc7_shscan_clk_stop_sync; | |
1652 | wire jtag_spc6_ss_cs_sync_reg_scanin; | |
1653 | wire jtag_spc6_ss_cs_sync_reg_scanout; | |
1654 | wire jtag_spc6_shscan_clk_stop_sync; | |
1655 | wire jtag_spc5_ss_cs_sync_reg_scanin; | |
1656 | wire jtag_spc5_ss_cs_sync_reg_scanout; | |
1657 | wire jtag_spc5_shscan_clk_stop_sync; | |
1658 | wire jtag_spc4_ss_cs_sync_reg_scanin; | |
1659 | wire jtag_spc4_ss_cs_sync_reg_scanout; | |
1660 | wire jtag_spc4_shscan_clk_stop_sync; | |
1661 | wire jtag_spc3_ss_cs_sync_reg_scanin; | |
1662 | wire jtag_spc3_ss_cs_sync_reg_scanout; | |
1663 | wire jtag_spc3_shscan_clk_stop_sync; | |
1664 | wire jtag_spc2_ss_cs_sync_reg_scanin; | |
1665 | wire jtag_spc2_ss_cs_sync_reg_scanout; | |
1666 | wire jtag_spc2_shscan_clk_stop_sync; | |
1667 | wire jtag_spc1_ss_cs_sync_reg_scanin; | |
1668 | wire jtag_spc1_ss_cs_sync_reg_scanout; | |
1669 | wire jtag_spc1_shscan_clk_stop_sync; | |
1670 | wire jtag_spc0_ss_cs_sync_reg_scanin; | |
1671 | wire jtag_spc0_ss_cs_sync_reg_scanout; | |
1672 | wire jtag_spc0_shscan_clk_stop_sync; | |
1673 | wire jtag_l2t7_ss_cs_sync_reg_scanin; | |
1674 | wire jtag_l2t7_ss_cs_sync_reg_scanout; | |
1675 | wire jtag_l2t7_shscan_clk_stop_sync; | |
1676 | wire jtag_l2t6_ss_cs_sync_reg_scanin; | |
1677 | wire jtag_l2t6_ss_cs_sync_reg_scanout; | |
1678 | wire jtag_l2t6_shscan_clk_stop_sync; | |
1679 | wire jtag_l2t5_ss_cs_sync_reg_scanin; | |
1680 | wire jtag_l2t5_ss_cs_sync_reg_scanout; | |
1681 | wire jtag_l2t5_shscan_clk_stop_sync; | |
1682 | wire jtag_l2t4_ss_cs_sync_reg_scanin; | |
1683 | wire jtag_l2t4_ss_cs_sync_reg_scanout; | |
1684 | wire jtag_l2t4_shscan_clk_stop_sync; | |
1685 | wire jtag_l2t3_ss_cs_sync_reg_scanin; | |
1686 | wire jtag_l2t3_ss_cs_sync_reg_scanout; | |
1687 | wire jtag_l2t3_shscan_clk_stop_sync; | |
1688 | wire jtag_l2t2_ss_cs_sync_reg_scanin; | |
1689 | wire jtag_l2t2_ss_cs_sync_reg_scanout; | |
1690 | wire jtag_l2t2_shscan_clk_stop_sync; | |
1691 | wire jtag_l2t1_ss_cs_sync_reg_scanin; | |
1692 | wire jtag_l2t1_ss_cs_sync_reg_scanout; | |
1693 | wire jtag_l2t1_shscan_clk_stop_sync; | |
1694 | wire jtag_l2t0_ss_cs_sync_reg_scanin; | |
1695 | wire jtag_l2t0_ss_cs_sync_reg_scanout; | |
1696 | wire jtag_l2t0_shscan_clk_stop_sync; | |
1697 | wire jtag_spc_ss_pce_ov_sync_reg_scanin; | |
1698 | wire jtag_spc_ss_pce_ov_sync_reg_scanout; | |
1699 | wire jtag_spc_shscan_pce_ov_sync; | |
1700 | wire jtag_l2t_ss_pce_ov_sync_reg_scanin; | |
1701 | wire jtag_l2t_ss_pce_ov_sync_reg_scanout; | |
1702 | wire jtag_l2t_shscan_pce_ov_sync; | |
1703 | wire jtag_clk_stop_req_sync_reg_scanin; | |
1704 | wire jtag_clk_stop_req_sync_reg_scanout; | |
1705 | wire jtag_efu_clear_instr_sync_reg_scanin; | |
1706 | wire jtag_efu_clear_instr_sync_reg_scanout; | |
1707 | wire instr_sstop_csmode_sync_reg_scanin; | |
1708 | wire instr_sstop_csmode_sync_reg_scanout; | |
1709 | wire sync_ff_jtagclkdlyupd_scanin; | |
1710 | wire sync_ff_jtagclkdlyupd_scanout; | |
1711 | wire jtag_serscan_sync_reg_scanin; | |
1712 | wire jtag_serscan_sync_reg_scanout; | |
1713 | wire jt_scan_mtmode_sync; | |
1714 | wire [20:0] shscan_clk_stop_sync; | |
1715 | wire shscan_clk_stop_io_sync_reg_scanin; | |
1716 | wire shscan_clk_stop_io_sync_reg_scanout; | |
1717 | wire [20:0] shscan_clk_stop_io; | |
1718 | wire spare_scanin; | |
1719 | wire spare_scanout; | |
1720 | wire [8:0] spare_flops_d; | |
1721 | wire [8:0] spare_flops_q; | |
1722 | wire [8:1] spare_flops_unused; | |
1723 | wire [0:0] spare0_flop_unused; | |
1724 | wire tcusig_noflush_scanout; | |
1725 | ||
1726 | ||
1727 | `define CSDEL 7 | |
1728 | `define CSDEL_MSB 6 | |
1729 | `define CSDEL_MAX 7'b1111111 | |
1730 | ||
1731 | // External Clocks - to CCU | |
1732 | input mio_ext_cmp_clk; | |
1733 | input mio_ext_dr_clk; | |
1734 | output tcu_ccu_ext_dr_clk; | |
1735 | output tcu_ccu_ext_cmp_clk; | |
1736 | output tcu_ccu_clk_stop; | |
1737 | output tcu_ccu_io_clk_stop; | |
1738 | output tcu_rst_clk_stop; | |
1739 | output tcu_rst_io_clk_stop; | |
1740 | ||
1741 | input mbist_clk_stop; | |
1742 | ||
1743 | // External Clock for JTAG Macrotest | |
1744 | input tck_clk_tree; | |
1745 | // External Clocks - for PEU | |
1746 | input mio_tcu_peu_clk_ext; | |
1747 | output tcu_peu_clk_ext; | |
1748 | // External Clocks - for NIU | |
1749 | input [5:0] mio_tcu_niu_clk_ext; | |
1750 | output mac_125rx_test_clk; | |
1751 | output mac_125tx_test_clk; | |
1752 | output mac_156rx_test_clk; | |
1753 | output mac_156tx_test_clk; | |
1754 | output mac_312rx_test_clk; | |
1755 | output mac_312tx_test_clk; | |
1756 | // PLL Bypass from Pins | |
1757 | input mio_tcu_pll_cmp_bypass; | |
1758 | // Divider Bypass to cluster headers | |
1759 | input mio_tcu_divider_bypass; | |
1760 | output tcu_div_bypass; | |
1761 | ||
1762 | // Synchronization enable | |
1763 | input cmp_io_sync_en; // enable io_clk_stops with this | |
1764 | input io_cmp_sync_en; // enable bank_enable (_baxx) | |
1765 | input cmp_dr_sync_en; // enable dr_clk_stops with this | |
1766 | ||
1767 | // Enable for PEU Test Congif Port | |
1768 | output tcu_peu_testmode; | |
1769 | // Testmode for NIU | |
1770 | output tcu_mac_testmode; | |
1771 | // Testmode for SPC Cores | |
1772 | output tcu_spc0_test_mode; | |
1773 | output tcu_spc1_test_mode; | |
1774 | output tcu_spc2_test_mode; | |
1775 | output tcu_spc3_test_mode; | |
1776 | output tcu_spc4_test_mode; | |
1777 | output tcu_spc5_test_mode; | |
1778 | output tcu_spc6_test_mode; | |
1779 | output tcu_spc7_test_mode; | |
1780 | // Testmode for RST | |
1781 | output tcu_rst_scan_mode; | |
1782 | // ATPG Test mode excluding Trans. Test | |
1783 | output tcu_atpg_mode; | |
1784 | ||
1785 | // To control fbd logic in MCU | |
1786 | output tcu_mcu_testmode; | |
1787 | ||
1788 | ||
1789 | //inputs | |
1790 | input io_aclk; | |
1791 | input io_bclk; | |
1792 | input l2clk; | |
1793 | input io_tdi; | |
1794 | input [30:0] io_scan_in; | |
1795 | ||
1796 | input [1:0] spc0_tcu_scan_in; | |
1797 | input [1:0] spc1_tcu_scan_in; | |
1798 | input [1:0] spc2_tcu_scan_in; | |
1799 | input [1:0] spc3_tcu_scan_in; | |
1800 | input [1:0] spc4_tcu_scan_in; | |
1801 | input [1:0] spc5_tcu_scan_in; | |
1802 | input [1:0] spc6_tcu_scan_in; | |
1803 | input [1:0] spc7_tcu_scan_in; | |
1804 | input soca_tcu_scan_in; | |
1805 | input socb_tcu_scan_in; | |
1806 | input socc_tcu_scan_in; | |
1807 | input socd_tcu_scan_in; | |
1808 | input soce_tcu_scan_in; | |
1809 | input socf_tcu_scan_in; | |
1810 | input socg_tcu_scan_in; | |
1811 | input soch_tcu_scan_in; | |
1812 | input soc0_tcu_scan_in; | |
1813 | input soc1_tcu_scan_in; | |
1814 | input soc2_tcu_scan_in; | |
1815 | input soc3_tcu_scan_in; | |
1816 | input soc4_tcu_scan_in; | |
1817 | input soc5_tcu_scan_in; | |
1818 | input soc6_tcu_scan_in; | |
1819 | input peu_tcu_scan_in; | |
1820 | input ccu_tcu_scan_in; | |
1821 | input jtag_sbs_scan_in; | |
1822 | input mio_tcu_bs_scan_out; | |
1823 | //input srdes_tcu_scan_in; | |
1824 | input io_test_mode; | |
1825 | input jtag_ser_scan_q; // decoded signal from jtag ECO yyyyyy | |
1826 | input io_scan_en; | |
1827 | input clk_stop_ac_trans_counter_initiated; | |
1828 | input io_ac_test_mode; | |
1829 | input io_ac_testtrig; | |
1830 | output ac_test_mode; | |
1831 | input [23:0] debug_reg_hard_stop_domain_1st; | |
1832 | input debug_cycle_counter_stop; | |
1833 | input debug_event_stop; | |
1834 | input spc_ss_mode; | |
1835 | input [7:0] spc_ss_sel; | |
1836 | //input instr_clock_sstop; | |
1837 | input instr_sstop_csmode; | |
1838 | input tcu_scan_chain; | |
1839 | // Reset Support | |
1840 | input POR_; | |
1841 | input jtag_clk_stop_req; | |
1842 | input jtagclkstop_ov; | |
1843 | input rst_tcu_flush_init_req; | |
1844 | input rst_tcu_flush_stop_req; | |
1845 | input rst_tcu_asicflush_stop_req; | |
1846 | input rst_wmr_protect; | |
1847 | input rst_tcu_dbr_gen; | |
1848 | output tcu_rst_flush_init_ack; | |
1849 | output tcu_rst_flush_stop_ack; | |
1850 | output tcu_rst_asicflush_stop_ack; | |
1851 | output tcu_rst_efu_done; | |
1852 | // Send signal to protect live blocks during scan flush | |
1853 | output flush_test_protect; | |
1854 | // To block inputs when in test protect mode | |
1855 | input tcu_test_protect_cmp; | |
1856 | // JTAG SCK Counter Bypass Signal | |
1857 | input jtag_sck_byp; | |
1858 | output tcu_sck_bypass; | |
1859 | // JTAG Access during POR | |
1860 | input jtag_por_enable; | |
1861 | output jtag_por_status; | |
1862 | // Clear and Start EFU during POR | |
1863 | input jtag_efu_clear_instr; // From JTAG | |
1864 | input [6:0] jtag_efu_rvclr; // From JTAG | |
1865 | output tcu_efu_read_start; // Start EFuse shifting rows | |
1866 | output [6:0] tcu_efu_rvclr; // Tell EFuse to clear destinations | |
1867 | // Serial Scan via JTAG (for scandump) | |
1868 | input jt_scan_in; // from TDI, via jtag ser_scan instruction | |
1869 | input jt_scan_en; // from jtag ser_scan instruction | |
1870 | input jt_scan_aclk; // from jtag ser_scan instruction | |
1871 | input jt_scan_bclk; // from jtag ser_scan instruction | |
1872 | output ser_scan_out; // to jtag, then to TDO | |
1873 | input chain_select; // enables sel_chain register for scandump | |
1874 | input [4:0] sel_chain; // selects one of 32 chains, others bypassed | |
1875 | // LBIST start signals, so array write inhibit can be generated from them | |
1876 | input [7:0] tcu_spc_lbist_start; | |
1877 | // Control of MBIST scan chains for SPC cores | |
1878 | input tap_spc0_mb_aclk; | |
1879 | input tap_spc0_mb_bclk; | |
1880 | input tap_spc0_mb_scan_en; | |
1881 | input tap_spc0_mb_clk_stop; | |
1882 | input tap_spc1_mb_aclk; | |
1883 | input tap_spc1_mb_bclk; | |
1884 | input tap_spc1_mb_scan_en; | |
1885 | input tap_spc1_mb_clk_stop; | |
1886 | input tap_spc2_mb_aclk; | |
1887 | input tap_spc2_mb_bclk; | |
1888 | input tap_spc2_mb_scan_en; | |
1889 | input tap_spc2_mb_clk_stop; | |
1890 | input tap_spc3_mb_aclk; | |
1891 | input tap_spc3_mb_bclk; | |
1892 | input tap_spc3_mb_scan_en; | |
1893 | input tap_spc3_mb_clk_stop; | |
1894 | input tap_spc4_mb_aclk; | |
1895 | input tap_spc4_mb_bclk; | |
1896 | input tap_spc4_mb_scan_en; | |
1897 | input tap_spc4_mb_clk_stop; | |
1898 | input tap_spc5_mb_aclk; | |
1899 | input tap_spc5_mb_bclk; | |
1900 | input tap_spc5_mb_scan_en; | |
1901 | input tap_spc5_mb_clk_stop; | |
1902 | input tap_spc6_mb_aclk; | |
1903 | input tap_spc6_mb_bclk; | |
1904 | input tap_spc6_mb_scan_en; | |
1905 | input tap_spc6_mb_clk_stop; | |
1906 | input tap_spc7_mb_aclk; | |
1907 | input tap_spc7_mb_bclk; | |
1908 | input tap_spc7_mb_scan_en; | |
1909 | input tap_spc7_mb_clk_stop; | |
1910 | ||
1911 | //scan | |
1912 | input scan_in; | |
1913 | output scan_out; | |
1914 | // Test Signals for MFG ATPG Scan | |
1915 | output tcu_dectest; | |
1916 | output tcu_muxtest; | |
1917 | ||
1918 | //outputs | |
1919 | output tcu_jtag_flush_req; | |
1920 | output tcu_jtag_flush_dly_req; | |
1921 | output tcu_aclk; | |
1922 | output tcu_bclk; | |
1923 | output tcu_scan_en; | |
1924 | input jtag_mt_enable; // enable for macrotest | |
1925 | // Scan controls to SPC0 | |
1926 | output tcu_spc0_aclk; | |
1927 | output tcu_spc0_bclk; | |
1928 | output tcu_spc0_scan_en; | |
1929 | output tcu_spc0_se_scancollar_in; | |
1930 | output tcu_spc0_se_scancollar_out; | |
1931 | output tcu_spc0_array_wr_inhibit; | |
1932 | // Scan controls to SPC1 | |
1933 | output tcu_spc1_aclk; | |
1934 | output tcu_spc1_bclk; | |
1935 | output tcu_spc1_scan_en; | |
1936 | output tcu_spc1_se_scancollar_in; | |
1937 | output tcu_spc1_se_scancollar_out; | |
1938 | output tcu_spc1_array_wr_inhibit; | |
1939 | // Scan controls to SPC2 | |
1940 | output tcu_spc2_aclk; | |
1941 | output tcu_spc2_bclk; | |
1942 | output tcu_spc2_scan_en; | |
1943 | output tcu_spc2_se_scancollar_in; | |
1944 | output tcu_spc2_se_scancollar_out; | |
1945 | output tcu_spc2_array_wr_inhibit; | |
1946 | // Scan controls to SPC3 | |
1947 | output tcu_spc3_aclk; | |
1948 | output tcu_spc3_bclk; | |
1949 | output tcu_spc3_scan_en; | |
1950 | output tcu_spc3_se_scancollar_in; | |
1951 | output tcu_spc3_se_scancollar_out; | |
1952 | output tcu_spc3_array_wr_inhibit; | |
1953 | // Scan controls to SPC4 | |
1954 | output tcu_spc4_aclk; | |
1955 | output tcu_spc4_bclk; | |
1956 | output tcu_spc4_scan_en; | |
1957 | output tcu_spc4_se_scancollar_in; | |
1958 | output tcu_spc4_se_scancollar_out; | |
1959 | output tcu_spc4_array_wr_inhibit; | |
1960 | // Scan controls to SPC5 | |
1961 | output tcu_spc5_aclk; | |
1962 | output tcu_spc5_bclk; | |
1963 | output tcu_spc5_scan_en; | |
1964 | output tcu_spc5_se_scancollar_in; | |
1965 | output tcu_spc5_se_scancollar_out; | |
1966 | output tcu_spc5_array_wr_inhibit; | |
1967 | // Scan controls to SPC6 | |
1968 | output tcu_spc6_aclk; | |
1969 | output tcu_spc6_bclk; | |
1970 | output tcu_spc6_scan_en; | |
1971 | output tcu_spc6_se_scancollar_in; | |
1972 | output tcu_spc6_se_scancollar_out; | |
1973 | output tcu_spc6_array_wr_inhibit; | |
1974 | // Scan controls to SPC7 | |
1975 | output tcu_spc7_aclk; | |
1976 | output tcu_spc7_bclk; | |
1977 | output tcu_spc7_scan_en; | |
1978 | output tcu_spc7_se_scancollar_in; | |
1979 | output tcu_spc7_se_scancollar_out; | |
1980 | output tcu_spc7_array_wr_inhibit; | |
1981 | ||
1982 | // Scan Controls to ASICs (NIU, DMU, PEU) | |
1983 | // NIU is RDP, MAC, RTX, and TDS | |
1984 | output tcu_asic_aclk; | |
1985 | output tcu_asic_bclk; | |
1986 | output tcu_asic_scan_en; | |
1987 | output tcu_asic_se_scancollar_in; | |
1988 | output tcu_asic_se_scancollar_out; | |
1989 | output tcu_asic_array_wr_inhibit; | |
1990 | ||
1991 | output tcu_int_se; // scan enable for TCU only | |
1992 | output tcu_jtag_se; // scan enable for jtag only | |
1993 | output tcu_int_aclk; // aclk for TCU only | |
1994 | output tcu_int_bclk; // bclk for TCU only | |
1995 | output tcu_int_ce; // pce for TCU only | |
1996 | output tcu_int_ce_to_ucb;// pce for TCU UCB only ECO A | |
1997 | output tcu_int_pce_ov;// pce override for TCU only | |
1998 | output tcu_jtag_aclk; // aclk for jtag only | |
1999 | output [1:0] tcu_spc0_scan_out; | |
2000 | output [1:0] tcu_spc1_scan_out; | |
2001 | output [1:0] tcu_spc2_scan_out; | |
2002 | output [1:0] tcu_spc3_scan_out; | |
2003 | output [1:0] tcu_spc4_scan_out; | |
2004 | output [1:0] tcu_spc5_scan_out; | |
2005 | output [1:0] tcu_spc6_scan_out; | |
2006 | output [1:0] tcu_spc7_scan_out; | |
2007 | output tcu_soca_scan_out; | |
2008 | output tcu_socb_scan_out; | |
2009 | output tcu_socc_scan_out; | |
2010 | output tcu_socd_scan_out; | |
2011 | output tcu_soce_scan_out; | |
2012 | output tcu_socf_scan_out; | |
2013 | output tcu_socg_scan_out; | |
2014 | output tcu_soch_scan_out; | |
2015 | output tcu_soc0_scan_out; | |
2016 | output tcu_soc1_scan_out; | |
2017 | output tcu_soc2_scan_out; | |
2018 | output tcu_soc3_scan_out; | |
2019 | output tcu_soc4_scan_out; | |
2020 | output tcu_soc5_scan_out; | |
2021 | output tcu_soc6_scan_out; | |
2022 | output tcu_peu_scan_out; | |
2023 | output tcu_rst_scan_out; | |
2024 | output tcu_sbs_scan_in; | |
2025 | output [30:0] tcu_pins_scan_out; | |
2026 | ||
2027 | output pre_spc0_clk_stop; | |
2028 | output pre_spc1_clk_stop; | |
2029 | output pre_spc2_clk_stop; | |
2030 | output pre_spc3_clk_stop; | |
2031 | output pre_spc4_clk_stop; | |
2032 | output pre_spc5_clk_stop; | |
2033 | output pre_spc6_clk_stop; | |
2034 | output pre_spc7_clk_stop; | |
2035 | ||
2036 | output pre_bnk0_clk_stop; | |
2037 | output pre_l2t0_clk_stop; | |
2038 | output pre_bnk1_clk_stop; | |
2039 | output pre_l2t1_clk_stop; | |
2040 | output pre_bnk2_clk_stop; | |
2041 | output pre_l2t2_clk_stop; | |
2042 | output pre_bnk3_clk_stop; | |
2043 | output pre_l2t3_clk_stop; | |
2044 | output pre_bnk4_clk_stop; | |
2045 | output pre_l2t4_clk_stop; | |
2046 | output pre_bnk5_clk_stop; | |
2047 | output pre_l2t5_clk_stop; | |
2048 | output pre_bnk6_clk_stop; | |
2049 | output pre_l2t6_clk_stop; | |
2050 | output pre_bnk7_clk_stop; | |
2051 | output pre_l2t7_clk_stop; | |
2052 | ||
2053 | ||
2054 | output pre_mcu0_clk_stop; | |
2055 | output pre_mcu0_io_clk_stop; | |
2056 | output pre_mcu0_dr_clk_stop; | |
2057 | output pre_mcu0_fbd_clk_stop; | |
2058 | ||
2059 | output pre_mcu1_clk_stop; | |
2060 | output pre_mcu1_io_clk_stop; | |
2061 | output pre_mcu1_dr_clk_stop; | |
2062 | output pre_mcu1_fbd_clk_stop; | |
2063 | ||
2064 | output pre_mcu2_clk_stop; | |
2065 | output pre_mcu2_io_clk_stop; | |
2066 | output pre_mcu2_dr_clk_stop; | |
2067 | output pre_mcu2_fbd_clk_stop; | |
2068 | ||
2069 | output pre_mcu3_clk_stop; | |
2070 | output pre_mcu3_io_clk_stop; | |
2071 | output pre_mcu3_dr_clk_stop; | |
2072 | output pre_mcu3_fbd_clk_stop; | |
2073 | ||
2074 | output pre_soc0_clk_stop; | |
2075 | output pre_soc0_io_clk_stop; | |
2076 | ||
2077 | output pre_soc1_io_clk_stop; | |
2078 | output pre_soc2_io_clk_stop; | |
2079 | output pre_soc3_clk_stop; | |
2080 | output pre_soc3_io_clk_stop; | |
2081 | ||
2082 | output tcu_pce_ov; | |
2083 | output ac_trans_test_counter_start; | |
2084 | ||
2085 | //These are for mbist to allow JTAG to control | |
2086 | // a portion of the scan chain when not in test mode | |
2087 | input spc0_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2088 | input tap_spc0_mb_scan_out; // from JTAG, muxed to core mbist | |
2089 | output tcu_spc0_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2090 | output spc0_tap_mb_scan_in; // goes to JTAG tdo | |
2091 | input spc1_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2092 | input tap_spc1_mb_scan_out; // from JTAG, muxed to core mbist | |
2093 | output tcu_spc1_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2094 | output spc1_tap_mb_scan_in; // goes to JTAG tdo | |
2095 | input spc2_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2096 | input tap_spc2_mb_scan_out; // from JTAG, muxed to core mbist | |
2097 | output tcu_spc2_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2098 | output spc2_tap_mb_scan_in; // goes to JTAG tdo | |
2099 | input spc3_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2100 | input tap_spc3_mb_scan_out; // from JTAG, muxed to core mbist | |
2101 | output tcu_spc3_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2102 | output spc3_tap_mb_scan_in; // goes to JTAG tdo | |
2103 | input spc4_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2104 | input tap_spc4_mb_scan_out; // from JTAG, muxed to core mbist | |
2105 | output tcu_spc4_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2106 | output spc4_tap_mb_scan_in; // goes to JTAG tdo | |
2107 | input spc5_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2108 | input tap_spc5_mb_scan_out; // from JTAG, muxed to core mbist | |
2109 | output tcu_spc5_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2110 | output spc5_tap_mb_scan_in; // goes to JTAG tdo | |
2111 | input spc6_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2112 | input tap_spc6_mb_scan_out; // from JTAG, muxed to core mbist | |
2113 | output tcu_spc6_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2114 | output spc6_tap_mb_scan_in; // goes to JTAG tdo | |
2115 | input spc7_tcu_mbist_scan_in; // from core mbist, goes to tdo or back to core | |
2116 | input tap_spc7_mb_scan_out; // from JTAG, muxed to core mbist | |
2117 | output tcu_spc7_mb_scan_out; // mux either JTAG or pad si; goes to core mbist | |
2118 | output spc7_tap_mb_scan_in; // goes to JTAG tdo | |
2119 | ||
2120 | // SOC MBIST Scan Outputs From TCU | |
2121 | output tcu_sii_mbist_scan_in; | |
2122 | output tcu_sio_mbist_scan_in; | |
2123 | output tcu_ncu_mbist_scan_in; | |
2124 | output tcu_mcu0_mbist_scan_in; | |
2125 | output tcu_mcu1_mbist_scan_in; | |
2126 | output tcu_mcu2_mbist_scan_in; | |
2127 | output tcu_mcu3_mbist_scan_in; | |
2128 | output tcu_l2b0_mbist_scan_in; | |
2129 | output tcu_l2b1_mbist_scan_in; | |
2130 | output tcu_l2b2_mbist_scan_in; | |
2131 | output tcu_l2b3_mbist_scan_in; | |
2132 | output tcu_l2b4_mbist_scan_in; | |
2133 | output tcu_l2b5_mbist_scan_in; | |
2134 | output tcu_l2b6_mbist_scan_in; | |
2135 | output tcu_l2b7_mbist_scan_in; | |
2136 | output tcu_l2t0_mbist_scan_in; | |
2137 | output tcu_l2t1_mbist_scan_in; | |
2138 | output tcu_l2t2_mbist_scan_in; | |
2139 | output tcu_l2t3_mbist_scan_in; | |
2140 | output tcu_l2t4_mbist_scan_in; | |
2141 | output tcu_l2t5_mbist_scan_in; | |
2142 | output tcu_l2t6_mbist_scan_in; | |
2143 | output tcu_l2t7_mbist_scan_in; | |
2144 | output tcu_dmu_mbist_scan_in; | |
2145 | output tcu_peu_mbist_scan_in; | |
2146 | output rdp_rdmc_mbist_scan_in; | |
2147 | output rtx_mbist_scan_in; | |
2148 | output tds_mbist_scan_in; | |
2149 | ||
2150 | // SOC MBIST Scan Input To TCU | |
2151 | input sii_tcu_mbist_scan_out; | |
2152 | input sio_tcu_mbist_scan_out; | |
2153 | input ncu_tcu_mbist_scan_out; | |
2154 | input mcu0_tcu_mbist_scan_out; | |
2155 | input mcu1_tcu_mbist_scan_out; | |
2156 | input mcu2_tcu_mbist_scan_out; | |
2157 | input mcu3_tcu_mbist_scan_out; | |
2158 | input l2b0_tcu_mbist_scan_out; | |
2159 | input l2b1_tcu_mbist_scan_out; | |
2160 | input l2b2_tcu_mbist_scan_out; | |
2161 | input l2b3_tcu_mbist_scan_out; | |
2162 | input l2b4_tcu_mbist_scan_out; | |
2163 | input l2b5_tcu_mbist_scan_out; | |
2164 | input l2b6_tcu_mbist_scan_out; | |
2165 | input l2b7_tcu_mbist_scan_out; | |
2166 | input l2t0_tcu_mbist_scan_out; | |
2167 | input l2t1_tcu_mbist_scan_out; | |
2168 | input l2t2_tcu_mbist_scan_out; | |
2169 | input l2t3_tcu_mbist_scan_out; | |
2170 | input l2t4_tcu_mbist_scan_out; | |
2171 | input l2t5_tcu_mbist_scan_out; | |
2172 | input l2t6_tcu_mbist_scan_out; | |
2173 | input l2t7_tcu_mbist_scan_out; | |
2174 | input dmu_tcu_mbist_scan_out; | |
2175 | input peu_tcu_mbist_scan_out; | |
2176 | input rdp_rdmc_mbist_scan_out; | |
2177 | input rtx_mbist_scan_out; | |
2178 | input tds_mbist_scan_out; | |
2179 | ||
2180 | input spc0_tcu_lbist_scan_out; | |
2181 | input spc1_tcu_lbist_scan_out; | |
2182 | input spc2_tcu_lbist_scan_out; | |
2183 | input spc3_tcu_lbist_scan_out; | |
2184 | input spc4_tcu_lbist_scan_out; | |
2185 | input spc5_tcu_lbist_scan_out; | |
2186 | input spc6_tcu_lbist_scan_out; | |
2187 | input spc7_tcu_lbist_scan_out; | |
2188 | output [7:0] tcu_spc_lbist_scan_in; | |
2189 | ||
2190 | //These are for Shadow scan (SHSCAN) to allow JTAG to control | |
2191 | // a portion of the scan chain when not in test mode | |
2192 | input spc0_tcu_shscan_scan_in; // from core 0 | |
2193 | input spc1_tcu_shscan_scan_in; | |
2194 | input spc2_tcu_shscan_scan_in; | |
2195 | input spc3_tcu_shscan_scan_in; | |
2196 | input spc4_tcu_shscan_scan_in; | |
2197 | input spc5_tcu_shscan_scan_in; | |
2198 | input spc6_tcu_shscan_scan_in; | |
2199 | input spc7_tcu_shscan_scan_in; // from core 7, also to jtag | |
2200 | output tcu_spc0_shscan_scan_out; // to core 0 | |
2201 | output tcu_spc1_shscan_scan_out; | |
2202 | output tcu_spc2_shscan_scan_out; | |
2203 | output tcu_spc3_shscan_scan_out; | |
2204 | output tcu_spc4_shscan_scan_out; | |
2205 | output tcu_spc5_shscan_scan_out; | |
2206 | output tcu_spc6_shscan_scan_out; | |
2207 | output tcu_spc7_shscan_scan_out; | |
2208 | input tap_spc0_shscan_scan_out; // from jtag TDI | |
2209 | output spc7_tap_shscan_scan_in; // to jtag TDO | |
2210 | // Shadow Scan ID and Clock-Stop Transferred to IO CLK Domain | |
2211 | input [2:0] jtag_spc_shscanid; // from jtag | |
2212 | output [2:0] tcu_spc_shscanid; // to SPC's in IO CLK Domain | |
2213 | input jtag_spc0_shscan_clk_stop; // from jtag | |
2214 | input jtag_spc1_shscan_clk_stop; // from jtag | |
2215 | input jtag_spc2_shscan_clk_stop; // from jtag | |
2216 | input jtag_spc3_shscan_clk_stop; // from jtag | |
2217 | input jtag_spc4_shscan_clk_stop; // from jtag | |
2218 | input jtag_spc5_shscan_clk_stop; // from jtag | |
2219 | input jtag_spc6_shscan_clk_stop; // from jtag | |
2220 | input jtag_spc7_shscan_clk_stop; // from jtag | |
2221 | output tcu_spc0_shscan_clk_stop; // to SPC in IO CLK Domain | |
2222 | output tcu_spc1_shscan_clk_stop; // to SPC in IO CLK Domain | |
2223 | output tcu_spc2_shscan_clk_stop; // to SPC in IO CLK Domain | |
2224 | output tcu_spc3_shscan_clk_stop; // to SPC in IO CLK Domain | |
2225 | output tcu_spc4_shscan_clk_stop; // to SPC in IO CLK Domain | |
2226 | output tcu_spc5_shscan_clk_stop; // to SPC in IO CLK Domain | |
2227 | output tcu_spc6_shscan_clk_stop; // to SPC in IO CLK Domain | |
2228 | output tcu_spc7_shscan_clk_stop; // to SPC in IO CLK Domain | |
2229 | input jtag_spc_shscan_pce_ov; // from jtag | |
2230 | output tcu_spc_shscan_pce_ov; // to SPC in IO CLK Domain | |
2231 | ||
2232 | input jtag_l2t0_shscan_clk_stop; // From tcu_jtag_ctl | |
2233 | input jtag_l2t1_shscan_clk_stop; // From tcu_jtag_ctl | |
2234 | input jtag_l2t2_shscan_clk_stop; // From tcu_jtag_ctl | |
2235 | input jtag_l2t3_shscan_clk_stop; // From tcu_jtag_ctl | |
2236 | input jtag_l2t4_shscan_clk_stop; // From tcu_jtag_ctl | |
2237 | input jtag_l2t5_shscan_clk_stop; // From tcu_jtag_ctl | |
2238 | input jtag_l2t6_shscan_clk_stop; // From tcu_jtag_ctl | |
2239 | input jtag_l2t7_shscan_clk_stop; // From tcu_jtag_ctl | |
2240 | input jtag_l2t_shscan_pce_ov; // From tcu_jtag_ctl | |
2241 | output tcu_l2t0_shscan_clk_stop; // To L2T in IO CLK Domain | |
2242 | output tcu_l2t1_shscan_clk_stop; // To L2T in IO CLK Domain | |
2243 | output tcu_l2t2_shscan_clk_stop; // To L2T in IO CLK Domain | |
2244 | output tcu_l2t3_shscan_clk_stop; // To L2T in IO CLK Domain | |
2245 | output tcu_l2t4_shscan_clk_stop; // To L2T in IO CLK Domain | |
2246 | output tcu_l2t5_shscan_clk_stop; // To L2T in IO CLK Domain | |
2247 | output tcu_l2t6_shscan_clk_stop; // To L2T in IO CLK Domain | |
2248 | output tcu_l2t7_shscan_clk_stop; // To L2T in IO CLK Domain | |
2249 | output tcu_l2t_shscan_pce_ov; // To L2T in IO CLK Domain | |
2250 | ||
2251 | // Core and L2 Bank Available and Enable Status | |
2252 | input [7:0] core_avail; // CMP Core Available, from EFuse | |
2253 | input ncu_spc0_core_enable_status; // core_en updated | |
2254 | input ncu_spc1_core_enable_status; // via SW and | |
2255 | input ncu_spc2_core_enable_status; // recognized after | |
2256 | input ncu_spc3_core_enable_status; // WMR2 | |
2257 | input ncu_spc4_core_enable_status; | |
2258 | input ncu_spc5_core_enable_status; | |
2259 | input ncu_spc6_core_enable_status; | |
2260 | input ncu_spc7_core_enable_status; | |
2261 | input [7:0] bank_avail; // L2 Bank Available, from EFuse | |
2262 | input ncu_spc_pm; | |
2263 | input ncu_spc_ba01; // Bank_enables; 01 affects | |
2264 | input ncu_spc_ba23; // L2 banks 0, 1 and mcu0 | |
2265 | input ncu_spc_ba45; | |
2266 | input ncu_spc_ba67; | |
2267 | ||
2268 | // Control of arrays during scan | |
2269 | output tcu_se_scancollar_in; | |
2270 | output tcu_se_scancollar_out; | |
2271 | output tcu_array_bypass; | |
2272 | output tcu_array_wr_inhibit; | |
2273 | ||
2274 | // JTAG interface for clock stop & debug support | |
2275 | input jtag_upd_cntdly; | |
2276 | input [`CSDEL_MSB:0] jtag_cntdly_data; | |
2277 | output [`CSDEL_MSB:0] csdel_data; | |
2278 | output clkseq_stop; | |
2279 | output clkseq_strt; | |
2280 | ||
2281 | // Cycle (Clock) Stretch | |
2282 | input cycle_stretch; // from dbg_ctl | |
2283 | output tcu_ccu_clk_stretch; | |
2284 | // Select signal to Mux in CCU | |
2285 | output [1:0] tcu_ccu_mux_sel; | |
2286 | ||
2287 | // To regs_ctl for debug support | |
2288 | output wmr_two; | |
2289 | ||
2290 | output start_bisx_por; | |
2291 | output start_bisx_wmr; | |
2292 | output stop_bisx_wmr; | |
2293 | ||
2294 | input instr_mbist_diag; | |
2295 | input soc_mbist_aclk; | |
2296 | input soc_mbist_bclk; | |
2297 | input soc_mbist_scan_en; | |
2298 | ||
2299 | input soc0_mbist_clk_stop; | |
2300 | input mcu0_mbist_clk_stop; | |
2301 | input mcu1_mbist_clk_stop; | |
2302 | input mcu2_mbist_clk_stop; | |
2303 | input mcu3_mbist_clk_stop; | |
2304 | ||
2305 | input l2b0_mbist_clk_stop; | |
2306 | input l2b1_mbist_clk_stop; | |
2307 | input l2b2_mbist_clk_stop; | |
2308 | input l2b3_mbist_clk_stop; | |
2309 | input l2b4_mbist_clk_stop; | |
2310 | input l2b5_mbist_clk_stop; | |
2311 | input l2b6_mbist_clk_stop; | |
2312 | input l2b7_mbist_clk_stop; | |
2313 | ||
2314 | input l2t0_mbist_clk_stop; | |
2315 | input l2t1_mbist_clk_stop; | |
2316 | input l2t2_mbist_clk_stop; | |
2317 | input l2t3_mbist_clk_stop; | |
2318 | input l2t4_mbist_clk_stop; | |
2319 | input l2t5_mbist_clk_stop; | |
2320 | input l2t6_mbist_clk_stop; | |
2321 | input l2t7_mbist_clk_stop; | |
2322 | ||
2323 | input dmu_mbist_clk_stop; | |
2324 | input peu_mbist_clk_stop; | |
2325 | ||
2326 | input rdp_mbist_clk_stop; | |
2327 | input rtx_mbist_clk_stop; | |
2328 | input tds_mbist_clk_stop; | |
2329 | ||
2330 | // Serdes ATPG | |
2331 | output tcu_srd_atpgse; | |
2332 | output tcu_srd_atpgd; | |
2333 | output tcu_mio_scan_out31; | |
2334 | output [2:0] tcu_srd_atpgmode; | |
2335 | input mio_tcu_scan_in31; | |
2336 | input srd_tcu_atpgq; | |
2337 | ||
2338 | input l2t0_tcu_shscan_scan_out; | |
2339 | input l2t1_tcu_shscan_scan_out; | |
2340 | input l2t2_tcu_shscan_scan_out; | |
2341 | input l2t3_tcu_shscan_scan_out; | |
2342 | input l2t4_tcu_shscan_scan_out; | |
2343 | input l2t5_tcu_shscan_scan_out; | |
2344 | input l2t6_tcu_shscan_scan_out; | |
2345 | input l2t7_tcu_shscan_scan_out; | |
2346 | output tcu_l2t0_shscan_scan_in; | |
2347 | output tcu_l2t1_shscan_scan_in; | |
2348 | output tcu_l2t2_shscan_scan_in; | |
2349 | output tcu_l2t3_shscan_scan_in; | |
2350 | output tcu_l2t4_shscan_scan_in; | |
2351 | output tcu_l2t5_shscan_scan_in; | |
2352 | output tcu_l2t6_shscan_scan_in; | |
2353 | output tcu_l2t7_shscan_scan_in; | |
2354 | ||
2355 | // CSR (From/To mbist_ctl) | |
2356 | input ucb_csr_wr; | |
2357 | input [5:0] ucb_csr_addr; | |
2358 | input [6:0] ucb_data_out; | |
2359 | ||
2360 | // Scan reassigns | |
2361 | assign l1en = tcu_int_ce; // 1'b1; // this is "ce" or "pce" | |
2362 | assign pce_ov = tcu_int_pce_ov; | |
2363 | assign stop = 1'b0; | |
2364 | assign se = tcu_int_se; | |
2365 | assign siclk = tcu_int_aclk; // tcu_scan_aclk; | |
2366 | assign soclk = tcu_int_bclk; // tcu_scan_bclk; | |
2367 | ||
2368 | //create clock headers | |
2369 | tcu_sigmux_ctl_l1clkhdr_ctl_macro cmp_clkgen ( | |
2370 | .l2clk (l2clk ), | |
2371 | .l1clk (l1clk ), | |
2372 | .l1en(l1en), | |
2373 | .pce_ov(pce_ov), | |
2374 | .stop(stop), | |
2375 | .se(se)); | |
2376 | ||
2377 | ||
2378 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 ucb_csr_wr_sync_reg ( | |
2379 | .scan_in ( ucb_csr_wr_sync_reg_scanin ), | |
2380 | .scan_out ( ucb_csr_wr_sync_reg_scanout ), | |
2381 | .l1clk ( l1clk ), | |
2382 | .en ( io_cmp_sync_en_local ), | |
2383 | .din ( ucb_csr_wr ), | |
2384 | .dout ( ucb_csr_wr_sync ), | |
2385 | .siclk(siclk), | |
2386 | .soclk(soclk)); | |
2387 | ||
2388 | assign ucb_sel_clkstp_delay = (ucb_csr_addr == 6'h24); | |
2389 | assign ucb_wr_clkstp_delay = ucb_csr_wr_sync && ucb_sel_clkstp_delay; | |
2390 | ||
2391 | ||
2392 | // Create a pce signal for TCU to use internally; it blocks clocks | |
2393 | // during the time TCU is flushing itself in POR1 | |
2394 | // It goes to all non jtag flop headers in TCU except for those | |
2395 | // in sigmux_ctl that need to control the initial flush | |
2396 | // Also, during TT it allows tcu to be scanned gracefully | |
2397 | assign tcu_int_ce = (POR_ & ~(por_one & int_flush_d6) & ~ac_test_mode) | (ac_test_mode & ac_tt_trigger_fr); | |
2398 | ||
2399 | // Added via ECO to flop this path to UCB flop headers for timing ECO A | |
2400 | assign tcu_int_ce_to_ucb = (POR_ & ~(por_one & int_flush_d6) & ~ac_test_mode) | (ac_test_mode & ac_tt_trigger_fr); | |
2401 | ||
2402 | // ******************************************************************** | |
2403 | // Protect logic when transitioning into Transition Test (TT or AC) Test Mode | |
2404 | // ******************************************************************** | |
2405 | // Used TDI as a convenient dedicated pin to block scan controls | |
2406 | // Block these scan control signals until decide if in TT mode or not | |
2407 | // To run ATPG, io_tdi must be low | |
2408 | // To enter TT, io_tdi must be high when io_test_mode goes high and held | |
2409 | // until io_ac_test_mode can stabilize, then brought low | |
2410 | assign test_mode_block = io_tdi; | |
2411 | assign test_mode_gated = io_test_mode & ~test_mode_block; | |
2412 | assign pin_aclk = test_mode_gated & io_aclk; | |
2413 | assign pin_bclk = test_mode_gated & io_bclk; | |
2414 | assign pin_scan_en = test_mode_gated & io_scan_en; | |
2415 | ||
2416 | // Block shared pins from MIO if io_test_mode is 1'b0 | |
2417 | assign ac_test_mode = test_mode_gated & io_ac_test_mode; | |
2418 | ||
2419 | //serdes control signal | |
2420 | //assign tcu_srdes_scancfg = io_test_mode ? io_srdes_scancfg : 2'b0; | |
2421 | ||
2422 | // To put peu in testmode to allow external clocks to be used | |
2423 | assign tcu_peu_testmode = io_test_mode; | |
2424 | assign tcu_mac_testmode = io_test_mode; | |
2425 | assign tcu_spc0_test_mode = io_test_mode | jt_scan_spc0; | |
2426 | assign tcu_spc1_test_mode = io_test_mode | jt_scan_spc1; | |
2427 | assign tcu_spc2_test_mode = io_test_mode | jt_scan_spc2; | |
2428 | assign tcu_spc3_test_mode = io_test_mode | jt_scan_spc3; | |
2429 | assign tcu_spc4_test_mode = io_test_mode | jt_scan_spc4; | |
2430 | assign tcu_spc5_test_mode = io_test_mode | jt_scan_spc5; | |
2431 | assign tcu_spc6_test_mode = io_test_mode | jt_scan_spc6; | |
2432 | assign tcu_spc7_test_mode = io_test_mode | jt_scan_spc7; | |
2433 | assign tcu_rst_scan_mode = tcu_atpg_mode; | |
2434 | ||
2435 | // disable fbd scan chain in MCU when tcu_mcu_testmode is off | |
2436 | // so, scan chain active when in atpg mode, or flush reset for por1, por2 | |
2437 | assign tcu_mcu_testmode = io_test_mode | (por_one | por_two); | |
2438 | ||
2439 | // This signal goes to Cluster Headers only, it should be active when | |
2440 | // io_test_mode is active but not transition test or LBist | |
2441 | // During macrotest needs to be off to allow write inhibit to get to arrays | |
2442 | assign tcu_atpg_mode = test_mode_gated & ~io_ac_test_mode; | |
2443 | //& (~mt_mode | (mt_mode & io_scan_en)); | |
2444 | ||
2445 | // ******************************************************************** | |
2446 | // External clocks from pins, to be used during testmode | |
2447 | // ******************************************************************** | |
2448 | assign tcu_ccu_ext_cmp_clk = jt_scan_mtmode ? tck_clk_tree : mio_ext_cmp_clk ; | |
2449 | assign tcu_ccu_ext_dr_clk = jt_scan_mtmode ? tck_clk_tree : mio_ext_dr_clk ; | |
2450 | ||
2451 | assign mac_125rx_test_clk = test_mode_gated ? mio_tcu_niu_clk_ext[0] : 1'b0; | |
2452 | assign mac_125tx_test_clk = test_mode_gated ? mio_tcu_niu_clk_ext[1] : 1'b0; | |
2453 | assign mac_156rx_test_clk = test_mode_gated ? mio_tcu_niu_clk_ext[2] : 1'b0; | |
2454 | assign mac_156tx_test_clk = test_mode_gated ? mio_tcu_niu_clk_ext[3] : 1'b0; | |
2455 | assign mac_312rx_test_clk = test_mode_gated ? mio_tcu_niu_clk_ext[4] : 1'b0; | |
2456 | assign mac_312tx_test_clk = test_mode_gated ? mio_tcu_niu_clk_ext[5] : 1'b0; | |
2457 | ||
2458 | assign tcu_peu_clk_ext = test_mode_gated ? mio_tcu_peu_clk_ext : 1'b0; | |
2459 | ||
2460 | assign tcu_div_bypass = (test_mode_gated & ~io_ac_test_mode) | |
2461 | ? mio_tcu_divider_bypass : 1'b0; | |
2462 | ||
2463 | assign pll_bypass = mio_tcu_pll_cmp_bypass; | |
2464 | assign tcu_ccu_clk_stretch = cycle_stretch; | |
2465 | // mux_sel: 00==PLL, 11==JTAG_Macrotest (TCK), 10=Ext_Clk, 01=Cycle_Stretch_Clk | |
2466 | // Ref_Clk not used | |
2467 | assign tcu_ccu_mux_sel[1:0] = pll_bypass ? 2'b10 | |
2468 | : ( test_mode_gated & ~io_ac_test_mode) ? 2'b10 | |
2469 | : ( test_mode_gated & io_ac_test_mode) ? 2'b00 | |
2470 | : tcu_ccu_clk_stretch ? 2'b01 | |
2471 | : ( jt_scan_mtmode ) ? 2'b11 | |
2472 | : 2'b00; // default - select PLL output | |
2473 | ||
2474 | // ******************************************************************** | |
2475 | // Transition Test | |
2476 | // ******************************************************************** | |
2477 | //create signal to start ac trans counter off de-assertion of sync | |
2478 | //io clock stops | |
2479 | assign ac_trans_test_counter_start = | |
2480 | ~(spc0_stopped & | |
2481 | spc1_stopped & | |
2482 | spc2_stopped & | |
2483 | spc3_stopped & | |
2484 | spc4_stopped & | |
2485 | spc5_stopped & | |
2486 | spc6_stopped & | |
2487 | spc7_stopped & | |
2488 | bnk0_stopped & | |
2489 | l2t0_stopped & | |
2490 | bnk1_stopped & | |
2491 | l2t1_stopped & | |
2492 | bnk2_stopped & | |
2493 | l2t2_stopped & | |
2494 | bnk3_stopped & | |
2495 | l2t3_stopped & | |
2496 | bnk4_stopped & | |
2497 | l2t4_stopped & | |
2498 | bnk5_stopped & | |
2499 | l2t5_stopped & | |
2500 | bnk6_stopped & | |
2501 | l2t6_stopped & | |
2502 | bnk7_stopped & | |
2503 | l2t7_stopped & | |
2504 | mcu0_stopped_tt & | |
2505 | mcu1_stopped_tt & | |
2506 | mcu2_stopped_tt & | |
2507 | mcu3_stopped_tt & | |
2508 | soc0_stopped_tt & | |
2509 | soc1_stopped_tt & | |
2510 | soc2_stopped_tt & | |
2511 | soc3_stopped_tt); //tcu_soc8en_clk_stop_sync_enclk); | |
2512 | ||
2513 | // Use these to block clock stops going out on unintended clock domains | |
2514 | // during Transition Test; set tt_io_clk with scan-only flop | |
2515 | // One or more CMP clock domains can be tested at same time | |
2516 | // One or more IO clock domains can be tested at same time | |
2517 | // Cannot test CMP and IO clock domains together | |
2518 | // No DR clock domain can be tested | |
2519 | assign tt_cmp_mode = ~(~ac_test_mode | ~tt_io_clk); | |
2520 | assign tt_io_mode = ~(~ac_test_mode | tt_io_clk); | |
2521 | assign tt_dr_mode = ~(~ac_test_mode); | |
2522 | ||
2523 | // ******************************************************************** | |
2524 | // Scan Chain Muxing | |
2525 | // ******************************************************************** | |
2526 | //later will have to add chain flexibility for jtag | |
2527 | // - use chain 0 for mbist | |
2528 | assign pre_tcu_spc0_scan_out[1:0] = io_test_mode ? io_scan_in[1:0] : 2'b0; | |
2529 | assign pre_tcu_spc1_scan_out[1:0] = io_test_mode ? io_scan_in[3:2] : 2'b0; | |
2530 | assign pre_tcu_spc2_scan_out[1:0] = io_test_mode ? io_scan_in[5:4] : 2'b0; | |
2531 | assign pre_tcu_spc3_scan_out[1:0] = io_test_mode ? io_scan_in[7:6] : 2'b0; | |
2532 | assign pre_tcu_spc4_scan_out[1:0] = io_test_mode ? io_scan_in[9:8] : 2'b0; | |
2533 | assign pre_tcu_spc5_scan_out[1:0] = io_test_mode ? io_scan_in[11:10] : 2'b0; | |
2534 | assign pre_tcu_spc6_scan_out[1:0] = io_test_mode ? io_scan_in[13:12] : 2'b0; | |
2535 | assign pre_tcu_spc7_scan_out[1:0] = io_test_mode ? io_scan_in[15:14] : 2'b0; | |
2536 | //need to assign tcu chain to part of soc | |
2537 | //mfg scan chain 30 first goes through tcu in manufac. scan | |
2538 | assign pre_tcu_soca_scan_out = io_test_mode ? io_scan_in[16] : 1'b0; | |
2539 | assign pre_tcu_socb_scan_out = io_test_mode ? io_scan_in[17] : 1'b0; | |
2540 | assign pre_tcu_socc_scan_out = io_test_mode ? io_scan_in[18] : 1'b0; | |
2541 | assign pre_tcu_socd_scan_out = io_test_mode ? io_scan_in[19] : 1'b0; | |
2542 | assign pre_tcu_soce_scan_out = io_test_mode ? io_scan_in[20] : 1'b0; | |
2543 | assign pre_tcu_socf_scan_out = io_test_mode ? io_scan_in[21] : 1'b0; | |
2544 | assign pre_tcu_socg_scan_out = io_test_mode ? io_scan_in[22] : 1'b0; | |
2545 | assign pre_tcu_soch_scan_out = io_test_mode ? io_scan_in[23] : 1'b0; | |
2546 | assign pre_tcu_soc0_scan_out = io_test_mode ? io_scan_in[24] : 1'b0; | |
2547 | assign pre_tcu_soc1_scan_out = io_test_mode ? io_scan_in[25] : 1'b0; | |
2548 | assign pre_tcu_soc2_scan_out = io_test_mode ? io_scan_in[26] : 1'b0; | |
2549 | assign pre_tcu_soc3_scan_out = io_test_mode ? io_scan_in[27] : 1'b0; | |
2550 | assign pre_tcu_soc4_scan_out = io_test_mode ? io_scan_in[28] : 1'b0; | |
2551 | assign pre_tcu_soc5_scan_out = io_test_mode ? io_scan_in[29] : 1'b0; | |
2552 | assign pre_tcu_soc6_scan_out = io_test_mode ? tcu_scan_chain : 1'b0; | |
2553 | ||
2554 | // Connect PEU into chain 30: first peu mbist, then peu scan chain | |
2555 | // then connect RST -> CCU scan chains into chain 30 | |
2556 | assign tcu_peu_scan_out = (io_test_mode | jt_scan) & peu_tcu_mbist_scan_out; | |
2557 | assign tcu_rst_scan_out = io_test_mode & peu_tcu_scan_in; | |
2558 | assign miobscan_or_peu_scan = tcu_atpg_mode ? mio_tcu_bs_scan_out : peu_tcu_scan_in; | |
2559 | ||
2560 | // Connect in Boundary Scan during ATPG mode only (to chain 30, after CCU) | |
2561 | // BScan goes from TCU to MCU0, MCU1, PEU, MAC, MCU3, MCU2, then MIO and back to TCU | |
2562 | assign tcu_sbs_scan_in = tcu_atpg_mode ? ccu_tcu_scan_in : jtag_sbs_scan_in; | |
2563 | ||
2564 | //assign tcu_pins_scan_out[1:0] = io_test_mode ? spc0_tcu_scan_in[1:0] : 2'b0; | |
2565 | //assign tcu_pins_scan_out[3:2] = io_test_mode ? spc1_tcu_scan_in[1:0] : 2'b0; | |
2566 | //assign tcu_pins_scan_out[5:4] = io_test_mode ? spc2_tcu_scan_in[1:0] : 2'b0; | |
2567 | //assign tcu_pins_scan_out[7:6] = io_test_mode ? spc3_tcu_scan_in[1:0] : 2'b0; | |
2568 | //assign tcu_pins_scan_out[9:8] = io_test_mode ? spc4_tcu_scan_in[1:0] : 2'b0; | |
2569 | //assign tcu_pins_scan_out[11:10] = io_test_mode ? spc5_tcu_scan_in[1:0] : 2'b0; | |
2570 | //assign tcu_pins_scan_out[13:12] = io_test_mode ? spc6_tcu_scan_in[1:0] : 2'b0; | |
2571 | //assign tcu_pins_scan_out[15:14] = io_test_mode ? spc7_tcu_scan_in[1:0] : 2'b0; | |
2572 | ||
2573 | assign tcu_pins_scan_out[1:0] = io_test_mode ? {spc0_tcu_scan_in[1], spc0_tcu_lbist_scan_out} : 2'b0; | |
2574 | assign tcu_pins_scan_out[3:2] = io_test_mode ? {spc1_tcu_scan_in[1], spc1_tcu_lbist_scan_out} : 2'b0; | |
2575 | assign tcu_pins_scan_out[5:4] = io_test_mode ? {spc2_tcu_scan_in[1], spc2_tcu_lbist_scan_out} : 2'b0; | |
2576 | assign tcu_pins_scan_out[7:6] = io_test_mode ? {spc3_tcu_scan_in[1], spc3_tcu_lbist_scan_out} : 2'b0; | |
2577 | assign tcu_pins_scan_out[9:8] = io_test_mode ? {spc4_tcu_scan_in[1], spc4_tcu_lbist_scan_out} : 2'b0; | |
2578 | assign tcu_pins_scan_out[11:10] = io_test_mode ? {spc5_tcu_scan_in[1], spc5_tcu_lbist_scan_out} : 2'b0; | |
2579 | assign tcu_pins_scan_out[13:12] = io_test_mode ? {spc6_tcu_scan_in[1], spc6_tcu_lbist_scan_out} : 2'b0; | |
2580 | assign tcu_pins_scan_out[15:14] = io_test_mode ? {spc7_tcu_scan_in[1], spc7_tcu_lbist_scan_out} : 2'b0; | |
2581 | ||
2582 | assign tcu_pins_scan_out[16] = io_test_mode ? soca_tcu_scan_in : 1'b0; | |
2583 | assign tcu_pins_scan_out[17] = io_test_mode ? socb_tcu_scan_in : 1'b0; | |
2584 | ||
2585 | //assign tcu_pins_scan_out[18] = io_test_mode ? socc_tcu_scan_in : 1'b0; | |
2586 | //assign tcu_pins_scan_out[19] = io_test_mode ? socd_tcu_scan_in : 1'b0; | |
2587 | //assign tcu_pins_scan_out[20] = io_test_mode ? soce_tcu_scan_in : 1'b0; | |
2588 | //assign tcu_pins_scan_out[21] = io_test_mode ? socf_tcu_scan_in : 1'b0; | |
2589 | //assign tcu_pins_scan_out[22] = io_test_mode ? socg_tcu_scan_in : 1'b0; | |
2590 | //assign tcu_pins_scan_out[23] = io_test_mode ? soch_tcu_scan_in : 1'b0; | |
2591 | //assign tcu_pins_scan_out[24] = io_test_mode ? soc0_tcu_scan_in : 1'b0; | |
2592 | //assign tcu_pins_scan_out[25] = io_test_mode ? soc1_tcu_scan_in : 1'b0; | |
2593 | //assign tcu_pins_scan_out[26] = io_test_mode ? soc2_tcu_scan_in : 1'b0; | |
2594 | //assign tcu_pins_scan_out[27] = io_test_mode ? soc3_tcu_scan_in : 1'b0; | |
2595 | //assign tcu_pins_scan_out[28] = io_test_mode ? soc4_tcu_scan_in : 1'b0; | |
2596 | //assign tcu_pins_scan_out[29] = io_test_mode ? soc5_tcu_scan_in : 1'b0; | |
2597 | //assign tcu_pins_scan_out[30] = io_test_mode ? soc6_tcu_scan_in : 1'b0; | |
2598 | ||
2599 | assign tcu_pins_scan_out[18] = io_test_mode ? mcu3_tcu_mbist_scan_out : 1'b0; | |
2600 | assign tcu_pins_scan_out[19] = io_test_mode ? dmu_tcu_mbist_scan_out : 1'b0; | |
2601 | assign tcu_pins_scan_out[20] = io_test_mode ? rdp_rdmc_mbist_scan_out : 1'b0; | |
2602 | assign tcu_pins_scan_out[21] = io_test_mode ? rtx_mbist_scan_out : 1'b0; | |
2603 | assign tcu_pins_scan_out[22] = io_test_mode ? sio_tcu_mbist_scan_out : 1'b0; | |
2604 | assign tcu_pins_scan_out[23] = io_test_mode ? l2b7_tcu_mbist_scan_out : 1'b0; | |
2605 | assign tcu_pins_scan_out[24] = io_test_mode ? l2t1_tcu_shscan_scan_out : 1'b0; | |
2606 | assign tcu_pins_scan_out[25] = io_test_mode ? l2t3_tcu_shscan_scan_out : 1'b0; | |
2607 | assign tcu_pins_scan_out[26] = io_test_mode ? l2t5_tcu_shscan_scan_out : 1'b0; | |
2608 | assign tcu_pins_scan_out[27] = io_test_mode ? l2t7_tcu_shscan_scan_out : 1'b0; | |
2609 | assign tcu_pins_scan_out[28] = io_test_mode ? tds_mbist_scan_out : 1'b0; | |
2610 | assign tcu_pins_scan_out[29] = io_test_mode ? soc5_tcu_scan_in : 1'b0; | |
2611 | assign tcu_pins_scan_out[30] = io_test_mode ? miobscan_or_peu_scan : 1'b0; | |
2612 | ||
2613 | //assign tcu_pin_srdes_scan_out = io_test_mode ? srdes_tcu_scan_in : 1'b0; | |
2614 | ||
2615 | // ******************************************************************** | |
2616 | // RST: Reset Sequence Support | |
2617 | // ******************************************************************** | |
2618 | // - These flops are Non-flushable, so they need a separate clock header | |
2619 | tcu_sigmux_ctl_l1clkhdr_ctl_macro nonflush_clkgen ( | |
2620 | .l2clk (l2clk ), | |
2621 | .se (tcu_int_nfse), | |
2622 | .l1en (tcu_int_nfce), | |
2623 | .pce_ov (1'b0), | |
2624 | .l1clk (nf_l1clk ), | |
2625 | .stop(stop)); | |
2626 | assign tcu_int_nfce = ~ac_test_mode; | |
2627 | assign rst_flush_req = flush_tcu | |
2628 | | (rst_tcu_flush_init_req_hold & ~rst_tcu_flush_stop_req_hold); | |
2629 | // ******************************************************************** | |
2630 | // Free-running l1clk during ATPG Mode | |
2631 | // ******************************************************************** | |
2632 | tcu_sigmux_ctl_l1clkhdr_ctl_macro freerun_clkgen ( | |
2633 | .l2clk (l2clk ), | |
2634 | .se (1'b0), //tcu_int_frse), | |
2635 | .l1en (1'b1), | |
2636 | .pce_ov (1'b1), | |
2637 | .l1clk (fr_l1clk ), | |
2638 | .stop(stop)); | |
2639 | ||
2640 | // ******************************************************************** | |
2641 | // FLUSH Reset Sequence Support | |
2642 | // ******************************************************************** | |
2643 | // Flop flush_req and delay by various cycles, to separate aclk, bclk and se changing | |
2644 | // so when flush_req changes, bclk sees it first, then se 48 cycles later | |
2645 | // and then aclk 24 cycles after that. Also, due to latencies in cluster header | |
2646 | // and global staging of clock stops after they leave tcu (5 pipeline stages), addt'l | |
2647 | // delays are needed in these boundary conditions: | |
2648 | // 1. when last clock stop asserts from TCU to when flush begins (48 cycles total) | |
2649 | // 2. when flush ends with scan_en deasserting to first clock stop deasserting from TCU | |
2650 | // 3. when last clock stop deasserts from TCU to tcu_rst_flush_stop_ack asserting | |
2651 | // - 24 cycles chosen to cover poorly timed aclk, bclk and scan_en routing | |
2652 | ||
2653 | // When a rst_tcu_flush_init_req is received by TCU from RST, it generates a signal | |
2654 | // flush_q0. This is then delayed by various amounts to allow separation of the | |
2655 | // signals required for flushing the scan chains deterministically | |
2656 | ||
2657 | assign ok_to_flush = cntstop_equal_max_q | flush_tcu; | |
2658 | assign flush_q0 = ~POR_ ? 1'b1 : (flush & ok_to_flush); | |
2659 | ||
2660 | // Counter starts when flush_q0 goes high; tap off counter values to delay flush_q0 | |
2661 | // Flush On Counter | |
2662 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_7 tcusig_foncnt_nf_reg | |
2663 | ( | |
2664 | .scan_in(tcusig_foncnt_nf_reg_scanin), | |
2665 | .scan_out(tcusig_foncnt_nf_reg_scanout), | |
2666 | .l1clk (nf_l1clk), | |
2667 | .siclk (tcu_int_nfaclk), | |
2668 | .soclk (tcu_int_nfbclk), | |
2669 | .clr (clear_flush_on_counter), | |
2670 | .din (flush_oncnt_din[6:0]), | |
2671 | .dout (flush_oncnt[6:0] ) | |
2672 | ); | |
2673 | assign flush_oncnt_din[6:0] = flush_oncnt[6:0] + 7'b1; | |
2674 | assign clear_flush_on_counter = ~flush_q0 | ~POR_; | |
2675 | assign flush_on_24 = flush_oncnt[6:0] == 7'b0011000; | |
2676 | assign flush_on_48 = flush_oncnt[6:0] == 7'b0110000; | |
2677 | assign flush_on_72 = flush_oncnt[6:0] == 7'b1001000; | |
2678 | assign flush_on_96 = flush_oncnt[6:0] == 7'b1100000; | |
2679 | ||
2680 | // Counter starts when flush_q0 goes low; tap off counter values to delay flush_q0 | |
2681 | // Flush Off Counter | |
2682 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_7 tcusig_foffcnt_nf_reg | |
2683 | ( | |
2684 | .scan_in(tcusig_foffcnt_nf_reg_scanin), | |
2685 | .scan_out(tcusig_foffcnt_nf_reg_scanout), | |
2686 | .l1clk (nf_l1clk), | |
2687 | .siclk (tcu_int_nfaclk), | |
2688 | .soclk (tcu_int_nfbclk), | |
2689 | .clr (clear_flush_off_counter), | |
2690 | .din (flush_offcnt_din[6:0]), | |
2691 | .dout (flush_offcnt[6:0] ) | |
2692 | ); | |
2693 | assign flush_offcnt_din[6:0] = flush_offcnt[6:0] + 7'b1; | |
2694 | assign clear_flush_off_counter = flush_q0 & ok_to_flush; //| ~POR_; | |
2695 | assign flush_off_24 = flush_offcnt[6:0] == 7'b0011000; | |
2696 | assign flush_off_48 = flush_offcnt[6:0] == 7'b0110000; | |
2697 | assign flush_off_72 = flush_offcnt[6:0] == 7'b1001000; | |
2698 | assign flush_off_96 = flush_offcnt[6:0] == 7'b1100000; | |
2699 | ||
2700 | // Delay flush_q0 based on counter value | |
2701 | // Delay of 24 cycles | |
2702 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_fq24_nf_reg | |
2703 | ( | |
2704 | .scan_in(tcusig_fq24_nf_reg_scanin), | |
2705 | .scan_out(tcusig_fq24_nf_reg_scanout), | |
2706 | .l1clk (nf_l1clk), | |
2707 | .siclk (tcu_int_nfaclk), | |
2708 | .soclk (tcu_int_nfbclk), | |
2709 | .en (enable_flush_q24_delay), | |
2710 | .din (flush_q0), | |
2711 | .dout (flush_q24) | |
2712 | ); | |
2713 | assign enable_flush_q24_delay = ~POR_ | (flush_q0 ? flush_on_24 : flush_off_24); | |
2714 | // Delay of 48 cycles | |
2715 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_fq48_nf_reg | |
2716 | ( | |
2717 | .scan_in(tcusig_fq48_nf_reg_scanin), | |
2718 | .scan_out(tcusig_fq48_nf_reg_scanout), | |
2719 | .l1clk (nf_l1clk), | |
2720 | .siclk (tcu_int_nfaclk), | |
2721 | .soclk (tcu_int_nfbclk), | |
2722 | .en (enable_flush_q48_delay), | |
2723 | .din (flush_q0), | |
2724 | .dout (flush_q48) | |
2725 | ); | |
2726 | assign enable_flush_q48_delay = ~POR_ | (flush_q0 ? flush_on_48 : flush_off_48); | |
2727 | // Delay of 72 cycles | |
2728 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_fq72_nf_reg | |
2729 | ( | |
2730 | .scan_in(tcusig_fq72_nf_reg_scanin), | |
2731 | .scan_out(tcusig_fq72_nf_reg_scanout), | |
2732 | .l1clk (nf_l1clk), | |
2733 | .siclk (tcu_int_nfaclk), | |
2734 | .soclk (tcu_int_nfbclk), | |
2735 | .en (enable_flush_q72_delay), | |
2736 | .din (flush_q0), | |
2737 | .dout (flush_q72) | |
2738 | ); | |
2739 | assign enable_flush_q72_delay = ~POR_ | (flush_q0 ? flush_on_72 : flush_off_72); | |
2740 | // Delay of 96 cycles | |
2741 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_fq96_nf_reg | |
2742 | ( | |
2743 | .scan_in(tcusig_fq96_nf_reg_scanin), | |
2744 | .scan_out(tcusig_fq96_nf_reg_scanout), | |
2745 | .l1clk (nf_l1clk), | |
2746 | .siclk (tcu_int_nfaclk), | |
2747 | .soclk (tcu_int_nfbclk), | |
2748 | .en (enable_flush_q96_delay), | |
2749 | .din (flush_q0), | |
2750 | .dout (flush_q96) | |
2751 | ); | |
2752 | assign enable_flush_q96_delay = ~POR_ | (flush_q0 ? flush_on_96 : flush_off_96); | |
2753 | ||
2754 | assign flush_off = io_test_mode ? 1'b0 : (~POR_ | (flush_q72 | flush_go)); | |
2755 | assign tcu_jtag_flush_dly_req = flush_off; // to jtag | |
2756 | assign flush_start = ~POR_ | flush_q96; | |
2757 | assign flush_go = ~POR_ | flush_q48; | |
2758 | ||
2759 | assign flush_test_protect = ~por_one & (flush_q24 | flush_q96); | |
2760 | ||
2761 | // Delay of at least 128 cycles - for delaying tcu_rst_flush_stop_ack generation by delaying | |
2762 | // recognition of all clock stops going off | |
2763 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_2 tcusig_cstopq48_nf_reg | |
2764 | ( | |
2765 | .scan_in(tcusig_cstopq48_nf_reg_scanin), | |
2766 | .scan_out(tcusig_cstopq48_nf_reg_scanout), | |
2767 | .l1clk (nf_l1clk), | |
2768 | .siclk (tcu_int_nfaclk), | |
2769 | .soclk (tcu_int_nfbclk), | |
2770 | .en (enable_cstop_q48_delay), | |
2771 | .din ({clk_stop_loops_all_off, clk_stop_loops_all_off_q48 }), | |
2772 | .dout ({clk_stop_loops_all_off_q48, clk_stop_loops_all_off_q128}) | |
2773 | ); | |
2774 | assign enable_cstop_q48_delay = ~POR_ | (clk_stop_loops_all_off ? flush_off_48 : flush_on_48); | |
2775 | ||
2776 | // This flop delays start of se, aclk high for flush by flopping the stop | |
2777 | // counter output when equal to max value; Counter hits max count after all clocks have | |
2778 | // been stopped, then this flop grabs that and holds it for duration of flush | |
2779 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__en_1__width_1 tcusig_flushdly_reg | |
2780 | ( | |
2781 | .scan_in(tcusig_flushdly_reg_scanin), | |
2782 | .scan_out(tcusig_flushdly_reg_scanout), | |
2783 | .l1clk (l1clk), | |
2784 | .clr (cntstart), | |
2785 | .en (clk_stop_loops_all_on & ~cntstop_equal_max_q), | |
2786 | .din (cntstop_equal_max), | |
2787 | .dout (cntstop_equal_max_q), | |
2788 | .siclk(siclk), | |
2789 | .soclk(soclk) | |
2790 | ); | |
2791 | ||
2792 | // ******************************************************************** | |
2793 | // END of FLUSH Reset Sequence Support | |
2794 | // ******************************************************************** | |
2795 | ||
2796 | // ******************************************************************** | |
2797 | // Hold and Create pulse when receiving rst_tcu_flush_init_req | |
2798 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__en_1__width_1 tcusig_fireq_reg | |
2799 | ( | |
2800 | .scan_in(tcusig_fireq_reg_scanin), | |
2801 | .scan_out(tcusig_fireq_reg_scanout), | |
2802 | .l1clk (l1clk), | |
2803 | .en (~rst_tcu_flush_init_req_hold), | |
2804 | .clr (rst_tcu_flush_stop_req), | |
2805 | .din (rst_tcu_flush_init_req), | |
2806 | .dout (rst_tcu_flush_init_req_hold), | |
2807 | .siclk(siclk), | |
2808 | .soclk(soclk) | |
2809 | ); | |
2810 | assign fireq = rst_tcu_flush_init_req & ~rst_tcu_flush_init_req_hold; | |
2811 | // ******************************************************************** | |
2812 | // Hold when receiving rst_tcu_flush_stop_req | |
2813 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__en_1__width_1 tcusig_fsreq_reg | |
2814 | ( | |
2815 | .scan_in(tcusig_fsreq_reg_scanin), | |
2816 | .scan_out(tcusig_fsreq_reg_scanout), | |
2817 | .l1clk (l1clk), | |
2818 | .en (~rst_tcu_flush_stop_req_hold), | |
2819 | .clr (rst_tcu_flush_init_req), | |
2820 | .din (rst_tcu_flush_stop_req), | |
2821 | .dout (rst_tcu_flush_stop_req_hold), | |
2822 | .siclk(siclk), | |
2823 | .soclk(soclk) | |
2824 | ); | |
2825 | ||
2826 | // ******************************************************************** | |
2827 | // Return acknowledge to RST | |
2828 | assign tcu_rst_asicflush_stop_ack = POR_ & (por_one & ~int_flush_d12) & ~ac_test_mode; | |
2829 | ||
2830 | // ******************************************************************** | |
2831 | // Detect por1, por2, wmr1, wmr2; non-scan flops | |
2832 | tcu_sigmux_ctl_msff_ctl_macro__clr__1__width_2 tcusig_rstsm_nf_reg | |
2833 | ( | |
2834 | .scan_in(tcusig_rstsm_nf_reg_scanin), | |
2835 | .scan_out(tcusig_rstsm_nf_reg_scanout), | |
2836 | .l1clk (nf_l1clk), | |
2837 | .siclk (tcu_int_nfaclk), //(1'b0), | |
2838 | .soclk (tcu_int_nfbclk), //(1'b0), | |
2839 | .clr_ (POR_), | |
2840 | .din (rst_sm_new[1:0]), | |
2841 | .dout (rst_sm_dout[1:0]) | |
2842 | ); | |
2843 | assign rst_sm[1:0] = ({2{ POR_ }} & rst_sm_dout[1:0]); | |
2844 | assign rst_sm_new = (rst_sm == 2'b11) ? fireq ? 2'b10 : rst_sm[1:0] | |
2845 | : fireq ? (rst_sm[1:0] + 2'b1) | |
2846 | : rst_sm[1:0]; | |
2847 | assign por_one = ~rst_sm[1] & ~rst_sm[0]; | |
2848 | assign por_two = ~rst_sm[1] & rst_sm[0]; | |
2849 | assign wmr_one = rst_sm[1] & ~rst_sm[0]; | |
2850 | assign wmr_two = rst_sm[1] & rst_sm[0]; | |
2851 | ||
2852 | // ******************************************************************** | |
2853 | // Return handshake signal to RST indicating flush has started | |
2854 | // flush init ack | |
2855 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_fiack_reg ( | |
2856 | .scan_in ( tcusig_fiack_reg_scanin ), | |
2857 | .scan_out ( tcusig_fiack_reg_scanout ), | |
2858 | .l1clk ( l1clk ), | |
2859 | .din ( tcu_rst_flush_init_ack_int ), | |
2860 | .dout ( tcu_rst_flush_init_ack_pre ), | |
2861 | .siclk(siclk), | |
2862 | .soclk(soclk) | |
2863 | ); | |
2864 | assign tcu_rst_flush_init_ack = tcu_rst_flush_init_ack_pre & ~ac_test_mode; | |
2865 | // If not asserted, assert it when flush_go and not in POR1 | |
2866 | // Deassert it when stop_ack comes | |
2867 | assign tcu_rst_flush_init_ack_int = !tcu_rst_flush_init_ack ? (!por_one & flush_start) | |
2868 | : tcu_rst_flush_stop_ack ? 1'b0 | |
2869 | : tcu_rst_flush_init_ack; | |
2870 | ||
2871 | // Start POR BISX after EFU is done | |
2872 | assign start_bisx_por = por_one && tcu_rst_efu_done; | |
2873 | ||
2874 | // Start WMR BISX when RST requested a flush stop and TCU acks it | |
2875 | assign start_bisx_wmr = wmr_one && rst_tcu_flush_stop_req && tcu_rst_flush_stop_ack; | |
2876 | ||
2877 | // Stop WMR BISX when RST enters WMR2 | |
2878 | assign stop_bisx_wmr = wmr_two; | |
2879 | ||
2880 | // ******************************************************************** | |
2881 | // Return handshake signal to RST indicating flush has stopped | |
2882 | // This signal already flopped | |
2883 | assign tcu_rst_flush_stop_ack = ~flush_clk_stop_active | ac_test_mode; | |
2884 | ||
2885 | // ******************************************************************** | |
2886 | // Tell tcu to flush, but only once | |
2887 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_tcuf_nf_reg | |
2888 | ( | |
2889 | .scan_in(tcusig_tcuf_nf_reg_scanin), | |
2890 | .scan_out(tcusig_tcuf_nf_reg_scanout), | |
2891 | .l1clk (nf_l1clk), | |
2892 | .siclk (tcu_int_nfaclk), //(1'b0), | |
2893 | .soclk (tcu_int_nfbclk), //(1'b0), | |
2894 | .en (flush_tcu), | |
2895 | .din (flush_tcu_req), | |
2896 | .dout (flush_tcu_req_hld) | |
2897 | ); | |
2898 | assign flush_tcu_req = por_one & ~rst_tcu_flush_stop_req; | |
2899 | //& ~(rst_tcu_flush_stop_req | rst_tcu_flush_stop_req_hold); | |
2900 | assign flush_tcu = ~POR_ | flush_tcu_req_hld; | |
2901 | ||
2902 | // ******************************************************************** | |
2903 | // This is new signal to tell tcu to flush | |
2904 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_tcuasicf_nf_reg | |
2905 | ( | |
2906 | .scan_in(tcusig_tcuasicf_nf_reg_scanin), | |
2907 | .scan_out(tcusig_tcuasicf_nf_reg_scanout), | |
2908 | .l1clk (nf_l1clk), | |
2909 | .siclk (tcu_int_nfaclk), //(1'b0), | |
2910 | .soclk (tcu_int_nfbclk), //(1'b0), | |
2911 | .en (asicflush_tcu), | |
2912 | .din (asicflush_tcu_req), | |
2913 | .dout (asicflush_tcu_req_hld) | |
2914 | ); | |
2915 | assign asicflush_tcu_req = por_one & ~rst_tcu_asicflush_stop_req; | |
2916 | assign asicflush_tcu = ~POR_ | asicflush_tcu_req_hld; | |
2917 | // These flops generate internal scan_en and aclk for TCU flush | |
2918 | tcu_sigmux_ctl_msff_ctl_macro__width_12 tcusig_intflush_nf_reg | |
2919 | ( | |
2920 | .scan_in(tcusig_intflush_nf_reg_scanin), | |
2921 | .scan_out(tcusig_intflush_nf_reg_scanout), | |
2922 | .l1clk (nf_l1clk), | |
2923 | .siclk (tcu_int_nfaclk), //(1'b0), | |
2924 | .soclk (tcu_int_nfbclk), //(1'b0), | |
2925 | .din ({int_flush, int_flush_d, int_flush_d2, int_flush_d3, int_flush_d4, int_flush_d5, | |
2926 | int_flush_d6, int_flush_d7, int_flush_d8, int_flush_d9, int_flush_d10, int_flush_d11}), | |
2927 | .dout ({int_flush_d, int_flush_d2, int_flush_d3, int_flush_d4, int_flush_d5, int_flush_d6, | |
2928 | int_flush_d7, int_flush_d8, int_flush_d9, int_flush_d10, int_flush_d11, int_flush_d12}) | |
2929 | ); | |
2930 | assign int_flush = asicflush_tcu_req_hld | ~POR_; | |
2931 | ||
2932 | // ******************************************************************** | |
2933 | // Tell EFUSE to Start, but first send a CLEAR signal | |
2934 | // Active only during POR sequence; JTAG accessible tcu_efu_rvclr[6:0] | |
2935 | // tcu_efu_rvclr[6] = 1 enables a clear | |
2936 | // tcu_efu_rvclr[5:0] = block_id per efuse spec selects Redundancy Value to clear | |
2937 | // tcu_efu_rvclr[5:0] = 11_1111 will tell efuse to clear all RV's | |
2938 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_6 tcusig_efctl_reg // sends all clear, then start | |
2939 | ( | |
2940 | .scan_in(tcusig_efctl_reg_scanin), | |
2941 | .scan_out(tcusig_efctl_reg_scanout), | |
2942 | .l1clk (l1clk), | |
2943 | .clr (efctl_clear), | |
2944 | .din (efctl_din[5:0]), | |
2945 | .dout (efctl_dout[5:0]), | |
2946 | .siclk(siclk), | |
2947 | .soclk(soclk) | |
2948 | ); | |
2949 | assign efu_clr_ok = efctl_dout[5] & ~efctl_dout[4] & ~efctl_dout[3] | |
2950 | & ~efctl_clear; | |
2951 | assign efctl_clear = (por_one | por_two) & flush_clk_stop_active; | |
2952 | assign efctl_hold = efctl_dout[5] & efctl_dout[4] & efctl_dout[3]; | |
2953 | assign efctl_din[5:0] = efctl_hold ? efctl_dout[5:0] | |
2954 | : (efctl_dout[5:0] + 6'b1); | |
2955 | ||
2956 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_15 tcusig_efcnt_reg // counts for efuse Xfer time | |
2957 | ( | |
2958 | .scan_in(tcusig_efcnt_reg_scanin), | |
2959 | .scan_out(tcusig_efcnt_reg_scanout), | |
2960 | .l1clk (l1clk), | |
2961 | .clr (efcnt_clear), | |
2962 | .din (efcnt_din[14:0]), | |
2963 | .dout (efcnt_dout[14:0]), | |
2964 | .siclk(siclk), | |
2965 | .soclk(soclk) | |
2966 | ); | |
2967 | assign efcnt_clear = ~efctl_hold; // stop counting at 0x4801 | |
2968 | assign efcnt_pre_hold = efcnt_dout[14] & efcnt_dout[11]; //&efcnt_dout[14:1]; | |
2969 | assign efcnt_hold = efcnt_pre_hold & efcnt_dout[0]; | |
2970 | assign efcnt_din[14:0] = efcnt_hold ? efcnt_dout[14:0] | |
2971 | : (efcnt_dout[14:0] + 15'b1); | |
2972 | ||
2973 | assign tcu_efu_rvclr[6:0] = jtag_efu_clear_instr_sync ? jtag_efu_rvclr[6:0] | |
2974 | : {7{efu_clr_ok}}; | |
2975 | assign tcu_efu_read_start = efctl_dout[5] & efctl_dout[4] & ~efctl_dout[3]; | |
2976 | assign efu_done_int = efcnt_hold; | |
2977 | assign tcu_rst_efu_done = (efu_done_int & ~jtag_por_active) | ac_test_mode; | |
2978 | ||
2979 | ||
2980 | // ******************************************************************** | |
2981 | // Clock Stop Logic | |
2982 | // ******************************************************************** | |
2983 | // 24 clock domains; stop in staggered fashion with starting point | |
2984 | // selected via a 24-bit register in tcu_regs_ctl | |
2985 | ||
2986 | assign strt_cnt_clr_ = ~flush_tcu; | |
2987 | ||
2988 | //create signals for which domain to stop first from register value | |
2989 | assign hard_stop_via_reg_din = {|debug_reg_hard_stop_domain_1st}; | |
2990 | assign clock_stop_active = hard_stop_via_reg | flush_clk_stop_active | coreavail_clk_stop_active | |
2991 | | jtag_clk_stop_active; | |
2992 | assign debug_stop_req = debug_cycle_counter_stop | debug_event_stop; | |
2993 | assign stop_req = debug_stop_req | coreavail_clk_stop_active | jtmb_clk_stop | |
2994 | | ((~por_one & (flush | flush_start)) | (por_one & flush_start)); | |
2995 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__en_1__width_1 tcusig_clkstopviareg_reg | |
2996 | ( | |
2997 | .scan_in(tcusig_clkstopviareg_reg_scanin), | |
2998 | .scan_out(tcusig_clkstopviareg_reg_scanout), | |
2999 | .l1clk (l1clk), | |
3000 | .clr (clk_stop_loops_off), | |
3001 | .en (debug_stop_req), | |
3002 | .din (hard_stop_via_reg_din), | |
3003 | .dout (hard_stop_via_reg), | |
3004 | .siclk(siclk), | |
3005 | .soclk(soclk) | |
3006 | ); | |
3007 | // ******************************************************************** | |
3008 | // JTAG Clock Stop mode - holds clock stop active until all clocks are restarted | |
3009 | tcu_sigmux_ctl_msff_ctl_macro__clr__1__width_1 tcusig_jtagclkstop_reg | |
3010 | ( | |
3011 | .scan_in(tcusig_jtagclkstop_reg_scanin), | |
3012 | .scan_out(tcusig_jtagclkstop_reg_scanout), | |
3013 | .l1clk (l1clk), | |
3014 | .clr_ (jtag_clk_stop_clear_), | |
3015 | .din (jtag_clk_stop), | |
3016 | .dout (jtag_clk_stop_active), | |
3017 | .siclk(siclk), | |
3018 | .soclk(soclk) | |
3019 | ); | |
3020 | assign jtag_clk_stop_clear_ = ~clk_stop_loops_all_off | jtmb_clk_stop; | |
3021 | //assign jtag_clk_stop_clear_ = soc8_stopped | jtag_clk_stop_req_sync; | |
3022 | assign jtag_clk_stop = jtmb_clk_stop | jtag_clk_stop_active; | |
3023 | // ******************************************************************** | |
3024 | // FLUSH mode - holds flush clock stop active until all clocks are restarted | |
3025 | // - all clocks restarted signaled by soc3 clk stop going low (last in sequence) | |
3026 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_flushclkstop_reg | |
3027 | ( | |
3028 | .scan_in(tcusig_flushclkstop_reg_scanin), | |
3029 | .scan_out(tcusig_flushclkstop_reg_scanout), | |
3030 | .l1clk (l1clk), | |
3031 | .din (flush_clk_stop_in), // invert din, dout since flush to zero | |
3032 | .dout (flush_clk_stop_active_l), | |
3033 | .siclk(siclk), | |
3034 | .soclk(soclk) | |
3035 | ); | |
3036 | assign flush_clk_stop_in = ~flush_clk_stop | ~flush_clear_; | |
3037 | assign flush_clk_stop_active = ~flush_clk_stop_active_l; | |
3038 | //assign flush_clear_ = soc3_stopped | flush; | |
3039 | assign flush_clear_ = ~clk_stop_loops_all_off_q128 | flush; | |
3040 | assign flush_clk_stop = flush | flush_clk_stop_active; | |
3041 | // ******************************************************************** | |
3042 | // Flop and delay rst_wmr_protect by a few io clock cycles to allow time | |
3043 | // for core_enable_status and bank_enable_status (baxx) to settle | |
3044 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_3 tcusig_warmrp_reg | |
3045 | ( | |
3046 | .scan_in(tcusig_warmrp_reg_scanin), | |
3047 | .scan_out(tcusig_warmrp_reg_scanout), | |
3048 | .l1clk (l1clk), | |
3049 | .en (io_cmp_sync_en_local), | |
3050 | .din ({rst_wmr_protect, rst_wmr_protect_d, rst_wmr_protect_d2 }), | |
3051 | .dout ({rst_wmr_protect_d, rst_wmr_protect_d2, rst_wmr_protect_sync}), | |
3052 | .siclk(siclk), | |
3053 | .soclk(soclk) | |
3054 | ); | |
3055 | // ******************************************************************** | |
3056 | // CORE_AVAILABLE mode - stop clocks based on core_available bits that are '0' | |
3057 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_1 tcusig_coreavailclkstop_reg | |
3058 | ( | |
3059 | .scan_in(tcusig_coreavailclkstop_reg_scanin), | |
3060 | .scan_out(tcusig_coreavailclkstop_reg_scanout), | |
3061 | .l1clk (l1clk), | |
3062 | .clr (coreavail_clear), | |
3063 | .din (coreavail_clk_stop), | |
3064 | .dout (coreavail_clk_stop_active_dout), | |
3065 | .siclk(siclk), | |
3066 | .soclk(soclk) | |
3067 | ); | |
3068 | assign coreavail_clk_stop_active = ~ac_test_mode & coreavail_clk_stop_active_dout; | |
3069 | assign core_avail_qualified = ~efcnt_pre_hold | ac_test_mode; | |
3070 | ||
3071 | // Core_Avail and Bank_Avail are treated similarly | |
3072 | assign core_avail_pre_hold[7:0] = core_avail[7:0] | {8{core_avail_qualified}}; | |
3073 | assign bank_avail_pre_hold[7:0] = bank_avail[7:0] | {8{core_avail_qualified}}; | |
3074 | assign core_avail_pre_hold_l[7:0] = ~core_avail_pre_hold[7:0]; | |
3075 | assign bank_avail_pre_hold_l[7:0] = ~bank_avail_pre_hold[7:0]; | |
3076 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_16 tcusig_ca_reg | |
3077 | ( | |
3078 | .scan_in(tcusig_ca_reg_scanin), | |
3079 | .scan_out(tcusig_ca_reg_scanout), | |
3080 | .l1clk (l1clk), | |
3081 | .en (ca_enable), | |
3082 | .din ({bank_avail_pre_hold_l[7:0],core_avail_pre_hold_l[7:0]}), | |
3083 | .dout ({bank_avail_hold_l[7:0], core_avail_hold_l[7:0]}), | |
3084 | .siclk(siclk), | |
3085 | .soclk(soclk) | |
3086 | ); | |
3087 | ||
3088 | assign core_avail_hold[7:0] = ~core_avail_hold_l[7:0]; | |
3089 | assign bank_avail_hold[7:0] = ~bank_avail_hold_l[7:0]; | |
3090 | assign ca_hold = tcu_rst_efu_done; // update core_avail with POR1/2 | |
3091 | assign ca_enable = ~ca_hold; | |
3092 | ||
3093 | assign all_cores_available = (&spc_avail) & (&l2bnk_avail); | |
3094 | assign coreavail_clk_stop = ~all_cores_available & ~ces_enable; // sequence if core_avail or core_en_st | |
3095 | // clear signal for core available mode | |
3096 | tcu_sigmux_ctl_msff_ctl_macro__clr__1__width_1 tcusig_coreavailclear_reg | |
3097 | ( | |
3098 | .scan_in(tcusig_coreavailclear_reg_scanin), | |
3099 | .scan_out(tcusig_coreavailclear_reg_scanout), | |
3100 | .l1clk (l1clk), | |
3101 | .clr_ (coreavail_clk_stop), | |
3102 | .din (mcu3_clk_stop_loop | coreavail_clear), // this was: --> spc7_clk_stop_loop | |
3103 | .dout (coreavail_clear_dout), | |
3104 | .siclk(siclk), | |
3105 | .soclk(soclk) | |
3106 | ); | |
3107 | assign coreavail_clear = ~ac_test_mode & coreavail_clear_dout; | |
3108 | // ******************************************************************** | |
3109 | // CORE_ENABLE_STATUS - also stop clocks based on core_enable_status bits that are '0' | |
3110 | // but only after wmr_two events | |
3111 | // Both core_en_status (8 bits) and L2_bank_en_status (4 bits) are included here | |
3112 | ||
3113 | // first, flop inputs and sync to io clock; these are core_enable and bank_enable combined | |
3114 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_13 tcusig_enstat_reg | |
3115 | ( | |
3116 | .scan_in(tcusig_enstat_reg_scanin), | |
3117 | .scan_out(tcusig_enstat_reg_scanout), | |
3118 | .l1clk (l1clk), | |
3119 | .en (enstat_en), //io_cmp_sync_en_local), | |
3120 | .din ({ncu_spc7_core_enable_status, ncu_spc6_core_enable_status, ncu_spc5_core_enable_status, | |
3121 | ncu_spc4_core_enable_status, ncu_spc3_core_enable_status, ncu_spc2_core_enable_status, | |
3122 | ncu_spc1_core_enable_status, ncu_spc0_core_enable_status, | |
3123 | ncu_spc_pm, ncu_spc_ba67, ncu_spc_ba45, ncu_spc_ba23, ncu_spc_ba01}), | |
3124 | .dout ({ncu_spc7_core_enable_status_io, ncu_spc6_core_enable_status_io, ncu_spc5_core_enable_status_io, | |
3125 | ncu_spc4_core_enable_status_io, ncu_spc3_core_enable_status_io, ncu_spc2_core_enable_status_io, | |
3126 | ncu_spc1_core_enable_status_io, ncu_spc0_core_enable_status_io, | |
3127 | ncu_spc_pm_io, ncu_spc_ba67_io, ncu_spc_ba45_io, ncu_spc_ba23_io, ncu_spc_ba01_io}), | |
3128 | .siclk(siclk), | |
3129 | .soclk(soclk) | |
3130 | ); | |
3131 | assign enstat_en = ~tcu_test_protect_cmp & io_cmp_sync_en_local; | |
3132 | ||
3133 | assign ncu_ba67 = ~ncu_spc_pm_io | ncu_spc_ba67_io; | |
3134 | assign ncu_ba45 = ~ncu_spc_pm_io | ncu_spc_ba45_io; | |
3135 | assign ncu_ba23 = ~ncu_spc_pm_io | ncu_spc_ba23_io; | |
3136 | assign ncu_ba01 = ~ncu_spc_pm_io | ncu_spc_ba01_io; | |
3137 | ||
3138 | assign core_en_status[11:0] = | |
3139 | { ncu_ba67, ncu_ba45, ncu_ba23, ncu_ba01, | |
3140 | ncu_spc7_core_enable_status_io,ncu_spc6_core_enable_status_io, | |
3141 | ncu_spc5_core_enable_status_io,ncu_spc4_core_enable_status_io, | |
3142 | ncu_spc3_core_enable_status_io,ncu_spc2_core_enable_status_io, | |
3143 | ncu_spc1_core_enable_status_io,ncu_spc0_core_enable_status_io | |
3144 | }; | |
3145 | assign core_enstat_qual_l = wmr_two & ~rst_wmr_protect_sync & tcu_rst_flush_stop_ack; | |
3146 | assign core_enstat_qual = ~core_enstat_qual_l; | |
3147 | // One-cycle pulse to allow core_en_stat value to be flopped and held | |
3148 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_cesq_reg | |
3149 | ( | |
3150 | .scan_in(tcusig_cesq_reg_scanin), | |
3151 | .scan_out(tcusig_cesq_reg_scanout), | |
3152 | .l1clk (l1clk), | |
3153 | .din (core_enstat_qual), | |
3154 | .dout (core_enstat_qual_dly), | |
3155 | .siclk(siclk), | |
3156 | .soclk(soclk) | |
3157 | ); | |
3158 | ||
3159 | assign core_en_status_pre_hold[11:0] = core_en_status[11:0] | {12{core_enstat_qual}}; | |
3160 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_12 tcusig_ces_reg | |
3161 | ( | |
3162 | .scan_in(tcusig_ces_reg_scanin), | |
3163 | .scan_out(tcusig_ces_reg_scanout), | |
3164 | .l1clk (l1clk), | |
3165 | .en (ces_enable), | |
3166 | .din (~core_en_status_pre_hold[11:0]), | |
3167 | .dout (core_en_status_hold_l[11:0]), | |
3168 | .siclk(siclk), | |
3169 | .soclk(soclk) | |
3170 | ); | |
3171 | assign core_en_status_hold[11:0] = ~core_en_status_hold_l[11:0]; | |
3172 | assign ces_enable = ~core_enstat_qual & core_enstat_qual_dly; // only update core_en_stat with WMR2 | |
3173 | ||
3174 | assign spc_avail[7:0] = core_avail_hold[7:0] & core_en_status_hold[7:0] ; | |
3175 | ||
3176 | assign l2bnk_avail[7:6] = bank_avail_hold[7:6] & {2{core_en_status_hold[11] }}; | |
3177 | assign l2bnk_avail[5:4] = bank_avail_hold[5:4] & {2{core_en_status_hold[10] }}; | |
3178 | assign l2bnk_avail[3:2] = bank_avail_hold[3:2] & {2{core_en_status_hold[9] }}; | |
3179 | assign l2bnk_avail[1:0] = bank_avail_hold[1:0] & {2{core_en_status_hold[8] }}; | |
3180 | ||
3181 | assign mcu3_avail_hold = bank_avail_hold[7] & bank_avail_hold[6]; | |
3182 | assign mcu2_avail_hold = bank_avail_hold[5] & bank_avail_hold[4]; | |
3183 | assign mcu1_avail_hold = bank_avail_hold[3] & bank_avail_hold[2]; | |
3184 | assign mcu0_avail_hold = bank_avail_hold[1] & bank_avail_hold[0]; | |
3185 | ||
3186 | //assign mcu3_avail = mcu3_avail_hold & core_en_status_hold[11]; | |
3187 | //assign mcu2_avail = mcu2_avail_hold & core_en_status_hold[10]; | |
3188 | //assign mcu1_avail = mcu1_avail_hold & core_en_status_hold[9] ; | |
3189 | //assign mcu0_avail = mcu0_avail_hold & core_en_status_hold[8] ; | |
3190 | ||
3191 | ||
3192 | // ******************************************************************** | |
3193 | // Clock Sequencer | |
3194 | // ******************************************************************** | |
3195 | ||
3196 | tcu_clkseq_ctl clkseq_ctl | |
3197 | ( | |
3198 | .debug_reg_hard_stop_domain_1st (debug_reg_hard_stop_domain_1st[23:0]), | |
3199 | .tcu_pce_ov (tcu_int_pce_ov), | |
3200 | .scan_in (clk_stop_seq_scanin), | |
3201 | .scan_out (clk_stop_seq_scanout), | |
3202 | .tcu_int_se(tcu_int_se), | |
3203 | .tcu_int_aclk(tcu_int_aclk), | |
3204 | .tcu_int_bclk(tcu_int_bclk), | |
3205 | .tcu_int_ce(tcu_int_ce), | |
3206 | .l2clk(l2clk), | |
3207 | .clock_stop_active(clock_stop_active), | |
3208 | .hard_stop_via_reg_din(hard_stop_via_reg_din), | |
3209 | .test_mode_gated(test_mode_gated), | |
3210 | .io_ac_test_mode(io_ac_test_mode), | |
3211 | .stop_req(stop_req), | |
3212 | .cntstart_equal_max(cntstart_equal_max), | |
3213 | .cntstop_equal_max(cntstop_equal_max), | |
3214 | .cntstart(cntstart), | |
3215 | .cntstop(cntstop), | |
3216 | .spc0_clk_stop_loop(spc0_clk_stop_loop), | |
3217 | .spc1_clk_stop_loop(spc1_clk_stop_loop), | |
3218 | .spc2_clk_stop_loop(spc2_clk_stop_loop), | |
3219 | .spc3_clk_stop_loop(spc3_clk_stop_loop), | |
3220 | .spc4_clk_stop_loop(spc4_clk_stop_loop), | |
3221 | .spc5_clk_stop_loop(spc5_clk_stop_loop), | |
3222 | .spc6_clk_stop_loop(spc6_clk_stop_loop), | |
3223 | .spc7_clk_stop_loop(spc7_clk_stop_loop), | |
3224 | .bnk0_clk_stop_loop(bnk0_clk_stop_loop), | |
3225 | .bnk1_clk_stop_loop(bnk1_clk_stop_loop), | |
3226 | .bnk2_clk_stop_loop(bnk2_clk_stop_loop), | |
3227 | .bnk3_clk_stop_loop(bnk3_clk_stop_loop), | |
3228 | .bnk4_clk_stop_loop(bnk4_clk_stop_loop), | |
3229 | .bnk5_clk_stop_loop(bnk5_clk_stop_loop), | |
3230 | .bnk6_clk_stop_loop(bnk6_clk_stop_loop), | |
3231 | .bnk7_clk_stop_loop(bnk7_clk_stop_loop), | |
3232 | .mcu0_clk_stop_loop(mcu0_clk_stop_loop), | |
3233 | .mcu1_clk_stop_loop(mcu1_clk_stop_loop), | |
3234 | .mcu2_clk_stop_loop(mcu2_clk_stop_loop), | |
3235 | .mcu3_clk_stop_loop(mcu3_clk_stop_loop), | |
3236 | .soc0_clk_stop_loop(soc0_clk_stop_loop), | |
3237 | .soc1_clk_stop_loop(soc1_clk_stop_loop), | |
3238 | .soc2_clk_stop_loop(soc2_clk_stop_loop), | |
3239 | .soc3_clk_stop_loop(soc3_clk_stop_loop), | |
3240 | .clk_stop_loops_all_on(clk_stop_loops_all_on), | |
3241 | .clk_stop_loops_all_off(clk_stop_loops_all_off) | |
3242 | ); | |
3243 | ||
3244 | assign clk_stop_loops_off = clk_stop_loops_all_off & ~debug_stop_req; | |
3245 | assign clkseq_stop = clk_stop_loops_all_on; // to jtag | |
3246 | assign clkseq_strt = clk_stop_loops_all_off; // to jtag | |
3247 | ||
3248 | // ******************************************************************** | |
3249 | // Delay each clock stop before sending it on to synchronizers | |
3250 | // ******************************************************************** | |
3251 | assign cntstop = stop_req & clock_stop_active; | |
3252 | assign cntstart = ~stop_req & clock_stop_active; | |
3253 | assign cntstop_equal_max = (cntstop_dout[`CSDEL_MSB:0] == cntdly_dout[`CSDEL_MSB:0]); | |
3254 | assign cntstart_equal_max = (cntstart_dout[`CSDEL_MSB:0] == cntdly_dout[`CSDEL_MSB:0]); | |
3255 | ||
3256 | assign cntstop_din[`CSDEL_MSB:0] = cntstop ? (cntstop_dout[`CSDEL_MSB:0] + `CSDEL'b1) | |
3257 | : cntstop_dout[`CSDEL_MSB:0]; | |
3258 | assign cntstart_din[`CSDEL_MSB:0] = cntstart ? (cntstart_dout[`CSDEL_MSB:0] + `CSDEL'b1) | |
3259 | : cntstart_dout[`CSDEL_MSB:0]; | |
3260 | ||
3261 | ||
3262 | // ******************************************************************** | |
3263 | // 2 counters; to insure common delay between starting/stopping clock | |
3264 | // domains; set `CSDEL=7 for 128 l2clk delays, `CSDEL_MSB=6 | |
3265 | // ******************************************************************** | |
3266 | // ******************************************************************** | |
3267 | // Register to set programmable delay between starts/stops | |
3268 | // ******************************************************************** | |
3269 | tcu_sigmux_ctl_msff_ctl_macro__width_7 tcusig_cntdly_reg | |
3270 | ( | |
3271 | .scan_in(tcusig_cntdly_reg_scanin), | |
3272 | .scan_out(tcusig_cntdly_reg_scanout), | |
3273 | .l1clk (l1clk), | |
3274 | .din (cntdly_din_l[`CSDEL_MSB:0]), | |
3275 | .dout (cntdly_dout_l[`CSDEL_MSB:0]), | |
3276 | .siclk(siclk), | |
3277 | .soclk(soclk) | |
3278 | ); | |
3279 | assign cntdly_din_l[`CSDEL_MSB:0] = ucb_wr_clkstp_delay ? ucb_data_out[`CSDEL_MSB:0] : | |
3280 | ~cntdly_din[`CSDEL_MSB:0]; | |
3281 | assign cntdly_dout[`CSDEL_MSB:0] = ~cntdly_dout_l[`CSDEL_MSB:0]; | |
3282 | ||
3283 | assign cntdly_din[`CSDEL_MSB:0] = jtag_upd_cntdly_sync ? jtag_cntdly_data[`CSDEL_MSB:0] | |
3284 | : cntdly_dout[`CSDEL_MSB:0]; | |
3285 | assign csdel_data[`CSDEL_MSB:0] = cntdly_dout[`CSDEL_MSB:0]; | |
3286 | ||
3287 | // ******************************************************************** | |
3288 | // This COUNTER counts to STOP CLOCKS: turn clocks OFF | |
3289 | // ******************************************************************** | |
3290 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_7 tcusig_cntstop_reg | |
3291 | ( | |
3292 | .scan_in(tcusig_cntstop_reg_scanin), | |
3293 | .scan_out(tcusig_cntstop_reg_scanout), | |
3294 | .l1clk (l1clk), | |
3295 | .clr (cntstop_equal_max), | |
3296 | .din ({`CSDEL{stop_cnt_en}} & cntstop_din[`CSDEL_MSB:0]), | |
3297 | .dout (cntstop_dout[`CSDEL_MSB:0]), | |
3298 | .siclk(siclk), | |
3299 | .soclk(soclk) | |
3300 | ); | |
3301 | assign stop_cnt_en = stop_req; | |
3302 | // ******************************************************************** | |
3303 | // This COUNTER counts to START CLOCKS: turn clocks ON | |
3304 | // ******************************************************************** | |
3305 | tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_7 tcusig_cntstart_reg | |
3306 | ( | |
3307 | .scan_in(tcusig_cntstart_reg_scanin), | |
3308 | .scan_out(tcusig_cntstart_reg_scanout), | |
3309 | .l1clk (l1clk), | |
3310 | .clr (cntstart_equal_max), | |
3311 | .din ({`CSDEL{strt_cnt_en}} & cntstart_din[`CSDEL_MSB:0]), | |
3312 | .dout (cntstart_dout[`CSDEL_MSB:0]), | |
3313 | .siclk(siclk), | |
3314 | .soclk(soclk) | |
3315 | ); | |
3316 | assign strt_cnt_en = ~stop_req & strt_cnt_clr_; | |
3317 | ||
3318 | // ******************************************************************** | |
3319 | // Flop soft-stop mode, hold until clock sequencer turns all spc clocks on again | |
3320 | // ******************************************************************** | |
3321 | // This allows clk seq. time to finish its operation | |
3322 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_ssmode_reg | |
3323 | ( | |
3324 | .scan_in(tcusig_ssmode_reg_scanin), | |
3325 | .scan_out(tcusig_ssmode_reg_scanout), | |
3326 | .l1clk (l1clk), | |
3327 | .en (ssmode_en), | |
3328 | .din (ss_req), | |
3329 | .dout (ss_mode), | |
3330 | .siclk(siclk), | |
3331 | .soclk(soclk) | |
3332 | ); | |
3333 | //assign ss_req = spc_ss_mode | instr_clock_sstop | instr_cs_mode; | |
3334 | assign core_sel_reg_nonzero = |spc_ss_sel[7:0]; | |
3335 | assign ss_req = spc_ss_mode | instr_sstop_csmode_sync | core_sel_reg_nonzero; | |
3336 | assign ssmode_en = ss_req | clk_stop_loops_all_off; | |
3337 | ||
3338 | // ******************************************************************** | |
3339 | // Flop soft-stop requests | |
3340 | // ******************************************************************** | |
3341 | // This allows signals to be extended until clk sequencer finishes | |
3342 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_8 tcusig_sssel_reg | |
3343 | ( | |
3344 | .scan_in(tcusig_sssel_reg_scanin), | |
3345 | .scan_out(tcusig_sssel_reg_scanout), | |
3346 | .l1clk (l1clk), | |
3347 | .en (sssel_en), | |
3348 | .din (spc_ss_sel[7:0]), | |
3349 | .dout (spc_ss_sel_d[7:0]), | |
3350 | .siclk(siclk), | |
3351 | .soclk(soclk) | |
3352 | ); | |
3353 | assign sssel_en = ~ss_mode; | |
3354 | assign spc_ss_sel_qual[7:0] = spc_ss_sel[7:0] | spc_ss_sel_d[7:0]; | |
3355 | ||
3356 | // ******************************************************************** | |
3357 | // ******************************************************************** | |
3358 | // Generation of clock stops before synchronizing them | |
3359 | // ******************************************************************** | |
3360 | assign spc0_clk_stop_cavail = spc0_clk_stop_loop & ~spc_avail[0]; | |
3361 | assign spc0_clk_stop_prepresync = coreavail_clk_stop_active ? spc0_clk_stop_cavail : spc0_clk_stop_loop; | |
3362 | assign spc0_clk_stop_presync = (coreavail_clear & ~spc_avail[0]) ? 1'b1 | |
3363 | : ac_test_mode ? spc0_clk_stop_sync // hold data | |
3364 | : (~all_cores_available & ~coreavail_clear) & ~spc0_clk_stop_loop & wmr_two ? spc0_clk_stop_sync | |
3365 | : ss_mode & ~spc_ss_sel_qual[0] ? 1'b0 | |
3366 | : spc0_clk_stop_prepresync; | |
3367 | ||
3368 | assign spc1_clk_stop_cavail = spc1_clk_stop_loop & ~spc_avail[1]; | |
3369 | assign spc1_clk_stop_prepresync = coreavail_clk_stop_active ? spc1_clk_stop_cavail : spc1_clk_stop_loop; | |
3370 | assign spc1_clk_stop_presync = (coreavail_clear & ~spc_avail[1]) ? 1'b1 | |
3371 | : ac_test_mode ? spc1_clk_stop_sync // hold data | |
3372 | : (~all_cores_available & ~coreavail_clear) & ~spc1_clk_stop_loop & wmr_two ? spc1_clk_stop_sync | |
3373 | : ss_mode & ~spc_ss_sel_qual[1] ? 1'b0 | |
3374 | : spc1_clk_stop_prepresync; | |
3375 | ||
3376 | assign spc2_clk_stop_cavail = spc2_clk_stop_loop & ~spc_avail[2]; | |
3377 | assign spc2_clk_stop_prepresync = coreavail_clk_stop_active ? spc2_clk_stop_cavail : spc2_clk_stop_loop; | |
3378 | assign spc2_clk_stop_presync = (coreavail_clear & ~spc_avail[2]) ? 1'b1 | |
3379 | : ac_test_mode ? spc2_clk_stop_sync // hold data | |
3380 | : (~all_cores_available & ~coreavail_clear) & ~spc2_clk_stop_loop & wmr_two ? spc2_clk_stop_sync | |
3381 | : ss_mode & ~spc_ss_sel_qual[2] ? 1'b0 | |
3382 | : spc2_clk_stop_prepresync; | |
3383 | ||
3384 | assign spc3_clk_stop_cavail = spc3_clk_stop_loop & ~spc_avail[3]; | |
3385 | assign spc3_clk_stop_prepresync = coreavail_clk_stop_active ? spc3_clk_stop_cavail : spc3_clk_stop_loop; | |
3386 | assign spc3_clk_stop_presync = (coreavail_clear & ~spc_avail[3]) ? 1'b1 | |
3387 | : ac_test_mode ? spc3_clk_stop_sync // hold data | |
3388 | : (~all_cores_available & ~coreavail_clear) & ~spc3_clk_stop_loop & wmr_two ? spc3_clk_stop_sync | |
3389 | : ss_mode & ~spc_ss_sel_qual[3] ? 1'b0 | |
3390 | : spc3_clk_stop_prepresync; | |
3391 | ||
3392 | assign spc4_clk_stop_cavail = spc4_clk_stop_loop & ~spc_avail[4]; | |
3393 | assign spc4_clk_stop_prepresync = coreavail_clk_stop_active ? spc4_clk_stop_cavail : spc4_clk_stop_loop; | |
3394 | assign spc4_clk_stop_presync = (coreavail_clear & ~spc_avail[4]) ? 1'b1 | |
3395 | : ac_test_mode ? spc4_clk_stop_sync // hold data | |
3396 | : (~all_cores_available & ~coreavail_clear) & ~spc4_clk_stop_loop & wmr_two ? spc4_clk_stop_sync | |
3397 | : ss_mode & ~spc_ss_sel_qual[4] ? 1'b0 | |
3398 | : spc4_clk_stop_prepresync; | |
3399 | ||
3400 | assign spc5_clk_stop_cavail = spc5_clk_stop_loop & ~spc_avail[5]; | |
3401 | assign spc5_clk_stop_prepresync = coreavail_clk_stop_active ? spc5_clk_stop_cavail : spc5_clk_stop_loop; | |
3402 | assign spc5_clk_stop_presync = (coreavail_clear & ~spc_avail[5]) ? 1'b1 | |
3403 | : ac_test_mode ? spc5_clk_stop_sync // hold data | |
3404 | : (~all_cores_available & ~coreavail_clear) & ~spc5_clk_stop_loop & wmr_two ? spc5_clk_stop_sync | |
3405 | : ss_mode & ~spc_ss_sel_qual[5] ? 1'b0 | |
3406 | : spc5_clk_stop_prepresync; | |
3407 | ||
3408 | assign spc6_clk_stop_cavail = spc6_clk_stop_loop & ~spc_avail[6]; | |
3409 | assign spc6_clk_stop_prepresync = coreavail_clk_stop_active? spc6_clk_stop_cavail : spc6_clk_stop_loop; | |
3410 | assign spc6_clk_stop_presync = (coreavail_clear & ~spc_avail[6]) ? 1'b1 | |
3411 | : ac_test_mode ? spc6_clk_stop_sync // hold data | |
3412 | : (~all_cores_available & ~coreavail_clear) & ~spc6_clk_stop_loop & wmr_two ? spc6_clk_stop_sync | |
3413 | : ss_mode & ~spc_ss_sel_qual[6] ? 1'b0 | |
3414 | : spc6_clk_stop_prepresync; | |
3415 | ||
3416 | assign spc7_clk_stop_cavail = spc7_clk_stop_loop & ~spc_avail[7]; | |
3417 | assign spc7_clk_stop_prepresync = coreavail_clk_stop_active ? spc7_clk_stop_cavail : spc7_clk_stop_loop; | |
3418 | assign spc7_clk_stop_presync = (coreavail_clear & ~spc_avail[7]) ? 1'b1 | |
3419 | : ac_test_mode ? spc7_clk_stop_sync // hold data | |
3420 | : (~all_cores_available & ~coreavail_clear) & ~spc7_clk_stop_loop & wmr_two ? spc7_clk_stop_sync | |
3421 | : ss_mode & ~spc_ss_sel_qual[7] ? 1'b0 | |
3422 | : spc7_clk_stop_prepresync; | |
3423 | ||
3424 | //soc | |
3425 | assign bnk0_clk_stop_cavail = bnk0_clk_stop_loop & ~l2bnk_avail[0]; | |
3426 | assign bnk0_clk_stop_prepresync = coreavail_clk_stop_active ? bnk0_clk_stop_cavail : bnk0_clk_stop_loop; | |
3427 | assign bnk0_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[0]) ? 1'b1 | |
3428 | : ac_test_mode ? bnk0_clk_stop_sync // hold data | |
3429 | : (~all_cores_available & ~coreavail_clear) & ~bnk0_clk_stop_loop & wmr_two ? bnk0_clk_stop_sync | |
3430 | : ss_mode ? 1'b0 | |
3431 | : bnk0_clk_stop_prepresync; | |
3432 | ||
3433 | assign l2t0_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk0_clk_stop_loop; | |
3434 | assign l2t0_clk_stop_presync = ac_test_mode ? l2t0_clk_stop_sync // hold data | |
3435 | : (~all_cores_available & ~coreavail_clear) & ~bnk0_clk_stop_loop & wmr_two ? l2t0_clk_stop_sync | |
3436 | : ss_mode ? 1'b0 | |
3437 | : l2t0_clk_stop_prepresync; | |
3438 | ||
3439 | assign bnk1_clk_stop_cavail = bnk1_clk_stop_loop & ~l2bnk_avail[1]; | |
3440 | assign bnk1_clk_stop_prepresync = coreavail_clk_stop_active ? bnk1_clk_stop_cavail : bnk1_clk_stop_loop; | |
3441 | assign bnk1_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[1]) ? 1'b1 | |
3442 | : ac_test_mode ? bnk1_clk_stop_sync // hold data | |
3443 | : (~all_cores_available & ~coreavail_clear) & ~bnk1_clk_stop_loop & wmr_two ? bnk1_clk_stop_sync | |
3444 | : ss_mode ? 1'b0 | |
3445 | : bnk1_clk_stop_prepresync; | |
3446 | ||
3447 | assign l2t1_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk1_clk_stop_loop; | |
3448 | assign l2t1_clk_stop_presync = ac_test_mode ? l2t1_clk_stop_sync // hold data | |
3449 | : (~all_cores_available & ~coreavail_clear) & ~bnk1_clk_stop_loop & wmr_two ? l2t1_clk_stop_sync | |
3450 | : ss_mode ? 1'b0 | |
3451 | : l2t1_clk_stop_prepresync; | |
3452 | ||
3453 | assign bnk2_clk_stop_cavail = bnk2_clk_stop_loop & ~l2bnk_avail[2]; | |
3454 | assign bnk2_clk_stop_prepresync = coreavail_clk_stop_active ? bnk2_clk_stop_cavail : bnk2_clk_stop_loop; | |
3455 | assign bnk2_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[2]) ? 1'b1 | |
3456 | : ac_test_mode ? bnk2_clk_stop_sync // hold data | |
3457 | : (~all_cores_available & ~coreavail_clear) & ~bnk2_clk_stop_loop & wmr_two ? bnk2_clk_stop_sync | |
3458 | : ss_mode ? 1'b0 | |
3459 | : bnk2_clk_stop_prepresync; | |
3460 | ||
3461 | assign l2t2_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk2_clk_stop_loop; | |
3462 | assign l2t2_clk_stop_presync = ac_test_mode ? l2t2_clk_stop_sync // hold data | |
3463 | : (~all_cores_available & ~coreavail_clear) & ~bnk2_clk_stop_loop & wmr_two ? l2t2_clk_stop_sync | |
3464 | : ss_mode ? 1'b0 | |
3465 | : l2t2_clk_stop_prepresync; | |
3466 | ||
3467 | assign bnk3_clk_stop_cavail = bnk3_clk_stop_loop & ~l2bnk_avail[3]; | |
3468 | assign bnk3_clk_stop_prepresync = coreavail_clk_stop_active ? bnk3_clk_stop_cavail : bnk3_clk_stop_loop; | |
3469 | assign bnk3_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[3]) ? 1'b1 | |
3470 | : ac_test_mode ? bnk3_clk_stop_sync // hold data | |
3471 | : (~all_cores_available & ~coreavail_clear) & ~bnk3_clk_stop_loop & wmr_two ? bnk3_clk_stop_sync | |
3472 | : ss_mode ? 1'b0 | |
3473 | : bnk3_clk_stop_prepresync; | |
3474 | ||
3475 | assign l2t3_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk3_clk_stop_loop; | |
3476 | assign l2t3_clk_stop_presync = ac_test_mode ? l2t3_clk_stop_sync // hold data | |
3477 | : (~all_cores_available & ~coreavail_clear) & ~bnk3_clk_stop_loop & wmr_two ? l2t3_clk_stop_sync | |
3478 | : ss_mode ? 1'b0 | |
3479 | : l2t3_clk_stop_prepresync; | |
3480 | ||
3481 | assign bnk4_clk_stop_cavail = bnk4_clk_stop_loop & ~l2bnk_avail[4]; | |
3482 | assign bnk4_clk_stop_prepresync = coreavail_clk_stop_active ? bnk4_clk_stop_cavail : bnk4_clk_stop_loop; | |
3483 | assign bnk4_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[4]) ? 1'b1 | |
3484 | : ac_test_mode ? bnk4_clk_stop_sync // hold data | |
3485 | : (~all_cores_available & ~coreavail_clear) & ~bnk4_clk_stop_loop & wmr_two ? bnk4_clk_stop_sync | |
3486 | : ss_mode ? 1'b0 | |
3487 | : bnk4_clk_stop_prepresync; | |
3488 | ||
3489 | assign l2t4_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk4_clk_stop_loop; | |
3490 | assign l2t4_clk_stop_presync = ac_test_mode ? l2t4_clk_stop_sync // hold data | |
3491 | : (~all_cores_available & ~coreavail_clear) & ~bnk4_clk_stop_loop & wmr_two ? l2t4_clk_stop_sync | |
3492 | : ss_mode ? 1'b0 | |
3493 | : l2t4_clk_stop_prepresync; | |
3494 | ||
3495 | assign bnk5_clk_stop_cavail = bnk5_clk_stop_loop & ~l2bnk_avail[5]; | |
3496 | assign bnk5_clk_stop_prepresync = coreavail_clk_stop_active ? bnk5_clk_stop_cavail : bnk5_clk_stop_loop; | |
3497 | assign bnk5_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[5]) ? 1'b1 | |
3498 | : ac_test_mode ? bnk5_clk_stop_sync // hold data | |
3499 | : (~all_cores_available & ~coreavail_clear) & ~bnk5_clk_stop_loop & wmr_two ? bnk5_clk_stop_sync | |
3500 | : ss_mode ? 1'b0 | |
3501 | : bnk5_clk_stop_prepresync; | |
3502 | ||
3503 | assign l2t5_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk5_clk_stop_loop; | |
3504 | assign l2t5_clk_stop_presync = ac_test_mode ? l2t5_clk_stop_sync // hold data | |
3505 | : (~all_cores_available & ~coreavail_clear) & ~bnk5_clk_stop_loop & wmr_two ? l2t5_clk_stop_sync | |
3506 | : ss_mode ? 1'b0 | |
3507 | : l2t5_clk_stop_prepresync; | |
3508 | ||
3509 | assign bnk6_clk_stop_cavail = bnk6_clk_stop_loop & ~l2bnk_avail[6]; | |
3510 | assign bnk6_clk_stop_prepresync = coreavail_clk_stop_active ? bnk6_clk_stop_cavail : bnk6_clk_stop_loop; | |
3511 | assign bnk6_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[6]) ? 1'b1 | |
3512 | : ac_test_mode ? bnk6_clk_stop_sync // hold data | |
3513 | : (~all_cores_available & ~coreavail_clear) & ~bnk6_clk_stop_loop & wmr_two ? bnk6_clk_stop_sync | |
3514 | : ss_mode ? 1'b0 | |
3515 | : bnk6_clk_stop_prepresync; | |
3516 | ||
3517 | assign l2t6_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk6_clk_stop_loop; | |
3518 | assign l2t6_clk_stop_presync = ac_test_mode ? l2t6_clk_stop_sync // hold data | |
3519 | : (~all_cores_available & ~coreavail_clear) & ~bnk6_clk_stop_loop & wmr_two ? l2t6_clk_stop_sync | |
3520 | : ss_mode ? 1'b0 | |
3521 | : l2t6_clk_stop_prepresync; | |
3522 | ||
3523 | assign bnk7_clk_stop_cavail = bnk7_clk_stop_loop & ~l2bnk_avail[7]; | |
3524 | assign bnk7_clk_stop_prepresync = coreavail_clk_stop_active ? bnk7_clk_stop_cavail : bnk7_clk_stop_loop; | |
3525 | assign bnk7_clk_stop_presync = (coreavail_clear & ~l2bnk_avail[7]) ? 1'b1 | |
3526 | : ac_test_mode ? bnk7_clk_stop_sync // hold data | |
3527 | : (~all_cores_available & ~coreavail_clear) & ~bnk7_clk_stop_loop & wmr_two ? bnk7_clk_stop_sync | |
3528 | : ss_mode ? 1'b0 | |
3529 | : bnk7_clk_stop_prepresync; | |
3530 | ||
3531 | assign l2t7_clk_stop_prepresync = coreavail_clk_stop_active ? 1'b0 : bnk7_clk_stop_loop; | |
3532 | assign l2t7_clk_stop_presync = ac_test_mode ? l2t7_clk_stop_sync // hold data | |
3533 | : (~all_cores_available & ~coreavail_clear) & ~bnk7_clk_stop_loop & wmr_two ? l2t7_clk_stop_sync | |
3534 | : ss_mode ? 1'b0 | |
3535 | : l2t7_clk_stop_prepresync; | |
3536 | ||
3537 | assign mcu0_clk_stop_cavail = mcu0_clk_stop_loop & (~l2bnk_avail[0] | ~l2bnk_avail[1]); | |
3538 | assign mcu0_clk_stop_prepresync = coreavail_clk_stop_active ? mcu0_clk_stop_cavail : mcu0_clk_stop_loop; | |
3539 | assign mcu0_clk_stop_presync = (coreavail_clear & (~l2bnk_avail[0] | ~l2bnk_avail[1])) ? 1'b1 | |
3540 | : ac_test_mode ? mcu0_clk_stop_sync // hold data | |
3541 | : (~all_cores_available & ~coreavail_clear) & ~mcu0_clk_stop_loop & wmr_two ? mcu0_clk_stop_sync | |
3542 | : ss_mode ? 1'b0 | |
3543 | : mcu0_clk_stop_prepresync; | |
3544 | ||
3545 | assign mcu1_clk_stop_cavail = mcu1_clk_stop_loop & (~l2bnk_avail[2] | ~l2bnk_avail[3]); | |
3546 | assign mcu1_clk_stop_prepresync = coreavail_clk_stop_active ? mcu1_clk_stop_cavail : mcu1_clk_stop_loop; | |
3547 | assign mcu1_clk_stop_presync = (coreavail_clear & (~l2bnk_avail[2] | ~l2bnk_avail[3])) ? 1'b1 | |
3548 | : ac_test_mode ? mcu1_clk_stop_sync // hold data | |
3549 | : (~all_cores_available & ~coreavail_clear) & ~mcu1_clk_stop_loop & wmr_two ? mcu1_clk_stop_sync | |
3550 | : ss_mode ? 1'b0 | |
3551 | : mcu1_clk_stop_prepresync; | |
3552 | ||
3553 | assign mcu2_clk_stop_cavail = mcu2_clk_stop_loop & (~l2bnk_avail[4] | ~l2bnk_avail[5]); | |
3554 | assign mcu2_clk_stop_prepresync = coreavail_clk_stop_active ? mcu2_clk_stop_cavail : mcu2_clk_stop_loop; | |
3555 | assign mcu2_clk_stop_presync = (coreavail_clear & (~l2bnk_avail[4] | ~l2bnk_avail[5])) ? 1'b1 | |
3556 | : ac_test_mode ? mcu2_clk_stop_sync // hold data | |
3557 | : (~all_cores_available & ~coreavail_clear) & ~mcu2_clk_stop_loop & wmr_two ? mcu2_clk_stop_sync | |
3558 | : ss_mode ? 1'b0 | |
3559 | : mcu2_clk_stop_prepresync; | |
3560 | ||
3561 | assign mcu3_clk_stop_cavail = mcu3_clk_stop_loop & (~l2bnk_avail[6] | ~l2bnk_avail[7]); | |
3562 | assign mcu3_clk_stop_prepresync = coreavail_clk_stop_active ? mcu3_clk_stop_cavail : mcu3_clk_stop_loop; | |
3563 | assign mcu3_clk_stop_presync = (coreavail_clear & (~l2bnk_avail[6] | ~l2bnk_avail[7])) ? 1'b1 | |
3564 | : ac_test_mode ? mcu3_clk_stop_sync // hold data | |
3565 | : (~all_cores_available & ~coreavail_clear) & ~mcu3_clk_stop_loop & wmr_two ? mcu3_clk_stop_sync | |
3566 | : ss_mode ? 1'b0 | |
3567 | : mcu3_clk_stop_prepresync; | |
3568 | ||
3569 | assign soc0_clk_stop_presync = ac_test_mode ? soc0_clk_stop_sync | |
3570 | : ss_mode ? 1'b0 | |
3571 | : soc0_clk_stop_loop; | |
3572 | assign soc1_clk_stop_presync = ac_test_mode ? soc1_clk_stop_sync | |
3573 | : ss_mode ? 1'b0 | |
3574 | : soc1_clk_stop_loop; | |
3575 | assign soc2_clk_stop_presync = ac_test_mode ? soc2_clk_stop_sync | |
3576 | : ss_mode ? 1'b0 | |
3577 | : soc2_clk_stop_loop; | |
3578 | assign soc3_clk_stop_presync = ac_test_mode ? soc3_clk_stop_sync | |
3579 | : ss_mode ? 1'b0 | |
3580 | : soc3_clk_stop_loop; | |
3581 | ||
3582 | // ******************************************************************** | |
3583 | // Synchronizers for transition test trigger from package pin | |
3584 | // ******************************************************************** | |
3585 | assign io_ac_tt_trigger = io_ac_testtrig & test_mode_gated; | |
3586 | assign tt_hold = ac_test_mode & ~ac_tt_trigger; | |
3587 | // synch flop is free running, non-scanned | |
3588 | cl_sc1_clksyncff_4x sync_ff_ac_tt_trigger_fr | |
3589 | (.si (1'b0), //(sync_ff_ac_tt_trigger_fr_scanin), | |
3590 | .so (sync_ff_ac_tt_trigger_fr_scanout_unused), | |
3591 | .l1clk (fr_l1clk), | |
3592 | .siclk (1'b0), | |
3593 | .soclk (1'b0), | |
3594 | .d (io_ac_tt_trigger), | |
3595 | .q (ac_tt_trigger_fr) | |
3596 | ); | |
3597 | // this is now observe flop for tt_trigger | |
3598 | cl_sc1_clksyncff_4x sync_ff_ac_tt_trigger | |
3599 | (.si (sync_ff_ac_tt_trigger_scanin), | |
3600 | .so (sync_ff_ac_tt_trigger_scanout), | |
3601 | .l1clk (l1clk), | |
3602 | .d (ac_tt_trigger_fr), | |
3603 | .q (ac_tt_trigger_fr_sync_unused), | |
3604 | .siclk(siclk), | |
3605 | .soclk(soclk) //(ac_tt_trigger) | |
3606 | ); | |
3607 | assign ac_tt_trigger = ac_tt_trigger_fr; | |
3608 | // ******************************************************************** | |
3609 | // Synchronizers for Clock Stops | |
3610 | // ******************************************************************** | |
3611 | // - These are not synchronizers anymore; all signals sent out in cmp clock domain | |
3612 | ||
3613 | assign spc0_clk_stop = tt_hold ? 1'b1 : spc0_clk_stop_q; | |
3614 | assign spc0_clk_stop_q = (spc0_clk_stop_sync | (~core_avail_hold[0] & wmr_two & ~ac_test_mode )); | |
3615 | assign spc1_clk_stop = tt_hold ? 1'b1 : spc1_clk_stop_q; | |
3616 | assign spc1_clk_stop_q = (spc1_clk_stop_sync | (~core_avail_hold[1] & wmr_two & ~ac_test_mode )); | |
3617 | assign spc2_clk_stop = tt_hold ? 1'b1 : spc2_clk_stop_q; | |
3618 | assign spc2_clk_stop_q = (spc2_clk_stop_sync | (~core_avail_hold[2] & wmr_two & ~ac_test_mode )); | |
3619 | assign spc3_clk_stop = tt_hold ? 1'b1 : spc3_clk_stop_q; | |
3620 | assign spc3_clk_stop_q = (spc3_clk_stop_sync | (~core_avail_hold[3] & wmr_two & ~ac_test_mode )); | |
3621 | assign spc4_clk_stop = tt_hold ? 1'b1 : spc4_clk_stop_q; | |
3622 | assign spc4_clk_stop_q = (spc4_clk_stop_sync | (~core_avail_hold[4] & wmr_two & ~ac_test_mode )); | |
3623 | assign spc5_clk_stop = tt_hold ? 1'b1 : spc5_clk_stop_q; | |
3624 | assign spc5_clk_stop_q = (spc5_clk_stop_sync | (~core_avail_hold[5] & wmr_two & ~ac_test_mode )); | |
3625 | assign spc6_clk_stop = tt_hold ? 1'b1 : spc6_clk_stop_q; | |
3626 | assign spc6_clk_stop_q = (spc6_clk_stop_sync | (~core_avail_hold[6] & wmr_two & ~ac_test_mode )); | |
3627 | assign spc7_clk_stop = tt_hold ? 1'b1 : spc7_clk_stop_q; | |
3628 | assign spc7_clk_stop_q = (spc7_clk_stop_sync | (~core_avail_hold[7] & wmr_two & ~ac_test_mode )); | |
3629 | ||
3630 | assign bnk0_clk_stop = tt_hold ? 1'b1 : bnk0_clk_stop_q; | |
3631 | assign bnk0_clk_stop_q = (bnk0_clk_stop_sync | (~bank_avail_hold[0] & wmr_two & ~ac_test_mode )); | |
3632 | assign l2t0_clk_stop = tt_hold ? 1'b1 : l2t0_clk_stop_sync; | |
3633 | assign bnk1_clk_stop = tt_hold ? 1'b1 : bnk1_clk_stop_q; | |
3634 | assign bnk1_clk_stop_q = (bnk1_clk_stop_sync | (~bank_avail_hold[1] & wmr_two & ~ac_test_mode )); | |
3635 | assign l2t1_clk_stop = tt_hold ? 1'b1 : l2t1_clk_stop_sync; | |
3636 | assign bnk2_clk_stop = tt_hold ? 1'b1 : bnk2_clk_stop_q; | |
3637 | assign bnk2_clk_stop_q = (bnk2_clk_stop_sync | (~bank_avail_hold[2] & wmr_two & ~ac_test_mode )); | |
3638 | assign l2t2_clk_stop = tt_hold ? 1'b1 : l2t2_clk_stop_sync; | |
3639 | assign bnk3_clk_stop = tt_hold ? 1'b1 : bnk3_clk_stop_q; | |
3640 | assign bnk3_clk_stop_q = (bnk3_clk_stop_sync | (~bank_avail_hold[3] & wmr_two & ~ac_test_mode )); | |
3641 | assign l2t3_clk_stop = tt_hold ? 1'b1 : l2t3_clk_stop_sync; | |
3642 | assign bnk4_clk_stop = tt_hold ? 1'b1 : bnk4_clk_stop_q; | |
3643 | assign bnk4_clk_stop_q = (bnk4_clk_stop_sync | (~bank_avail_hold[4] & wmr_two & ~ac_test_mode )); | |
3644 | assign l2t4_clk_stop = tt_hold ? 1'b1 : l2t4_clk_stop_sync; | |
3645 | assign bnk5_clk_stop = tt_hold ? 1'b1 : bnk5_clk_stop_q; | |
3646 | assign bnk5_clk_stop_q = (bnk5_clk_stop_sync | (~bank_avail_hold[5] & wmr_two & ~ac_test_mode )); | |
3647 | assign l2t5_clk_stop = tt_hold ? 1'b1 : l2t5_clk_stop_sync; | |
3648 | assign bnk6_clk_stop = tt_hold ? 1'b1 : bnk6_clk_stop_q; | |
3649 | assign bnk6_clk_stop_q = (bnk6_clk_stop_sync | (~bank_avail_hold[6] & wmr_two & ~ac_test_mode )); | |
3650 | assign l2t6_clk_stop = tt_hold ? 1'b1 : l2t6_clk_stop_sync; | |
3651 | assign bnk7_clk_stop = tt_hold ? 1'b1 : bnk7_clk_stop_q; | |
3652 | assign bnk7_clk_stop_q = (bnk7_clk_stop_sync | (~bank_avail_hold[7] & wmr_two & ~ac_test_mode )); | |
3653 | assign l2t7_clk_stop = tt_hold ? 1'b1 : l2t7_clk_stop_sync; | |
3654 | ||
3655 | assign mcu0_clk_stop = tt_hold ? 1'b1 : mcu0_clk_stop_q; | |
3656 | assign mcu0_clk_stop_q = (mcu0_clk_stop_sync | (~mcu0_avail_hold & wmr_two & ~ac_test_mode )); | |
3657 | assign mcu1_clk_stop = tt_hold ? 1'b1 : mcu1_clk_stop_q; | |
3658 | assign mcu1_clk_stop_q = (mcu1_clk_stop_sync | (~mcu1_avail_hold & wmr_two & ~ac_test_mode )); | |
3659 | assign mcu2_clk_stop = tt_hold ? 1'b1 : mcu2_clk_stop_q; | |
3660 | assign mcu2_clk_stop_q = (mcu2_clk_stop_sync | (~mcu2_avail_hold & wmr_two & ~ac_test_mode )); | |
3661 | assign mcu3_clk_stop = tt_hold ? 1'b1 : mcu3_clk_stop_q; | |
3662 | assign mcu3_clk_stop_q = (mcu3_clk_stop_sync | (~mcu3_avail_hold & wmr_two & ~ac_test_mode )); | |
3663 | ||
3664 | // ******** sync spc0 clk stop ******************* | |
3665 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc0_0 | |
3666 | ( | |
3667 | .scan_in(sync_ff_clk_stop_spc0_0_scanin), | |
3668 | .scan_out(sync_ff_clk_stop_spc0_0_scanout), | |
3669 | .din (~spc0_clk_stop_presync), | |
3670 | .dout (spc0_clk_stop_sync_l), | |
3671 | .l1clk (l1clk), | |
3672 | .siclk(siclk), | |
3673 | .soclk(soclk)); | |
3674 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc0_1 | |
3675 | ( | |
3676 | .scan_in(sync_ff_clk_stop_spc0_1_scanin), | |
3677 | .scan_out(sync_ff_clk_stop_spc0_1_scanout), | |
3678 | .din (~spc0_clk_stop), | |
3679 | .dout (spc0_stopped_l), | |
3680 | .l1clk (l1clk), | |
3681 | .siclk(siclk), | |
3682 | .soclk(soclk)); | |
3683 | assign spc0_clk_stop_sync = ~spc0_clk_stop_sync_l; | |
3684 | assign spc0_stopped = ~spc0_stopped_l; | |
3685 | // ******** sync spc1 clk stop ******************* | |
3686 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc1_0 | |
3687 | ( | |
3688 | .scan_in(sync_ff_clk_stop_spc1_0_scanin), | |
3689 | .scan_out(sync_ff_clk_stop_spc1_0_scanout), | |
3690 | .din (~spc1_clk_stop_presync), | |
3691 | .dout (spc1_clk_stop_sync_l), | |
3692 | .l1clk (l1clk), | |
3693 | .siclk(siclk), | |
3694 | .soclk(soclk)); | |
3695 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc1_1 | |
3696 | ( | |
3697 | .scan_in(sync_ff_clk_stop_spc1_1_scanin), | |
3698 | .scan_out(sync_ff_clk_stop_spc1_1_scanout), | |
3699 | .din (~spc1_clk_stop), | |
3700 | .dout (spc1_stopped_l), | |
3701 | .l1clk (l1clk), | |
3702 | .siclk(siclk), | |
3703 | .soclk(soclk)); | |
3704 | assign spc1_clk_stop_sync = ~spc1_clk_stop_sync_l; | |
3705 | assign spc1_stopped = ~spc1_stopped_l; | |
3706 | // ******** sync spc2 clk stop ******************* | |
3707 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc2_0 | |
3708 | ( | |
3709 | .scan_in(sync_ff_clk_stop_spc2_0_scanin), | |
3710 | .scan_out(sync_ff_clk_stop_spc2_0_scanout), | |
3711 | .din (~spc2_clk_stop_presync), | |
3712 | .dout (spc2_clk_stop_sync_l), | |
3713 | .l1clk (l1clk), | |
3714 | .siclk(siclk), | |
3715 | .soclk(soclk)); | |
3716 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc2_1 | |
3717 | ( | |
3718 | .scan_in(sync_ff_clk_stop_spc2_1_scanin), | |
3719 | .scan_out(sync_ff_clk_stop_spc2_1_scanout), | |
3720 | .din (~spc2_clk_stop), | |
3721 | .dout (spc2_stopped_l), | |
3722 | .l1clk (l1clk), | |
3723 | .siclk(siclk), | |
3724 | .soclk(soclk)); | |
3725 | assign spc2_clk_stop_sync = ~spc2_clk_stop_sync_l; | |
3726 | assign spc2_stopped = ~spc2_stopped_l; | |
3727 | // ******** sync spc3_clk stop ******************* | |
3728 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc3_0 | |
3729 | ( | |
3730 | .scan_in(sync_ff_clk_stop_spc3_0_scanin), | |
3731 | .scan_out(sync_ff_clk_stop_spc3_0_scanout), | |
3732 | .din (~spc3_clk_stop_presync), | |
3733 | .dout (spc3_clk_stop_sync_l), | |
3734 | .l1clk (l1clk), | |
3735 | .siclk(siclk), | |
3736 | .soclk(soclk)); | |
3737 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc3_1 | |
3738 | ( | |
3739 | .scan_in(sync_ff_clk_stop_spc3_1_scanin), | |
3740 | .scan_out(sync_ff_clk_stop_spc3_1_scanout), | |
3741 | .din (~spc3_clk_stop), | |
3742 | .dout (spc3_stopped_l), | |
3743 | .l1clk (l1clk), | |
3744 | .siclk(siclk), | |
3745 | .soclk(soclk)); | |
3746 | assign spc3_clk_stop_sync = ~spc3_clk_stop_sync_l; | |
3747 | assign spc3_stopped = ~spc3_stopped_l; | |
3748 | // ******** sync spc4_clk stop ******************* | |
3749 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc4_0 | |
3750 | ( | |
3751 | .scan_in(sync_ff_clk_stop_spc4_0_scanin), | |
3752 | .scan_out(sync_ff_clk_stop_spc4_0_scanout), | |
3753 | .din (~spc4_clk_stop_presync), | |
3754 | .dout (spc4_clk_stop_sync_l), | |
3755 | .l1clk (l1clk), | |
3756 | .siclk(siclk), | |
3757 | .soclk(soclk)); | |
3758 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc4_1 | |
3759 | ( | |
3760 | .scan_in(sync_ff_clk_stop_spc4_1_scanin), | |
3761 | .scan_out(sync_ff_clk_stop_spc4_1_scanout), | |
3762 | .din (~spc4_clk_stop), | |
3763 | .dout (spc4_stopped_l), | |
3764 | .l1clk (l1clk), | |
3765 | .siclk(siclk), | |
3766 | .soclk(soclk)); | |
3767 | assign spc4_clk_stop_sync = ~spc4_clk_stop_sync_l; | |
3768 | assign spc4_stopped = ~spc4_stopped_l; | |
3769 | // ******** sync spc5_clk stop ******************* | |
3770 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc5_0 | |
3771 | ( | |
3772 | .scan_in(sync_ff_clk_stop_spc5_0_scanin), | |
3773 | .scan_out(sync_ff_clk_stop_spc5_0_scanout), | |
3774 | .din (~spc5_clk_stop_presync), | |
3775 | .dout (spc5_clk_stop_sync_l), | |
3776 | .l1clk (l1clk), | |
3777 | .siclk(siclk), | |
3778 | .soclk(soclk)); | |
3779 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc5_1 | |
3780 | ( | |
3781 | .scan_in(sync_ff_clk_stop_spc5_1_scanin), | |
3782 | .scan_out(sync_ff_clk_stop_spc5_1_scanout), | |
3783 | .din (~spc5_clk_stop), | |
3784 | .dout (spc5_stopped_l), | |
3785 | .l1clk (l1clk), | |
3786 | .siclk(siclk), | |
3787 | .soclk(soclk)); | |
3788 | assign spc5_clk_stop_sync = ~spc5_clk_stop_sync_l; | |
3789 | assign spc5_stopped = ~spc5_stopped_l; | |
3790 | // ******** sync spc6_clk stop ******************* | |
3791 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc6_0 | |
3792 | ( | |
3793 | .scan_in(sync_ff_clk_stop_spc6_0_scanin), | |
3794 | .scan_out(sync_ff_clk_stop_spc6_0_scanout), | |
3795 | .din (~spc6_clk_stop_presync), | |
3796 | .dout (spc6_clk_stop_sync_l), | |
3797 | .l1clk (l1clk), | |
3798 | .siclk(siclk), | |
3799 | .soclk(soclk)); | |
3800 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc6_1 | |
3801 | ( | |
3802 | .scan_in(sync_ff_clk_stop_spc6_1_scanin), | |
3803 | .scan_out(sync_ff_clk_stop_spc6_1_scanout), | |
3804 | .din (~spc6_clk_stop), | |
3805 | .dout (spc6_stopped_l), | |
3806 | .l1clk (l1clk), | |
3807 | .siclk(siclk), | |
3808 | .soclk(soclk)); | |
3809 | assign spc6_clk_stop_sync = ~spc6_clk_stop_sync_l; | |
3810 | assign spc6_stopped = ~spc6_stopped_l; | |
3811 | // ******** sync spc7_clk stop ******************* | |
3812 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc7_0 | |
3813 | ( | |
3814 | .scan_in(sync_ff_clk_stop_spc7_0_scanin), | |
3815 | .scan_out(sync_ff_clk_stop_spc7_0_scanout), | |
3816 | .din (~spc7_clk_stop_presync), | |
3817 | .dout (spc7_clk_stop_sync_l), | |
3818 | .l1clk (l1clk), | |
3819 | .siclk(siclk), | |
3820 | .soclk(soclk)); | |
3821 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_spc7_1 | |
3822 | ( | |
3823 | .scan_in(sync_ff_clk_stop_spc7_1_scanin), | |
3824 | .scan_out(sync_ff_clk_stop_spc7_1_scanout), | |
3825 | .din (~spc7_clk_stop), | |
3826 | .dout (spc7_stopped_l), | |
3827 | .l1clk (l1clk), | |
3828 | .siclk(siclk), | |
3829 | .soclk(soclk)); | |
3830 | assign spc7_clk_stop_sync = ~spc7_clk_stop_sync_l; | |
3831 | assign spc7_stopped = ~spc7_stopped_l; | |
3832 | // ******** sync bnk0_clk stop ******************* | |
3833 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk0_0 | |
3834 | ( | |
3835 | .scan_in(sync_ff_clk_stop_bnk0_0_scanin), | |
3836 | .scan_out(sync_ff_clk_stop_bnk0_0_scanout), | |
3837 | .din (~bnk0_clk_stop_presync), | |
3838 | .dout (bnk0_clk_stop_sync_l), | |
3839 | .l1clk (l1clk), | |
3840 | .siclk(siclk), | |
3841 | .soclk(soclk)); | |
3842 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk0_1 | |
3843 | ( | |
3844 | .scan_in(sync_ff_clk_stop_bnk0_1_scanin), | |
3845 | .scan_out(sync_ff_clk_stop_bnk0_1_scanout), | |
3846 | .din (~bnk0_clk_stop), | |
3847 | .dout (bnk0_stopped_l), | |
3848 | .l1clk (l1clk), | |
3849 | .siclk(siclk), | |
3850 | .soclk(soclk)); | |
3851 | assign bnk0_clk_stop_sync = ~bnk0_clk_stop_sync_l; | |
3852 | assign bnk0_stopped = ~bnk0_stopped_l; | |
3853 | // ******** sync l2t0_clk stop ******************* | |
3854 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t0_0 | |
3855 | ( | |
3856 | .scan_in(sync_ff_clk_stop_l2t0_0_scanin), | |
3857 | .scan_out(sync_ff_clk_stop_l2t0_0_scanout), | |
3858 | .din (~l2t0_clk_stop_presync), | |
3859 | .dout (l2t0_clk_stop_sync_l), | |
3860 | .l1clk (l1clk), | |
3861 | .siclk(siclk), | |
3862 | .soclk(soclk)); | |
3863 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t0_1 | |
3864 | ( | |
3865 | .scan_in(sync_ff_clk_stop_l2t0_1_scanin), | |
3866 | .scan_out(sync_ff_clk_stop_l2t0_1_scanout), | |
3867 | .din (~l2t0_clk_stop), | |
3868 | .dout (l2t0_stopped_l), | |
3869 | .l1clk (l1clk), | |
3870 | .siclk(siclk), | |
3871 | .soclk(soclk)); | |
3872 | assign l2t0_clk_stop_sync = ~l2t0_clk_stop_sync_l; | |
3873 | assign l2t0_stopped = ~l2t0_stopped_l; | |
3874 | // ******** sync bnk1_clk stop ******************* | |
3875 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk1_0 | |
3876 | ( | |
3877 | .scan_in(sync_ff_clk_stop_bnk1_0_scanin), | |
3878 | .scan_out(sync_ff_clk_stop_bnk1_0_scanout), | |
3879 | .din (~bnk1_clk_stop_presync), | |
3880 | .dout (bnk1_clk_stop_sync_l), | |
3881 | .l1clk (l1clk), | |
3882 | .siclk(siclk), | |
3883 | .soclk(soclk)); | |
3884 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk1_1 | |
3885 | ( | |
3886 | .scan_in(sync_ff_clk_stop_bnk1_1_scanin), | |
3887 | .scan_out(sync_ff_clk_stop_bnk1_1_scanout), | |
3888 | .din (~bnk1_clk_stop), | |
3889 | .dout (bnk1_stopped_l), | |
3890 | .l1clk (l1clk), | |
3891 | .siclk(siclk), | |
3892 | .soclk(soclk)); | |
3893 | assign bnk1_clk_stop_sync = ~bnk1_clk_stop_sync_l; | |
3894 | assign bnk1_stopped = ~bnk1_stopped_l; | |
3895 | // ******** sync l2t1_clk stop ******************* | |
3896 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t1_0 | |
3897 | ( | |
3898 | .scan_in(sync_ff_clk_stop_l2t1_0_scanin), | |
3899 | .scan_out(sync_ff_clk_stop_l2t1_0_scanout), | |
3900 | .din (~l2t1_clk_stop_presync), | |
3901 | .dout (l2t1_clk_stop_sync_l), | |
3902 | .l1clk (l1clk), | |
3903 | .siclk(siclk), | |
3904 | .soclk(soclk)); | |
3905 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t1_1 | |
3906 | ( | |
3907 | .scan_in(sync_ff_clk_stop_l2t1_1_scanin), | |
3908 | .scan_out(sync_ff_clk_stop_l2t1_1_scanout), | |
3909 | .din (~l2t1_clk_stop), | |
3910 | .dout (l2t1_stopped_l), | |
3911 | .l1clk (l1clk), | |
3912 | .siclk(siclk), | |
3913 | .soclk(soclk)); | |
3914 | assign l2t1_clk_stop_sync = ~l2t1_clk_stop_sync_l; | |
3915 | assign l2t1_stopped = ~l2t1_stopped_l; | |
3916 | // ******** sync bnk2_clk stop ******************* | |
3917 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk2_0 | |
3918 | ( | |
3919 | .scan_in(sync_ff_clk_stop_bnk2_0_scanin), | |
3920 | .scan_out(sync_ff_clk_stop_bnk2_0_scanout), | |
3921 | .din (~bnk2_clk_stop_presync), | |
3922 | .dout (bnk2_clk_stop_sync_l), | |
3923 | .l1clk (l1clk), | |
3924 | .siclk(siclk), | |
3925 | .soclk(soclk)); | |
3926 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk2_1 | |
3927 | ( | |
3928 | .scan_in(sync_ff_clk_stop_bnk2_1_scanin), | |
3929 | .scan_out(sync_ff_clk_stop_bnk2_1_scanout), | |
3930 | .din (~bnk2_clk_stop), | |
3931 | .dout (bnk2_stopped_l), | |
3932 | .l1clk (l1clk), | |
3933 | .siclk(siclk), | |
3934 | .soclk(soclk)); | |
3935 | assign bnk2_clk_stop_sync = ~bnk2_clk_stop_sync_l; | |
3936 | assign bnk2_stopped = ~bnk2_stopped_l; | |
3937 | // ******** sync l2t2_clk stop ******************* | |
3938 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t2_0 | |
3939 | ( | |
3940 | .scan_in(sync_ff_clk_stop_l2t2_0_scanin), | |
3941 | .scan_out(sync_ff_clk_stop_l2t2_0_scanout), | |
3942 | .din (~l2t2_clk_stop_presync), | |
3943 | .dout (l2t2_clk_stop_sync_l), | |
3944 | .l1clk (l1clk), | |
3945 | .siclk(siclk), | |
3946 | .soclk(soclk)); | |
3947 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t2_1 | |
3948 | ( | |
3949 | .scan_in(sync_ff_clk_stop_l2t2_1_scanin), | |
3950 | .scan_out(sync_ff_clk_stop_l2t2_1_scanout), | |
3951 | .din (~l2t2_clk_stop), | |
3952 | .dout (l2t2_stopped_l), | |
3953 | .l1clk (l1clk), | |
3954 | .siclk(siclk), | |
3955 | .soclk(soclk)); | |
3956 | assign l2t2_clk_stop_sync = ~l2t2_clk_stop_sync_l; | |
3957 | assign l2t2_stopped = ~l2t2_stopped_l; | |
3958 | // ******** sync bnk3_clk stop ******************* | |
3959 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk3_0 | |
3960 | ( | |
3961 | .scan_in(sync_ff_clk_stop_bnk3_0_scanin), | |
3962 | .scan_out(sync_ff_clk_stop_bnk3_0_scanout), | |
3963 | .din (~bnk3_clk_stop_presync), | |
3964 | .dout (bnk3_clk_stop_sync_l), | |
3965 | .l1clk (l1clk), | |
3966 | .siclk(siclk), | |
3967 | .soclk(soclk)); | |
3968 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk3_1 | |
3969 | ( | |
3970 | .scan_in(sync_ff_clk_stop_bnk3_1_scanin), | |
3971 | .scan_out(sync_ff_clk_stop_bnk3_1_scanout), | |
3972 | .din (~bnk3_clk_stop), | |
3973 | .dout (bnk3_stopped_l), | |
3974 | .l1clk (l1clk), | |
3975 | .siclk(siclk), | |
3976 | .soclk(soclk)); | |
3977 | assign bnk3_clk_stop_sync = ~bnk3_clk_stop_sync_l; | |
3978 | assign bnk3_stopped = ~bnk3_stopped_l; | |
3979 | // ******** sync l2t3_clk stop ******************* | |
3980 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t3_0 | |
3981 | ( | |
3982 | .scan_in(sync_ff_clk_stop_l2t3_0_scanin), | |
3983 | .scan_out(sync_ff_clk_stop_l2t3_0_scanout), | |
3984 | .din (~l2t3_clk_stop_presync), | |
3985 | .dout (l2t3_clk_stop_sync_l), | |
3986 | .l1clk (l1clk), | |
3987 | .siclk(siclk), | |
3988 | .soclk(soclk)); | |
3989 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t3_1 | |
3990 | ( | |
3991 | .scan_in(sync_ff_clk_stop_l2t3_1_scanin), | |
3992 | .scan_out(sync_ff_clk_stop_l2t3_1_scanout), | |
3993 | .din (~l2t3_clk_stop), | |
3994 | .dout (l2t3_stopped_l), | |
3995 | .l1clk (l1clk), | |
3996 | .siclk(siclk), | |
3997 | .soclk(soclk)); | |
3998 | assign l2t3_clk_stop_sync = ~l2t3_clk_stop_sync_l; | |
3999 | assign l2t3_stopped = ~l2t3_stopped_l; | |
4000 | // ******** sync bnk4_clk stop ******************* | |
4001 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk4_0 | |
4002 | ( | |
4003 | .scan_in(sync_ff_clk_stop_bnk4_0_scanin), | |
4004 | .scan_out(sync_ff_clk_stop_bnk4_0_scanout), | |
4005 | .din (~bnk4_clk_stop_presync), | |
4006 | .dout (bnk4_clk_stop_sync_l), | |
4007 | .l1clk (l1clk), | |
4008 | .siclk(siclk), | |
4009 | .soclk(soclk)); | |
4010 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk4_1 | |
4011 | ( | |
4012 | .scan_in(sync_ff_clk_stop_bnk4_1_scanin), | |
4013 | .scan_out(sync_ff_clk_stop_bnk4_1_scanout), | |
4014 | .din (~bnk4_clk_stop), | |
4015 | .dout (bnk4_stopped_l), | |
4016 | .l1clk (l1clk), | |
4017 | .siclk(siclk), | |
4018 | .soclk(soclk)); | |
4019 | assign bnk4_clk_stop_sync = ~bnk4_clk_stop_sync_l; | |
4020 | assign bnk4_stopped = ~bnk4_stopped_l; | |
4021 | // ******** sync l2t4_clk stop ******************* | |
4022 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t4_0 | |
4023 | ( | |
4024 | .scan_in(sync_ff_clk_stop_l2t4_0_scanin), | |
4025 | .scan_out(sync_ff_clk_stop_l2t4_0_scanout), | |
4026 | .din (~l2t4_clk_stop_presync), | |
4027 | .dout (l2t4_clk_stop_sync_l), | |
4028 | .l1clk (l1clk), | |
4029 | .siclk(siclk), | |
4030 | .soclk(soclk)); | |
4031 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t4_1 | |
4032 | ( | |
4033 | .scan_in(sync_ff_clk_stop_l2t4_1_scanin), | |
4034 | .scan_out(sync_ff_clk_stop_l2t4_1_scanout), | |
4035 | .din (~l2t4_clk_stop), | |
4036 | .dout (l2t4_stopped_l), | |
4037 | .l1clk (l1clk), | |
4038 | .siclk(siclk), | |
4039 | .soclk(soclk)); | |
4040 | assign l2t4_clk_stop_sync = ~l2t4_clk_stop_sync_l; | |
4041 | assign l2t4_stopped = ~l2t4_stopped_l; | |
4042 | // ******** sync bnk5_clk stop ******************* | |
4043 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk5_0 | |
4044 | ( | |
4045 | .scan_in(sync_ff_clk_stop_bnk5_0_scanin), | |
4046 | .scan_out(sync_ff_clk_stop_bnk5_0_scanout), | |
4047 | .din (~bnk5_clk_stop_presync), | |
4048 | .dout (bnk5_clk_stop_sync_l), | |
4049 | .l1clk (l1clk), | |
4050 | .siclk(siclk), | |
4051 | .soclk(soclk)); | |
4052 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk5_1 | |
4053 | ( | |
4054 | .scan_in(sync_ff_clk_stop_bnk5_1_scanin), | |
4055 | .scan_out(sync_ff_clk_stop_bnk5_1_scanout), | |
4056 | .din (~bnk5_clk_stop), | |
4057 | .dout (bnk5_stopped_l), | |
4058 | .l1clk (l1clk), | |
4059 | .siclk(siclk), | |
4060 | .soclk(soclk)); | |
4061 | assign bnk5_clk_stop_sync = ~bnk5_clk_stop_sync_l; | |
4062 | assign bnk5_stopped = ~bnk5_stopped_l; | |
4063 | // ******** sync l2t5_clk stop ******************* | |
4064 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t5_0 | |
4065 | ( | |
4066 | .scan_in(sync_ff_clk_stop_l2t5_0_scanin), | |
4067 | .scan_out(sync_ff_clk_stop_l2t5_0_scanout), | |
4068 | .din (~l2t5_clk_stop_presync), | |
4069 | .dout (l2t5_clk_stop_sync_l), | |
4070 | .l1clk (l1clk), | |
4071 | .siclk(siclk), | |
4072 | .soclk(soclk)); | |
4073 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t5_1 | |
4074 | ( | |
4075 | .scan_in(sync_ff_clk_stop_l2t5_1_scanin), | |
4076 | .scan_out(sync_ff_clk_stop_l2t5_1_scanout), | |
4077 | .din (~l2t5_clk_stop), | |
4078 | .dout (l2t5_stopped_l), | |
4079 | .l1clk (l1clk), | |
4080 | .siclk(siclk), | |
4081 | .soclk(soclk)); | |
4082 | assign l2t5_clk_stop_sync = ~l2t5_clk_stop_sync_l; | |
4083 | assign l2t5_stopped = ~l2t5_stopped_l; | |
4084 | // ******** sync bnk6_clk stop ******************* | |
4085 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk6_0 | |
4086 | ( | |
4087 | .scan_in(sync_ff_clk_stop_bnk6_0_scanin), | |
4088 | .scan_out(sync_ff_clk_stop_bnk6_0_scanout), | |
4089 | .din (~bnk6_clk_stop_presync), | |
4090 | .dout (bnk6_clk_stop_sync_l), | |
4091 | .l1clk (l1clk), | |
4092 | .siclk(siclk), | |
4093 | .soclk(soclk)); | |
4094 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk6_1 | |
4095 | ( | |
4096 | .scan_in(sync_ff_clk_stop_bnk6_1_scanin), | |
4097 | .scan_out(sync_ff_clk_stop_bnk6_1_scanout), | |
4098 | .din (~bnk6_clk_stop), | |
4099 | .dout (bnk6_stopped_l), | |
4100 | .l1clk (l1clk), | |
4101 | .siclk(siclk), | |
4102 | .soclk(soclk)); | |
4103 | assign bnk6_clk_stop_sync = ~bnk6_clk_stop_sync_l; | |
4104 | assign bnk6_stopped = ~bnk6_stopped_l; | |
4105 | // ******** sync l2t6_clk stop ******************* | |
4106 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t6_0 | |
4107 | ( | |
4108 | .scan_in(sync_ff_clk_stop_l2t6_0_scanin), | |
4109 | .scan_out(sync_ff_clk_stop_l2t6_0_scanout), | |
4110 | .din (~l2t6_clk_stop_presync), | |
4111 | .dout (l2t6_clk_stop_sync_l), | |
4112 | .l1clk (l1clk), | |
4113 | .siclk(siclk), | |
4114 | .soclk(soclk)); | |
4115 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t6_1 | |
4116 | ( | |
4117 | .scan_in(sync_ff_clk_stop_l2t6_1_scanin), | |
4118 | .scan_out(sync_ff_clk_stop_l2t6_1_scanout), | |
4119 | .din (~l2t6_clk_stop), | |
4120 | .dout (l2t6_stopped_l), | |
4121 | .l1clk (l1clk), | |
4122 | .siclk(siclk), | |
4123 | .soclk(soclk)); | |
4124 | assign l2t6_clk_stop_sync = ~l2t6_clk_stop_sync_l; | |
4125 | assign l2t6_stopped = ~l2t6_stopped_l; | |
4126 | // ******** sync bnk7_clk stop ******************* | |
4127 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk7_0 | |
4128 | ( | |
4129 | .scan_in(sync_ff_clk_stop_bnk7_0_scanin), | |
4130 | .scan_out(sync_ff_clk_stop_bnk7_0_scanout), | |
4131 | .din (~bnk7_clk_stop_presync), | |
4132 | .dout (bnk7_clk_stop_sync_l), | |
4133 | .l1clk (l1clk), | |
4134 | .siclk(siclk), | |
4135 | .soclk(soclk)); | |
4136 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_bnk7_1 | |
4137 | ( | |
4138 | .scan_in(sync_ff_clk_stop_bnk7_1_scanin), | |
4139 | .scan_out(sync_ff_clk_stop_bnk7_1_scanout), | |
4140 | .din (~bnk7_clk_stop), | |
4141 | .dout (bnk7_stopped_l), | |
4142 | .l1clk (l1clk), | |
4143 | .siclk(siclk), | |
4144 | .soclk(soclk)); | |
4145 | assign bnk7_clk_stop_sync = ~bnk7_clk_stop_sync_l; | |
4146 | assign bnk7_stopped = ~bnk7_stopped_l; | |
4147 | // ******** sync l2t7_clk stop ******************* | |
4148 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t7_0 | |
4149 | ( | |
4150 | .scan_in(sync_ff_clk_stop_l2t7_0_scanin), | |
4151 | .scan_out(sync_ff_clk_stop_l2t7_0_scanout), | |
4152 | .din (~l2t7_clk_stop_presync), | |
4153 | .dout (l2t7_clk_stop_sync_l), | |
4154 | .l1clk (l1clk), | |
4155 | .siclk(siclk), | |
4156 | .soclk(soclk)); | |
4157 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_l2t7_1 | |
4158 | ( | |
4159 | .scan_in(sync_ff_clk_stop_l2t7_1_scanin), | |
4160 | .scan_out(sync_ff_clk_stop_l2t7_1_scanout), | |
4161 | .din (~l2t7_clk_stop), | |
4162 | .dout (l2t7_stopped_l), | |
4163 | .l1clk (l1clk), | |
4164 | .siclk(siclk), | |
4165 | .soclk(soclk)); | |
4166 | assign l2t7_clk_stop_sync = ~l2t7_clk_stop_sync_l; | |
4167 | assign l2t7_stopped = ~l2t7_stopped_l; | |
4168 | // ******** sync mcu0_clk stop ******************* | |
4169 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu0_0 | |
4170 | ( | |
4171 | .scan_in(sync_ff_clk_stop_mcu0_0_scanin), | |
4172 | .scan_out(sync_ff_clk_stop_mcu0_0_scanout), | |
4173 | .din (~mcu0_clk_stop_presync), | |
4174 | .dout (mcu0_clk_stop_sync_l), | |
4175 | .l1clk (l1clk), | |
4176 | .siclk(siclk), | |
4177 | .soclk(soclk)); | |
4178 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu0_1 | |
4179 | ( | |
4180 | .scan_in(sync_ff_clk_stop_mcu0_1_scanin), | |
4181 | .scan_out(sync_ff_clk_stop_mcu0_1_scanout), | |
4182 | .din (mcu0_cmp_clk_stop_l), | |
4183 | .dout (mcu0_stopped_l), | |
4184 | .l1clk (l1clk), | |
4185 | .siclk(siclk), | |
4186 | .soclk(soclk)); | |
4187 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_mcu0_1 | |
4188 | ( // io clock domain | |
4189 | .scan_in(sync_ff_ioclk_stop_mcu0_1_scanin), | |
4190 | .scan_out(sync_ff_ioclk_stop_mcu0_1_scanout), | |
4191 | .en (cmp_io_sync_en_local), | |
4192 | .din (mcu0_io_clk_stop_l), | |
4193 | .dout (mcu0_io_stopped_l), | |
4194 | .l1clk (l1clk), | |
4195 | .siclk(siclk), | |
4196 | .soclk(soclk)); | |
4197 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_drclk_stop_mcu0_1 //,en=1) | |
4198 | ( // dr clock domain | |
4199 | .scan_in(sync_ff_drclk_stop_mcu0_1_scanin), | |
4200 | .scan_out(sync_ff_drclk_stop_mcu0_1_scanout), | |
4201 | //.en (cmp_dr_sync_en_local), | |
4202 | .din (mcu0_dr_clk_stop_l), | |
4203 | .dout (mcu0_dr_stopped_l), | |
4204 | .l1clk (l1clk), | |
4205 | .siclk(siclk), | |
4206 | .soclk(soclk)); | |
4207 | ||
4208 | assign mcu0_cmp_clk_stop_l = ~( tt_cmp_mode | mcu0_clk_stop ); | |
4209 | assign mcu0_io_clk_stop_l = ~( tt_io_mode | mcu0_clk_stop ); | |
4210 | assign mcu0_dr_clk_stop_l = ~( tt_dr_mode | mcu0_clk_stop ); | |
4211 | ||
4212 | assign mcu0_clk_stop_sync = ~mcu0_clk_stop_sync_l; | |
4213 | assign mcu0_stopped = ~mcu0_stopped_l; | |
4214 | assign mcu0_io_stopped = ~mcu0_io_stopped_l; | |
4215 | assign mcu0_dr_stopped = ~mcu0_dr_stopped_l; | |
4216 | assign mcu0_stopped_tt = tt_io_clk ? mcu0_io_stopped : mcu0_stopped; | |
4217 | // ******** sync mcu1_clk stop ******************* | |
4218 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu1_0 | |
4219 | ( | |
4220 | .scan_in(sync_ff_clk_stop_mcu1_0_scanin), | |
4221 | .scan_out(sync_ff_clk_stop_mcu1_0_scanout), | |
4222 | .din (~mcu1_clk_stop_presync), | |
4223 | .dout (mcu1_clk_stop_sync_l), | |
4224 | .l1clk (l1clk), | |
4225 | .siclk(siclk), | |
4226 | .soclk(soclk)); | |
4227 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu1_1 | |
4228 | ( | |
4229 | .scan_in(sync_ff_clk_stop_mcu1_1_scanin), | |
4230 | .scan_out(sync_ff_clk_stop_mcu1_1_scanout), | |
4231 | .din (mcu1_cmp_clk_stop_l), | |
4232 | .dout (mcu1_stopped_l), | |
4233 | .l1clk (l1clk), | |
4234 | .siclk(siclk), | |
4235 | .soclk(soclk)); | |
4236 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_mcu1_1 | |
4237 | ( // io clock domain | |
4238 | .scan_in(sync_ff_ioclk_stop_mcu1_1_scanin), | |
4239 | .scan_out(sync_ff_ioclk_stop_mcu1_1_scanout), | |
4240 | .en (cmp_io_sync_en_local), | |
4241 | .din (mcu1_io_clk_stop_l), | |
4242 | .dout (mcu1_io_stopped_l), | |
4243 | .l1clk (l1clk), | |
4244 | .siclk(siclk), | |
4245 | .soclk(soclk)); | |
4246 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_drclk_stop_mcu1_1 //,en=1) | |
4247 | ( // dr clock domain | |
4248 | .scan_in(sync_ff_drclk_stop_mcu1_1_scanin), | |
4249 | .scan_out(sync_ff_drclk_stop_mcu1_1_scanout), | |
4250 | //.en (cmp_dr_sync_en_local), | |
4251 | .din (mcu1_dr_clk_stop_l), | |
4252 | .dout (mcu1_dr_stopped_l), | |
4253 | .l1clk (l1clk), | |
4254 | .siclk(siclk), | |
4255 | .soclk(soclk)); | |
4256 | ||
4257 | assign mcu1_cmp_clk_stop_l = ~( tt_cmp_mode | mcu1_clk_stop ); | |
4258 | assign mcu1_io_clk_stop_l = ~( tt_io_mode | mcu1_clk_stop ); | |
4259 | assign mcu1_dr_clk_stop_l = ~( tt_dr_mode | mcu1_clk_stop ); | |
4260 | ||
4261 | assign mcu1_clk_stop_sync = ~mcu1_clk_stop_sync_l; | |
4262 | assign mcu1_stopped = ~mcu1_stopped_l; | |
4263 | assign mcu1_io_stopped = ~mcu1_io_stopped_l; | |
4264 | assign mcu1_dr_stopped = ~mcu1_dr_stopped_l; | |
4265 | assign mcu1_stopped_tt = tt_io_clk ? mcu1_io_stopped : mcu1_stopped; | |
4266 | // ******** sync mcu2_clk stop ******************* | |
4267 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu2_0 | |
4268 | ( | |
4269 | .scan_in(sync_ff_clk_stop_mcu2_0_scanin), | |
4270 | .scan_out(sync_ff_clk_stop_mcu2_0_scanout), | |
4271 | .din (~mcu2_clk_stop_presync), | |
4272 | .dout (mcu2_clk_stop_sync_l), | |
4273 | .l1clk (l1clk), | |
4274 | .siclk(siclk), | |
4275 | .soclk(soclk)); | |
4276 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu2_1 | |
4277 | ( | |
4278 | .scan_in(sync_ff_clk_stop_mcu2_1_scanin), | |
4279 | .scan_out(sync_ff_clk_stop_mcu2_1_scanout), | |
4280 | .din (mcu2_cmp_clk_stop_l), | |
4281 | .dout (mcu2_stopped_l), | |
4282 | .l1clk (l1clk), | |
4283 | .siclk(siclk), | |
4284 | .soclk(soclk)); | |
4285 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_mcu2_1 | |
4286 | ( // io clock domain | |
4287 | .scan_in(sync_ff_ioclk_stop_mcu2_1_scanin), | |
4288 | .scan_out(sync_ff_ioclk_stop_mcu2_1_scanout), | |
4289 | .en (cmp_io_sync_en_local), | |
4290 | .din (mcu2_io_clk_stop_l), | |
4291 | .dout (mcu2_io_stopped_l), | |
4292 | .l1clk (l1clk), | |
4293 | .siclk(siclk), | |
4294 | .soclk(soclk)); | |
4295 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_drclk_stop_mcu2_1 //,en=1) | |
4296 | ( // dr clock domain | |
4297 | .scan_in(sync_ff_drclk_stop_mcu2_1_scanin), | |
4298 | .scan_out(sync_ff_drclk_stop_mcu2_1_scanout), | |
4299 | //.en (cmp_dr_sync_en_local), | |
4300 | .din (mcu2_dr_clk_stop_l), | |
4301 | .dout (mcu2_dr_stopped_l), | |
4302 | .l1clk (l1clk), | |
4303 | .siclk(siclk), | |
4304 | .soclk(soclk)); | |
4305 | ||
4306 | assign mcu2_cmp_clk_stop_l = ~( tt_cmp_mode | mcu2_clk_stop ); | |
4307 | assign mcu2_io_clk_stop_l = ~( tt_io_mode | mcu2_clk_stop ); | |
4308 | assign mcu2_dr_clk_stop_l = ~( tt_dr_mode | mcu2_clk_stop ); | |
4309 | ||
4310 | assign mcu2_clk_stop_sync = ~mcu2_clk_stop_sync_l; | |
4311 | assign mcu2_stopped = ~mcu2_stopped_l; | |
4312 | assign mcu2_io_stopped = ~mcu2_io_stopped_l; | |
4313 | assign mcu2_dr_stopped = ~mcu2_dr_stopped_l; | |
4314 | assign mcu2_stopped_tt = tt_io_clk ? mcu2_io_stopped : mcu2_stopped; | |
4315 | // ******** sync mcu3_clk stop ******************* | |
4316 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu3_0 | |
4317 | ( | |
4318 | .scan_in(sync_ff_clk_stop_mcu3_0_scanin), | |
4319 | .scan_out(sync_ff_clk_stop_mcu3_0_scanout), | |
4320 | .din (~mcu3_clk_stop_presync), | |
4321 | .dout (mcu3_clk_stop_sync_l), | |
4322 | .l1clk (l1clk), | |
4323 | .siclk(siclk), | |
4324 | .soclk(soclk)); | |
4325 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_mcu3_1 | |
4326 | ( | |
4327 | .scan_in(sync_ff_clk_stop_mcu3_1_scanin), | |
4328 | .scan_out(sync_ff_clk_stop_mcu3_1_scanout), | |
4329 | .din (mcu3_cmp_clk_stop_l), | |
4330 | .dout (mcu3_stopped_l), | |
4331 | .l1clk (l1clk), | |
4332 | .siclk(siclk), | |
4333 | .soclk(soclk)); | |
4334 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_mcu3_1 | |
4335 | ( // io clock domain | |
4336 | .scan_in(sync_ff_ioclk_stop_mcu3_1_scanin), | |
4337 | .scan_out(sync_ff_ioclk_stop_mcu3_1_scanout), | |
4338 | .en (cmp_io_sync_en_local), | |
4339 | .din (mcu3_io_clk_stop_l), | |
4340 | .dout (mcu3_io_stopped_l), | |
4341 | .l1clk (l1clk), | |
4342 | .siclk(siclk), | |
4343 | .soclk(soclk)); | |
4344 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_drclk_stop_mcu3_1 //,en=1) | |
4345 | ( // dr clock domain | |
4346 | .scan_in(sync_ff_drclk_stop_mcu3_1_scanin), | |
4347 | .scan_out(sync_ff_drclk_stop_mcu3_1_scanout), | |
4348 | //.en (cmp_dr_sync_en_local), | |
4349 | .din (mcu3_dr_clk_stop_l), | |
4350 | .dout (mcu3_dr_stopped_l), | |
4351 | .l1clk (l1clk), | |
4352 | .siclk(siclk), | |
4353 | .soclk(soclk)); | |
4354 | ||
4355 | assign mcu3_cmp_clk_stop_l = ~( tt_cmp_mode | mcu3_clk_stop ); | |
4356 | assign mcu3_io_clk_stop_l = ~( tt_io_mode | mcu3_clk_stop ); | |
4357 | assign mcu3_dr_clk_stop_l = ~( tt_dr_mode | mcu3_clk_stop ); | |
4358 | ||
4359 | assign mcu3_clk_stop_sync = ~mcu3_clk_stop_sync_l; | |
4360 | assign mcu3_stopped = ~mcu3_stopped_l; | |
4361 | assign mcu3_io_stopped = ~mcu3_io_stopped_l; | |
4362 | assign mcu3_dr_stopped = ~mcu3_dr_stopped_l; | |
4363 | assign mcu3_stopped_tt = tt_io_clk ? mcu3_io_stopped : mcu3_stopped; | |
4364 | // ******** sync soc0_clk stop ******************* | |
4365 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_soc0_0 | |
4366 | ( | |
4367 | .scan_in(sync_ff_clk_stop_soc0_0_scanin), | |
4368 | .scan_out(sync_ff_clk_stop_soc0_0_scanout), | |
4369 | .din (~soc0_clk_stop_presync), | |
4370 | .dout (soc0_clk_stop_sync_l), | |
4371 | .l1clk (l1clk), | |
4372 | .siclk(siclk), | |
4373 | .soclk(soclk)); | |
4374 | assign soc0_clk_stop = tt_hold ? 1'b1 : soc0_clk_stop_sync; | |
4375 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_soc0_1 | |
4376 | ( | |
4377 | .scan_in(sync_ff_clk_stop_soc0_1_scanin), | |
4378 | .scan_out(sync_ff_clk_stop_soc0_1_scanout), | |
4379 | .din (soc0_cmp_clk_stop_l), | |
4380 | .dout (soc0_stopped_l), | |
4381 | .l1clk (l1clk), | |
4382 | .siclk(siclk), | |
4383 | .soclk(soclk)); | |
4384 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_soc0_1 | |
4385 | ( // io clock domain | |
4386 | .scan_in(sync_ff_ioclk_stop_soc0_1_scanin), | |
4387 | .scan_out(sync_ff_ioclk_stop_soc0_1_scanout), | |
4388 | .en (cmp_io_sync_en_local), | |
4389 | .din (soc0_io_clk_stop_l), | |
4390 | .dout (soc0_io_stopped_l), | |
4391 | .l1clk (l1clk), | |
4392 | .siclk(siclk), | |
4393 | .soclk(soclk)); | |
4394 | //msff_ctl_macro sync_ff_drclk_stop_soc0_1 (width=1,en=1) | |
4395 | //( // dr clock domain | |
4396 | // .scan_in(sync_ff_drclk_stop_soc0_1_scanin), | |
4397 | // .scan_out(sync_ff_drclk_stop_soc0_1_scanout), | |
4398 | // .en (cmp_dr_sync_en_local), | |
4399 | // .din (~soc0_clk_stop), | |
4400 | // .dout (soc0_dr_stopped_l), | |
4401 | // .l1clk (l1clk)); | |
4402 | ||
4403 | assign soc0_cmp_clk_stop_l = ~( tt_cmp_mode | soc0_clk_stop ); | |
4404 | assign soc0_io_clk_stop_l = ~( tt_io_mode | soc0_clk_stop ); | |
4405 | ||
4406 | assign soc0_clk_stop_sync = ~soc0_clk_stop_sync_l; | |
4407 | assign soc0_stopped = ~soc0_stopped_l; | |
4408 | assign soc0_io_stopped = ~soc0_io_stopped_l; | |
4409 | //assign soc0_dr_stopped = ~soc0_dr_stopped_l; | |
4410 | assign soc0_stopped_tt = tt_io_clk ? soc0_io_stopped : soc0_stopped; | |
4411 | // ******** sync soc1_clk stop ******************* | |
4412 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_soc1_0 | |
4413 | ( | |
4414 | .scan_in(sync_ff_clk_stop_soc1_0_scanin), | |
4415 | .scan_out(sync_ff_clk_stop_soc1_0_scanout), | |
4416 | .din (~soc1_clk_stop_presync), | |
4417 | .dout (soc1_clk_stop_sync_l), | |
4418 | .l1clk (l1clk), | |
4419 | .siclk(siclk), | |
4420 | .soclk(soclk)); | |
4421 | assign soc1_clk_stop = tt_hold ? 1'b1 : soc1_clk_stop_sync; | |
4422 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_soc1_1 | |
4423 | ( // io clock domain | |
4424 | .scan_in(sync_ff_ioclk_stop_soc1_1_scanin), | |
4425 | .scan_out(sync_ff_ioclk_stop_soc1_1_scanout), | |
4426 | .en (cmp_io_sync_en_local), | |
4427 | .din (soc1_io_clk_stop_l), | |
4428 | .dout (soc1_io_stopped_l), | |
4429 | .l1clk (l1clk), | |
4430 | .siclk(siclk), | |
4431 | .soclk(soclk)); | |
4432 | ||
4433 | assign soc1_io_clk_stop_l = ~( tt_io_mode | soc1_clk_stop ); | |
4434 | ||
4435 | assign soc1_clk_stop_sync = ~soc1_clk_stop_sync_l; | |
4436 | assign soc1_io_stopped = ~soc1_io_stopped_l; | |
4437 | //assign soc1_stopped = soc1_io_stopped; | |
4438 | assign soc1_stopped_tt = tt_io_clk ? soc1_io_stopped : 1'b1; | |
4439 | // ******** sync soc2_clk stop ******************* | |
4440 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_soc2_0 | |
4441 | ( | |
4442 | .scan_in(sync_ff_clk_stop_soc2_0_scanin), | |
4443 | .scan_out(sync_ff_clk_stop_soc2_0_scanout), | |
4444 | .din (~soc2_clk_stop_presync), | |
4445 | .dout (soc2_clk_stop_sync_l), | |
4446 | .l1clk (l1clk), | |
4447 | .siclk(siclk), | |
4448 | .soclk(soclk)); | |
4449 | assign soc2_clk_stop = tt_hold ? 1'b1 : soc2_clk_stop_sync; | |
4450 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_soc2_1 | |
4451 | ( // io clock domain | |
4452 | .scan_in(sync_ff_ioclk_stop_soc2_1_scanin), | |
4453 | .scan_out(sync_ff_ioclk_stop_soc2_1_scanout), | |
4454 | .en (cmp_io_sync_en_local), | |
4455 | .din (soc2_io_clk_stop_l), | |
4456 | .dout (soc2_io_stopped_l), | |
4457 | .l1clk (l1clk), | |
4458 | .siclk(siclk), | |
4459 | .soclk(soclk)); | |
4460 | ||
4461 | assign soc2_io_clk_stop_l = ~( tt_io_mode | soc2_clk_stop ); | |
4462 | ||
4463 | assign soc2_clk_stop_sync = ~soc2_clk_stop_sync_l; | |
4464 | assign soc2_io_stopped = ~soc2_io_stopped_l; | |
4465 | //assign soc2_stopped = soc2_io_stopped; | |
4466 | assign soc2_stopped_tt = tt_io_clk ? soc2_io_stopped : 1'b1; | |
4467 | // ******** sync soc3_clk stop ******************* | |
4468 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_soc3_0 | |
4469 | ( | |
4470 | .scan_in(sync_ff_clk_stop_soc3_0_scanin), | |
4471 | .scan_out(sync_ff_clk_stop_soc3_0_scanout), | |
4472 | .din (~soc3_clk_stop_presync), | |
4473 | .dout (soc3_clk_stop_sync_l), | |
4474 | .l1clk (l1clk), | |
4475 | .siclk(siclk), | |
4476 | .soclk(soclk)); | |
4477 | assign soc3_clk_stop = tt_hold ? 1'b1 : soc3_clk_stop_sync; | |
4478 | tcu_sigmux_ctl_msff_ctl_macro__width_1 sync_ff_clk_stop_soc3_1 | |
4479 | ( | |
4480 | .scan_in(sync_ff_clk_stop_soc3_1_scanin), | |
4481 | .scan_out(sync_ff_clk_stop_soc3_1_scanout), | |
4482 | .din (soc3_cmp_clk_stop_l), | |
4483 | .dout (soc3_stopped_l), | |
4484 | .l1clk (l1clk), | |
4485 | .siclk(siclk), | |
4486 | .soclk(soclk)); | |
4487 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 sync_ff_ioclk_stop_soc3_1 | |
4488 | ( // io clock domain | |
4489 | .scan_in(sync_ff_ioclk_stop_soc3_1_scanin), | |
4490 | .scan_out(sync_ff_ioclk_stop_soc3_1_scanout), | |
4491 | .en (cmp_io_sync_en_local), | |
4492 | .din (soc3_io_clk_stop_l), | |
4493 | .dout (soc3_io_stopped_l), | |
4494 | .l1clk (l1clk), | |
4495 | .siclk(siclk), | |
4496 | .soclk(soclk)); | |
4497 | ||
4498 | assign soc3_cmp_clk_stop_l = ~( tt_cmp_mode | soc3_clk_stop ); | |
4499 | assign soc3_io_clk_stop_l = ~( tt_io_mode | soc3_clk_stop ); | |
4500 | ||
4501 | assign soc3_clk_stop_sync = ~soc3_clk_stop_sync_l; | |
4502 | assign soc3_stopped = ~soc3_stopped_l; | |
4503 | assign soc3_io_stopped = ~soc3_io_stopped_l; | |
4504 | assign soc3_stopped_tt = tt_io_clk ? soc3_io_stopped : soc3_stopped; | |
4505 | ||
4506 | ||
4507 | // ******************************************************************** | |
4508 | // clock domain selection bit for transition test, to select between | |
4509 | // cmp and io domains; set by scan | |
4510 | // ******************************************************************** | |
4511 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_ttclksel_reg | |
4512 | ( | |
4513 | .scan_in(tcusig_ttclksel_reg_scanin), | |
4514 | .scan_out(tcusig_ttclksel_reg_scanout), | |
4515 | .din (tt_io_clk), | |
4516 | .dout (tt_io_clk), | |
4517 | .l1clk (l1clk), | |
4518 | .siclk(siclk), | |
4519 | .soclk(soclk)); | |
4520 | ||
4521 | // ******************************************************************** | |
4522 | //clk_stops going out of TCU; need to gate with core_available for cores | |
4523 | //will have to have local clk stop for jtag mode and such | |
4524 | // ******************************************************************** | |
4525 | //cores | |
4526 | assign pre_spc0_clk_stop = spc0_stopped | clk_stop_ac_trans_counter_initiated | tap_spc0_mb_clk_stop_sync; | |
4527 | assign pre_spc1_clk_stop = spc1_stopped | clk_stop_ac_trans_counter_initiated | tap_spc1_mb_clk_stop_sync; | |
4528 | assign pre_spc2_clk_stop = spc2_stopped | clk_stop_ac_trans_counter_initiated | tap_spc2_mb_clk_stop_sync; | |
4529 | assign pre_spc3_clk_stop = spc3_stopped | clk_stop_ac_trans_counter_initiated | tap_spc3_mb_clk_stop_sync; | |
4530 | assign pre_spc4_clk_stop = spc4_stopped | clk_stop_ac_trans_counter_initiated | tap_spc4_mb_clk_stop_sync; | |
4531 | assign pre_spc5_clk_stop = spc5_stopped | clk_stop_ac_trans_counter_initiated | tap_spc5_mb_clk_stop_sync; | |
4532 | assign pre_spc6_clk_stop = spc6_stopped | clk_stop_ac_trans_counter_initiated | tap_spc6_mb_clk_stop_sync; | |
4533 | assign pre_spc7_clk_stop = spc7_stopped | clk_stop_ac_trans_counter_initiated | tap_spc7_mb_clk_stop_sync; | |
4534 | //soc clk_stops going out of TCU | |
4535 | assign pre_bnk0_clk_stop = bnk0_stopped | clk_stop_ac_trans_counter_initiated | l2b0_mbist_clk_stop_sync; | |
4536 | assign pre_l2t0_clk_stop = l2t0_stopped | clk_stop_ac_trans_counter_initiated | l2t0_mbist_clk_stop_sync; | |
4537 | assign pre_bnk1_clk_stop = bnk1_stopped | clk_stop_ac_trans_counter_initiated | l2b1_mbist_clk_stop_sync; | |
4538 | assign pre_l2t1_clk_stop = l2t1_stopped | clk_stop_ac_trans_counter_initiated | l2t1_mbist_clk_stop_sync; | |
4539 | assign pre_bnk2_clk_stop = bnk2_stopped | clk_stop_ac_trans_counter_initiated | l2b2_mbist_clk_stop_sync; | |
4540 | assign pre_l2t2_clk_stop = l2t2_stopped | clk_stop_ac_trans_counter_initiated | l2t2_mbist_clk_stop_sync; | |
4541 | assign pre_bnk3_clk_stop = bnk3_stopped | clk_stop_ac_trans_counter_initiated | l2b3_mbist_clk_stop_sync; | |
4542 | assign pre_l2t3_clk_stop = l2t3_stopped | clk_stop_ac_trans_counter_initiated | l2t3_mbist_clk_stop_sync; | |
4543 | assign pre_bnk4_clk_stop = bnk4_stopped | clk_stop_ac_trans_counter_initiated | l2b4_mbist_clk_stop_sync; | |
4544 | assign pre_l2t4_clk_stop = l2t4_stopped | clk_stop_ac_trans_counter_initiated | l2t4_mbist_clk_stop_sync; | |
4545 | assign pre_bnk5_clk_stop = bnk5_stopped | clk_stop_ac_trans_counter_initiated | l2b5_mbist_clk_stop_sync; | |
4546 | assign pre_l2t5_clk_stop = l2t5_stopped | clk_stop_ac_trans_counter_initiated | l2t5_mbist_clk_stop_sync; | |
4547 | assign pre_bnk6_clk_stop = bnk6_stopped | clk_stop_ac_trans_counter_initiated | l2b6_mbist_clk_stop_sync; | |
4548 | assign pre_l2t6_clk_stop = l2t6_stopped | clk_stop_ac_trans_counter_initiated | l2t6_mbist_clk_stop_sync; | |
4549 | assign pre_bnk7_clk_stop = bnk7_stopped | clk_stop_ac_trans_counter_initiated | l2b7_mbist_clk_stop_sync; | |
4550 | assign pre_l2t7_clk_stop = l2t7_stopped | clk_stop_ac_trans_counter_initiated | l2t7_mbist_clk_stop_sync; | |
4551 | ||
4552 | assign pre_mcu0_clk_stop = mcu0_stopped | clk_stop_ac_trans_counter_initiated | mcu0_mbist_clk_stop_sync; | |
4553 | assign pre_mcu0_io_clk_stop = mcu0_io_stopped | clk_stop_ac_trans_counter_initiated | mcu0_mbist_clk_stop_sync; | |
4554 | assign pre_mcu0_dr_clk_stop = mcu0_dr_stopped | clk_stop_ac_trans_counter_initiated | mcu0_mbist_clk_stop_sync; | |
4555 | assign pre_mcu0_fbd_clk_stop = (mcu0_io_stopped & ~ac_test_mode & (por_one | por_two | ~mcu0_avail_hold | ~l2bnk_avail[0] | ~l2bnk_avail[1])) | |
4556 | | (pre_mcu0_io_clk_stop & ac_test_mode); | |
4557 | ||
4558 | assign pre_mcu1_clk_stop = mcu1_stopped | clk_stop_ac_trans_counter_initiated | mcu1_mbist_clk_stop_sync; | |
4559 | assign pre_mcu1_io_clk_stop = mcu1_io_stopped | clk_stop_ac_trans_counter_initiated | mcu1_mbist_clk_stop_sync; | |
4560 | assign pre_mcu1_dr_clk_stop = mcu1_dr_stopped | clk_stop_ac_trans_counter_initiated | mcu1_mbist_clk_stop_sync; | |
4561 | assign pre_mcu1_fbd_clk_stop = (mcu1_io_stopped & ~ac_test_mode & (por_one | por_two | ~mcu1_avail_hold | ~l2bnk_avail[2] | ~l2bnk_avail[3])) | |
4562 | | (pre_mcu1_io_clk_stop & ac_test_mode); | |
4563 | ||
4564 | assign pre_mcu2_clk_stop = mcu2_stopped | clk_stop_ac_trans_counter_initiated | mcu2_mbist_clk_stop_sync; | |
4565 | assign pre_mcu2_io_clk_stop = mcu2_io_stopped | clk_stop_ac_trans_counter_initiated | mcu2_mbist_clk_stop_sync; | |
4566 | assign pre_mcu2_dr_clk_stop = mcu2_dr_stopped | clk_stop_ac_trans_counter_initiated | mcu2_mbist_clk_stop_sync; | |
4567 | assign pre_mcu2_fbd_clk_stop = (mcu2_io_stopped & ~ac_test_mode & (por_one | por_two | ~mcu2_avail_hold | ~l2bnk_avail[4] | ~l2bnk_avail[5])) | |
4568 | | (pre_mcu2_io_clk_stop & ac_test_mode); | |
4569 | ||
4570 | assign pre_mcu3_clk_stop = mcu3_stopped | clk_stop_ac_trans_counter_initiated | mcu3_mbist_clk_stop_sync; | |
4571 | assign pre_mcu3_io_clk_stop = mcu3_io_stopped | clk_stop_ac_trans_counter_initiated | mcu3_mbist_clk_stop_sync; | |
4572 | assign pre_mcu3_dr_clk_stop = mcu3_dr_stopped | clk_stop_ac_trans_counter_initiated | mcu3_mbist_clk_stop_sync; | |
4573 | assign pre_mcu3_fbd_clk_stop = (mcu3_io_stopped & ~ac_test_mode & (por_one | por_two | ~mcu3_avail_hold | ~l2bnk_avail[6] | ~l2bnk_avail[7])) | |
4574 | | (pre_mcu3_io_clk_stop & ac_test_mode); | |
4575 | ||
4576 | assign pre_soc0_clk_stop = soc0_stopped | clk_stop_ac_trans_counter_initiated | soc0_mbist_clk_stop_sync; | |
4577 | assign pre_soc0_io_clk_stop = soc0_io_stopped | clk_stop_ac_trans_counter_initiated | soc0_mbist_clk_stop_sync; | |
4578 | ||
4579 | assign pre_soc1_io_clk_stop =(soc1_io_stopped & asic_stop_en) | clk_stop_ac_trans_counter_initiated | asic_por_stop | | |
4580 | rdp_mbist_clk_stop_sync | rtx_mbist_clk_stop_sync | tds_mbist_clk_stop_sync; | |
4581 | assign pre_soc2_io_clk_stop =(soc2_io_stopped & asic_stop_en) | clk_stop_ac_trans_counter_initiated | dmu_mbist_clk_stop_sync | asic_por_stop; | |
4582 | assign pre_soc3_clk_stop =(soc3_stopped & asic_stop_en) | clk_stop_ac_trans_counter_initiated | peu_mbist_clk_stop_sync | asic_por_stop; | |
4583 | assign pre_soc3_io_clk_stop =(soc3_io_stopped & asic_stop_en) | clk_stop_ac_trans_counter_initiated | peu_mbist_clk_stop_sync | asic_por_stop; | |
4584 | ||
4585 | ||
4586 | ||
4587 | ||
4588 | // ******************************************************************** | |
4589 | // MBIST Scan Chain Multiplexing | |
4590 | // ******************************************************************** | |
4591 | // When test_mode=1, put mbist scan chain into core scan chain | |
4592 | // else, put it between tdi and tdo | |
4593 | assign spc0_mb_scan_out = io_test_mode ? pre_tcu_spc0_scan_out[0] | |
4594 | : (~flush_drive_0 & tap_spc0_mb_scan_out); | |
4595 | assign spc0_tap_mb_scan_in = spc0_tcu_mbist_scan_in; | |
4596 | assign tcu_spc0_scan_out[0] = io_test_mode ? spc0_tcu_mbist_scan_in : ser_scan_spc0_ch0; | |
4597 | assign tcu_spc0_mb_scan_out = jt_scan ? jt_scan_in : spc0_mb_scan_out; | |
4598 | assign tcu_spc_lbist_scan_in[0] = (io_test_mode || jt_scan) ? spc0_tcu_scan_in[0] : 1'b0; | |
4599 | ||
4600 | assign spc1_mb_scan_out = io_test_mode ? pre_tcu_spc1_scan_out[0] | |
4601 | : (~flush_drive_0 & tap_spc1_mb_scan_out); | |
4602 | assign spc1_tap_mb_scan_in = spc1_tcu_mbist_scan_in; | |
4603 | assign tcu_spc1_scan_out[0] = io_test_mode ? spc1_tcu_mbist_scan_in : ser_scan_spc1_ch0; | |
4604 | assign tcu_spc1_mb_scan_out = jt_scan ? byp_spc0_ch1_so : spc1_mb_scan_out; | |
4605 | assign tcu_spc_lbist_scan_in[1] = (io_test_mode || jt_scan) ? spc1_tcu_scan_in[0] : 1'b0; | |
4606 | ||
4607 | assign spc2_mb_scan_out = io_test_mode ? pre_tcu_spc2_scan_out[0] | |
4608 | : (~flush_drive_0 & tap_spc2_mb_scan_out); | |
4609 | assign spc2_tap_mb_scan_in = spc2_tcu_mbist_scan_in; | |
4610 | assign tcu_spc2_scan_out[0] = io_test_mode ? spc2_tcu_mbist_scan_in : ser_scan_spc2_ch0; | |
4611 | assign tcu_spc2_mb_scan_out = jt_scan ? byp_spc1_ch1_so : spc2_mb_scan_out; | |
4612 | assign tcu_spc_lbist_scan_in[2] = (io_test_mode || jt_scan) ? spc2_tcu_scan_in[0] : 1'b0; | |
4613 | ||
4614 | assign spc3_mb_scan_out = io_test_mode ? pre_tcu_spc3_scan_out[0] | |
4615 | : (~flush_drive_0 & tap_spc3_mb_scan_out); | |
4616 | assign spc3_tap_mb_scan_in = spc3_tcu_mbist_scan_in; | |
4617 | assign tcu_spc3_scan_out[0] = io_test_mode ? spc3_tcu_mbist_scan_in : ser_scan_spc3_ch0; | |
4618 | assign tcu_spc3_mb_scan_out = jt_scan ? byp_spc2_ch1_so : spc3_mb_scan_out; | |
4619 | assign tcu_spc_lbist_scan_in[3] = (io_test_mode || jt_scan) ? spc3_tcu_scan_in[0] : 1'b0; | |
4620 | ||
4621 | assign spc4_mb_scan_out = io_test_mode ? pre_tcu_spc4_scan_out[0] | |
4622 | : (~flush_drive_0 & tap_spc4_mb_scan_out); | |
4623 | assign spc4_tap_mb_scan_in = spc4_tcu_mbist_scan_in; | |
4624 | assign tcu_spc4_scan_out[0] = io_test_mode ? spc4_tcu_mbist_scan_in : ser_scan_spc4_ch0; | |
4625 | assign tcu_spc4_mb_scan_out = jt_scan ? byp_spc3_ch1_so : spc4_mb_scan_out; | |
4626 | assign tcu_spc_lbist_scan_in[4] = (io_test_mode || jt_scan) ? spc4_tcu_scan_in[0] : 1'b0; | |
4627 | ||
4628 | assign spc5_mb_scan_out = io_test_mode ? pre_tcu_spc5_scan_out[0] | |
4629 | : (~flush_drive_0 & tap_spc5_mb_scan_out); | |
4630 | assign spc5_tap_mb_scan_in = spc5_tcu_mbist_scan_in; | |
4631 | assign tcu_spc5_scan_out[0] = io_test_mode ? spc5_tcu_mbist_scan_in : ser_scan_spc5_ch0; | |
4632 | assign tcu_spc5_mb_scan_out = jt_scan ? byp_spc4_ch1_so : spc5_mb_scan_out; | |
4633 | assign tcu_spc_lbist_scan_in[5] = (io_test_mode || jt_scan) ? spc5_tcu_scan_in[0] : 1'b0; | |
4634 | ||
4635 | assign spc6_mb_scan_out = io_test_mode ? pre_tcu_spc6_scan_out[0] | |
4636 | : (~flush_drive_0 & tap_spc6_mb_scan_out); | |
4637 | assign spc6_tap_mb_scan_in = spc6_tcu_mbist_scan_in; | |
4638 | assign tcu_spc6_scan_out[0] = io_test_mode ? spc6_tcu_mbist_scan_in : ser_scan_spc6_ch0; | |
4639 | assign tcu_spc6_mb_scan_out = jt_scan ? byp_spc5_ch1_so : spc6_mb_scan_out; | |
4640 | assign tcu_spc_lbist_scan_in[6] = (io_test_mode || jt_scan) ? spc6_tcu_scan_in[0] : 1'b0; | |
4641 | ||
4642 | assign spc7_mb_scan_out = io_test_mode ? pre_tcu_spc7_scan_out[0] | |
4643 | : (~flush_drive_0 & tap_spc7_mb_scan_out); | |
4644 | assign spc7_tap_mb_scan_in = spc7_tcu_mbist_scan_in; | |
4645 | assign tcu_spc7_scan_out[0] = io_test_mode ? spc7_tcu_mbist_scan_in : ser_scan_spc7_ch0; | |
4646 | assign tcu_spc7_mb_scan_out = jt_scan ? byp_spc6_ch1_so : spc7_mb_scan_out; | |
4647 | assign tcu_spc_lbist_scan_in[7] = (io_test_mode || jt_scan) ? spc7_tcu_scan_in[0] : 1'b0; | |
4648 | ||
4649 | assign not_flush_and_io_tdi = !flush_drive_0 && io_tdi; | |
4650 | ||
4651 | assign tcu_sii_mbist_scan_in = (io_test_mode || jt_scan) ? ncu_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4652 | assign tcu_sio_mbist_scan_in = (io_test_mode || jt_scan) ? sii_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4653 | assign tcu_ncu_mbist_scan_in = (io_test_mode || jt_scan) ? socg_tcu_scan_in : not_flush_and_io_tdi; | |
4654 | assign tcu_mcu0_mbist_scan_in = (io_test_mode || jt_scan) ? socc_tcu_scan_in : not_flush_and_io_tdi; | |
4655 | assign tcu_mcu1_mbist_scan_in = (io_test_mode || jt_scan) ? mcu0_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4656 | assign tcu_mcu2_mbist_scan_in = (io_test_mode || jt_scan) ? mcu1_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4657 | assign tcu_mcu3_mbist_scan_in = (io_test_mode || jt_scan) ? mcu2_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4658 | assign tcu_l2b0_mbist_scan_in = (io_test_mode || jt_scan) ? soch_tcu_scan_in : not_flush_and_io_tdi; | |
4659 | assign tcu_l2b1_mbist_scan_in = (io_test_mode || jt_scan) ? l2b0_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4660 | assign tcu_l2b2_mbist_scan_in = (io_test_mode || jt_scan) ? l2b1_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4661 | assign tcu_l2b3_mbist_scan_in = (io_test_mode || jt_scan) ? l2b2_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4662 | assign tcu_l2b4_mbist_scan_in = (io_test_mode || jt_scan) ? l2b3_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4663 | assign tcu_l2b5_mbist_scan_in = (io_test_mode || jt_scan) ? l2b4_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4664 | assign tcu_l2b6_mbist_scan_in = (io_test_mode || jt_scan) ? l2b5_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4665 | assign tcu_l2b7_mbist_scan_in = (io_test_mode || jt_scan) ? l2b6_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4666 | ||
4667 | assign tcu_l2t0_mbist_scan_in = (io_test_mode || jt_scan) ? soc0_tcu_scan_in : not_flush_and_io_tdi; | |
4668 | assign tcu_l2t1_mbist_scan_in = (io_test_mode || jt_scan) ? l2t0_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4669 | assign tcu_l2t2_mbist_scan_in = (io_test_mode || jt_scan) ? soc1_tcu_scan_in : not_flush_and_io_tdi; | |
4670 | assign tcu_l2t3_mbist_scan_in = (io_test_mode || jt_scan) ? l2t2_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4671 | assign tcu_l2t4_mbist_scan_in = (io_test_mode || jt_scan) ? soc2_tcu_scan_in : not_flush_and_io_tdi; | |
4672 | assign tcu_l2t5_mbist_scan_in = (io_test_mode || jt_scan) ? l2t4_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4673 | assign tcu_l2t6_mbist_scan_in = (io_test_mode || jt_scan) ? soc3_tcu_scan_in : not_flush_and_io_tdi; | |
4674 | assign tcu_l2t7_mbist_scan_in = (io_test_mode || jt_scan) ? l2t6_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4675 | ||
4676 | assign tcu_l2t0_shscan_scan_in = (io_test_mode || jt_scan) ? l2t1_tcu_mbist_scan_out : not_flush_and_io_tdi; | |
4677 | assign tcu_l2t1_shscan_scan_in = l2t0_tcu_shscan_scan_out; | |
4678 | assign tcu_l2t2_shscan_scan_in = (io_test_mode || jt_scan) ? l2t3_tcu_mbist_scan_out : l2t1_tcu_shscan_scan_out; | |
4679 | assign tcu_l2t3_shscan_scan_in = l2t2_tcu_shscan_scan_out; | |
4680 | assign tcu_l2t4_shscan_scan_in = (io_test_mode || jt_scan) ? l2t5_tcu_mbist_scan_out : l2t3_tcu_shscan_scan_out; | |
4681 | assign tcu_l2t5_shscan_scan_in = l2t4_tcu_shscan_scan_out; | |
4682 | assign tcu_l2t6_shscan_scan_in = (io_test_mode || jt_scan) ? l2t7_tcu_mbist_scan_out : l2t5_tcu_shscan_scan_out; | |
4683 | assign tcu_l2t7_shscan_scan_in = l2t6_tcu_shscan_scan_out; | |
4684 | ||
4685 | assign tcu_dmu_mbist_scan_in = (io_test_mode || jt_scan) ? socd_tcu_scan_in : not_flush_and_io_tdi; | |
4686 | assign tcu_peu_mbist_scan_in = (io_test_mode || jt_scan) ? soc6_tcu_scan_in :not_flush_and_io_tdi; | |
4687 | assign rdp_rdmc_mbist_scan_in = (io_test_mode || jt_scan) ? soce_tcu_scan_in : not_flush_and_io_tdi; | |
4688 | assign rtx_mbist_scan_in = (io_test_mode || jt_scan) ? socf_tcu_scan_in : not_flush_and_io_tdi; | |
4689 | assign tds_mbist_scan_in = (io_test_mode || jt_scan) ? soc4_tcu_scan_in : not_flush_and_io_tdi; | |
4690 | ||
4691 | ||
4692 | // ******************************************************************** | |
4693 | // SHSCAN Scan Chain Multiplexing | |
4694 | // ******************************************************************** | |
4695 | // When test_mode=1, put SHSCAN scan chain into core scan chain | |
4696 | // else, put it between tdi and tdo | |
4697 | // - only cores at this time, add SOC later | |
4698 | // - need to put in actual logic later | |
4699 | ||
4700 | assign spc0_shscan_scan_out = io_test_mode ? pre_tcu_spc0_scan_out[1] | |
4701 | : (~flush_drive_0 & tap_spc0_shscan_scan_out); | |
4702 | assign tcu_spc0_scan_out[1] = io_test_mode ? spc0_tcu_shscan_scan_in : ser_scan_spc0_ch1; | |
4703 | assign byp_spc0_tcu_shscan_scan_in = core_avail[0] ? spc0_tcu_shscan_scan_in | |
4704 | : spc0_shscan_scan_out; | |
4705 | assign tcu_spc0_shscan_scan_out = jt_scan ? byp_spc0_ch0_so : spc0_shscan_scan_out; | |
4706 | ||
4707 | assign spc1_shscan_scan_out = io_test_mode ? pre_tcu_spc1_scan_out[1] | |
4708 | : (~flush_drive_0 & byp_spc0_tcu_shscan_scan_in); | |
4709 | assign tcu_spc1_scan_out[1] = io_test_mode ? spc1_tcu_shscan_scan_in : ser_scan_spc1_ch1; | |
4710 | assign byp_spc1_tcu_shscan_scan_in = core_avail[1] ? spc1_tcu_shscan_scan_in | |
4711 | : spc1_shscan_scan_out; | |
4712 | assign tcu_spc1_shscan_scan_out = jt_scan ? byp_spc1_ch0_so : spc1_shscan_scan_out; | |
4713 | ||
4714 | assign spc2_shscan_scan_out = io_test_mode ? pre_tcu_spc2_scan_out[1] | |
4715 | : (~flush_drive_0 & byp_spc1_tcu_shscan_scan_in); | |
4716 | assign tcu_spc2_scan_out[1] = io_test_mode ? spc2_tcu_shscan_scan_in : ser_scan_spc2_ch1; | |
4717 | assign byp_spc2_tcu_shscan_scan_in = core_avail[2] ? spc2_tcu_shscan_scan_in | |
4718 | : spc2_shscan_scan_out; | |
4719 | assign tcu_spc2_shscan_scan_out = jt_scan ? byp_spc2_ch0_so : spc2_shscan_scan_out; | |
4720 | ||
4721 | assign spc3_shscan_scan_out = io_test_mode ? pre_tcu_spc3_scan_out[1] | |
4722 | : (~flush_drive_0 & byp_spc2_tcu_shscan_scan_in); | |
4723 | assign tcu_spc3_scan_out[1] = io_test_mode ? spc3_tcu_shscan_scan_in : ser_scan_spc3_ch1; | |
4724 | assign byp_spc3_tcu_shscan_scan_in = core_avail[3] ? spc3_tcu_shscan_scan_in | |
4725 | : spc3_shscan_scan_out; | |
4726 | assign tcu_spc3_shscan_scan_out = jt_scan ? byp_spc3_ch0_so : spc3_shscan_scan_out; | |
4727 | ||
4728 | assign spc4_shscan_scan_out = io_test_mode ? pre_tcu_spc4_scan_out[1] | |
4729 | : (~flush_drive_0 & byp_spc3_tcu_shscan_scan_in); | |
4730 | assign tcu_spc4_scan_out[1] = io_test_mode ? spc4_tcu_shscan_scan_in : ser_scan_spc4_ch1; | |
4731 | assign byp_spc4_tcu_shscan_scan_in = core_avail[4] ? spc4_tcu_shscan_scan_in | |
4732 | : spc4_shscan_scan_out; | |
4733 | assign tcu_spc4_shscan_scan_out = jt_scan ? byp_spc4_ch0_so : spc4_shscan_scan_out; | |
4734 | ||
4735 | assign spc5_shscan_scan_out = io_test_mode ? pre_tcu_spc5_scan_out[1] | |
4736 | : (~flush_drive_0 & byp_spc4_tcu_shscan_scan_in); | |
4737 | assign tcu_spc5_scan_out[1] = io_test_mode ? spc5_tcu_shscan_scan_in : ser_scan_spc5_ch1; | |
4738 | assign byp_spc5_tcu_shscan_scan_in = core_avail[5] ? spc5_tcu_shscan_scan_in | |
4739 | : spc5_shscan_scan_out; | |
4740 | assign tcu_spc5_shscan_scan_out = jt_scan ? byp_spc5_ch0_so : spc5_shscan_scan_out; | |
4741 | ||
4742 | assign spc6_shscan_scan_out = io_test_mode ? pre_tcu_spc6_scan_out[1] | |
4743 | : (~flush_drive_0 & byp_spc5_tcu_shscan_scan_in); | |
4744 | assign tcu_spc6_scan_out[1] = io_test_mode ? spc6_tcu_shscan_scan_in : ser_scan_spc6_ch1; | |
4745 | assign byp_spc6_tcu_shscan_scan_in = core_avail[6] ? spc6_tcu_shscan_scan_in | |
4746 | : spc6_shscan_scan_out; | |
4747 | assign tcu_spc6_shscan_scan_out = jt_scan ? byp_spc6_ch0_so : spc6_shscan_scan_out; | |
4748 | ||
4749 | assign spc7_shscan_scan_out = io_test_mode ? pre_tcu_spc7_scan_out[1] | |
4750 | : (~flush_drive_0 & byp_spc6_tcu_shscan_scan_in); | |
4751 | assign tcu_spc7_scan_out[1] = io_test_mode ? spc7_tcu_shscan_scan_in : ser_scan_spc7_ch1; | |
4752 | assign byp_spc7_tcu_shscan_scan_in = core_avail[7] ? spc7_tcu_shscan_scan_in | |
4753 | : spc7_shscan_scan_out; | |
4754 | assign tcu_spc7_shscan_scan_out = jt_scan ? byp_spc7_ch0_so : spc7_shscan_scan_out; | |
4755 | ||
4756 | assign spc7_tap_shscan_scan_in = byp_spc7_tcu_shscan_scan_in; | |
4757 | ||
4758 | // ******************************************************************** | |
4759 | // JTAG Serial Scan Chain Multiplexing - Concatenate all chains | |
4760 | // ******************************************************************** | |
4761 | // When test_mode=1, turn off jt_scan mode | |
4762 | // When jt_scan = 1, concatenate all chains | |
4763 | // - only cores at this time, add SOC later | |
4764 | ||
4765 | assign ser_scan_spc0_ch0 = jt_scan ? spc0_tcu_mbist_scan_in : 1'b0; | |
4766 | assign ser_scan_spc1_ch0 = jt_scan ? spc1_tcu_mbist_scan_in : 1'b0; | |
4767 | assign ser_scan_spc2_ch0 = jt_scan ? spc2_tcu_mbist_scan_in : 1'b0; | |
4768 | assign ser_scan_spc3_ch0 = jt_scan ? spc3_tcu_mbist_scan_in : 1'b0; | |
4769 | assign ser_scan_spc4_ch0 = jt_scan ? spc4_tcu_mbist_scan_in : 1'b0; | |
4770 | assign ser_scan_spc5_ch0 = jt_scan ? spc5_tcu_mbist_scan_in : 1'b0; | |
4771 | assign ser_scan_spc6_ch0 = jt_scan ? spc6_tcu_mbist_scan_in : 1'b0; | |
4772 | assign ser_scan_spc7_ch0 = jt_scan ? spc7_tcu_mbist_scan_in : 1'b0; | |
4773 | ||
4774 | ||
4775 | assign ser_scan_spc0_ch1 = jt_scan ? spc0_tcu_shscan_scan_in : 1'b0; | |
4776 | assign ser_scan_spc1_ch1 = jt_scan ? spc1_tcu_shscan_scan_in : 1'b0; | |
4777 | assign ser_scan_spc2_ch1 = jt_scan ? spc2_tcu_shscan_scan_in : 1'b0; | |
4778 | assign ser_scan_spc3_ch1 = jt_scan ? spc3_tcu_shscan_scan_in : 1'b0; | |
4779 | assign ser_scan_spc4_ch1 = jt_scan ? spc4_tcu_shscan_scan_in : 1'b0; | |
4780 | assign ser_scan_spc5_ch1 = jt_scan ? spc5_tcu_shscan_scan_in : 1'b0; | |
4781 | assign ser_scan_spc6_ch1 = jt_scan ? spc6_tcu_shscan_scan_in : 1'b0; | |
4782 | assign ser_scan_spc7_ch1 = jt_scan ? spc7_tcu_shscan_scan_in : 1'b0; | |
4783 | ||
4784 | ||
4785 | //assign tcu_spc0_scan_out[2] = jt_scan ? byp_spc0_ch1_so : pre_tcu_spc0_scan_out[2]; | |
4786 | //assign tcu_spc1_scan_out[2] = jt_scan ? byp_spc1_ch1_so : pre_tcu_spc1_scan_out[2]; | |
4787 | //assign tcu_spc2_scan_out[2] = jt_scan ? byp_spc2_ch1_so : pre_tcu_spc2_scan_out[2]; | |
4788 | //assign tcu_spc3_scan_out[2] = jt_scan ? byp_spc3_ch1_so : pre_tcu_spc3_scan_out[2]; | |
4789 | //assign tcu_spc4_scan_out[2] = jt_scan ? byp_spc4_ch1_so : pre_tcu_spc4_scan_out[2]; | |
4790 | //assign tcu_spc5_scan_out[2] = jt_scan ? byp_spc5_ch1_so : pre_tcu_spc5_scan_out[2]; | |
4791 | //assign tcu_spc6_scan_out[2] = jt_scan ? byp_spc6_ch1_so : pre_tcu_spc6_scan_out[2]; | |
4792 | //assign tcu_spc7_scan_out[2] = jt_scan ? byp_spc7_ch1_so : pre_tcu_spc7_scan_out[2]; | |
4793 | ||
4794 | assign tcu_soca_scan_out = jt_scan ? byp_spc7_ch1_so : pre_tcu_soca_scan_out; | |
4795 | assign tcu_socb_scan_out = jt_scan ? byp_soca_so : pre_tcu_socb_scan_out; | |
4796 | assign tcu_socc_scan_out = jt_scan ? byp_socb_so : pre_tcu_socc_scan_out; | |
4797 | assign tcu_socd_scan_out = jt_scan ? byp_socc_so : pre_tcu_socd_scan_out; | |
4798 | assign tcu_soce_scan_out = jt_scan ? byp_socd_so : pre_tcu_soce_scan_out; | |
4799 | assign tcu_socf_scan_out = jt_scan ? byp_soce_so : pre_tcu_socf_scan_out; | |
4800 | assign tcu_socg_scan_out = jt_scan ? byp_socf_so : pre_tcu_socg_scan_out; | |
4801 | assign tcu_soch_scan_out = jt_scan ? byp_socg_so : pre_tcu_soch_scan_out; | |
4802 | ||
4803 | assign tcu_soc0_scan_out = jt_scan ? byp_soch_so : pre_tcu_soc0_scan_out; | |
4804 | assign tcu_soc1_scan_out = jt_scan ? byp_soc0_so : pre_tcu_soc1_scan_out; | |
4805 | assign tcu_soc2_scan_out = jt_scan ? byp_soc1_so : pre_tcu_soc2_scan_out; | |
4806 | assign tcu_soc3_scan_out = jt_scan ? byp_soc2_so : pre_tcu_soc3_scan_out; | |
4807 | assign tcu_soc4_scan_out = jt_scan ? byp_soc3_so : pre_tcu_soc4_scan_out; | |
4808 | assign tcu_soc5_scan_out = jt_scan ? byp_soc4_so : pre_tcu_soc5_scan_out; | |
4809 | assign tcu_soc6_scan_out = jt_scan ? byp_soc5_so : pre_tcu_soc6_scan_out; | |
4810 | //assign tcu_srdes_scan_out = jt_scan ? byp_soc6_so : pre_tcu_srdes_scan_out; | |
4811 | ||
4812 | ||
4813 | // bypass chains | |
4814 | // bypass all but the selected chain | |
4815 | assign sel_spc0_chains = ((sel_chain[4:0] == 5'b00000)|(sel_chain[4:0] == 5'b00001)); | |
4816 | assign sel_spc1_chains = ((sel_chain[4:0] == 5'b00010)|(sel_chain[4:0] == 5'b00011)); | |
4817 | assign sel_spc2_chains = ((sel_chain[4:0] == 5'b00100)|(sel_chain[4:0] == 5'b00101)); | |
4818 | assign sel_spc3_chains = ((sel_chain[4:0] == 5'b00110)|(sel_chain[4:0] == 5'b00111)); | |
4819 | assign sel_spc4_chains = ((sel_chain[4:0] == 5'b01000)|(sel_chain[4:0] == 5'b01001)); | |
4820 | assign sel_spc5_chains = ((sel_chain[4:0] == 5'b01010)|(sel_chain[4:0] == 5'b01011)); | |
4821 | assign sel_spc6_chains = ((sel_chain[4:0] == 5'b01100)|(sel_chain[4:0] == 5'b01101)); | |
4822 | assign sel_spc7_chains = ((sel_chain[4:0] == 5'b01110)|(sel_chain[4:0] == 5'b01111)); | |
4823 | ||
4824 | assign byp_spc0_ch0 = chain_select & ~sel_spc0_chains; //~(sel_chain[4:0] == 5'b00000); | |
4825 | assign byp_spc0_ch1 = chain_select & ~sel_spc0_chains; //~(sel_chain[4:0] == 5'b00001); | |
4826 | //assign byp_spc0_ch2 = chain_select & ~sel_spc0_chains; //~(sel_chain[4:0] == 5'b00010); | |
4827 | assign byp_spc1_ch0 = chain_select & ~sel_spc1_chains; //~(sel_chain[4:0] == 5'b00011); | |
4828 | assign byp_spc1_ch1 = chain_select & ~sel_spc1_chains; //~(sel_chain[4:0] == 5'b00100); | |
4829 | //assign byp_spc1_ch2 = chain_select & ~sel_spc1_chains; //~(sel_chain[4:0] == 5'b00101); | |
4830 | assign byp_spc2_ch0 = chain_select & ~sel_spc2_chains; //~(sel_chain[4:0] == 5'b00110); | |
4831 | assign byp_spc2_ch1 = chain_select & ~sel_spc2_chains; //~(sel_chain[4:0] == 5'b00111); | |
4832 | //assign byp_spc2_ch2 = chain_select & ~sel_spc2_chains; //~(sel_chain[4:0] == 5'b01000); | |
4833 | assign byp_spc3_ch0 = chain_select & ~sel_spc3_chains; //~(sel_chain[4:0] == 5'b01001); | |
4834 | assign byp_spc3_ch1 = chain_select & ~sel_spc3_chains; //~(sel_chain[4:0] == 5'b01010); | |
4835 | //assign byp_spc3_ch2 = chain_select & ~sel_spc3_chains; //~(sel_chain[4:0] == 5'b01011); | |
4836 | assign byp_spc4_ch0 = chain_select & ~sel_spc4_chains; //~(sel_chain[4:0] == 5'b01100); | |
4837 | assign byp_spc4_ch1 = chain_select & ~sel_spc4_chains; //~(sel_chain[4:0] == 5'b01101); | |
4838 | //assign byp_spc4_ch2 = chain_select & ~sel_spc4_chains; //~(sel_chain[4:0] == 5'b01110); | |
4839 | assign byp_spc5_ch0 = chain_select & ~sel_spc5_chains; //~(sel_chain[4:0] == 5'b01111); | |
4840 | assign byp_spc5_ch1 = chain_select & ~sel_spc5_chains; //~(sel_chain[4:0] == 5'b10000); | |
4841 | //assign byp_spc5_ch2 = chain_select & ~sel_spc5_chains; //~(sel_chain[4:0] == 5'b10001); | |
4842 | assign byp_spc6_ch0 = chain_select & ~sel_spc6_chains; //~(sel_chain[4:0] == 5'b10010); | |
4843 | assign byp_spc6_ch1 = chain_select & ~sel_spc6_chains; //~(sel_chain[4:0] == 5'b10011); | |
4844 | //assign byp_spc6_ch2 = chain_select & ~sel_spc6_chains; //~(sel_chain[4:0] == 5'b10100); | |
4845 | assign byp_spc7_ch0 = chain_select & ~sel_spc7_chains; //~(sel_chain[4:0] == 5'b10101); | |
4846 | assign byp_spc7_ch1 = chain_select & ~sel_spc7_chains; //~(sel_chain[4:0] == 5'b10110); | |
4847 | //assign byp_spc7_ch2 = chain_select & ~sel_spc7_chains; //~(sel_chain[4:0] == 5'b10111); | |
4848 | assign byp_soca = chain_select & ~(sel_chain[4:0] == 5'b10000); // old chain 2 of spc0 | |
4849 | assign byp_socb = chain_select & ~(sel_chain[4:0] == 5'b10001); // old chain 2 of spc1 | |
4850 | assign byp_socc = chain_select & ~(sel_chain[4:0] == 5'b10010); // etc. | |
4851 | assign byp_socd = chain_select & ~(sel_chain[4:0] == 5'b10011); | |
4852 | assign byp_soce = chain_select & ~(sel_chain[4:0] == 5'b10100); | |
4853 | assign byp_socf = chain_select & ~(sel_chain[4:0] == 5'b10101); | |
4854 | assign byp_socg = chain_select & ~(sel_chain[4:0] == 5'b10110); | |
4855 | assign byp_soch = chain_select & ~(sel_chain[4:0] == 5'b10111); | |
4856 | assign byp_soc0 = chain_select & ~(sel_chain[4:0] == 5'b11000); | |
4857 | assign byp_soc1 = chain_select & ~(sel_chain[4:0] == 5'b11001); | |
4858 | assign byp_soc2 = chain_select & ~(sel_chain[4:0] == 5'b11010); | |
4859 | assign byp_soc3 = chain_select & ~(sel_chain[4:0] == 5'b11011); | |
4860 | assign byp_soc4 = chain_select & ~(sel_chain[4:0] == 5'b11100); | |
4861 | assign byp_soc5 = chain_select & ~(sel_chain[4:0] == 5'b11101); | |
4862 | assign byp_soc6 = chain_select & ~(sel_chain[4:0] == 5'b11110); | |
4863 | ||
4864 | //assign byp_srdes = chain_select & ~(sel_chain[4:0] == 5'b11111); | |
4865 | ||
4866 | ||
4867 | //assign byp_spc0_ch0_so = byp_spc0_ch0 ? tcu_spc0_mb_scan_out : spc0_tcu_scan_in[0]; | |
4868 | assign byp_spc0_ch0_so = byp_spc0_ch0 ? tcu_spc0_mb_scan_out : spc0_tcu_lbist_scan_out; | |
4869 | assign byp_spc0_ch1_so = byp_spc0_ch1 ? tcu_spc0_shscan_scan_out : spc0_tcu_scan_in[1]; | |
4870 | //assign byp_spc0_ch2_so = byp_spc0_ch2 ? tcu_spc0_scan_out[2] : spc0_tcu_scan_in[2]; | |
4871 | ||
4872 | //assign byp_spc1_ch0_so = byp_spc1_ch0 ? tcu_spc1_mb_scan_out : spc1_tcu_scan_in[0]; | |
4873 | assign byp_spc1_ch0_so = byp_spc1_ch0 ? tcu_spc1_mb_scan_out : spc1_tcu_lbist_scan_out; | |
4874 | assign byp_spc1_ch1_so = byp_spc1_ch1 ? tcu_spc1_shscan_scan_out : spc1_tcu_scan_in[1]; | |
4875 | //assign byp_spc1_ch2_so = byp_spc1_ch2 ? tcu_spc1_scan_out[2] : spc1_tcu_scan_in[2]; | |
4876 | ||
4877 | //assign byp_spc2_ch0_so = byp_spc2_ch0 ? tcu_spc2_mb_scan_out : spc2_tcu_scan_in[0]; | |
4878 | assign byp_spc2_ch0_so = byp_spc2_ch0 ? tcu_spc2_mb_scan_out : spc2_tcu_lbist_scan_out; | |
4879 | assign byp_spc2_ch1_so = byp_spc2_ch1 ? tcu_spc2_shscan_scan_out : spc2_tcu_scan_in[1]; | |
4880 | //assign byp_spc2_ch2_so = byp_spc2_ch2 ? tcu_spc2_scan_out[2] : spc2_tcu_scan_in[2]; | |
4881 | ||
4882 | //assign byp_spc3_ch0_so = byp_spc3_ch0 ? tcu_spc3_mb_scan_out : spc3_tcu_scan_in[0]; | |
4883 | assign byp_spc3_ch0_so = byp_spc3_ch0 ? tcu_spc3_mb_scan_out : spc3_tcu_lbist_scan_out; | |
4884 | assign byp_spc3_ch1_so = byp_spc3_ch1 ? tcu_spc3_shscan_scan_out : spc3_tcu_scan_in[1]; | |
4885 | //assign byp_spc3_ch2_so = byp_spc3_ch2 ? tcu_spc3_scan_out[2] : spc3_tcu_scan_in[2]; | |
4886 | ||
4887 | //assign byp_spc4_ch0_so = byp_spc4_ch0 ? tcu_spc4_mb_scan_out : spc4_tcu_scan_in[0]; | |
4888 | assign byp_spc4_ch0_so = byp_spc4_ch0 ? tcu_spc4_mb_scan_out : spc4_tcu_lbist_scan_out; | |
4889 | assign byp_spc4_ch1_so = byp_spc4_ch1 ? tcu_spc4_shscan_scan_out : spc4_tcu_scan_in[1]; | |
4890 | //assign byp_spc4_ch2_so = byp_spc4_ch2 ? tcu_spc4_scan_out[2] : spc4_tcu_scan_in[2]; | |
4891 | ||
4892 | //assign byp_spc5_ch0_so = byp_spc5_ch0 ? tcu_spc5_mb_scan_out : spc5_tcu_scan_in[0]; | |
4893 | assign byp_spc5_ch0_so = byp_spc5_ch0 ? tcu_spc5_mb_scan_out : spc5_tcu_lbist_scan_out; | |
4894 | assign byp_spc5_ch1_so = byp_spc5_ch1 ? tcu_spc5_shscan_scan_out : spc5_tcu_scan_in[1]; | |
4895 | //assign byp_spc5_ch2_so = byp_spc5_ch2 ? tcu_spc5_scan_out[2] : spc5_tcu_scan_in[2]; | |
4896 | ||
4897 | //assign byp_spc6_ch0_so = byp_spc6_ch0 ? tcu_spc6_mb_scan_out : spc6_tcu_scan_in[0]; | |
4898 | assign byp_spc6_ch0_so = byp_spc6_ch0 ? tcu_spc6_mb_scan_out : spc6_tcu_lbist_scan_out; | |
4899 | assign byp_spc6_ch1_so = byp_spc6_ch1 ? tcu_spc6_shscan_scan_out : spc6_tcu_scan_in[1]; | |
4900 | //assign byp_spc6_ch2_so = byp_spc6_ch2 ? tcu_spc6_scan_out[2] : spc6_tcu_scan_in[2]; | |
4901 | ||
4902 | //assign byp_spc7_ch0_so = byp_spc7_ch0 ? tcu_spc7_mb_scan_out : spc7_tcu_scan_in[0]; | |
4903 | assign byp_spc7_ch0_so = byp_spc7_ch0 ? tcu_spc7_mb_scan_out : spc7_tcu_lbist_scan_out; | |
4904 | assign byp_spc7_ch1_so = byp_spc7_ch1 ? tcu_spc7_shscan_scan_out : spc7_tcu_scan_in[1]; | |
4905 | //assign byp_spc7_ch2_so = byp_spc7_ch2 ? tcu_spc7_scan_out[2] : spc7_tcu_scan_in[2]; | |
4906 | ||
4907 | assign byp_soca_so = byp_soca ? tcu_soca_scan_out : soca_tcu_scan_in; | |
4908 | assign byp_socb_so = byp_socb ? tcu_socb_scan_out : socb_tcu_scan_in; | |
4909 | ||
4910 | //assign byp_socc_so = byp_socc ? tcu_socc_scan_out : socc_tcu_scan_in; | |
4911 | //assign byp_socd_so = byp_socd ? tcu_socd_scan_out : socd_tcu_scan_in; | |
4912 | //assign byp_soce_so = byp_soce ? tcu_soce_scan_out : soce_tcu_scan_in; | |
4913 | //assign byp_socf_so = byp_socf ? tcu_socf_scan_out : socf_tcu_scan_in; | |
4914 | //assign byp_socg_so = byp_socg ? tcu_socg_scan_out : socg_tcu_scan_in; | |
4915 | //assign byp_soch_so = byp_soch ? tcu_soch_scan_out : soch_tcu_scan_in; | |
4916 | ||
4917 | //assign byp_soc0_so = byp_soc0 ? tcu_soc0_scan_out : soc0_tcu_scan_in; | |
4918 | //assign byp_soc1_so = byp_soc1 ? tcu_soc1_scan_out : soc1_tcu_scan_in; | |
4919 | //assign byp_soc2_so = byp_soc2 ? tcu_soc2_scan_out : soc2_tcu_scan_in; | |
4920 | //assign byp_soc3_so = byp_soc3 ? tcu_soc3_scan_out : soc3_tcu_scan_in; | |
4921 | //assign byp_soc4_so = byp_soc4 ? tcu_soc4_scan_out : soc4_tcu_scan_in; | |
4922 | //assign byp_soc5_so = byp_soc5 ? tcu_soc5_scan_out : soc5_tcu_scan_in; | |
4923 | //assign byp_soc6_so = byp_soc6 ? tcu_soc6_scan_out : soc6_tcu_scan_in; | |
4924 | assign byp_socc_so = byp_socc ? tcu_socc_scan_out : mcu3_tcu_mbist_scan_out; | |
4925 | assign byp_socd_so = byp_socd ? tcu_socd_scan_out : dmu_tcu_mbist_scan_out; | |
4926 | assign byp_soce_so = byp_soce ? tcu_soce_scan_out : rdp_rdmc_mbist_scan_out; | |
4927 | assign byp_socf_so = byp_socf ? tcu_socf_scan_out : rtx_mbist_scan_out; | |
4928 | assign byp_socg_so = byp_socg ? tcu_socg_scan_out : sio_tcu_mbist_scan_out; | |
4929 | assign byp_soch_so = byp_soch ? tcu_soch_scan_out : l2b7_tcu_mbist_scan_out; | |
4930 | assign byp_soc0_so = byp_soc0 ? tcu_soc0_scan_out : l2t1_tcu_shscan_scan_out; | |
4931 | assign byp_soc1_so = byp_soc1 ? tcu_soc1_scan_out : l2t3_tcu_shscan_scan_out; | |
4932 | assign byp_soc2_so = byp_soc2 ? tcu_soc2_scan_out : l2t5_tcu_shscan_scan_out; | |
4933 | assign byp_soc3_so = byp_soc3 ? tcu_soc3_scan_out : l2t7_tcu_shscan_scan_out; | |
4934 | assign byp_soc4_so = byp_soc4 ? tcu_soc4_scan_out : tds_mbist_scan_out; | |
4935 | assign byp_soc5_so = byp_soc5 ? tcu_soc5_scan_out : soc5_tcu_scan_in; | |
4936 | assign byp_soc6_so = byp_soc6 ? tcu_soc6_scan_out : miobscan_or_peu_scan; | |
4937 | ||
4938 | //assign byp_srdes_so = byp_srdes ? tcu_srdes_scan_out : srdes_tcu_scan_in; | |
4939 | ||
4940 | //assign ser_scan_out = byp_srdes_so; // goes to jtag TDO for serial scan | |
4941 | assign ser_scan_out = byp_soc6_so; | |
4942 | ||
4943 | // ******************************************************************** | |
4944 | // Scan Controls | |
4945 | // io_test_mode ==> ATPG | |
4946 | // jt_scan ==> JTAG scan (no capture, load/unload only) | |
4947 | // flush_mode ==> Flush the scan chains (TCU only in POR1) | |
4948 | // mt_mode ==> MacroTest enable flop in jtag_ctl | |
4949 | // lbist_mode ==> Logic BIST; handled by lbist_ctl in SPC cores | |
4950 | // tt_mode ==> Transition Test (AC scan) - covered by io_test_mode | |
4951 | // ******************************************************************** | |
4952 | assign mt_mode = jtag_mt_enable; | |
4953 | assign jt_scan = jtag_ser_scan_q & ~io_test_mode; // ECO yyyyyy | |
4954 | assign jt_scan_mtmode = jt_scan & mt_mode; | |
4955 | ||
4956 | assign tcu_scan_en = | |
4957 | io_test_mode ? pin_scan_en | |
4958 | : jt_scan ? (jt_scan_en & ~sel_only_spc_scan) | |
4959 | : instr_mbist_diag ? soc_mbist_scan_en | |
4960 | : fm_scan_en; | |
4961 | assign tcu_int_se = io_test_mode ? pin_scan_en : (~POR_ | (por_one & int_flush_d3)); | |
4962 | assign tcu_int_nfse = io_test_mode ? pin_scan_en : 1'b0; | |
4963 | //assign tcu_int_frse = ac_test_mode ? 1'b0 : pin_scan_en; | |
4964 | assign tcu_jtag_se = io_test_mode ? pin_scan_en : 1'b0; | |
4965 | ||
4966 | assign tcu_se_scancollar_in = | |
4967 | io_test_mode ? pin_scan_en | mt_mode // includes tt_mode | |
4968 | : jt_scan ? ((jt_scan_en | mt_mode) & ~sel_only_spc_scan) | |
4969 | : flush_mode ? fm_scan_en //1'b1 | |
4970 | : 1'b0; | |
4971 | ||
4972 | assign tcu_se_scancollar_out = | |
4973 | io_test_mode ? pin_scan_en // includes tt_mode | |
4974 | : jt_scan ? (jt_scan_en & ~sel_only_spc_scan) | |
4975 | : flush_mode ? fm_scan_en //1'b1 | |
4976 | : 1'b0; | |
4977 | ||
4978 | assign tcu_array_bypass = io_test_mode ? ~mt_mode //1'b1 | |
4979 | //: jt_scan ? ~mt_mode //1'b1 | |
4980 | : 1'b0; | |
4981 | ||
4982 | assign tcu_array_wr_inhibit = | |
4983 | io_test_mode ? pin_scan_en | ~mt_mode //1'b1 // includes tt_mode | |
4984 | : jt_scan ? ((jt_scan_en | ~mt_mode) & ~sel_only_spc_scan) //1'b1 | |
4985 | : flush_mode ? fm_scan_en | |
4986 | : 1'b0; | |
4987 | ||
4988 | //mux scan clocks based on testmode | |
4989 | assign tcu_aclk = | |
4990 | io_test_mode ? pin_aclk | |
4991 | : jt_scan ? (jt_scan_aclk & ~sel_only_spc_scan) | |
4992 | : instr_mbist_diag ? soc_mbist_aclk | |
4993 | : fm_aclk; | |
4994 | ||
4995 | assign tcu_bclk = | |
4996 | io_test_mode ? pin_bclk | |
4997 | : jt_scan ? (jt_scan_bclk & ~sel_only_spc_scan) | |
4998 | : instr_mbist_diag ? soc_mbist_bclk | |
4999 | : fm_bclk; //1'b0; | |
5000 | ||
5001 | assign flush_mode = flush_off; | |
5002 | ||
5003 | assign tcu_dectest = // active low | |
5004 | io_test_mode ? atpg_dectest //1'b0 // includes tt_mode | |
5005 | : 1'b1; | |
5006 | ||
5007 | assign tcu_muxtest = // active low | |
5008 | io_test_mode ? atpg_muxtest // ECO MUXTEST //1'b0 // includes tt_mode | |
5009 | : 1'b1; | |
5010 | ||
5011 | // ********* Assign CONSTANT SCAN CONTROL values here *********** | |
5012 | // ********* Assign CORE-UNIQUE SCAN CONTROL values here *********** | |
5013 | assign sel_spc0 = sel_spc0_chains | ~chain_select; | |
5014 | assign sel_spc1 = sel_spc1_chains | ~chain_select; | |
5015 | assign sel_spc2 = sel_spc2_chains | ~chain_select; | |
5016 | assign sel_spc3 = sel_spc3_chains | ~chain_select; | |
5017 | assign sel_spc4 = sel_spc4_chains | ~chain_select; | |
5018 | assign sel_spc5 = sel_spc5_chains | ~chain_select; | |
5019 | assign sel_spc6 = sel_spc6_chains | ~chain_select; | |
5020 | assign sel_spc7 = sel_spc7_chains | ~chain_select; | |
5021 | ||
5022 | assign sel_only_spc_scan = (sel_spc0_chains | sel_spc1_chains | sel_spc2_chains | sel_spc3_chains | |
5023 | | sel_spc4_chains | sel_spc5_chains | sel_spc6_chains | sel_spc7_chains) | |
5024 | & chain_select; | |
5025 | ||
5026 | assign jt_scan_spc0 = jt_scan & sel_spc0; | |
5027 | assign jt_scan_spc1 = jt_scan & sel_spc1; | |
5028 | assign jt_scan_spc2 = jt_scan & sel_spc2; | |
5029 | assign jt_scan_spc3 = jt_scan & sel_spc3; | |
5030 | assign jt_scan_spc4 = jt_scan & sel_spc4; | |
5031 | assign jt_scan_spc5 = jt_scan & sel_spc5; | |
5032 | assign jt_scan_spc6 = jt_scan & sel_spc6; | |
5033 | assign jt_scan_spc7 = jt_scan & sel_spc7; | |
5034 | ||
5035 | // Values for SCAN_EN generation | |
5036 | assign jt_spc0_scan_en = jt_scan_en & sel_spc0; | |
5037 | assign jt_spc1_scan_en = jt_scan_en & sel_spc1; | |
5038 | assign jt_spc2_scan_en = jt_scan_en & sel_spc2; | |
5039 | assign jt_spc3_scan_en = jt_scan_en & sel_spc3; | |
5040 | assign jt_spc4_scan_en = jt_scan_en & sel_spc4; | |
5041 | assign jt_spc5_scan_en = jt_scan_en & sel_spc5; | |
5042 | assign jt_spc6_scan_en = jt_scan_en & sel_spc6; | |
5043 | assign jt_spc7_scan_en = jt_scan_en & sel_spc7; | |
5044 | assign fm_scan_en = ~POR_ | flush_q72; | |
5045 | assign fm_asic_scan_en = ~POR_ | int_flush; | |
5046 | // Values for ACLK generation | |
5047 | assign jt_spc0_aclk = jt_scan_aclk & sel_spc0; | |
5048 | assign jt_spc1_aclk = jt_scan_aclk & sel_spc1; | |
5049 | assign jt_spc2_aclk = jt_scan_aclk & sel_spc2; | |
5050 | assign jt_spc3_aclk = jt_scan_aclk & sel_spc3; | |
5051 | assign jt_spc4_aclk = jt_scan_aclk & sel_spc4; | |
5052 | assign jt_spc5_aclk = jt_scan_aclk & sel_spc5; | |
5053 | assign jt_spc6_aclk = jt_scan_aclk & sel_spc6; | |
5054 | assign jt_spc7_aclk = jt_scan_aclk & sel_spc7; | |
5055 | assign fm_aclk = ~POR_ | (flush_go & flush_start); // FLUSH_mode Aclk | |
5056 | // Values for BCLK generation | |
5057 | assign jt_spc0_bclk = jt_scan_bclk & sel_spc0; | |
5058 | assign jt_spc1_bclk = jt_scan_bclk & sel_spc1; | |
5059 | assign jt_spc2_bclk = jt_scan_bclk & sel_spc2; | |
5060 | assign jt_spc3_bclk = jt_scan_bclk & sel_spc3; | |
5061 | assign jt_spc4_bclk = jt_scan_bclk & sel_spc4; | |
5062 | assign jt_spc5_bclk = jt_scan_bclk & sel_spc5; | |
5063 | assign jt_spc6_bclk = jt_scan_bclk & sel_spc6; | |
5064 | assign jt_spc7_bclk = jt_scan_bclk & sel_spc7; | |
5065 | assign fm_bclk = flush_go & ~flush_start; // FLUSH_mode Bclk | |
5066 | // ******************** For SPC0 ************************ | |
5067 | assign tcu_spc0_scan_en = io_test_mode ? pin_scan_en | |
5068 | : jt_scan_spc0 ? jt_spc0_scan_en | |
5069 | : flush_mode ? fm_scan_en | |
5070 | : tap_spc0_mb_scan_en; | |
5071 | ||
5072 | assign tcu_spc0_aclk = io_test_mode ? pin_aclk | |
5073 | : jt_scan_spc0 ? jt_spc0_aclk | |
5074 | : flush_mode ? fm_aclk | |
5075 | : tap_spc0_mb_aclk; | |
5076 | ||
5077 | assign tcu_spc0_bclk = io_test_mode ? pin_bclk | |
5078 | : jt_scan_spc0 ? jt_spc0_bclk | |
5079 | : flush_mode ? fm_bclk | |
5080 | : tap_spc0_mb_bclk; | |
5081 | ||
5082 | assign tcu_spc0_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5083 | : jt_scan_spc0 ? jt_spc0_scan_en | mt_mode | |
5084 | : flush_mode ? fm_scan_en | |
5085 | : tap_spc0_mb_scan_en; | |
5086 | ||
5087 | assign tcu_spc0_se_scancollar_out = io_test_mode ? pin_scan_en | |
5088 | : jt_scan_spc0 ? jt_spc0_scan_en | |
5089 | : flush_mode ? fm_scan_en | |
5090 | : tap_spc0_mb_scan_en; | |
5091 | ||
5092 | assign tcu_spc0_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5093 | : jt_scan_spc0 ? jt_spc0_scan_en | ~mt_mode //jt_awi_spc0 | |
5094 | : flush_mode ? fm_scan_en | |
5095 | : tcu_spc_lbist_start[0] ? 1'b1 | |
5096 | : 1'b0; | |
5097 | // ******************** For SPC1 ************************ | |
5098 | assign tcu_spc1_scan_en = io_test_mode ? pin_scan_en | |
5099 | : jt_scan_spc1 ? jt_spc1_scan_en | |
5100 | : flush_mode ? fm_scan_en | |
5101 | : tap_spc1_mb_scan_en; | |
5102 | ||
5103 | assign tcu_spc1_aclk = io_test_mode ? pin_aclk | |
5104 | : jt_scan_spc1 ? jt_spc1_aclk | |
5105 | : flush_mode ? fm_aclk | |
5106 | : tap_spc1_mb_aclk; | |
5107 | ||
5108 | assign tcu_spc1_bclk = io_test_mode ? pin_bclk | |
5109 | : jt_scan_spc1 ? jt_spc1_bclk | |
5110 | : flush_mode ? fm_bclk | |
5111 | : tap_spc1_mb_bclk; | |
5112 | ||
5113 | assign tcu_spc1_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5114 | : jt_scan_spc1 ? jt_spc1_scan_en | mt_mode | |
5115 | : flush_mode ? fm_scan_en | |
5116 | : tap_spc1_mb_scan_en; | |
5117 | ||
5118 | assign tcu_spc1_se_scancollar_out = io_test_mode ? pin_scan_en | |
5119 | : jt_scan_spc1 ? jt_spc1_scan_en | |
5120 | : flush_mode ? fm_scan_en | |
5121 | : tap_spc1_mb_scan_en; | |
5122 | ||
5123 | assign tcu_spc1_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5124 | : jt_scan_spc1 ? jt_spc1_scan_en | ~mt_mode | |
5125 | : flush_mode ? fm_scan_en | |
5126 | : tcu_spc_lbist_start[1] ? 1'b1 | |
5127 | : 1'b0; | |
5128 | // ******************** For SPC2 ************************ | |
5129 | assign tcu_spc2_scan_en = io_test_mode ? pin_scan_en | |
5130 | : jt_scan_spc2 ? jt_spc2_scan_en | |
5131 | : flush_mode ? fm_scan_en | |
5132 | : tap_spc2_mb_scan_en; | |
5133 | ||
5134 | assign tcu_spc2_aclk = io_test_mode ? pin_aclk | |
5135 | : jt_scan_spc2 ? jt_spc2_aclk | |
5136 | : flush_mode ? fm_aclk | |
5137 | : tap_spc2_mb_aclk; | |
5138 | ||
5139 | assign tcu_spc2_bclk = io_test_mode ? pin_bclk | |
5140 | : jt_scan_spc2 ? jt_spc2_bclk | |
5141 | : flush_mode ? fm_bclk | |
5142 | : tap_spc2_mb_bclk; | |
5143 | ||
5144 | assign tcu_spc2_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5145 | : jt_scan_spc2 ? jt_spc2_scan_en | mt_mode | |
5146 | : flush_mode ? fm_scan_en | |
5147 | : tap_spc2_mb_scan_en; | |
5148 | ||
5149 | assign tcu_spc2_se_scancollar_out = io_test_mode ? pin_scan_en | |
5150 | : jt_scan_spc2 ? jt_spc2_scan_en | |
5151 | : flush_mode ? fm_scan_en | |
5152 | : tap_spc2_mb_scan_en; | |
5153 | ||
5154 | assign tcu_spc2_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5155 | : jt_scan_spc2 ? jt_spc2_scan_en | ~mt_mode | |
5156 | : flush_mode ? fm_scan_en | |
5157 | : tcu_spc_lbist_start[2] ? 1'b1 | |
5158 | : 1'b0; | |
5159 | // ******************** For SPC3 ************************ | |
5160 | assign tcu_spc3_scan_en = io_test_mode ? pin_scan_en | |
5161 | : jt_scan_spc3 ? jt_spc3_scan_en | |
5162 | : flush_mode ? fm_scan_en | |
5163 | : tap_spc3_mb_scan_en; | |
5164 | ||
5165 | assign tcu_spc3_aclk = io_test_mode ? pin_aclk | |
5166 | : jt_scan_spc3 ? jt_spc3_aclk | |
5167 | : flush_mode ? fm_aclk | |
5168 | : tap_spc3_mb_aclk; | |
5169 | ||
5170 | assign tcu_spc3_bclk = io_test_mode ? pin_bclk | |
5171 | : jt_scan_spc3 ? jt_spc3_bclk | |
5172 | : flush_mode ? fm_bclk | |
5173 | : tap_spc3_mb_bclk; | |
5174 | ||
5175 | assign tcu_spc3_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5176 | : jt_scan_spc3 ? jt_spc3_scan_en | mt_mode | |
5177 | : flush_mode ? fm_scan_en | |
5178 | : tap_spc3_mb_scan_en; | |
5179 | ||
5180 | assign tcu_spc3_se_scancollar_out = io_test_mode ? pin_scan_en | |
5181 | : jt_scan_spc3 ? jt_spc3_scan_en | |
5182 | : flush_mode ? fm_scan_en | |
5183 | : tap_spc3_mb_scan_en; | |
5184 | ||
5185 | assign tcu_spc3_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5186 | : jt_scan_spc3 ? jt_spc3_scan_en | ~mt_mode | |
5187 | : flush_mode ? fm_scan_en | |
5188 | : tcu_spc_lbist_start[3] ? 1'b1 | |
5189 | : 1'b0; | |
5190 | // ******************** For SPC4 ************************ | |
5191 | assign tcu_spc4_scan_en = io_test_mode ? pin_scan_en | |
5192 | : jt_scan_spc4 ? jt_spc4_scan_en | |
5193 | : flush_mode ? fm_scan_en | |
5194 | : tap_spc4_mb_scan_en; | |
5195 | ||
5196 | assign tcu_spc4_aclk = io_test_mode ? pin_aclk | |
5197 | : jt_scan_spc4 ? jt_spc4_aclk | |
5198 | : flush_mode ? fm_aclk | |
5199 | : tap_spc4_mb_aclk; | |
5200 | ||
5201 | assign tcu_spc4_bclk = io_test_mode ? pin_bclk | |
5202 | : jt_scan_spc4 ? jt_spc4_bclk | |
5203 | : flush_mode ? fm_bclk | |
5204 | : tap_spc4_mb_bclk; | |
5205 | ||
5206 | assign tcu_spc4_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5207 | : jt_scan_spc4 ? jt_spc4_scan_en | mt_mode | |
5208 | : flush_mode ? fm_scan_en | |
5209 | : tap_spc4_mb_scan_en; | |
5210 | ||
5211 | assign tcu_spc4_se_scancollar_out = io_test_mode ? pin_scan_en | |
5212 | : jt_scan_spc4 ? jt_spc4_scan_en | |
5213 | : flush_mode ? fm_scan_en | |
5214 | : tap_spc4_mb_scan_en; | |
5215 | ||
5216 | assign tcu_spc4_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5217 | : jt_scan_spc4 ? jt_spc4_scan_en | ~mt_mode | |
5218 | : flush_mode ? fm_scan_en | |
5219 | : tcu_spc_lbist_start[4] ? 1'b1 | |
5220 | : 1'b0; | |
5221 | // ******************** For SPC5 ************************ | |
5222 | assign tcu_spc5_scan_en = io_test_mode ? pin_scan_en | |
5223 | : jt_scan_spc5 ? jt_spc5_scan_en | |
5224 | : flush_mode ? fm_scan_en | |
5225 | : tap_spc5_mb_scan_en; | |
5226 | ||
5227 | assign tcu_spc5_aclk = io_test_mode ? pin_aclk | |
5228 | : jt_scan_spc5 ? jt_spc5_aclk | |
5229 | : flush_mode ? fm_aclk | |
5230 | : tap_spc5_mb_aclk; | |
5231 | ||
5232 | assign tcu_spc5_bclk = io_test_mode ? pin_bclk | |
5233 | : jt_scan_spc5 ? jt_spc5_bclk | |
5234 | : flush_mode ? fm_bclk | |
5235 | : tap_spc5_mb_bclk; | |
5236 | ||
5237 | assign tcu_spc5_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5238 | : jt_scan_spc5 ? jt_spc5_scan_en | mt_mode | |
5239 | : flush_mode ? fm_scan_en | |
5240 | : tap_spc5_mb_scan_en; | |
5241 | ||
5242 | assign tcu_spc5_se_scancollar_out = io_test_mode ? pin_scan_en | |
5243 | : jt_scan_spc5 ? jt_spc5_scan_en | |
5244 | : flush_mode ? fm_scan_en | |
5245 | : tap_spc5_mb_scan_en; | |
5246 | ||
5247 | assign tcu_spc5_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5248 | : jt_scan_spc5 ? jt_spc5_scan_en | ~mt_mode | |
5249 | : flush_mode ? fm_scan_en | |
5250 | : tcu_spc_lbist_start[5] ? 1'b1 | |
5251 | : 1'b0; | |
5252 | // ******************** For SPC6 ************************ | |
5253 | assign tcu_spc6_scan_en = io_test_mode ? pin_scan_en | |
5254 | : jt_scan_spc6 ? jt_spc6_scan_en | |
5255 | : flush_mode ? fm_scan_en | |
5256 | : tap_spc6_mb_scan_en; | |
5257 | ||
5258 | assign tcu_spc6_aclk = io_test_mode ? pin_aclk | |
5259 | : jt_scan_spc6 ? jt_spc6_aclk | |
5260 | : flush_mode ? fm_aclk | |
5261 | : tap_spc6_mb_aclk; | |
5262 | ||
5263 | assign tcu_spc6_bclk = io_test_mode ? pin_bclk | |
5264 | : jt_scan_spc6 ? jt_spc6_bclk | |
5265 | : flush_mode ? fm_bclk | |
5266 | : tap_spc6_mb_bclk; | |
5267 | ||
5268 | assign tcu_spc6_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5269 | : jt_scan_spc6 ? jt_spc6_scan_en | mt_mode | |
5270 | : flush_mode ? fm_scan_en | |
5271 | : tap_spc6_mb_scan_en; | |
5272 | ||
5273 | assign tcu_spc6_se_scancollar_out = io_test_mode ? pin_scan_en | |
5274 | : jt_scan_spc6 ? jt_spc6_scan_en | |
5275 | : flush_mode ? fm_scan_en | |
5276 | : tap_spc6_mb_scan_en; | |
5277 | ||
5278 | assign tcu_spc6_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5279 | : jt_scan_spc6 ? jt_spc6_scan_en | ~mt_mode | |
5280 | : flush_mode ? fm_scan_en | |
5281 | : tcu_spc_lbist_start[6] ? 1'b1 | |
5282 | : 1'b0; | |
5283 | // ******************** For SPC7 ************************ | |
5284 | assign tcu_spc7_scan_en = io_test_mode ? pin_scan_en | |
5285 | : jt_scan_spc7 ? jt_spc7_scan_en | |
5286 | : flush_mode ? fm_scan_en | |
5287 | : tap_spc7_mb_scan_en; | |
5288 | ||
5289 | assign tcu_spc7_aclk = io_test_mode ? pin_aclk | |
5290 | : jt_scan_spc7 ? jt_spc7_aclk | |
5291 | : flush_mode ? fm_aclk | |
5292 | : tap_spc7_mb_aclk; | |
5293 | ||
5294 | assign tcu_spc7_bclk = io_test_mode ? pin_bclk | |
5295 | : jt_scan_spc7 ? jt_spc7_bclk | |
5296 | : flush_mode ? fm_bclk | |
5297 | : tap_spc7_mb_bclk; | |
5298 | ||
5299 | assign tcu_spc7_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5300 | : jt_scan_spc7 ? jt_spc7_scan_en | mt_mode | |
5301 | : flush_mode ? fm_scan_en | |
5302 | : tap_spc7_mb_scan_en; | |
5303 | ||
5304 | assign tcu_spc7_se_scancollar_out = io_test_mode ? pin_scan_en | |
5305 | : jt_scan_spc7 ? jt_spc7_scan_en | |
5306 | : flush_mode ? fm_scan_en | |
5307 | : tap_spc7_mb_scan_en; | |
5308 | ||
5309 | assign tcu_spc7_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5310 | : jt_scan_spc7 ? jt_spc7_scan_en | ~mt_mode | |
5311 | : flush_mode ? fm_scan_en | |
5312 | : tcu_spc_lbist_start[7] ? 1'b1 | |
5313 | : 1'b0; | |
5314 | // *********** End of SPC Scan Controls ***************** | |
5315 | ||
5316 | // ******************** For ASICs ************************ | |
5317 | // NIU (MAC, RDP, RTX, TDS), DMU and PEU | |
5318 | //assign asic_active = (por_one | rst_tcu_clk_stop | jtag_clk_stop_active) & ~io_test_mode; | |
5319 | //assign asic_stop_en = (wmr_one | wmr_two | jtag_clk_stop_active) & ~io_test_mode & ~rst_tcu_dbr_gen; | |
5320 | assign asic_stop_en = ((wmr_one | wmr_two | jtag_clk_stop_active) & ~rst_tcu_dbr_gen) | ac_test_mode; | |
5321 | assign asic_por_stop = (~POR_ | (por_one & int_flush_d6)) & ~io_test_mode; | |
5322 | ||
5323 | assign tcu_asic_scan_en = io_test_mode ? pin_scan_en | |
5324 | : jt_scan ? jt_scan_en & ~sel_only_spc_scan | |
5325 | : flush_mode ? fm_asic_scan_en // & ~sel_only_spc_scan | |
5326 | : instr_mbist_diag ? soc_mbist_scan_en | |
5327 | : 1'b0; | |
5328 | ||
5329 | assign tcu_asic_aclk = io_test_mode ? pin_aclk | |
5330 | : jt_scan ? jt_scan_aclk & ~sel_only_spc_scan | |
5331 | : flush_mode ? 1'b0 // fm_aclk - don't flush ASICs | |
5332 | : instr_mbist_diag ? soc_mbist_aclk | |
5333 | : 1'b0; | |
5334 | ||
5335 | assign tcu_asic_bclk = io_test_mode ? pin_bclk | |
5336 | : jt_scan ? jt_scan_bclk & ~sel_only_spc_scan | |
5337 | : flush_mode ? 1'b0 // don't flush ASICs | |
5338 | : instr_mbist_diag ? soc_mbist_bclk | |
5339 | : 1'b0; | |
5340 | ||
5341 | assign tcu_asic_se_scancollar_in = io_test_mode ? pin_scan_en | mt_mode | |
5342 | : jt_scan ? ((jt_scan_en | mt_mode) & ~sel_only_spc_scan) | |
5343 | : flush_mode ? fm_asic_scan_en | |
5344 | : instr_mbist_diag ? soc_mbist_scan_en | |
5345 | : 1'b0; | |
5346 | ||
5347 | assign tcu_asic_se_scancollar_out = io_test_mode ? pin_scan_en | |
5348 | : jt_scan ? jt_scan_en & ~sel_only_spc_scan | |
5349 | : flush_mode ? fm_asic_scan_en | |
5350 | : instr_mbist_diag ? soc_mbist_scan_en | |
5351 | : 1'b0; | |
5352 | ||
5353 | assign tcu_asic_array_wr_inhibit = io_test_mode ? pin_scan_en | ~mt_mode //1'b1 | |
5354 | : jt_scan ? ((jt_scan_en | ~mt_mode) & ~sel_only_spc_scan) | |
5355 | : flush_mode ? fm_asic_scan_en | |
5356 | : 1'b0; | |
5357 | // *********** End of ASIC Scan Controls ***************** | |
5358 | ||
5359 | ||
5360 | assign tcu_int_aclk = io_test_mode ? pin_aclk : (~POR_ | por_one & int_flush); | |
5361 | assign tcu_int_bclk = io_test_mode ? pin_bclk : 1'b0; | |
5362 | assign tcu_jtag_aclk = io_test_mode ? pin_aclk : 1'b0; | |
5363 | ||
5364 | assign tcu_int_nfaclk = io_test_mode ? pin_aclk : 1'b0; | |
5365 | assign tcu_int_nfbclk = io_test_mode ? pin_bclk : 1'b0; | |
5366 | ||
5367 | //over ride power saving pce signal | |
5368 | assign tcu_pce_ov = io_test_mode ? atpg_pce_ov : 1'b0; | |
5369 | assign tcu_int_pce_ov= ac_test_mode ? 1'b0 : tcu_pce_ov; | |
5370 | ||
5371 | // Flush scan chains when requested by reset unit | |
5372 | assign flush = io_test_mode ? 1'b0 : rst_flush_req; | |
5373 | assign tcu_jtag_flush_req = flush_go; // to jtag | |
5374 | assign flush_drive_0 = flush_mode & fm_scan_en; // si to zero needs to follow flush scan enable | |
5375 | ||
5376 | // for Scan Flush, drive scan_in to low if not in test_mode | |
5377 | assign int_scan_in = io_test_mode ? scan_in : 1'b0; | |
5378 | ||
5379 | // ******************************************************************** | |
5380 | // Synchronizer for JTAG Stop Request | |
5381 | // ******************************************************************** | |
5382 | // jtag can request a clock stop, or mbist can request clk stop but mbist | |
5383 | // request is gated by cycle counter | |
5384 | assign jtmb_clk_stop = (jtag_clk_stop_req_sync && !jtagclkstop_ov) | mbist_clk_stop; | |
5385 | ||
5386 | // ******************************************************************** | |
5387 | // SerDes ATPG Logic - to Serdes Macros, not SOC's | |
5388 | // ******************************************************************** | |
5389 | assign tcu_srd_atpgse = io_test_mode & pin_scan_en; | |
5390 | ||
5391 | assign tcu_srd_atpgmode[2] = io_test_mode; | |
5392 | assign tcu_srd_atpgmode[1:0] = ac_test_mode ? {serdes_ac_mode_1,serdes_ac_mode_0} | |
5393 | : 2'b00; | |
5394 | assign tcu_srd_atpgd = io_test_mode & mio_tcu_scan_in31; | |
5395 | assign tcu_mio_scan_out31 = srd_tcu_atpgq; | |
5396 | ||
5397 | tcu_sigmux_ctl_msff_ctl_macro__width_2 tcusig_srdacmode_reg | |
5398 | ( | |
5399 | .scan_in(tcusig_srdacmode_reg_scanin), | |
5400 | .scan_out(tcusig_srdacmode_reg_scanout), | |
5401 | .l1clk (l1clk), | |
5402 | .din ({serdes_ac_mode_1, serdes_ac_mode_0}), | |
5403 | .dout ({serdes_ac_mode_1, serdes_ac_mode_0}), | |
5404 | .siclk(siclk), | |
5405 | .soclk(soclk) | |
5406 | ); | |
5407 | ||
5408 | // ******************************************************************** | |
5409 | // Synchronizer Enable Pulses from cluster header | |
5410 | // ******************************************************************** | |
5411 | tcu_sigmux_ctl_msff_ctl_macro__width_3 tcusig_cmpdrsync_reg | |
5412 | ( | |
5413 | .scan_in(tcusig_cmpdrsync_reg_scanin), | |
5414 | .scan_out(tcusig_cmpdrsync_reg_scanout), | |
5415 | .l1clk (l1clk), | |
5416 | .din ({cmp_io_sync_en, io_cmp_sync_en, cmp_dr_sync_en }), | |
5417 | .dout ({cmp_io_sync_en_local, io_cmp_sync_en_local, cmp_dr_sync_en_local_unused}), | |
5418 | .siclk(siclk), | |
5419 | .soclk(soclk) | |
5420 | ); | |
5421 | ||
5422 | // ******************************************************************** | |
5423 | // PCE_OV - want a scan-only flop for control | |
5424 | // DECTEST - also scan-only flop | |
5425 | // ******************************************************************** | |
5426 | // For ATPG, scan in desired value | |
5427 | tcu_sigmux_ctl_msff_ctl_macro__width_2 tcusig_pceov_reg | |
5428 | ( | |
5429 | .scan_in(tcusig_pceov_reg_scanin), | |
5430 | .scan_out(tcusig_pceov_reg_scanout), | |
5431 | .l1clk (l1clk), | |
5432 | .din ({atpg_pce_ov, atpg_dectest}), | |
5433 | .dout ({atpg_pce_ov, atpg_dectest}), | |
5434 | .siclk(siclk), | |
5435 | .soclk(soclk) | |
5436 | ); | |
5437 | ||
5438 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_ccu_clk_stop_reg ( | |
5439 | .scan_in ( tcusig_ccu_clk_stop_reg_scanin ), | |
5440 | .scan_out ( tcusig_ccu_clk_stop_reg_scanout ), | |
5441 | .l1clk ( l1clk ), | |
5442 | .din ( tcu_ccu_clk_stop_din ), | |
5443 | .dout ( tcu_ccu_clk_stop_dout ), | |
5444 | .siclk(siclk), | |
5445 | .soclk(soclk)); | |
5446 | ||
5447 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_ccu_io_clk_stop_reg ( | |
5448 | .scan_in ( tcusig_ccu_io_clk_stop_reg_scanin ), | |
5449 | .scan_out ( tcusig_ccu_io_clk_stop_reg_scanout ), | |
5450 | .l1clk ( l1clk ), | |
5451 | .din ( tcu_ccu_io_clk_stop_din ), | |
5452 | .dout ( tcu_ccu_io_clk_stop_dout ), | |
5453 | .siclk(siclk), | |
5454 | .soclk(soclk)); | |
5455 | ||
5456 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_rst_clk_stop_reg ( | |
5457 | .scan_in ( tcusig_rst_clk_stop_reg_scanin ), | |
5458 | .scan_out ( tcusig_rst_clk_stop_reg_scanout ), | |
5459 | .l1clk ( l1clk ), | |
5460 | .din ( tcu_rst_clk_stop_din ), | |
5461 | .dout ( tcu_rst_clk_stop_dout ), | |
5462 | .siclk(siclk), | |
5463 | .soclk(soclk)); | |
5464 | ||
5465 | tcu_sigmux_ctl_msff_ctl_macro__width_1 tcusig_rst_io_clk_stop_reg ( | |
5466 | .scan_in ( tcusig_rst_io_clk_stop_reg_scanin ), | |
5467 | .scan_out ( tcusig_rst_io_clk_stop_reg_scanout ), | |
5468 | .l1clk ( l1clk ), | |
5469 | .din ( tcu_rst_io_clk_stop_din ), | |
5470 | .dout ( tcu_rst_io_clk_stop_dout ), | |
5471 | .siclk(siclk), | |
5472 | .soclk(soclk)); | |
5473 | ||
5474 | assign tcu_ccu_clk_stop_din = tcu_ccu_clk_stop_dout; | |
5475 | assign tcu_ccu_io_clk_stop_din = tcu_ccu_io_clk_stop_dout; | |
5476 | assign tcu_rst_clk_stop_din = tcu_rst_clk_stop_dout; | |
5477 | assign tcu_rst_io_clk_stop_din = tcu_rst_io_clk_stop_dout; | |
5478 | ||
5479 | assign tcu_ccu_clk_stop = tcu_ccu_clk_stop_dout & ~ac_test_mode; | |
5480 | assign tcu_ccu_io_clk_stop = tcu_ccu_io_clk_stop_dout & ~ac_test_mode; | |
5481 | assign tcu_rst_clk_stop = tcu_rst_clk_stop_dout & ~ac_test_mode; | |
5482 | assign tcu_rst_io_clk_stop = tcu_rst_io_clk_stop_dout & ~ac_test_mode; | |
5483 | ||
5484 | // ******************************************************************** | |
5485 | // Synchronizer for JTAG Access during POR | |
5486 | // ******************************************************************** | |
5487 | cl_sc1_clksyncff_4x sync_ff_jtag_por_acc | |
5488 | (.si (sync_ff_jtagporacc_scanin), | |
5489 | .so (sync_ff_jtagporacc_scanout), | |
5490 | .l1clk (l1clk), | |
5491 | .d (jtag_por_enable), | |
5492 | .q (jtag_por_enable_sync), | |
5493 | .siclk(siclk), | |
5494 | .soclk(soclk) | |
5495 | ); | |
5496 | ||
5497 | assign jtag_por_active = jtag_por_enable_sync & por_two; | |
5498 | assign jtag_por_status = jtag_por_active; | |
5499 | ||
5500 | // ******************************************************************** | |
5501 | // Synchronizer for NCU SCK Counter Bypass, signal generated via JTAG | |
5502 | // ******************************************************************** | |
5503 | cl_sc1_clksyncff_4x sync_ff_sck_byp | |
5504 | (.si (sync_ff_sckbyp_scanin), | |
5505 | .so (sync_ff_sckbyp_scanout), | |
5506 | .l1clk (l1clk), | |
5507 | .d (jtag_sck_byp), | |
5508 | .q (jtag_sck_byp_sync), | |
5509 | .siclk(siclk), | |
5510 | .soclk(soclk) | |
5511 | ); | |
5512 | ||
5513 | assign pre_sck_bypass = jtag_sck_byp_sync; | |
5514 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 tcusig_sck_reg | |
5515 | ( | |
5516 | .scan_in(tcusig_sck_reg_scanin), | |
5517 | .scan_out(tcusig_sck_reg_scanout), | |
5518 | .en (cmp_io_sync_en_local), | |
5519 | .din (pre_sck_bypass), | |
5520 | .dout (tcu_sck_bypass), | |
5521 | .l1clk (l1clk), | |
5522 | .siclk(siclk), | |
5523 | .soclk(soclk)); | |
5524 | ||
5525 | //================================================== | |
5526 | // Synchronizers | |
5527 | // From TCK to IO | |
5528 | //================================================== | |
5529 | //================================================== | |
5530 | // SPC MBIST Clock Stop | |
5531 | //================================================== | |
5532 | cl_sc1_clksyncff_4x tap_spc7_mb_cs_sync_reg ( | |
5533 | .si ( tap_spc7_mb_cs_sync_reg_scanin ), | |
5534 | .so ( tap_spc7_mb_cs_sync_reg_scanout ), | |
5535 | .l1clk ( l1clk ), | |
5536 | .d ( tap_spc7_mb_clk_stop ), | |
5537 | .q ( tap_spc7_mb_clk_stop_sync ), | |
5538 | .siclk(siclk), | |
5539 | .soclk(soclk)); | |
5540 | ||
5541 | cl_sc1_clksyncff_4x tap_spc6_mb_cs_sync_reg ( | |
5542 | .si ( tap_spc6_mb_cs_sync_reg_scanin ), | |
5543 | .so ( tap_spc6_mb_cs_sync_reg_scanout ), | |
5544 | .l1clk ( l1clk ), | |
5545 | .d ( tap_spc6_mb_clk_stop ), | |
5546 | .q ( tap_spc6_mb_clk_stop_sync ), | |
5547 | .siclk(siclk), | |
5548 | .soclk(soclk)); | |
5549 | ||
5550 | cl_sc1_clksyncff_4x tap_spc5_mb_cs_sync_reg ( | |
5551 | .si ( tap_spc5_mb_cs_sync_reg_scanin ), | |
5552 | .so ( tap_spc5_mb_cs_sync_reg_scanout ), | |
5553 | .l1clk ( l1clk ), | |
5554 | .d ( tap_spc5_mb_clk_stop ), | |
5555 | .q ( tap_spc5_mb_clk_stop_sync ), | |
5556 | .siclk(siclk), | |
5557 | .soclk(soclk)); | |
5558 | ||
5559 | cl_sc1_clksyncff_4x tap_spc4_mb_cs_sync_reg ( | |
5560 | .si ( tap_spc4_mb_cs_sync_reg_scanin ), | |
5561 | .so ( tap_spc4_mb_cs_sync_reg_scanout ), | |
5562 | .l1clk ( l1clk ), | |
5563 | .d ( tap_spc4_mb_clk_stop ), | |
5564 | .q ( tap_spc4_mb_clk_stop_sync ), | |
5565 | .siclk(siclk), | |
5566 | .soclk(soclk)); | |
5567 | ||
5568 | cl_sc1_clksyncff_4x tap_spc3_mb_cs_sync_reg ( | |
5569 | .si ( tap_spc3_mb_cs_sync_reg_scanin ), | |
5570 | .so ( tap_spc3_mb_cs_sync_reg_scanout ), | |
5571 | .l1clk ( l1clk ), | |
5572 | .d ( tap_spc3_mb_clk_stop ), | |
5573 | .q ( tap_spc3_mb_clk_stop_sync ), | |
5574 | .siclk(siclk), | |
5575 | .soclk(soclk)); | |
5576 | ||
5577 | cl_sc1_clksyncff_4x tap_spc2_mb_cs_sync_reg ( | |
5578 | .si ( tap_spc2_mb_cs_sync_reg_scanin ), | |
5579 | .so ( tap_spc2_mb_cs_sync_reg_scanout ), | |
5580 | .l1clk ( l1clk ), | |
5581 | .d ( tap_spc2_mb_clk_stop ), | |
5582 | .q ( tap_spc2_mb_clk_stop_sync ), | |
5583 | .siclk(siclk), | |
5584 | .soclk(soclk)); | |
5585 | ||
5586 | cl_sc1_clksyncff_4x tap_spc1_mb_cs_sync_reg ( | |
5587 | .si ( tap_spc1_mb_cs_sync_reg_scanin ), | |
5588 | .so ( tap_spc1_mb_cs_sync_reg_scanout ), | |
5589 | .l1clk ( l1clk ), | |
5590 | .d ( tap_spc1_mb_clk_stop ), | |
5591 | .q ( tap_spc1_mb_clk_stop_sync ), | |
5592 | .siclk(siclk), | |
5593 | .soclk(soclk)); | |
5594 | ||
5595 | cl_sc1_clksyncff_4x tap_spc0_mb_cs_sync_reg ( | |
5596 | .si ( tap_spc0_mb_cs_sync_reg_scanin ), | |
5597 | .so ( tap_spc0_mb_cs_sync_reg_scanout ), | |
5598 | .l1clk ( l1clk ), | |
5599 | .d ( tap_spc0_mb_clk_stop ), | |
5600 | .q ( tap_spc0_mb_clk_stop_sync ), | |
5601 | .siclk(siclk), | |
5602 | .soclk(soclk)); | |
5603 | ||
5604 | //================================================== | |
5605 | // L2T MBIST Clock Stop | |
5606 | //================================================== | |
5607 | ||
5608 | cl_sc1_clksyncff_4x l2t7_mbist_cs_sync_reg ( | |
5609 | .si ( l2t7_mbist_cs_sync_reg_scanin ), | |
5610 | .so ( l2t7_mbist_cs_sync_reg_scanout ), | |
5611 | .l1clk ( l1clk ), | |
5612 | .d ( l2t7_mbist_clk_stop ), | |
5613 | .q ( l2t7_mbist_clk_stop_sync ), | |
5614 | .siclk(siclk), | |
5615 | .soclk(soclk)); | |
5616 | ||
5617 | cl_sc1_clksyncff_4x l2t6_mbist_cs_sync_reg ( | |
5618 | .si ( l2t6_mbist_cs_sync_reg_scanin ), | |
5619 | .so ( l2t6_mbist_cs_sync_reg_scanout ), | |
5620 | .l1clk ( l1clk ), | |
5621 | .d ( l2t6_mbist_clk_stop ), | |
5622 | .q ( l2t6_mbist_clk_stop_sync ), | |
5623 | .siclk(siclk), | |
5624 | .soclk(soclk)); | |
5625 | ||
5626 | cl_sc1_clksyncff_4x l2t5_mbist_cs_sync_reg ( | |
5627 | .si ( l2t5_mbist_cs_sync_reg_scanin ), | |
5628 | .so ( l2t5_mbist_cs_sync_reg_scanout ), | |
5629 | .l1clk ( l1clk ), | |
5630 | .d ( l2t5_mbist_clk_stop ), | |
5631 | .q ( l2t5_mbist_clk_stop_sync ), | |
5632 | .siclk(siclk), | |
5633 | .soclk(soclk)); | |
5634 | ||
5635 | cl_sc1_clksyncff_4x l2t4_mbist_cs_sync_reg ( | |
5636 | .si ( l2t4_mbist_cs_sync_reg_scanin ), | |
5637 | .so ( l2t4_mbist_cs_sync_reg_scanout ), | |
5638 | .l1clk ( l1clk ), | |
5639 | .d ( l2t4_mbist_clk_stop ), | |
5640 | .q ( l2t4_mbist_clk_stop_sync ), | |
5641 | .siclk(siclk), | |
5642 | .soclk(soclk)); | |
5643 | ||
5644 | cl_sc1_clksyncff_4x l2t3_mbist_cs_sync_reg ( | |
5645 | .si ( l2t3_mbist_cs_sync_reg_scanin ), | |
5646 | .so ( l2t3_mbist_cs_sync_reg_scanout ), | |
5647 | .l1clk ( l1clk ), | |
5648 | .d ( l2t3_mbist_clk_stop ), | |
5649 | .q ( l2t3_mbist_clk_stop_sync ), | |
5650 | .siclk(siclk), | |
5651 | .soclk(soclk)); | |
5652 | ||
5653 | cl_sc1_clksyncff_4x l2t2_mbist_cs_sync_reg ( | |
5654 | .si ( l2t2_mbist_cs_sync_reg_scanin ), | |
5655 | .so ( l2t2_mbist_cs_sync_reg_scanout ), | |
5656 | .l1clk ( l1clk ), | |
5657 | .d ( l2t2_mbist_clk_stop ), | |
5658 | .q ( l2t2_mbist_clk_stop_sync ), | |
5659 | .siclk(siclk), | |
5660 | .soclk(soclk)); | |
5661 | ||
5662 | cl_sc1_clksyncff_4x l2t1_mbist_cs_sync_reg ( | |
5663 | .si ( l2t1_mbist_cs_sync_reg_scanin ), | |
5664 | .so ( l2t1_mbist_cs_sync_reg_scanout ), | |
5665 | .l1clk ( l1clk ), | |
5666 | .d ( l2t1_mbist_clk_stop ), | |
5667 | .q ( l2t1_mbist_clk_stop_sync ), | |
5668 | .siclk(siclk), | |
5669 | .soclk(soclk)); | |
5670 | ||
5671 | cl_sc1_clksyncff_4x l2t0_mbist_cs_sync_reg ( | |
5672 | .si ( l2t0_mbist_cs_sync_reg_scanin ), | |
5673 | .so ( l2t0_mbist_cs_sync_reg_scanout ), | |
5674 | .l1clk ( l1clk ), | |
5675 | .d ( l2t0_mbist_clk_stop ), | |
5676 | .q ( l2t0_mbist_clk_stop_sync ), | |
5677 | .siclk(siclk), | |
5678 | .soclk(soclk)); | |
5679 | ||
5680 | //================================================== | |
5681 | // L2B MBIST Clock Stop | |
5682 | //================================================== | |
5683 | cl_sc1_clksyncff_4x l2b7_mbist_cs_sync_reg ( | |
5684 | .si ( l2b7_mbist_cs_sync_reg_scanin ), | |
5685 | .so ( l2b7_mbist_cs_sync_reg_scanout ), | |
5686 | .l1clk ( l1clk ), | |
5687 | .d ( l2b7_mbist_clk_stop ), | |
5688 | .q ( l2b7_mbist_clk_stop_sync ), | |
5689 | .siclk(siclk), | |
5690 | .soclk(soclk)); | |
5691 | ||
5692 | cl_sc1_clksyncff_4x l2b6_mbist_cs_sync_reg ( | |
5693 | .si ( l2b6_mbist_cs_sync_reg_scanin ), | |
5694 | .so ( l2b6_mbist_cs_sync_reg_scanout ), | |
5695 | .l1clk ( l1clk ), | |
5696 | .d ( l2b6_mbist_clk_stop ), | |
5697 | .q ( l2b6_mbist_clk_stop_sync ), | |
5698 | .siclk(siclk), | |
5699 | .soclk(soclk)); | |
5700 | ||
5701 | cl_sc1_clksyncff_4x l2b5_mbist_cs_sync_reg ( | |
5702 | .si ( l2b5_mbist_cs_sync_reg_scanin ), | |
5703 | .so ( l2b5_mbist_cs_sync_reg_scanout ), | |
5704 | .l1clk ( l1clk ), | |
5705 | .d ( l2b5_mbist_clk_stop ), | |
5706 | .q ( l2b5_mbist_clk_stop_sync ), | |
5707 | .siclk(siclk), | |
5708 | .soclk(soclk)); | |
5709 | ||
5710 | cl_sc1_clksyncff_4x l2b4_mbist_cs_sync_reg ( | |
5711 | .si ( l2b4_mbist_cs_sync_reg_scanin ), | |
5712 | .so ( l2b4_mbist_cs_sync_reg_scanout ), | |
5713 | .l1clk ( l1clk ), | |
5714 | .d ( l2b4_mbist_clk_stop ), | |
5715 | .q ( l2b4_mbist_clk_stop_sync ), | |
5716 | .siclk(siclk), | |
5717 | .soclk(soclk)); | |
5718 | ||
5719 | cl_sc1_clksyncff_4x l2b3_mbist_cs_sync_reg ( | |
5720 | .si ( l2b3_mbist_cs_sync_reg_scanin ), | |
5721 | .so ( l2b3_mbist_cs_sync_reg_scanout ), | |
5722 | .l1clk ( l1clk ), | |
5723 | .d ( l2b3_mbist_clk_stop ), | |
5724 | .q ( l2b3_mbist_clk_stop_sync ), | |
5725 | .siclk(siclk), | |
5726 | .soclk(soclk)); | |
5727 | ||
5728 | cl_sc1_clksyncff_4x l2b2_mbist_cs_sync_reg ( | |
5729 | .si ( l2b2_mbist_cs_sync_reg_scanin ), | |
5730 | .so ( l2b2_mbist_cs_sync_reg_scanout ), | |
5731 | .l1clk ( l1clk ), | |
5732 | .d ( l2b2_mbist_clk_stop ), | |
5733 | .q ( l2b2_mbist_clk_stop_sync ), | |
5734 | .siclk(siclk), | |
5735 | .soclk(soclk)); | |
5736 | ||
5737 | cl_sc1_clksyncff_4x l2b1_mbist_cs_sync_reg ( | |
5738 | .si ( l2b1_mbist_cs_sync_reg_scanin ), | |
5739 | .so ( l2b1_mbist_cs_sync_reg_scanout ), | |
5740 | .l1clk ( l1clk ), | |
5741 | .d ( l2b1_mbist_clk_stop ), | |
5742 | .q ( l2b1_mbist_clk_stop_sync ), | |
5743 | .siclk(siclk), | |
5744 | .soclk(soclk)); | |
5745 | ||
5746 | cl_sc1_clksyncff_4x l2b0_mbist_cs_sync_reg ( | |
5747 | .si ( l2b0_mbist_cs_sync_reg_scanin ), | |
5748 | .so ( l2b0_mbist_cs_sync_reg_scanout ), | |
5749 | .l1clk ( l1clk ), | |
5750 | .d ( l2b0_mbist_clk_stop ), | |
5751 | .q ( l2b0_mbist_clk_stop_sync ), | |
5752 | .siclk(siclk), | |
5753 | .soclk(soclk)); | |
5754 | ||
5755 | //================================================== | |
5756 | // Other SOC MBIST Clock Stop | |
5757 | //================================================== | |
5758 | cl_sc1_clksyncff_4x soc0_mbist_cs_sync_reg ( | |
5759 | .si ( soc0_mbist_cs_sync_reg_scanin ), | |
5760 | .so ( soc0_mbist_cs_sync_reg_scanout ), | |
5761 | .l1clk ( l1clk ), | |
5762 | .d ( soc0_mbist_clk_stop ), | |
5763 | .q ( soc0_mbist_clk_stop_sync ), | |
5764 | .siclk(siclk), | |
5765 | .soclk(soclk)); | |
5766 | ||
5767 | cl_sc1_clksyncff_4x mcu3_mbist_cs_sync_reg ( | |
5768 | .si ( mcu3_mbist_cs_sync_reg_scanin ), | |
5769 | .so ( mcu3_mbist_cs_sync_reg_scanout ), | |
5770 | .l1clk ( l1clk ), | |
5771 | .d ( mcu3_mbist_clk_stop ), | |
5772 | .q ( mcu3_mbist_clk_stop_sync ), | |
5773 | .siclk(siclk), | |
5774 | .soclk(soclk)); | |
5775 | ||
5776 | cl_sc1_clksyncff_4x mcu2_mbist_cs_sync_reg ( | |
5777 | .si ( mcu2_mbist_cs_sync_reg_scanin ), | |
5778 | .so ( mcu2_mbist_cs_sync_reg_scanout ), | |
5779 | .l1clk ( l1clk ), | |
5780 | .d ( mcu2_mbist_clk_stop ), | |
5781 | .q ( mcu2_mbist_clk_stop_sync ), | |
5782 | .siclk(siclk), | |
5783 | .soclk(soclk)); | |
5784 | ||
5785 | cl_sc1_clksyncff_4x mcu1_mbist_cs_sync_reg ( | |
5786 | .si ( mcu1_mbist_cs_sync_reg_scanin ), | |
5787 | .so ( mcu1_mbist_cs_sync_reg_scanout ), | |
5788 | .l1clk ( l1clk ), | |
5789 | .d ( mcu1_mbist_clk_stop ), | |
5790 | .q ( mcu1_mbist_clk_stop_sync ), | |
5791 | .siclk(siclk), | |
5792 | .soclk(soclk)); | |
5793 | ||
5794 | cl_sc1_clksyncff_4x mcu0_mbist_cs_sync_reg ( | |
5795 | .si ( mcu0_mbist_cs_sync_reg_scanin ), | |
5796 | .so ( mcu0_mbist_cs_sync_reg_scanout ), | |
5797 | .l1clk ( l1clk ), | |
5798 | .d ( mcu0_mbist_clk_stop ), | |
5799 | .q ( mcu0_mbist_clk_stop_sync ), | |
5800 | .siclk(siclk), | |
5801 | .soclk(soclk)); | |
5802 | ||
5803 | cl_sc1_clksyncff_4x dmu_mbist_cs_sync_reg ( | |
5804 | .si ( dmu_mbist_cs_sync_reg_scanin ), | |
5805 | .so ( dmu_mbist_cs_sync_reg_scanout ), | |
5806 | .l1clk ( l1clk ), | |
5807 | .d ( dmu_mbist_clk_stop ), | |
5808 | .q ( dmu_mbist_clk_stop_sync ), | |
5809 | .siclk(siclk), | |
5810 | .soclk(soclk)); | |
5811 | ||
5812 | cl_sc1_clksyncff_4x peu_mbist_cs_sync_reg ( | |
5813 | .si ( peu_mbist_cs_sync_reg_scanin ), | |
5814 | .so ( peu_mbist_cs_sync_reg_scanout ), | |
5815 | .l1clk ( l1clk ), | |
5816 | .d ( peu_mbist_clk_stop ), | |
5817 | .q ( peu_mbist_clk_stop_sync ), | |
5818 | .siclk(siclk), | |
5819 | .soclk(soclk)); | |
5820 | ||
5821 | cl_sc1_clksyncff_4x rdp_mbist_cs_sync_reg ( | |
5822 | .si ( rdp_mbist_cs_sync_reg_scanin ), | |
5823 | .so ( rdp_mbist_cs_sync_reg_scanout ), | |
5824 | .l1clk ( l1clk ), | |
5825 | .d ( rdp_mbist_clk_stop ), | |
5826 | .q ( rdp_mbist_clk_stop_sync ), | |
5827 | .siclk(siclk), | |
5828 | .soclk(soclk)); | |
5829 | ||
5830 | cl_sc1_clksyncff_4x rtx_mbist_cs_sync_reg ( | |
5831 | .si ( rtx_mbist_cs_sync_reg_scanin ), | |
5832 | .so ( rtx_mbist_cs_sync_reg_scanout ), | |
5833 | .l1clk ( l1clk ), | |
5834 | .d ( rtx_mbist_clk_stop ), | |
5835 | .q ( rtx_mbist_clk_stop_sync ), | |
5836 | .siclk(siclk), | |
5837 | .soclk(soclk)); | |
5838 | ||
5839 | cl_sc1_clksyncff_4x tds_mbist_cs_sync_reg ( | |
5840 | .si ( tds_mbist_cs_sync_reg_scanin ), | |
5841 | .so ( tds_mbist_cs_sync_reg_scanout ), | |
5842 | .l1clk ( l1clk ), | |
5843 | .d ( tds_mbist_clk_stop ), | |
5844 | .q ( tds_mbist_clk_stop_sync ), | |
5845 | .siclk(siclk), | |
5846 | .soclk(soclk)); | |
5847 | ||
5848 | //================================================== | |
5849 | // SPC Shadow Scan Clock Stop | |
5850 | //================================================== | |
5851 | cl_sc1_clksyncff_4x jtag_spc7_ss_cs_sync_reg ( | |
5852 | .si ( jtag_spc7_ss_cs_sync_reg_scanin ), | |
5853 | .so ( jtag_spc7_ss_cs_sync_reg_scanout ), | |
5854 | .l1clk ( l1clk ), | |
5855 | .d ( jtag_spc7_shscan_clk_stop ), | |
5856 | .q ( jtag_spc7_shscan_clk_stop_sync ), | |
5857 | .siclk(siclk), | |
5858 | .soclk(soclk)); | |
5859 | ||
5860 | cl_sc1_clksyncff_4x jtag_spc6_ss_cs_sync_reg ( | |
5861 | .si ( jtag_spc6_ss_cs_sync_reg_scanin ), | |
5862 | .so ( jtag_spc6_ss_cs_sync_reg_scanout ), | |
5863 | .l1clk ( l1clk ), | |
5864 | .d ( jtag_spc6_shscan_clk_stop ), | |
5865 | .q ( jtag_spc6_shscan_clk_stop_sync ), | |
5866 | .siclk(siclk), | |
5867 | .soclk(soclk)); | |
5868 | ||
5869 | cl_sc1_clksyncff_4x jtag_spc5_ss_cs_sync_reg ( | |
5870 | .si ( jtag_spc5_ss_cs_sync_reg_scanin ), | |
5871 | .so ( jtag_spc5_ss_cs_sync_reg_scanout ), | |
5872 | .l1clk ( l1clk ), | |
5873 | .d ( jtag_spc5_shscan_clk_stop ), | |
5874 | .q ( jtag_spc5_shscan_clk_stop_sync ), | |
5875 | .siclk(siclk), | |
5876 | .soclk(soclk)); | |
5877 | ||
5878 | cl_sc1_clksyncff_4x jtag_spc4_ss_cs_sync_reg ( | |
5879 | .si ( jtag_spc4_ss_cs_sync_reg_scanin ), | |
5880 | .so ( jtag_spc4_ss_cs_sync_reg_scanout ), | |
5881 | .l1clk ( l1clk ), | |
5882 | .d ( jtag_spc4_shscan_clk_stop ), | |
5883 | .q ( jtag_spc4_shscan_clk_stop_sync ), | |
5884 | .siclk(siclk), | |
5885 | .soclk(soclk)); | |
5886 | ||
5887 | cl_sc1_clksyncff_4x jtag_spc3_ss_cs_sync_reg ( | |
5888 | .si ( jtag_spc3_ss_cs_sync_reg_scanin ), | |
5889 | .so ( jtag_spc3_ss_cs_sync_reg_scanout ), | |
5890 | .l1clk ( l1clk ), | |
5891 | .d ( jtag_spc3_shscan_clk_stop ), | |
5892 | .q ( jtag_spc3_shscan_clk_stop_sync ), | |
5893 | .siclk(siclk), | |
5894 | .soclk(soclk)); | |
5895 | ||
5896 | cl_sc1_clksyncff_4x jtag_spc2_ss_cs_sync_reg ( | |
5897 | .si ( jtag_spc2_ss_cs_sync_reg_scanin ), | |
5898 | .so ( jtag_spc2_ss_cs_sync_reg_scanout ), | |
5899 | .l1clk ( l1clk ), | |
5900 | .d ( jtag_spc2_shscan_clk_stop ), | |
5901 | .q ( jtag_spc2_shscan_clk_stop_sync ), | |
5902 | .siclk(siclk), | |
5903 | .soclk(soclk)); | |
5904 | ||
5905 | cl_sc1_clksyncff_4x jtag_spc1_ss_cs_sync_reg ( | |
5906 | .si ( jtag_spc1_ss_cs_sync_reg_scanin ), | |
5907 | .so ( jtag_spc1_ss_cs_sync_reg_scanout ), | |
5908 | .l1clk ( l1clk ), | |
5909 | .d ( jtag_spc1_shscan_clk_stop ), | |
5910 | .q ( jtag_spc1_shscan_clk_stop_sync ), | |
5911 | .siclk(siclk), | |
5912 | .soclk(soclk)); | |
5913 | ||
5914 | cl_sc1_clksyncff_4x jtag_spc0_ss_cs_sync_reg ( | |
5915 | .si ( jtag_spc0_ss_cs_sync_reg_scanin ), | |
5916 | .so ( jtag_spc0_ss_cs_sync_reg_scanout ), | |
5917 | .l1clk ( l1clk ), | |
5918 | .d ( jtag_spc0_shscan_clk_stop ), | |
5919 | .q ( jtag_spc0_shscan_clk_stop_sync ), | |
5920 | .siclk(siclk), | |
5921 | .soclk(soclk)); | |
5922 | ||
5923 | //================================================== | |
5924 | // L2T Shadow Scan Clock Stop | |
5925 | //================================================== | |
5926 | cl_sc1_clksyncff_4x jtag_l2t7_ss_cs_sync_reg ( | |
5927 | .si ( jtag_l2t7_ss_cs_sync_reg_scanin ), | |
5928 | .so ( jtag_l2t7_ss_cs_sync_reg_scanout ), | |
5929 | .l1clk ( l1clk ), | |
5930 | .d ( jtag_l2t7_shscan_clk_stop ), | |
5931 | .q ( jtag_l2t7_shscan_clk_stop_sync ), | |
5932 | .siclk(siclk), | |
5933 | .soclk(soclk)); | |
5934 | ||
5935 | cl_sc1_clksyncff_4x jtag_l2t6_ss_cs_sync_reg ( | |
5936 | .si ( jtag_l2t6_ss_cs_sync_reg_scanin ), | |
5937 | .so ( jtag_l2t6_ss_cs_sync_reg_scanout ), | |
5938 | .l1clk ( l1clk ), | |
5939 | .d ( jtag_l2t6_shscan_clk_stop ), | |
5940 | .q ( jtag_l2t6_shscan_clk_stop_sync ), | |
5941 | .siclk(siclk), | |
5942 | .soclk(soclk)); | |
5943 | ||
5944 | cl_sc1_clksyncff_4x jtag_l2t5_ss_cs_sync_reg ( | |
5945 | .si ( jtag_l2t5_ss_cs_sync_reg_scanin ), | |
5946 | .so ( jtag_l2t5_ss_cs_sync_reg_scanout ), | |
5947 | .l1clk ( l1clk ), | |
5948 | .d ( jtag_l2t5_shscan_clk_stop ), | |
5949 | .q ( jtag_l2t5_shscan_clk_stop_sync ), | |
5950 | .siclk(siclk), | |
5951 | .soclk(soclk)); | |
5952 | ||
5953 | cl_sc1_clksyncff_4x jtag_l2t4_ss_cs_sync_reg ( | |
5954 | .si ( jtag_l2t4_ss_cs_sync_reg_scanin ), | |
5955 | .so ( jtag_l2t4_ss_cs_sync_reg_scanout ), | |
5956 | .l1clk ( l1clk ), | |
5957 | .d ( jtag_l2t4_shscan_clk_stop ), | |
5958 | .q ( jtag_l2t4_shscan_clk_stop_sync ), | |
5959 | .siclk(siclk), | |
5960 | .soclk(soclk)); | |
5961 | ||
5962 | cl_sc1_clksyncff_4x jtag_l2t3_ss_cs_sync_reg ( | |
5963 | .si ( jtag_l2t3_ss_cs_sync_reg_scanin ), | |
5964 | .so ( jtag_l2t3_ss_cs_sync_reg_scanout ), | |
5965 | .l1clk ( l1clk ), | |
5966 | .d ( jtag_l2t3_shscan_clk_stop ), | |
5967 | .q ( jtag_l2t3_shscan_clk_stop_sync ), | |
5968 | .siclk(siclk), | |
5969 | .soclk(soclk)); | |
5970 | ||
5971 | cl_sc1_clksyncff_4x jtag_l2t2_ss_cs_sync_reg ( | |
5972 | .si ( jtag_l2t2_ss_cs_sync_reg_scanin ), | |
5973 | .so ( jtag_l2t2_ss_cs_sync_reg_scanout ), | |
5974 | .l1clk ( l1clk ), | |
5975 | .d ( jtag_l2t2_shscan_clk_stop ), | |
5976 | .q ( jtag_l2t2_shscan_clk_stop_sync ), | |
5977 | .siclk(siclk), | |
5978 | .soclk(soclk)); | |
5979 | ||
5980 | cl_sc1_clksyncff_4x jtag_l2t1_ss_cs_sync_reg ( | |
5981 | .si ( jtag_l2t1_ss_cs_sync_reg_scanin ), | |
5982 | .so ( jtag_l2t1_ss_cs_sync_reg_scanout ), | |
5983 | .l1clk ( l1clk ), | |
5984 | .d ( jtag_l2t1_shscan_clk_stop ), | |
5985 | .q ( jtag_l2t1_shscan_clk_stop_sync ), | |
5986 | .siclk(siclk), | |
5987 | .soclk(soclk)); | |
5988 | ||
5989 | cl_sc1_clksyncff_4x jtag_l2t0_ss_cs_sync_reg ( | |
5990 | .si ( jtag_l2t0_ss_cs_sync_reg_scanin ), | |
5991 | .so ( jtag_l2t0_ss_cs_sync_reg_scanout ), | |
5992 | .l1clk ( l1clk ), | |
5993 | .d ( jtag_l2t0_shscan_clk_stop ), | |
5994 | .q ( jtag_l2t0_shscan_clk_stop_sync ), | |
5995 | .siclk(siclk), | |
5996 | .soclk(soclk)); | |
5997 | ||
5998 | cl_sc1_clksyncff_4x jtag_spc_ss_pce_ov_sync_reg ( | |
5999 | .si ( jtag_spc_ss_pce_ov_sync_reg_scanin ), | |
6000 | .so ( jtag_spc_ss_pce_ov_sync_reg_scanout ), | |
6001 | .l1clk ( l1clk ), | |
6002 | .d ( jtag_spc_shscan_pce_ov ), | |
6003 | .q ( jtag_spc_shscan_pce_ov_sync ), | |
6004 | .siclk(siclk), | |
6005 | .soclk(soclk)); | |
6006 | ||
6007 | cl_sc1_clksyncff_4x jtag_l2t_ss_pce_ov_sync_reg ( | |
6008 | .si ( jtag_l2t_ss_pce_ov_sync_reg_scanin ), | |
6009 | .so ( jtag_l2t_ss_pce_ov_sync_reg_scanout ), | |
6010 | .l1clk ( l1clk ), | |
6011 | .d ( jtag_l2t_shscan_pce_ov ), | |
6012 | .q ( jtag_l2t_shscan_pce_ov_sync ), | |
6013 | .siclk(siclk), | |
6014 | .soclk(soclk)); | |
6015 | ||
6016 | cl_sc1_clksyncff_4x jtag_clk_stop_req_sync_reg ( | |
6017 | .si ( jtag_clk_stop_req_sync_reg_scanin ), | |
6018 | .so ( jtag_clk_stop_req_sync_reg_scanout ), | |
6019 | .l1clk ( l1clk ), | |
6020 | .d ( jtag_clk_stop_req ), | |
6021 | .q ( jtag_clk_stop_req_sync ), | |
6022 | .siclk(siclk), | |
6023 | .soclk(soclk)); | |
6024 | ||
6025 | cl_sc1_clksyncff_4x jtag_efu_clear_instr_sync_reg ( | |
6026 | .si ( jtag_efu_clear_instr_sync_reg_scanin ), | |
6027 | .so ( jtag_efu_clear_instr_sync_reg_scanout ), | |
6028 | .l1clk ( l1clk ), | |
6029 | .d ( jtag_efu_clear_instr ), | |
6030 | .q ( jtag_efu_clear_instr_sync ), | |
6031 | .siclk(siclk), | |
6032 | .soclk(soclk)); | |
6033 | ||
6034 | cl_sc1_clksyncff_4x instr_sstop_csmode_sync_reg ( | |
6035 | .si ( instr_sstop_csmode_sync_reg_scanin ), | |
6036 | .so ( instr_sstop_csmode_sync_reg_scanout ), | |
6037 | .l1clk ( l1clk ), | |
6038 | .d ( instr_sstop_csmode ), | |
6039 | .q ( instr_sstop_csmode_sync ), | |
6040 | .siclk(siclk), | |
6041 | .soclk(soclk)); | |
6042 | ||
6043 | cl_sc1_clksyncff_4x sync_ff_jtag_clkdly_upd ( | |
6044 | .si ( sync_ff_jtagclkdlyupd_scanin ), | |
6045 | .so ( sync_ff_jtagclkdlyupd_scanout ), | |
6046 | .l1clk ( l1clk ), | |
6047 | .d ( jtag_upd_cntdly ), | |
6048 | .q ( jtag_upd_cntdly_sync ), | |
6049 | .siclk(siclk), | |
6050 | .soclk(soclk)); | |
6051 | //================================================== | |
6052 | // Synchronize jtag serial scan to send to ccu mux select | |
6053 | //================================================== | |
6054 | cl_sc1_clksyncff_4x jtag_serscan_sync_reg ( | |
6055 | .si ( jtag_serscan_sync_reg_scanin ), | |
6056 | .so ( jtag_serscan_sync_reg_scanout ), | |
6057 | .l1clk ( l1clk ), | |
6058 | .d ( jt_scan_mtmode ), | |
6059 | .q ( jt_scan_mtmode_sync ), | |
6060 | .siclk(siclk), | |
6061 | .soclk(soclk)); | |
6062 | ||
6063 | ||
6064 | //====================================================================== | |
6065 | // Transfer Signals to L2T Using IO Clock | |
6066 | // Shadow Scan Clock Stops, Shadow Scan PCE OV & Shadow Scan ID | |
6067 | //====================================================================== | |
6068 | assign shscan_clk_stop_sync[20:0] = { | |
6069 | jtag_spc7_shscan_clk_stop_sync, jtag_spc6_shscan_clk_stop_sync, | |
6070 | jtag_spc5_shscan_clk_stop_sync, jtag_spc4_shscan_clk_stop_sync, | |
6071 | jtag_spc3_shscan_clk_stop_sync, jtag_spc2_shscan_clk_stop_sync, | |
6072 | jtag_spc1_shscan_clk_stop_sync, jtag_spc0_shscan_clk_stop_sync, | |
6073 | jtag_l2t7_shscan_clk_stop_sync, jtag_l2t6_shscan_clk_stop_sync, | |
6074 | jtag_l2t5_shscan_clk_stop_sync, jtag_l2t4_shscan_clk_stop_sync, | |
6075 | jtag_l2t3_shscan_clk_stop_sync, jtag_l2t2_shscan_clk_stop_sync, | |
6076 | jtag_l2t1_shscan_clk_stop_sync, jtag_l2t0_shscan_clk_stop_sync, | |
6077 | jtag_spc_shscan_pce_ov_sync, jtag_l2t_shscan_pce_ov_sync, | |
6078 | jtag_spc_shscanid}; | |
6079 | ||
6080 | tcu_sigmux_ctl_msff_ctl_macro__en_1__width_21 shscan_clk_stop_io_sync_reg ( | |
6081 | .scan_in ( shscan_clk_stop_io_sync_reg_scanin ), | |
6082 | .scan_out ( shscan_clk_stop_io_sync_reg_scanout ), | |
6083 | .en ( io_cmp_sync_en_local ), | |
6084 | .din ( shscan_clk_stop_sync[20:0] ), | |
6085 | .dout ( shscan_clk_stop_io[20:0] ), | |
6086 | .l1clk ( l1clk ), | |
6087 | .siclk(siclk), | |
6088 | .soclk(soclk)); | |
6089 | ||
6090 | assign { | |
6091 | tcu_spc7_shscan_clk_stop, tcu_spc6_shscan_clk_stop, | |
6092 | tcu_spc5_shscan_clk_stop, tcu_spc4_shscan_clk_stop, | |
6093 | tcu_spc3_shscan_clk_stop, tcu_spc2_shscan_clk_stop, | |
6094 | tcu_spc1_shscan_clk_stop, tcu_spc0_shscan_clk_stop, | |
6095 | tcu_l2t7_shscan_clk_stop, tcu_l2t6_shscan_clk_stop, | |
6096 | tcu_l2t5_shscan_clk_stop, tcu_l2t4_shscan_clk_stop, | |
6097 | tcu_l2t3_shscan_clk_stop, tcu_l2t2_shscan_clk_stop, | |
6098 | tcu_l2t1_shscan_clk_stop, tcu_l2t0_shscan_clk_stop, | |
6099 | tcu_spc_shscan_pce_ov, tcu_l2t_shscan_pce_ov, | |
6100 | tcu_spc_shscanid} | |
6101 | = shscan_clk_stop_io; | |
6102 | ||
6103 | //================================================== | |
6104 | // Spare Gates | |
6105 | //================================================== | |
6106 | // ---------------------------------------------------------------------- | |
6107 | // Removed for ECO to make flops visible in SunV | |
6108 | // | |
6109 | //spare_ctl_macro spare (num=9) ( | |
6110 | // .l1clk ( l1clk ), | |
6111 | // .scan_in ( spare_scanin ), | |
6112 | // .scan_out ( spare_scanout )); | |
6113 | ||
6114 | // Added for ECO to make flops visible | |
6115 | ||
6116 | // - this is an expansion of spare_ctl_macro with just the gates | |
6117 | tcu_sigmux_ctl_spare_ctl_macro__flops_0__num_9 spare_gates ( | |
6118 | ); | |
6119 | ||
6120 | tcu_sigmux_ctl_msff_ctl_macro__scanreverse_1__width_9 spare_flops ( | |
6121 | .scan_in(spare_scanin), | |
6122 | .scan_out(spare_scanout), | |
6123 | .l1clk(l1clk), | |
6124 | .din (spare_flops_d[8:0]), | |
6125 | .dout (spare_flops_q[8:0]), | |
6126 | .siclk(siclk), | |
6127 | .soclk(soclk) | |
6128 | ); | |
6129 | ||
6130 | assign spare_flops_d[8] = 1'b0; | |
6131 | assign spare_flops_d[7] = 1'b0; | |
6132 | assign spare_flops_d[6] = 1'b0; | |
6133 | assign spare_flops_d[5] = 1'b0; | |
6134 | assign spare_flops_d[4] = 1'b0; | |
6135 | assign spare_flops_d[3] = atpg_muxtest; // ECO MUXTEST | |
6136 | assign spare_flops_d[2] = 1'b0; | |
6137 | assign spare_flops_d[1] = 1'b0; | |
6138 | assign spare_flops_d[0] = 1'b0; | |
6139 | ||
6140 | assign spare_flops_unused[8] = spare_flops_q[8]; | |
6141 | assign spare_flops_unused[7] = spare_flops_q[7]; | |
6142 | assign spare_flops_unused[6] = spare_flops_q[6]; | |
6143 | assign spare_flops_unused[5] = spare_flops_q[5]; | |
6144 | assign spare_flops_unused[4] = spare_flops_q[4]; | |
6145 | assign atpg_muxtest = spare_flops_q[3]; // ECO MUXTEST | |
6146 | assign spare_flops_unused[2] = spare_flops_q[2]; | |
6147 | assign spare_flops_unused[1] = spare_flops_q[1]; | |
6148 | assign spare0_flop_unused[0] = spare_flops_q[0]; | |
6149 | ||
6150 | // ---------------------------------------------------------------------- | |
6151 | ||
6152 | // -hand modified to stitch non-scan (except for mfg mode) flops | |
6153 | // fixscan start: | |
6154 | ||
6155 | // These are flops that are "No-Flush" (_nf_), excluded from flush reset | |
6156 | //assign tcusig_fgo_nf_reg_scanin = int_scan_in ; | |
6157 | //assign tcusig_flush_nf_reg_scanin = tcusig_fgo_nf_reg_scanout ; | |
6158 | ||
6159 | //assign tcusig_foncnt_nf_reg_scanin = tcusig_flush_nf_reg_scanout ; | |
6160 | assign ucb_csr_wr_sync_reg_scanin = int_scan_in ; | |
6161 | assign tcusig_foncnt_nf_reg_scanin = ucb_csr_wr_sync_reg_scanout ; | |
6162 | assign tcusig_foffcnt_nf_reg_scanin = tcusig_foncnt_nf_reg_scanout ; | |
6163 | assign tcusig_fq24_nf_reg_scanin = tcusig_foffcnt_nf_reg_scanout ; | |
6164 | assign tcusig_fq48_nf_reg_scanin = tcusig_fq24_nf_reg_scanout ; | |
6165 | assign tcusig_fq72_nf_reg_scanin = tcusig_fq48_nf_reg_scanout ; | |
6166 | assign tcusig_fq96_nf_reg_scanin = tcusig_fq72_nf_reg_scanout ; | |
6167 | assign tcusig_cstopq48_nf_reg_scanin = tcusig_fq96_nf_reg_scanout ; | |
6168 | ||
6169 | assign tcusig_rstsm_nf_reg_scanin = tcusig_cstopq48_nf_reg_scanout ; | |
6170 | assign tcusig_tcuf_nf_reg_scanin = tcusig_rstsm_nf_reg_scanout ; | |
6171 | assign tcusig_tcuasicf_nf_reg_scanin = tcusig_tcuf_nf_reg_scanout ; | |
6172 | assign tcusig_intflush_nf_reg_scanin = tcusig_tcuasicf_nf_reg_scanout ; | |
6173 | ||
6174 | assign tcusig_noflush_scanout = io_test_mode ? tcusig_intflush_nf_reg_scanout : int_scan_in; | |
6175 | ||
6176 | assign tcusig_flushdly_reg_scanin = tcusig_noflush_scanout; //int_scan_in; | |
6177 | assign tcusig_fireq_reg_scanin = tcusig_flushdly_reg_scanout; | |
6178 | assign tcusig_fsreq_reg_scanin = tcusig_fireq_reg_scanout ; | |
6179 | //assign tcusig_afsreq_reg_scanin = tcusig_fsreq_reg_scanout; | |
6180 | assign tcusig_fiack_reg_scanin = tcusig_fsreq_reg_scanout; | |
6181 | assign tcusig_efctl_reg_scanin = tcusig_fiack_reg_scanout; | |
6182 | assign tcusig_efcnt_reg_scanin = tcusig_efctl_reg_scanout ; | |
6183 | assign tcusig_clkstopviareg_reg_scanin = tcusig_efcnt_reg_scanout ; | |
6184 | assign tcusig_jtagclkstop_reg_scanin = tcusig_clkstopviareg_reg_scanout; | |
6185 | assign tcusig_flushclkstop_reg_scanin = tcusig_jtagclkstop_reg_scanout; | |
6186 | assign tcusig_warmrp_reg_scanin = tcusig_flushclkstop_reg_scanout; | |
6187 | assign tcusig_coreavailclkstop_reg_scanin = tcusig_warmrp_reg_scanout; | |
6188 | assign tcusig_ca_reg_scanin = tcusig_coreavailclkstop_reg_scanout; | |
6189 | assign tcusig_coreavailclear_reg_scanin = tcusig_ca_reg_scanout ; | |
6190 | assign tcusig_enstat_reg_scanin = tcusig_coreavailclear_reg_scanout; | |
6191 | assign tcusig_cesq_reg_scanin = tcusig_enstat_reg_scanout; | |
6192 | assign tcusig_ces_reg_scanin = tcusig_cesq_reg_scanout ; | |
6193 | assign clk_stop_seq_scanin = tcusig_ces_reg_scanout; | |
6194 | assign tcusig_cntdly_reg_scanin = clk_stop_seq_scanout; | |
6195 | assign tcusig_cntstop_reg_scanin = tcusig_cntdly_reg_scanout; | |
6196 | assign tcusig_cntstart_reg_scanin = tcusig_cntstop_reg_scanout; | |
6197 | ||
6198 | assign tcusig_ssmode_reg_scanin = tcusig_cntstart_reg_scanout; | |
6199 | assign tcusig_sssel_reg_scanin = tcusig_ssmode_reg_scanout; | |
6200 | ||
6201 | //assign sync_ff_ac_tt_trigger_ce_scanin = tcusig_sssel_reg_scanout; | |
6202 | //assign sync_ff_ac_tt_trigger_scanin = sync_ff_ac_tt_trigger_ce_scanout; | |
6203 | assign sync_ff_ac_tt_trigger_scanin = tcusig_sssel_reg_scanout; | |
6204 | ||
6205 | assign sync_ff_clk_stop_spc0_0_scanin = sync_ff_ac_tt_trigger_scanout; | |
6206 | assign sync_ff_clk_stop_spc0_1_scanin = sync_ff_clk_stop_spc0_0_scanout; | |
6207 | assign sync_ff_clk_stop_spc1_0_scanin = sync_ff_clk_stop_spc0_1_scanout; | |
6208 | assign sync_ff_clk_stop_spc1_1_scanin = sync_ff_clk_stop_spc1_0_scanout; | |
6209 | assign sync_ff_clk_stop_spc2_0_scanin = sync_ff_clk_stop_spc1_1_scanout; | |
6210 | assign sync_ff_clk_stop_spc2_1_scanin = sync_ff_clk_stop_spc2_0_scanout; | |
6211 | assign sync_ff_clk_stop_spc3_0_scanin = sync_ff_clk_stop_spc2_1_scanout; | |
6212 | assign sync_ff_clk_stop_spc3_1_scanin = sync_ff_clk_stop_spc3_0_scanout; | |
6213 | assign sync_ff_clk_stop_spc4_0_scanin = sync_ff_clk_stop_spc3_1_scanout; | |
6214 | assign sync_ff_clk_stop_spc4_1_scanin = sync_ff_clk_stop_spc4_0_scanout; | |
6215 | assign sync_ff_clk_stop_spc5_0_scanin = sync_ff_clk_stop_spc4_1_scanout; | |
6216 | assign sync_ff_clk_stop_spc5_1_scanin = sync_ff_clk_stop_spc5_0_scanout; | |
6217 | assign sync_ff_clk_stop_spc6_0_scanin = sync_ff_clk_stop_spc5_1_scanout; | |
6218 | assign sync_ff_clk_stop_spc6_1_scanin = sync_ff_clk_stop_spc6_0_scanout; | |
6219 | assign sync_ff_clk_stop_spc7_0_scanin = sync_ff_clk_stop_spc6_1_scanout; | |
6220 | assign sync_ff_clk_stop_spc7_1_scanin = sync_ff_clk_stop_spc7_0_scanout; | |
6221 | assign sync_ff_clk_stop_bnk0_0_scanin = sync_ff_clk_stop_spc7_1_scanout; | |
6222 | assign sync_ff_clk_stop_bnk0_1_scanin = sync_ff_clk_stop_bnk0_0_scanout; | |
6223 | assign sync_ff_clk_stop_l2t0_0_scanin = sync_ff_clk_stop_bnk0_1_scanout; | |
6224 | assign sync_ff_clk_stop_l2t0_1_scanin = sync_ff_clk_stop_l2t0_0_scanout; | |
6225 | assign sync_ff_clk_stop_bnk1_0_scanin = sync_ff_clk_stop_l2t0_1_scanout; | |
6226 | assign sync_ff_clk_stop_bnk1_1_scanin = sync_ff_clk_stop_bnk1_0_scanout; | |
6227 | assign sync_ff_clk_stop_l2t1_0_scanin = sync_ff_clk_stop_bnk1_1_scanout; | |
6228 | assign sync_ff_clk_stop_l2t1_1_scanin = sync_ff_clk_stop_l2t1_0_scanout; | |
6229 | assign sync_ff_clk_stop_bnk2_0_scanin = sync_ff_clk_stop_l2t1_1_scanout; | |
6230 | assign sync_ff_clk_stop_bnk2_1_scanin = sync_ff_clk_stop_bnk2_0_scanout; | |
6231 | assign sync_ff_clk_stop_l2t2_0_scanin = sync_ff_clk_stop_bnk2_1_scanout; | |
6232 | assign sync_ff_clk_stop_l2t2_1_scanin = sync_ff_clk_stop_l2t2_0_scanout; | |
6233 | assign sync_ff_clk_stop_bnk3_0_scanin = sync_ff_clk_stop_l2t2_1_scanout; | |
6234 | assign sync_ff_clk_stop_bnk3_1_scanin = sync_ff_clk_stop_bnk3_0_scanout; | |
6235 | assign sync_ff_clk_stop_l2t3_0_scanin = sync_ff_clk_stop_bnk3_1_scanout; | |
6236 | assign sync_ff_clk_stop_l2t3_1_scanin = sync_ff_clk_stop_l2t3_0_scanout; | |
6237 | assign sync_ff_clk_stop_bnk4_0_scanin = sync_ff_clk_stop_l2t3_1_scanout; | |
6238 | assign sync_ff_clk_stop_bnk4_1_scanin = sync_ff_clk_stop_bnk4_0_scanout; | |
6239 | assign sync_ff_clk_stop_l2t4_0_scanin = sync_ff_clk_stop_bnk4_1_scanout; | |
6240 | assign sync_ff_clk_stop_l2t4_1_scanin = sync_ff_clk_stop_l2t4_0_scanout; | |
6241 | assign sync_ff_clk_stop_bnk5_0_scanin = sync_ff_clk_stop_l2t4_1_scanout; | |
6242 | assign sync_ff_clk_stop_bnk5_1_scanin = sync_ff_clk_stop_bnk5_0_scanout; | |
6243 | assign sync_ff_clk_stop_l2t5_0_scanin = sync_ff_clk_stop_bnk5_1_scanout; | |
6244 | assign sync_ff_clk_stop_l2t5_1_scanin = sync_ff_clk_stop_l2t5_0_scanout; | |
6245 | assign sync_ff_clk_stop_bnk6_0_scanin = sync_ff_clk_stop_l2t5_1_scanout; | |
6246 | assign sync_ff_clk_stop_bnk6_1_scanin = sync_ff_clk_stop_bnk6_0_scanout; | |
6247 | assign sync_ff_clk_stop_l2t6_0_scanin = sync_ff_clk_stop_bnk6_1_scanout; | |
6248 | assign sync_ff_clk_stop_l2t6_1_scanin = sync_ff_clk_stop_l2t6_0_scanout; | |
6249 | assign sync_ff_clk_stop_bnk7_0_scanin = sync_ff_clk_stop_l2t6_1_scanout; | |
6250 | assign sync_ff_clk_stop_bnk7_1_scanin = sync_ff_clk_stop_bnk7_0_scanout; | |
6251 | assign sync_ff_clk_stop_l2t7_0_scanin = sync_ff_clk_stop_bnk7_1_scanout; | |
6252 | assign sync_ff_clk_stop_l2t7_1_scanin = sync_ff_clk_stop_l2t7_0_scanout; | |
6253 | ||
6254 | assign sync_ff_clk_stop_mcu0_0_scanin = sync_ff_clk_stop_l2t7_1_scanout; | |
6255 | assign sync_ff_clk_stop_mcu0_1_scanin = sync_ff_clk_stop_mcu0_0_scanout; | |
6256 | assign sync_ff_ioclk_stop_mcu0_1_scanin = sync_ff_clk_stop_mcu0_1_scanout; | |
6257 | assign sync_ff_drclk_stop_mcu0_1_scanin = sync_ff_ioclk_stop_mcu0_1_scanout; | |
6258 | ||
6259 | assign sync_ff_clk_stop_mcu1_0_scanin = sync_ff_drclk_stop_mcu0_1_scanout; | |
6260 | assign sync_ff_clk_stop_mcu1_1_scanin = sync_ff_clk_stop_mcu1_0_scanout; | |
6261 | assign sync_ff_ioclk_stop_mcu1_1_scanin = sync_ff_clk_stop_mcu1_1_scanout; | |
6262 | assign sync_ff_drclk_stop_mcu1_1_scanin = sync_ff_ioclk_stop_mcu1_1_scanout; | |
6263 | ||
6264 | assign sync_ff_clk_stop_mcu2_0_scanin = sync_ff_drclk_stop_mcu1_1_scanout; | |
6265 | assign sync_ff_clk_stop_mcu2_1_scanin = sync_ff_clk_stop_mcu2_0_scanout; | |
6266 | assign sync_ff_ioclk_stop_mcu2_1_scanin = sync_ff_clk_stop_mcu2_1_scanout; | |
6267 | assign sync_ff_drclk_stop_mcu2_1_scanin = sync_ff_ioclk_stop_mcu2_1_scanout; | |
6268 | ||
6269 | assign sync_ff_clk_stop_mcu3_0_scanin = sync_ff_drclk_stop_mcu2_1_scanout; | |
6270 | assign sync_ff_clk_stop_mcu3_1_scanin = sync_ff_clk_stop_mcu3_0_scanout; | |
6271 | assign sync_ff_ioclk_stop_mcu3_1_scanin = sync_ff_clk_stop_mcu3_1_scanout; | |
6272 | assign sync_ff_drclk_stop_mcu3_1_scanin = sync_ff_ioclk_stop_mcu3_1_scanout; | |
6273 | ||
6274 | assign sync_ff_clk_stop_soc0_0_scanin = sync_ff_drclk_stop_mcu3_1_scanout; | |
6275 | assign sync_ff_clk_stop_soc0_1_scanin = sync_ff_clk_stop_soc0_0_scanout; | |
6276 | assign sync_ff_ioclk_stop_soc0_1_scanin = sync_ff_clk_stop_soc0_1_scanout; | |
6277 | //assign sync_ff_drclk_stop_soc0_1_scanin = sync_ff_ioclk_stop_soc0_1_scanout; | |
6278 | ||
6279 | //assign sync_ff_clk_stop_soc1_0_scanin = sync_ff_drclk_stop_soc0_1_scanout; | |
6280 | assign sync_ff_clk_stop_soc1_0_scanin = sync_ff_ioclk_stop_soc0_1_scanout; | |
6281 | assign sync_ff_ioclk_stop_soc1_1_scanin = sync_ff_clk_stop_soc1_0_scanout; | |
6282 | assign sync_ff_clk_stop_soc2_0_scanin = sync_ff_ioclk_stop_soc1_1_scanout; | |
6283 | assign sync_ff_ioclk_stop_soc2_1_scanin = sync_ff_clk_stop_soc2_0_scanout; | |
6284 | assign sync_ff_clk_stop_soc3_0_scanin = sync_ff_ioclk_stop_soc2_1_scanout; | |
6285 | assign sync_ff_clk_stop_soc3_1_scanin = sync_ff_clk_stop_soc3_0_scanout; | |
6286 | assign sync_ff_ioclk_stop_soc3_1_scanin = sync_ff_clk_stop_soc3_1_scanout; | |
6287 | assign tcusig_ttclksel_reg_scanin = sync_ff_ioclk_stop_soc3_1_scanout; | |
6288 | assign tcusig_srdacmode_reg_scanin = tcusig_ttclksel_reg_scanout; | |
6289 | assign tcusig_cmpdrsync_reg_scanin = tcusig_srdacmode_reg_scanout; | |
6290 | assign tcusig_pceov_reg_scanin = tcusig_cmpdrsync_reg_scanout; | |
6291 | assign tcusig_ccu_clk_stop_reg_scanin = tcusig_pceov_reg_scanout; | |
6292 | assign tcusig_ccu_io_clk_stop_reg_scanin = tcusig_ccu_clk_stop_reg_scanout; | |
6293 | assign tcusig_rst_clk_stop_reg_scanin = tcusig_ccu_io_clk_stop_reg_scanout; | |
6294 | assign tcusig_rst_io_clk_stop_reg_scanin = tcusig_rst_clk_stop_reg_scanout; | |
6295 | assign sync_ff_jtagporacc_scanin = tcusig_rst_io_clk_stop_reg_scanout; | |
6296 | assign sync_ff_sckbyp_scanin = sync_ff_jtagporacc_scanout; | |
6297 | assign tcusig_sck_reg_scanin = sync_ff_sckbyp_scanout; | |
6298 | assign tap_spc7_mb_cs_sync_reg_scanin = tcusig_sck_reg_scanout; | |
6299 | assign tap_spc6_mb_cs_sync_reg_scanin = tap_spc7_mb_cs_sync_reg_scanout; | |
6300 | assign tap_spc5_mb_cs_sync_reg_scanin = tap_spc6_mb_cs_sync_reg_scanout; | |
6301 | assign tap_spc4_mb_cs_sync_reg_scanin = tap_spc5_mb_cs_sync_reg_scanout; | |
6302 | assign tap_spc3_mb_cs_sync_reg_scanin = tap_spc4_mb_cs_sync_reg_scanout; | |
6303 | assign tap_spc2_mb_cs_sync_reg_scanin = tap_spc3_mb_cs_sync_reg_scanout; | |
6304 | assign tap_spc1_mb_cs_sync_reg_scanin = tap_spc2_mb_cs_sync_reg_scanout; | |
6305 | assign tap_spc0_mb_cs_sync_reg_scanin = tap_spc1_mb_cs_sync_reg_scanout; | |
6306 | assign l2t7_mbist_cs_sync_reg_scanin = tap_spc0_mb_cs_sync_reg_scanout; | |
6307 | assign l2t6_mbist_cs_sync_reg_scanin = l2t7_mbist_cs_sync_reg_scanout; | |
6308 | assign l2t5_mbist_cs_sync_reg_scanin = l2t6_mbist_cs_sync_reg_scanout; | |
6309 | assign l2t4_mbist_cs_sync_reg_scanin = l2t5_mbist_cs_sync_reg_scanout; | |
6310 | assign l2t3_mbist_cs_sync_reg_scanin = l2t4_mbist_cs_sync_reg_scanout; | |
6311 | assign l2t2_mbist_cs_sync_reg_scanin = l2t3_mbist_cs_sync_reg_scanout; | |
6312 | assign l2t1_mbist_cs_sync_reg_scanin = l2t2_mbist_cs_sync_reg_scanout; | |
6313 | assign l2t0_mbist_cs_sync_reg_scanin = l2t1_mbist_cs_sync_reg_scanout; | |
6314 | assign l2b7_mbist_cs_sync_reg_scanin = l2t0_mbist_cs_sync_reg_scanout; | |
6315 | assign l2b6_mbist_cs_sync_reg_scanin = l2b7_mbist_cs_sync_reg_scanout; | |
6316 | assign l2b5_mbist_cs_sync_reg_scanin = l2b6_mbist_cs_sync_reg_scanout; | |
6317 | assign l2b4_mbist_cs_sync_reg_scanin = l2b5_mbist_cs_sync_reg_scanout; | |
6318 | assign l2b3_mbist_cs_sync_reg_scanin = l2b4_mbist_cs_sync_reg_scanout; | |
6319 | assign l2b2_mbist_cs_sync_reg_scanin = l2b3_mbist_cs_sync_reg_scanout; | |
6320 | assign l2b1_mbist_cs_sync_reg_scanin = l2b2_mbist_cs_sync_reg_scanout; | |
6321 | assign l2b0_mbist_cs_sync_reg_scanin = l2b1_mbist_cs_sync_reg_scanout; | |
6322 | assign soc0_mbist_cs_sync_reg_scanin = l2b0_mbist_cs_sync_reg_scanout; | |
6323 | assign mcu3_mbist_cs_sync_reg_scanin = soc0_mbist_cs_sync_reg_scanout; | |
6324 | assign mcu2_mbist_cs_sync_reg_scanin = mcu3_mbist_cs_sync_reg_scanout; | |
6325 | assign mcu1_mbist_cs_sync_reg_scanin = mcu2_mbist_cs_sync_reg_scanout; | |
6326 | assign mcu0_mbist_cs_sync_reg_scanin = mcu1_mbist_cs_sync_reg_scanout; | |
6327 | assign dmu_mbist_cs_sync_reg_scanin = mcu0_mbist_cs_sync_reg_scanout; | |
6328 | assign peu_mbist_cs_sync_reg_scanin = dmu_mbist_cs_sync_reg_scanout; | |
6329 | assign rdp_mbist_cs_sync_reg_scanin = peu_mbist_cs_sync_reg_scanout; | |
6330 | assign rtx_mbist_cs_sync_reg_scanin = rdp_mbist_cs_sync_reg_scanout; | |
6331 | assign tds_mbist_cs_sync_reg_scanin = rtx_mbist_cs_sync_reg_scanout; | |
6332 | assign jtag_spc7_ss_cs_sync_reg_scanin = tds_mbist_cs_sync_reg_scanout; | |
6333 | assign jtag_spc6_ss_cs_sync_reg_scanin = jtag_spc7_ss_cs_sync_reg_scanout; | |
6334 | assign jtag_spc5_ss_cs_sync_reg_scanin = jtag_spc6_ss_cs_sync_reg_scanout; | |
6335 | assign jtag_spc4_ss_cs_sync_reg_scanin = jtag_spc5_ss_cs_sync_reg_scanout; | |
6336 | assign jtag_spc3_ss_cs_sync_reg_scanin = jtag_spc4_ss_cs_sync_reg_scanout; | |
6337 | assign jtag_spc2_ss_cs_sync_reg_scanin = jtag_spc3_ss_cs_sync_reg_scanout; | |
6338 | assign jtag_spc1_ss_cs_sync_reg_scanin = jtag_spc2_ss_cs_sync_reg_scanout; | |
6339 | assign jtag_spc0_ss_cs_sync_reg_scanin = jtag_spc1_ss_cs_sync_reg_scanout; | |
6340 | assign jtag_l2t7_ss_cs_sync_reg_scanin = jtag_spc0_ss_cs_sync_reg_scanout; | |
6341 | assign jtag_l2t6_ss_cs_sync_reg_scanin = jtag_l2t7_ss_cs_sync_reg_scanout; | |
6342 | assign jtag_l2t5_ss_cs_sync_reg_scanin = jtag_l2t6_ss_cs_sync_reg_scanout; | |
6343 | assign jtag_l2t4_ss_cs_sync_reg_scanin = jtag_l2t5_ss_cs_sync_reg_scanout; | |
6344 | assign jtag_l2t3_ss_cs_sync_reg_scanin = jtag_l2t4_ss_cs_sync_reg_scanout; | |
6345 | assign jtag_l2t2_ss_cs_sync_reg_scanin = jtag_l2t3_ss_cs_sync_reg_scanout; | |
6346 | assign jtag_l2t1_ss_cs_sync_reg_scanin = jtag_l2t2_ss_cs_sync_reg_scanout; | |
6347 | assign jtag_l2t0_ss_cs_sync_reg_scanin = jtag_l2t1_ss_cs_sync_reg_scanout; | |
6348 | assign jtag_spc_ss_pce_ov_sync_reg_scanin = jtag_l2t0_ss_cs_sync_reg_scanout; | |
6349 | assign jtag_l2t_ss_pce_ov_sync_reg_scanin = jtag_spc_ss_pce_ov_sync_reg_scanout; | |
6350 | assign jtag_clk_stop_req_sync_reg_scanin = jtag_l2t_ss_pce_ov_sync_reg_scanout; | |
6351 | assign jtag_efu_clear_instr_sync_reg_scanin = jtag_clk_stop_req_sync_reg_scanout; | |
6352 | assign instr_sstop_csmode_sync_reg_scanin = jtag_efu_clear_instr_sync_reg_scanout; | |
6353 | assign sync_ff_jtagclkdlyupd_scanin = instr_sstop_csmode_sync_reg_scanout; | |
6354 | assign jtag_serscan_sync_reg_scanin = sync_ff_jtagclkdlyupd_scanout; | |
6355 | assign shscan_clk_stop_io_sync_reg_scanin = jtag_serscan_sync_reg_scanout; | |
6356 | assign spare_scanin = shscan_clk_stop_io_sync_reg_scanout; | |
6357 | assign scan_out = spare_scanout; | |
6358 | // fixscan end: | |
6359 | endmodule | |
6360 | ||
6361 | ||
6362 | ||
6363 | ||
6364 | ||
6365 | ||
6366 | // any PARAMS parms go into naming of macro | |
6367 | ||
6368 | module tcu_sigmux_ctl_l1clkhdr_ctl_macro ( | |
6369 | l2clk, | |
6370 | l1en, | |
6371 | pce_ov, | |
6372 | stop, | |
6373 | se, | |
6374 | l1clk); | |
6375 | ||
6376 | ||
6377 | input l2clk; | |
6378 | input l1en; | |
6379 | input pce_ov; | |
6380 | input stop; | |
6381 | input se; | |
6382 | output l1clk; | |
6383 | ||
6384 | ||
6385 | ||
6386 | ||
6387 | ||
6388 | cl_sc1_l1hdr_8x c_0 ( | |
6389 | ||
6390 | ||
6391 | .l2clk(l2clk), | |
6392 | .pce(l1en), | |
6393 | .l1clk(l1clk), | |
6394 | .se(se), | |
6395 | .pce_ov(pce_ov), | |
6396 | .stop(stop) | |
6397 | ); | |
6398 | ||
6399 | ||
6400 | ||
6401 | endmodule | |
6402 | ||
6403 | ||
6404 | ||
6405 | ||
6406 | ||
6407 | ||
6408 | ||
6409 | ||
6410 | ||
6411 | ||
6412 | ||
6413 | ||
6414 | ||
6415 | // any PARAMS parms go into naming of macro | |
6416 | ||
6417 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_1 ( | |
6418 | din, | |
6419 | en, | |
6420 | l1clk, | |
6421 | scan_in, | |
6422 | siclk, | |
6423 | soclk, | |
6424 | dout, | |
6425 | scan_out); | |
6426 | wire [0:0] fdin; | |
6427 | ||
6428 | input [0:0] din; | |
6429 | input en; | |
6430 | input l1clk; | |
6431 | input scan_in; | |
6432 | ||
6433 | ||
6434 | input siclk; | |
6435 | input soclk; | |
6436 | ||
6437 | output [0:0] dout; | |
6438 | output scan_out; | |
6439 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
6440 | ||
6441 | ||
6442 | ||
6443 | ||
6444 | ||
6445 | ||
6446 | dff #(1) d0_0 ( | |
6447 | .l1clk(l1clk), | |
6448 | .siclk(siclk), | |
6449 | .soclk(soclk), | |
6450 | .d(fdin[0:0]), | |
6451 | .si(scan_in), | |
6452 | .so(scan_out), | |
6453 | .q(dout[0:0]) | |
6454 | ); | |
6455 | ||
6456 | ||
6457 | ||
6458 | ||
6459 | ||
6460 | ||
6461 | ||
6462 | ||
6463 | ||
6464 | ||
6465 | ||
6466 | ||
6467 | endmodule | |
6468 | ||
6469 | ||
6470 | ||
6471 | ||
6472 | ||
6473 | ||
6474 | ||
6475 | ||
6476 | ||
6477 | ||
6478 | ||
6479 | ||
6480 | ||
6481 | // any PARAMS parms go into naming of macro | |
6482 | ||
6483 | module tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_7 ( | |
6484 | din, | |
6485 | clr, | |
6486 | l1clk, | |
6487 | scan_in, | |
6488 | siclk, | |
6489 | soclk, | |
6490 | dout, | |
6491 | scan_out); | |
6492 | wire [6:0] fdin; | |
6493 | wire [5:0] so; | |
6494 | ||
6495 | input [6:0] din; | |
6496 | input clr; | |
6497 | input l1clk; | |
6498 | input scan_in; | |
6499 | ||
6500 | ||
6501 | input siclk; | |
6502 | input soclk; | |
6503 | ||
6504 | output [6:0] dout; | |
6505 | output scan_out; | |
6506 | assign fdin[6:0] = din[6:0] & ~{7{clr}}; | |
6507 | ||
6508 | ||
6509 | ||
6510 | ||
6511 | ||
6512 | ||
6513 | dff #(7) d0_0 ( | |
6514 | .l1clk(l1clk), | |
6515 | .siclk(siclk), | |
6516 | .soclk(soclk), | |
6517 | .d(fdin[6:0]), | |
6518 | .si({scan_in,so[5:0]}), | |
6519 | .so({so[5:0],scan_out}), | |
6520 | .q(dout[6:0]) | |
6521 | ); | |
6522 | ||
6523 | ||
6524 | ||
6525 | ||
6526 | ||
6527 | ||
6528 | ||
6529 | ||
6530 | ||
6531 | ||
6532 | ||
6533 | ||
6534 | endmodule | |
6535 | ||
6536 | ||
6537 | ||
6538 | ||
6539 | ||
6540 | ||
6541 | ||
6542 | ||
6543 | ||
6544 | ||
6545 | ||
6546 | ||
6547 | ||
6548 | // any PARAMS parms go into naming of macro | |
6549 | ||
6550 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_2 ( | |
6551 | din, | |
6552 | en, | |
6553 | l1clk, | |
6554 | scan_in, | |
6555 | siclk, | |
6556 | soclk, | |
6557 | dout, | |
6558 | scan_out); | |
6559 | wire [1:0] fdin; | |
6560 | wire [0:0] so; | |
6561 | ||
6562 | input [1:0] din; | |
6563 | input en; | |
6564 | input l1clk; | |
6565 | input scan_in; | |
6566 | ||
6567 | ||
6568 | input siclk; | |
6569 | input soclk; | |
6570 | ||
6571 | output [1:0] dout; | |
6572 | output scan_out; | |
6573 | assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}}); | |
6574 | ||
6575 | ||
6576 | ||
6577 | ||
6578 | ||
6579 | ||
6580 | dff #(2) d0_0 ( | |
6581 | .l1clk(l1clk), | |
6582 | .siclk(siclk), | |
6583 | .soclk(soclk), | |
6584 | .d(fdin[1:0]), | |
6585 | .si({scan_in,so[0:0]}), | |
6586 | .so({so[0:0],scan_out}), | |
6587 | .q(dout[1:0]) | |
6588 | ); | |
6589 | ||
6590 | ||
6591 | ||
6592 | ||
6593 | ||
6594 | ||
6595 | ||
6596 | ||
6597 | ||
6598 | ||
6599 | ||
6600 | ||
6601 | endmodule | |
6602 | ||
6603 | ||
6604 | ||
6605 | ||
6606 | ||
6607 | ||
6608 | ||
6609 | ||
6610 | ||
6611 | ||
6612 | ||
6613 | ||
6614 | ||
6615 | // any PARAMS parms go into naming of macro | |
6616 | ||
6617 | module tcu_sigmux_ctl_msff_ctl_macro__clr_1__en_1__width_1 ( | |
6618 | din, | |
6619 | en, | |
6620 | clr, | |
6621 | l1clk, | |
6622 | scan_in, | |
6623 | siclk, | |
6624 | soclk, | |
6625 | dout, | |
6626 | scan_out); | |
6627 | wire [0:0] fdin; | |
6628 | ||
6629 | input [0:0] din; | |
6630 | input en; | |
6631 | input clr; | |
6632 | input l1clk; | |
6633 | input scan_in; | |
6634 | ||
6635 | ||
6636 | input siclk; | |
6637 | input soclk; | |
6638 | ||
6639 | output [0:0] dout; | |
6640 | output scan_out; | |
6641 | assign fdin[0:0] = (din[0:0] & {1{en}} & ~{1{clr}}) | (dout[0:0] & ~{1{en}} & ~{1{clr}}); | |
6642 | ||
6643 | ||
6644 | ||
6645 | ||
6646 | ||
6647 | ||
6648 | dff #(1) d0_0 ( | |
6649 | .l1clk(l1clk), | |
6650 | .siclk(siclk), | |
6651 | .soclk(soclk), | |
6652 | .d(fdin[0:0]), | |
6653 | .si(scan_in), | |
6654 | .so(scan_out), | |
6655 | .q(dout[0:0]) | |
6656 | ); | |
6657 | ||
6658 | ||
6659 | ||
6660 | ||
6661 | ||
6662 | ||
6663 | ||
6664 | ||
6665 | ||
6666 | ||
6667 | ||
6668 | ||
6669 | endmodule | |
6670 | ||
6671 | ||
6672 | ||
6673 | ||
6674 | ||
6675 | ||
6676 | ||
6677 | ||
6678 | ||
6679 | ||
6680 | ||
6681 | ||
6682 | ||
6683 | // any PARAMS parms go into naming of macro | |
6684 | ||
6685 | module tcu_sigmux_ctl_msff_ctl_macro__clr__1__width_2 ( | |
6686 | din, | |
6687 | clr_, | |
6688 | l1clk, | |
6689 | scan_in, | |
6690 | siclk, | |
6691 | soclk, | |
6692 | dout, | |
6693 | scan_out); | |
6694 | wire [1:0] fdin; | |
6695 | wire [0:0] so; | |
6696 | ||
6697 | input [1:0] din; | |
6698 | input clr_; | |
6699 | input l1clk; | |
6700 | input scan_in; | |
6701 | ||
6702 | ||
6703 | input siclk; | |
6704 | input soclk; | |
6705 | ||
6706 | output [1:0] dout; | |
6707 | output scan_out; | |
6708 | assign fdin[1:0] = din[1:0] & ~{2{(~clr_)}}; | |
6709 | ||
6710 | ||
6711 | ||
6712 | ||
6713 | ||
6714 | ||
6715 | dff #(2) d0_0 ( | |
6716 | .l1clk(l1clk), | |
6717 | .siclk(siclk), | |
6718 | .soclk(soclk), | |
6719 | .d(fdin[1:0]), | |
6720 | .si({scan_in,so[0:0]}), | |
6721 | .so({so[0:0],scan_out}), | |
6722 | .q(dout[1:0]) | |
6723 | ); | |
6724 | ||
6725 | ||
6726 | ||
6727 | ||
6728 | ||
6729 | ||
6730 | ||
6731 | ||
6732 | ||
6733 | ||
6734 | ||
6735 | ||
6736 | endmodule | |
6737 | ||
6738 | ||
6739 | ||
6740 | ||
6741 | ||
6742 | ||
6743 | ||
6744 | ||
6745 | ||
6746 | ||
6747 | ||
6748 | ||
6749 | ||
6750 | // any PARAMS parms go into naming of macro | |
6751 | ||
6752 | module tcu_sigmux_ctl_msff_ctl_macro__width_1 ( | |
6753 | din, | |
6754 | l1clk, | |
6755 | scan_in, | |
6756 | siclk, | |
6757 | soclk, | |
6758 | dout, | |
6759 | scan_out); | |
6760 | wire [0:0] fdin; | |
6761 | ||
6762 | input [0:0] din; | |
6763 | input l1clk; | |
6764 | input scan_in; | |
6765 | ||
6766 | ||
6767 | input siclk; | |
6768 | input soclk; | |
6769 | ||
6770 | output [0:0] dout; | |
6771 | output scan_out; | |
6772 | assign fdin[0:0] = din[0:0]; | |
6773 | ||
6774 | ||
6775 | ||
6776 | ||
6777 | ||
6778 | ||
6779 | dff #(1) d0_0 ( | |
6780 | .l1clk(l1clk), | |
6781 | .siclk(siclk), | |
6782 | .soclk(soclk), | |
6783 | .d(fdin[0:0]), | |
6784 | .si(scan_in), | |
6785 | .so(scan_out), | |
6786 | .q(dout[0:0]) | |
6787 | ); | |
6788 | ||
6789 | ||
6790 | ||
6791 | ||
6792 | ||
6793 | ||
6794 | ||
6795 | ||
6796 | ||
6797 | ||
6798 | ||
6799 | ||
6800 | endmodule | |
6801 | ||
6802 | ||
6803 | ||
6804 | ||
6805 | ||
6806 | ||
6807 | ||
6808 | ||
6809 | ||
6810 | ||
6811 | ||
6812 | ||
6813 | ||
6814 | // any PARAMS parms go into naming of macro | |
6815 | ||
6816 | module tcu_sigmux_ctl_msff_ctl_macro__width_12 ( | |
6817 | din, | |
6818 | l1clk, | |
6819 | scan_in, | |
6820 | siclk, | |
6821 | soclk, | |
6822 | dout, | |
6823 | scan_out); | |
6824 | wire [11:0] fdin; | |
6825 | wire [10:0] so; | |
6826 | ||
6827 | input [11:0] din; | |
6828 | input l1clk; | |
6829 | input scan_in; | |
6830 | ||
6831 | ||
6832 | input siclk; | |
6833 | input soclk; | |
6834 | ||
6835 | output [11:0] dout; | |
6836 | output scan_out; | |
6837 | assign fdin[11:0] = din[11:0]; | |
6838 | ||
6839 | ||
6840 | ||
6841 | ||
6842 | ||
6843 | ||
6844 | dff #(12) d0_0 ( | |
6845 | .l1clk(l1clk), | |
6846 | .siclk(siclk), | |
6847 | .soclk(soclk), | |
6848 | .d(fdin[11:0]), | |
6849 | .si({scan_in,so[10:0]}), | |
6850 | .so({so[10:0],scan_out}), | |
6851 | .q(dout[11:0]) | |
6852 | ); | |
6853 | ||
6854 | ||
6855 | ||
6856 | ||
6857 | ||
6858 | ||
6859 | ||
6860 | ||
6861 | ||
6862 | ||
6863 | ||
6864 | ||
6865 | endmodule | |
6866 | ||
6867 | ||
6868 | ||
6869 | ||
6870 | ||
6871 | ||
6872 | ||
6873 | ||
6874 | ||
6875 | ||
6876 | ||
6877 | ||
6878 | ||
6879 | // any PARAMS parms go into naming of macro | |
6880 | ||
6881 | module tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_6 ( | |
6882 | din, | |
6883 | clr, | |
6884 | l1clk, | |
6885 | scan_in, | |
6886 | siclk, | |
6887 | soclk, | |
6888 | dout, | |
6889 | scan_out); | |
6890 | wire [5:0] fdin; | |
6891 | wire [4:0] so; | |
6892 | ||
6893 | input [5:0] din; | |
6894 | input clr; | |
6895 | input l1clk; | |
6896 | input scan_in; | |
6897 | ||
6898 | ||
6899 | input siclk; | |
6900 | input soclk; | |
6901 | ||
6902 | output [5:0] dout; | |
6903 | output scan_out; | |
6904 | assign fdin[5:0] = din[5:0] & ~{6{clr}}; | |
6905 | ||
6906 | ||
6907 | ||
6908 | ||
6909 | ||
6910 | ||
6911 | dff #(6) d0_0 ( | |
6912 | .l1clk(l1clk), | |
6913 | .siclk(siclk), | |
6914 | .soclk(soclk), | |
6915 | .d(fdin[5:0]), | |
6916 | .si({scan_in,so[4:0]}), | |
6917 | .so({so[4:0],scan_out}), | |
6918 | .q(dout[5:0]) | |
6919 | ); | |
6920 | ||
6921 | ||
6922 | ||
6923 | ||
6924 | ||
6925 | ||
6926 | ||
6927 | ||
6928 | ||
6929 | ||
6930 | ||
6931 | ||
6932 | endmodule | |
6933 | ||
6934 | ||
6935 | ||
6936 | ||
6937 | ||
6938 | ||
6939 | ||
6940 | ||
6941 | ||
6942 | ||
6943 | ||
6944 | ||
6945 | ||
6946 | // any PARAMS parms go into naming of macro | |
6947 | ||
6948 | module tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_15 ( | |
6949 | din, | |
6950 | clr, | |
6951 | l1clk, | |
6952 | scan_in, | |
6953 | siclk, | |
6954 | soclk, | |
6955 | dout, | |
6956 | scan_out); | |
6957 | wire [14:0] fdin; | |
6958 | wire [13:0] so; | |
6959 | ||
6960 | input [14:0] din; | |
6961 | input clr; | |
6962 | input l1clk; | |
6963 | input scan_in; | |
6964 | ||
6965 | ||
6966 | input siclk; | |
6967 | input soclk; | |
6968 | ||
6969 | output [14:0] dout; | |
6970 | output scan_out; | |
6971 | assign fdin[14:0] = din[14:0] & ~{15{clr}}; | |
6972 | ||
6973 | ||
6974 | ||
6975 | ||
6976 | ||
6977 | ||
6978 | dff #(15) d0_0 ( | |
6979 | .l1clk(l1clk), | |
6980 | .siclk(siclk), | |
6981 | .soclk(soclk), | |
6982 | .d(fdin[14:0]), | |
6983 | .si({scan_in,so[13:0]}), | |
6984 | .so({so[13:0],scan_out}), | |
6985 | .q(dout[14:0]) | |
6986 | ); | |
6987 | ||
6988 | ||
6989 | ||
6990 | ||
6991 | ||
6992 | ||
6993 | ||
6994 | ||
6995 | ||
6996 | ||
6997 | ||
6998 | ||
6999 | endmodule | |
7000 | ||
7001 | ||
7002 | ||
7003 | ||
7004 | ||
7005 | ||
7006 | ||
7007 | ||
7008 | ||
7009 | ||
7010 | ||
7011 | ||
7012 | ||
7013 | // any PARAMS parms go into naming of macro | |
7014 | ||
7015 | module tcu_sigmux_ctl_msff_ctl_macro__clr__1__width_1 ( | |
7016 | din, | |
7017 | clr_, | |
7018 | l1clk, | |
7019 | scan_in, | |
7020 | siclk, | |
7021 | soclk, | |
7022 | dout, | |
7023 | scan_out); | |
7024 | wire [0:0] fdin; | |
7025 | ||
7026 | input [0:0] din; | |
7027 | input clr_; | |
7028 | input l1clk; | |
7029 | input scan_in; | |
7030 | ||
7031 | ||
7032 | input siclk; | |
7033 | input soclk; | |
7034 | ||
7035 | output [0:0] dout; | |
7036 | output scan_out; | |
7037 | assign fdin[0:0] = din[0:0] & ~{1{(~clr_)}}; | |
7038 | ||
7039 | ||
7040 | ||
7041 | ||
7042 | ||
7043 | ||
7044 | dff #(1) d0_0 ( | |
7045 | .l1clk(l1clk), | |
7046 | .siclk(siclk), | |
7047 | .soclk(soclk), | |
7048 | .d(fdin[0:0]), | |
7049 | .si(scan_in), | |
7050 | .so(scan_out), | |
7051 | .q(dout[0:0]) | |
7052 | ); | |
7053 | ||
7054 | ||
7055 | ||
7056 | ||
7057 | ||
7058 | ||
7059 | ||
7060 | ||
7061 | ||
7062 | ||
7063 | ||
7064 | ||
7065 | endmodule | |
7066 | ||
7067 | ||
7068 | ||
7069 | ||
7070 | ||
7071 | ||
7072 | ||
7073 | ||
7074 | ||
7075 | ||
7076 | ||
7077 | ||
7078 | ||
7079 | // any PARAMS parms go into naming of macro | |
7080 | ||
7081 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_3 ( | |
7082 | din, | |
7083 | en, | |
7084 | l1clk, | |
7085 | scan_in, | |
7086 | siclk, | |
7087 | soclk, | |
7088 | dout, | |
7089 | scan_out); | |
7090 | wire [2:0] fdin; | |
7091 | wire [1:0] so; | |
7092 | ||
7093 | input [2:0] din; | |
7094 | input en; | |
7095 | input l1clk; | |
7096 | input scan_in; | |
7097 | ||
7098 | ||
7099 | input siclk; | |
7100 | input soclk; | |
7101 | ||
7102 | output [2:0] dout; | |
7103 | output scan_out; | |
7104 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
7105 | ||
7106 | ||
7107 | ||
7108 | ||
7109 | ||
7110 | ||
7111 | dff #(3) d0_0 ( | |
7112 | .l1clk(l1clk), | |
7113 | .siclk(siclk), | |
7114 | .soclk(soclk), | |
7115 | .d(fdin[2:0]), | |
7116 | .si({scan_in,so[1:0]}), | |
7117 | .so({so[1:0],scan_out}), | |
7118 | .q(dout[2:0]) | |
7119 | ); | |
7120 | ||
7121 | ||
7122 | ||
7123 | ||
7124 | ||
7125 | ||
7126 | ||
7127 | ||
7128 | ||
7129 | ||
7130 | ||
7131 | ||
7132 | endmodule | |
7133 | ||
7134 | ||
7135 | ||
7136 | ||
7137 | ||
7138 | ||
7139 | ||
7140 | ||
7141 | ||
7142 | ||
7143 | ||
7144 | ||
7145 | ||
7146 | // any PARAMS parms go into naming of macro | |
7147 | ||
7148 | module tcu_sigmux_ctl_msff_ctl_macro__clr_1__width_1 ( | |
7149 | din, | |
7150 | clr, | |
7151 | l1clk, | |
7152 | scan_in, | |
7153 | siclk, | |
7154 | soclk, | |
7155 | dout, | |
7156 | scan_out); | |
7157 | wire [0:0] fdin; | |
7158 | ||
7159 | input [0:0] din; | |
7160 | input clr; | |
7161 | input l1clk; | |
7162 | input scan_in; | |
7163 | ||
7164 | ||
7165 | input siclk; | |
7166 | input soclk; | |
7167 | ||
7168 | output [0:0] dout; | |
7169 | output scan_out; | |
7170 | assign fdin[0:0] = din[0:0] & ~{1{clr}}; | |
7171 | ||
7172 | ||
7173 | ||
7174 | ||
7175 | ||
7176 | ||
7177 | dff #(1) d0_0 ( | |
7178 | .l1clk(l1clk), | |
7179 | .siclk(siclk), | |
7180 | .soclk(soclk), | |
7181 | .d(fdin[0:0]), | |
7182 | .si(scan_in), | |
7183 | .so(scan_out), | |
7184 | .q(dout[0:0]) | |
7185 | ); | |
7186 | ||
7187 | ||
7188 | ||
7189 | ||
7190 | ||
7191 | ||
7192 | ||
7193 | ||
7194 | ||
7195 | ||
7196 | ||
7197 | ||
7198 | endmodule | |
7199 | ||
7200 | ||
7201 | ||
7202 | ||
7203 | ||
7204 | ||
7205 | ||
7206 | ||
7207 | ||
7208 | ||
7209 | ||
7210 | ||
7211 | ||
7212 | // any PARAMS parms go into naming of macro | |
7213 | ||
7214 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_16 ( | |
7215 | din, | |
7216 | en, | |
7217 | l1clk, | |
7218 | scan_in, | |
7219 | siclk, | |
7220 | soclk, | |
7221 | dout, | |
7222 | scan_out); | |
7223 | wire [15:0] fdin; | |
7224 | wire [14:0] so; | |
7225 | ||
7226 | input [15:0] din; | |
7227 | input en; | |
7228 | input l1clk; | |
7229 | input scan_in; | |
7230 | ||
7231 | ||
7232 | input siclk; | |
7233 | input soclk; | |
7234 | ||
7235 | output [15:0] dout; | |
7236 | output scan_out; | |
7237 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
7238 | ||
7239 | ||
7240 | ||
7241 | ||
7242 | ||
7243 | ||
7244 | dff #(16) d0_0 ( | |
7245 | .l1clk(l1clk), | |
7246 | .siclk(siclk), | |
7247 | .soclk(soclk), | |
7248 | .d(fdin[15:0]), | |
7249 | .si({scan_in,so[14:0]}), | |
7250 | .so({so[14:0],scan_out}), | |
7251 | .q(dout[15:0]) | |
7252 | ); | |
7253 | ||
7254 | ||
7255 | ||
7256 | ||
7257 | ||
7258 | ||
7259 | ||
7260 | ||
7261 | ||
7262 | ||
7263 | ||
7264 | ||
7265 | endmodule | |
7266 | ||
7267 | ||
7268 | ||
7269 | ||
7270 | ||
7271 | ||
7272 | ||
7273 | ||
7274 | ||
7275 | ||
7276 | ||
7277 | ||
7278 | ||
7279 | // any PARAMS parms go into naming of macro | |
7280 | ||
7281 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_13 ( | |
7282 | din, | |
7283 | en, | |
7284 | l1clk, | |
7285 | scan_in, | |
7286 | siclk, | |
7287 | soclk, | |
7288 | dout, | |
7289 | scan_out); | |
7290 | wire [12:0] fdin; | |
7291 | wire [11:0] so; | |
7292 | ||
7293 | input [12:0] din; | |
7294 | input en; | |
7295 | input l1clk; | |
7296 | input scan_in; | |
7297 | ||
7298 | ||
7299 | input siclk; | |
7300 | input soclk; | |
7301 | ||
7302 | output [12:0] dout; | |
7303 | output scan_out; | |
7304 | assign fdin[12:0] = (din[12:0] & {13{en}}) | (dout[12:0] & ~{13{en}}); | |
7305 | ||
7306 | ||
7307 | ||
7308 | ||
7309 | ||
7310 | ||
7311 | dff #(13) d0_0 ( | |
7312 | .l1clk(l1clk), | |
7313 | .siclk(siclk), | |
7314 | .soclk(soclk), | |
7315 | .d(fdin[12:0]), | |
7316 | .si({scan_in,so[11:0]}), | |
7317 | .so({so[11:0],scan_out}), | |
7318 | .q(dout[12:0]) | |
7319 | ); | |
7320 | ||
7321 | ||
7322 | ||
7323 | ||
7324 | ||
7325 | ||
7326 | ||
7327 | ||
7328 | ||
7329 | ||
7330 | ||
7331 | ||
7332 | endmodule | |
7333 | ||
7334 | ||
7335 | ||
7336 | ||
7337 | ||
7338 | ||
7339 | ||
7340 | ||
7341 | ||
7342 | ||
7343 | ||
7344 | ||
7345 | ||
7346 | // any PARAMS parms go into naming of macro | |
7347 | ||
7348 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_12 ( | |
7349 | din, | |
7350 | en, | |
7351 | l1clk, | |
7352 | scan_in, | |
7353 | siclk, | |
7354 | soclk, | |
7355 | dout, | |
7356 | scan_out); | |
7357 | wire [11:0] fdin; | |
7358 | wire [10:0] so; | |
7359 | ||
7360 | input [11:0] din; | |
7361 | input en; | |
7362 | input l1clk; | |
7363 | input scan_in; | |
7364 | ||
7365 | ||
7366 | input siclk; | |
7367 | input soclk; | |
7368 | ||
7369 | output [11:0] dout; | |
7370 | output scan_out; | |
7371 | assign fdin[11:0] = (din[11:0] & {12{en}}) | (dout[11:0] & ~{12{en}}); | |
7372 | ||
7373 | ||
7374 | ||
7375 | ||
7376 | ||
7377 | ||
7378 | dff #(12) d0_0 ( | |
7379 | .l1clk(l1clk), | |
7380 | .siclk(siclk), | |
7381 | .soclk(soclk), | |
7382 | .d(fdin[11:0]), | |
7383 | .si({scan_in,so[10:0]}), | |
7384 | .so({so[10:0],scan_out}), | |
7385 | .q(dout[11:0]) | |
7386 | ); | |
7387 | ||
7388 | ||
7389 | ||
7390 | ||
7391 | ||
7392 | ||
7393 | ||
7394 | ||
7395 | ||
7396 | ||
7397 | ||
7398 | ||
7399 | endmodule | |
7400 | ||
7401 | ||
7402 | ||
7403 | ||
7404 | ||
7405 | ||
7406 | // any PARAMS parms go into naming of macro | |
7407 | ||
7408 | module tcu_sigmux_ctl_msff_ctl_macro__width_7 ( | |
7409 | din, | |
7410 | l1clk, | |
7411 | scan_in, | |
7412 | siclk, | |
7413 | soclk, | |
7414 | dout, | |
7415 | scan_out); | |
7416 | wire [6:0] fdin; | |
7417 | wire [5:0] so; | |
7418 | ||
7419 | input [6:0] din; | |
7420 | input l1clk; | |
7421 | input scan_in; | |
7422 | ||
7423 | ||
7424 | input siclk; | |
7425 | input soclk; | |
7426 | ||
7427 | output [6:0] dout; | |
7428 | output scan_out; | |
7429 | assign fdin[6:0] = din[6:0]; | |
7430 | ||
7431 | ||
7432 | ||
7433 | ||
7434 | ||
7435 | ||
7436 | dff #(7) d0_0 ( | |
7437 | .l1clk(l1clk), | |
7438 | .siclk(siclk), | |
7439 | .soclk(soclk), | |
7440 | .d(fdin[6:0]), | |
7441 | .si({scan_in,so[5:0]}), | |
7442 | .so({so[5:0],scan_out}), | |
7443 | .q(dout[6:0]) | |
7444 | ); | |
7445 | ||
7446 | ||
7447 | ||
7448 | ||
7449 | ||
7450 | ||
7451 | ||
7452 | ||
7453 | ||
7454 | ||
7455 | ||
7456 | ||
7457 | endmodule | |
7458 | ||
7459 | ||
7460 | ||
7461 | ||
7462 | ||
7463 | ||
7464 | ||
7465 | ||
7466 | ||
7467 | ||
7468 | ||
7469 | ||
7470 | ||
7471 | // any PARAMS parms go into naming of macro | |
7472 | ||
7473 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_8 ( | |
7474 | din, | |
7475 | en, | |
7476 | l1clk, | |
7477 | scan_in, | |
7478 | siclk, | |
7479 | soclk, | |
7480 | dout, | |
7481 | scan_out); | |
7482 | wire [7:0] fdin; | |
7483 | wire [6:0] so; | |
7484 | ||
7485 | input [7:0] din; | |
7486 | input en; | |
7487 | input l1clk; | |
7488 | input scan_in; | |
7489 | ||
7490 | ||
7491 | input siclk; | |
7492 | input soclk; | |
7493 | ||
7494 | output [7:0] dout; | |
7495 | output scan_out; | |
7496 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
7497 | ||
7498 | ||
7499 | ||
7500 | ||
7501 | ||
7502 | ||
7503 | dff #(8) d0_0 ( | |
7504 | .l1clk(l1clk), | |
7505 | .siclk(siclk), | |
7506 | .soclk(soclk), | |
7507 | .d(fdin[7:0]), | |
7508 | .si({scan_in,so[6:0]}), | |
7509 | .so({so[6:0],scan_out}), | |
7510 | .q(dout[7:0]) | |
7511 | ); | |
7512 | ||
7513 | ||
7514 | ||
7515 | ||
7516 | ||
7517 | ||
7518 | ||
7519 | ||
7520 | ||
7521 | ||
7522 | ||
7523 | ||
7524 | endmodule | |
7525 | ||
7526 | ||
7527 | ||
7528 | ||
7529 | ||
7530 | ||
7531 | ||
7532 | ||
7533 | ||
7534 | ||
7535 | ||
7536 | ||
7537 | ||
7538 | // any PARAMS parms go into naming of macro | |
7539 | ||
7540 | module tcu_sigmux_ctl_msff_ctl_macro__width_2 ( | |
7541 | din, | |
7542 | l1clk, | |
7543 | scan_in, | |
7544 | siclk, | |
7545 | soclk, | |
7546 | dout, | |
7547 | scan_out); | |
7548 | wire [1:0] fdin; | |
7549 | wire [0:0] so; | |
7550 | ||
7551 | input [1:0] din; | |
7552 | input l1clk; | |
7553 | input scan_in; | |
7554 | ||
7555 | ||
7556 | input siclk; | |
7557 | input soclk; | |
7558 | ||
7559 | output [1:0] dout; | |
7560 | output scan_out; | |
7561 | assign fdin[1:0] = din[1:0]; | |
7562 | ||
7563 | ||
7564 | ||
7565 | ||
7566 | ||
7567 | ||
7568 | dff #(2) d0_0 ( | |
7569 | .l1clk(l1clk), | |
7570 | .siclk(siclk), | |
7571 | .soclk(soclk), | |
7572 | .d(fdin[1:0]), | |
7573 | .si({scan_in,so[0:0]}), | |
7574 | .so({so[0:0],scan_out}), | |
7575 | .q(dout[1:0]) | |
7576 | ); | |
7577 | ||
7578 | ||
7579 | ||
7580 | ||
7581 | ||
7582 | ||
7583 | ||
7584 | ||
7585 | ||
7586 | ||
7587 | ||
7588 | ||
7589 | endmodule | |
7590 | ||
7591 | ||
7592 | ||
7593 | ||
7594 | ||
7595 | ||
7596 | ||
7597 | ||
7598 | ||
7599 | ||
7600 | ||
7601 | ||
7602 | ||
7603 | // any PARAMS parms go into naming of macro | |
7604 | ||
7605 | module tcu_sigmux_ctl_msff_ctl_macro__width_3 ( | |
7606 | din, | |
7607 | l1clk, | |
7608 | scan_in, | |
7609 | siclk, | |
7610 | soclk, | |
7611 | dout, | |
7612 | scan_out); | |
7613 | wire [2:0] fdin; | |
7614 | wire [1:0] so; | |
7615 | ||
7616 | input [2:0] din; | |
7617 | input l1clk; | |
7618 | input scan_in; | |
7619 | ||
7620 | ||
7621 | input siclk; | |
7622 | input soclk; | |
7623 | ||
7624 | output [2:0] dout; | |
7625 | output scan_out; | |
7626 | assign fdin[2:0] = din[2:0]; | |
7627 | ||
7628 | ||
7629 | ||
7630 | ||
7631 | ||
7632 | ||
7633 | dff #(3) d0_0 ( | |
7634 | .l1clk(l1clk), | |
7635 | .siclk(siclk), | |
7636 | .soclk(soclk), | |
7637 | .d(fdin[2:0]), | |
7638 | .si({scan_in,so[1:0]}), | |
7639 | .so({so[1:0],scan_out}), | |
7640 | .q(dout[2:0]) | |
7641 | ); | |
7642 | ||
7643 | ||
7644 | ||
7645 | ||
7646 | ||
7647 | ||
7648 | ||
7649 | ||
7650 | ||
7651 | ||
7652 | ||
7653 | ||
7654 | endmodule | |
7655 | ||
7656 | ||
7657 | ||
7658 | ||
7659 | ||
7660 | ||
7661 | ||
7662 | ||
7663 | ||
7664 | ||
7665 | ||
7666 | ||
7667 | ||
7668 | // any PARAMS parms go into naming of macro | |
7669 | ||
7670 | module tcu_sigmux_ctl_msff_ctl_macro__en_1__width_21 ( | |
7671 | din, | |
7672 | en, | |
7673 | l1clk, | |
7674 | scan_in, | |
7675 | siclk, | |
7676 | soclk, | |
7677 | dout, | |
7678 | scan_out); | |
7679 | wire [20:0] fdin; | |
7680 | wire [19:0] so; | |
7681 | ||
7682 | input [20:0] din; | |
7683 | input en; | |
7684 | input l1clk; | |
7685 | input scan_in; | |
7686 | ||
7687 | ||
7688 | input siclk; | |
7689 | input soclk; | |
7690 | ||
7691 | output [20:0] dout; | |
7692 | output scan_out; | |
7693 | assign fdin[20:0] = (din[20:0] & {21{en}}) | (dout[20:0] & ~{21{en}}); | |
7694 | ||
7695 | ||
7696 | ||
7697 | ||
7698 | ||
7699 | ||
7700 | dff #(21) d0_0 ( | |
7701 | .l1clk(l1clk), | |
7702 | .siclk(siclk), | |
7703 | .soclk(soclk), | |
7704 | .d(fdin[20:0]), | |
7705 | .si({scan_in,so[19:0]}), | |
7706 | .so({so[19:0],scan_out}), | |
7707 | .q(dout[20:0]) | |
7708 | ); | |
7709 | ||
7710 | ||
7711 | ||
7712 | ||
7713 | ||
7714 | ||
7715 | ||
7716 | ||
7717 | ||
7718 | ||
7719 | ||
7720 | ||
7721 | endmodule | |
7722 | ||
7723 | ||
7724 | ||
7725 | ||
7726 | ||
7727 | ||
7728 | ||
7729 | ||
7730 | ||
7731 | // Description: Spare gate macro for control blocks | |
7732 | // | |
7733 | // Param num controls the number of times the macro is added | |
7734 | // flops=0 can be used to use only combination spare logic | |
7735 | ||
7736 | ||
7737 | module tcu_sigmux_ctl_spare_ctl_macro__flops_0__num_9; | |
7738 | wire spare0_buf_32x_unused; | |
7739 | wire spare0_nand3_8x_unused; | |
7740 | wire spare0_inv_8x_unused; | |
7741 | wire spare0_aoi22_4x_unused; | |
7742 | wire spare0_buf_8x_unused; | |
7743 | wire spare0_oai22_4x_unused; | |
7744 | wire spare0_inv_16x_unused; | |
7745 | wire spare0_nand2_16x_unused; | |
7746 | wire spare0_nor3_4x_unused; | |
7747 | wire spare0_nand2_8x_unused; | |
7748 | wire spare0_buf_16x_unused; | |
7749 | wire spare0_nor2_16x_unused; | |
7750 | wire spare0_inv_32x_unused; | |
7751 | wire spare1_buf_32x_unused; | |
7752 | wire spare1_nand3_8x_unused; | |
7753 | wire spare1_inv_8x_unused; | |
7754 | wire spare1_aoi22_4x_unused; | |
7755 | wire spare1_buf_8x_unused; | |
7756 | wire spare1_oai22_4x_unused; | |
7757 | wire spare1_inv_16x_unused; | |
7758 | wire spare1_nand2_16x_unused; | |
7759 | wire spare1_nor3_4x_unused; | |
7760 | wire spare1_nand2_8x_unused; | |
7761 | wire spare1_buf_16x_unused; | |
7762 | wire spare1_nor2_16x_unused; | |
7763 | wire spare1_inv_32x_unused; | |
7764 | wire spare2_buf_32x_unused; | |
7765 | wire spare2_nand3_8x_unused; | |
7766 | wire spare2_inv_8x_unused; | |
7767 | wire spare2_aoi22_4x_unused; | |
7768 | wire spare2_buf_8x_unused; | |
7769 | wire spare2_oai22_4x_unused; | |
7770 | wire spare2_inv_16x_unused; | |
7771 | wire spare2_nand2_16x_unused; | |
7772 | wire spare2_nor3_4x_unused; | |
7773 | wire spare2_nand2_8x_unused; | |
7774 | wire spare2_buf_16x_unused; | |
7775 | wire spare2_nor2_16x_unused; | |
7776 | wire spare2_inv_32x_unused; | |
7777 | wire spare3_buf_32x_unused; | |
7778 | wire spare3_nand3_8x_unused; | |
7779 | wire spare3_inv_8x_unused; | |
7780 | wire spare3_aoi22_4x_unused; | |
7781 | wire spare3_buf_8x_unused; | |
7782 | wire spare3_oai22_4x_unused; | |
7783 | wire spare3_inv_16x_unused; | |
7784 | wire spare3_nand2_16x_unused; | |
7785 | wire spare3_nor3_4x_unused; | |
7786 | wire spare3_nand2_8x_unused; | |
7787 | wire spare3_buf_16x_unused; | |
7788 | wire spare3_nor2_16x_unused; | |
7789 | wire spare3_inv_32x_unused; | |
7790 | wire spare4_buf_32x_unused; | |
7791 | wire spare4_nand3_8x_unused; | |
7792 | wire spare4_inv_8x_unused; | |
7793 | wire spare4_aoi22_4x_unused; | |
7794 | wire spare4_buf_8x_unused; | |
7795 | wire spare4_oai22_4x_unused; | |
7796 | wire spare4_inv_16x_unused; | |
7797 | wire spare4_nand2_16x_unused; | |
7798 | wire spare4_nor3_4x_unused; | |
7799 | wire spare4_nand2_8x_unused; | |
7800 | wire spare4_buf_16x_unused; | |
7801 | wire spare4_nor2_16x_unused; | |
7802 | wire spare4_inv_32x_unused; | |
7803 | wire spare5_buf_32x_unused; | |
7804 | wire spare5_nand3_8x_unused; | |
7805 | wire spare5_inv_8x_unused; | |
7806 | wire spare5_aoi22_4x_unused; | |
7807 | wire spare5_buf_8x_unused; | |
7808 | wire spare5_oai22_4x_unused; | |
7809 | wire spare5_inv_16x_unused; | |
7810 | wire spare5_nand2_16x_unused; | |
7811 | wire spare5_nor3_4x_unused; | |
7812 | wire spare5_nand2_8x_unused; | |
7813 | wire spare5_buf_16x_unused; | |
7814 | wire spare5_nor2_16x_unused; | |
7815 | wire spare5_inv_32x_unused; | |
7816 | wire spare6_buf_32x_unused; | |
7817 | wire spare6_nand3_8x_unused; | |
7818 | wire spare6_inv_8x_unused; | |
7819 | wire spare6_aoi22_4x_unused; | |
7820 | wire spare6_buf_8x_unused; | |
7821 | wire spare6_oai22_4x_unused; | |
7822 | wire spare6_inv_16x_unused; | |
7823 | wire spare6_nand2_16x_unused; | |
7824 | wire spare6_nor3_4x_unused; | |
7825 | wire spare6_nand2_8x_unused; | |
7826 | wire spare6_buf_16x_unused; | |
7827 | wire spare6_nor2_16x_unused; | |
7828 | wire spare6_inv_32x_unused; | |
7829 | wire spare7_buf_32x_unused; | |
7830 | wire spare7_nand3_8x_unused; | |
7831 | wire spare7_inv_8x_unused; | |
7832 | wire spare7_aoi22_4x_unused; | |
7833 | wire spare7_buf_8x_unused; | |
7834 | wire spare7_oai22_4x_unused; | |
7835 | wire spare7_inv_16x_unused; | |
7836 | wire spare7_nand2_16x_unused; | |
7837 | wire spare7_nor3_4x_unused; | |
7838 | wire spare7_nand2_8x_unused; | |
7839 | wire spare7_buf_16x_unused; | |
7840 | wire spare7_nor2_16x_unused; | |
7841 | wire spare7_inv_32x_unused; | |
7842 | wire spare8_buf_32x_unused; | |
7843 | wire spare8_nand3_8x_unused; | |
7844 | wire spare8_inv_8x_unused; | |
7845 | wire spare8_aoi22_4x_unused; | |
7846 | wire spare8_buf_8x_unused; | |
7847 | wire spare8_oai22_4x_unused; | |
7848 | wire spare8_inv_16x_unused; | |
7849 | wire spare8_nand2_16x_unused; | |
7850 | wire spare8_nor3_4x_unused; | |
7851 | wire spare8_nand2_8x_unused; | |
7852 | wire spare8_buf_16x_unused; | |
7853 | wire spare8_nor2_16x_unused; | |
7854 | wire spare8_inv_32x_unused; | |
7855 | ||
7856 | ||
7857 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
7858 | .out(spare0_buf_32x_unused)); | |
7859 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
7860 | .in1(1'b1), | |
7861 | .in2(1'b1), | |
7862 | .out(spare0_nand3_8x_unused)); | |
7863 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
7864 | .out(spare0_inv_8x_unused)); | |
7865 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
7866 | .in01(1'b1), | |
7867 | .in10(1'b1), | |
7868 | .in11(1'b1), | |
7869 | .out(spare0_aoi22_4x_unused)); | |
7870 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
7871 | .out(spare0_buf_8x_unused)); | |
7872 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
7873 | .in01(1'b1), | |
7874 | .in10(1'b1), | |
7875 | .in11(1'b1), | |
7876 | .out(spare0_oai22_4x_unused)); | |
7877 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
7878 | .out(spare0_inv_16x_unused)); | |
7879 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
7880 | .in1(1'b1), | |
7881 | .out(spare0_nand2_16x_unused)); | |
7882 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
7883 | .in1(1'b0), | |
7884 | .in2(1'b0), | |
7885 | .out(spare0_nor3_4x_unused)); | |
7886 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
7887 | .in1(1'b1), | |
7888 | .out(spare0_nand2_8x_unused)); | |
7889 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
7890 | .out(spare0_buf_16x_unused)); | |
7891 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
7892 | .in1(1'b0), | |
7893 | .out(spare0_nor2_16x_unused)); | |
7894 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
7895 | .out(spare0_inv_32x_unused)); | |
7896 | ||
7897 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
7898 | .out(spare1_buf_32x_unused)); | |
7899 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
7900 | .in1(1'b1), | |
7901 | .in2(1'b1), | |
7902 | .out(spare1_nand3_8x_unused)); | |
7903 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
7904 | .out(spare1_inv_8x_unused)); | |
7905 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
7906 | .in01(1'b1), | |
7907 | .in10(1'b1), | |
7908 | .in11(1'b1), | |
7909 | .out(spare1_aoi22_4x_unused)); | |
7910 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
7911 | .out(spare1_buf_8x_unused)); | |
7912 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
7913 | .in01(1'b1), | |
7914 | .in10(1'b1), | |
7915 | .in11(1'b1), | |
7916 | .out(spare1_oai22_4x_unused)); | |
7917 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
7918 | .out(spare1_inv_16x_unused)); | |
7919 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
7920 | .in1(1'b1), | |
7921 | .out(spare1_nand2_16x_unused)); | |
7922 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
7923 | .in1(1'b0), | |
7924 | .in2(1'b0), | |
7925 | .out(spare1_nor3_4x_unused)); | |
7926 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
7927 | .in1(1'b1), | |
7928 | .out(spare1_nand2_8x_unused)); | |
7929 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
7930 | .out(spare1_buf_16x_unused)); | |
7931 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
7932 | .in1(1'b0), | |
7933 | .out(spare1_nor2_16x_unused)); | |
7934 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
7935 | .out(spare1_inv_32x_unused)); | |
7936 | ||
7937 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
7938 | .out(spare2_buf_32x_unused)); | |
7939 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
7940 | .in1(1'b1), | |
7941 | .in2(1'b1), | |
7942 | .out(spare2_nand3_8x_unused)); | |
7943 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
7944 | .out(spare2_inv_8x_unused)); | |
7945 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
7946 | .in01(1'b1), | |
7947 | .in10(1'b1), | |
7948 | .in11(1'b1), | |
7949 | .out(spare2_aoi22_4x_unused)); | |
7950 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
7951 | .out(spare2_buf_8x_unused)); | |
7952 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
7953 | .in01(1'b1), | |
7954 | .in10(1'b1), | |
7955 | .in11(1'b1), | |
7956 | .out(spare2_oai22_4x_unused)); | |
7957 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
7958 | .out(spare2_inv_16x_unused)); | |
7959 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
7960 | .in1(1'b1), | |
7961 | .out(spare2_nand2_16x_unused)); | |
7962 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
7963 | .in1(1'b0), | |
7964 | .in2(1'b0), | |
7965 | .out(spare2_nor3_4x_unused)); | |
7966 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
7967 | .in1(1'b1), | |
7968 | .out(spare2_nand2_8x_unused)); | |
7969 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
7970 | .out(spare2_buf_16x_unused)); | |
7971 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
7972 | .in1(1'b0), | |
7973 | .out(spare2_nor2_16x_unused)); | |
7974 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
7975 | .out(spare2_inv_32x_unused)); | |
7976 | ||
7977 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
7978 | .out(spare3_buf_32x_unused)); | |
7979 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
7980 | .in1(1'b1), | |
7981 | .in2(1'b1), | |
7982 | .out(spare3_nand3_8x_unused)); | |
7983 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
7984 | .out(spare3_inv_8x_unused)); | |
7985 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
7986 | .in01(1'b1), | |
7987 | .in10(1'b1), | |
7988 | .in11(1'b1), | |
7989 | .out(spare3_aoi22_4x_unused)); | |
7990 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
7991 | .out(spare3_buf_8x_unused)); | |
7992 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
7993 | .in01(1'b1), | |
7994 | .in10(1'b1), | |
7995 | .in11(1'b1), | |
7996 | .out(spare3_oai22_4x_unused)); | |
7997 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
7998 | .out(spare3_inv_16x_unused)); | |
7999 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
8000 | .in1(1'b1), | |
8001 | .out(spare3_nand2_16x_unused)); | |
8002 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
8003 | .in1(1'b0), | |
8004 | .in2(1'b0), | |
8005 | .out(spare3_nor3_4x_unused)); | |
8006 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
8007 | .in1(1'b1), | |
8008 | .out(spare3_nand2_8x_unused)); | |
8009 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
8010 | .out(spare3_buf_16x_unused)); | |
8011 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
8012 | .in1(1'b0), | |
8013 | .out(spare3_nor2_16x_unused)); | |
8014 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
8015 | .out(spare3_inv_32x_unused)); | |
8016 | ||
8017 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
8018 | .out(spare4_buf_32x_unused)); | |
8019 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
8020 | .in1(1'b1), | |
8021 | .in2(1'b1), | |
8022 | .out(spare4_nand3_8x_unused)); | |
8023 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
8024 | .out(spare4_inv_8x_unused)); | |
8025 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
8026 | .in01(1'b1), | |
8027 | .in10(1'b1), | |
8028 | .in11(1'b1), | |
8029 | .out(spare4_aoi22_4x_unused)); | |
8030 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
8031 | .out(spare4_buf_8x_unused)); | |
8032 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
8033 | .in01(1'b1), | |
8034 | .in10(1'b1), | |
8035 | .in11(1'b1), | |
8036 | .out(spare4_oai22_4x_unused)); | |
8037 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
8038 | .out(spare4_inv_16x_unused)); | |
8039 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
8040 | .in1(1'b1), | |
8041 | .out(spare4_nand2_16x_unused)); | |
8042 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
8043 | .in1(1'b0), | |
8044 | .in2(1'b0), | |
8045 | .out(spare4_nor3_4x_unused)); | |
8046 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
8047 | .in1(1'b1), | |
8048 | .out(spare4_nand2_8x_unused)); | |
8049 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
8050 | .out(spare4_buf_16x_unused)); | |
8051 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
8052 | .in1(1'b0), | |
8053 | .out(spare4_nor2_16x_unused)); | |
8054 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
8055 | .out(spare4_inv_32x_unused)); | |
8056 | ||
8057 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
8058 | .out(spare5_buf_32x_unused)); | |
8059 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
8060 | .in1(1'b1), | |
8061 | .in2(1'b1), | |
8062 | .out(spare5_nand3_8x_unused)); | |
8063 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
8064 | .out(spare5_inv_8x_unused)); | |
8065 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
8066 | .in01(1'b1), | |
8067 | .in10(1'b1), | |
8068 | .in11(1'b1), | |
8069 | .out(spare5_aoi22_4x_unused)); | |
8070 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
8071 | .out(spare5_buf_8x_unused)); | |
8072 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
8073 | .in01(1'b1), | |
8074 | .in10(1'b1), | |
8075 | .in11(1'b1), | |
8076 | .out(spare5_oai22_4x_unused)); | |
8077 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
8078 | .out(spare5_inv_16x_unused)); | |
8079 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
8080 | .in1(1'b1), | |
8081 | .out(spare5_nand2_16x_unused)); | |
8082 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
8083 | .in1(1'b0), | |
8084 | .in2(1'b0), | |
8085 | .out(spare5_nor3_4x_unused)); | |
8086 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
8087 | .in1(1'b1), | |
8088 | .out(spare5_nand2_8x_unused)); | |
8089 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
8090 | .out(spare5_buf_16x_unused)); | |
8091 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
8092 | .in1(1'b0), | |
8093 | .out(spare5_nor2_16x_unused)); | |
8094 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
8095 | .out(spare5_inv_32x_unused)); | |
8096 | ||
8097 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
8098 | .out(spare6_buf_32x_unused)); | |
8099 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
8100 | .in1(1'b1), | |
8101 | .in2(1'b1), | |
8102 | .out(spare6_nand3_8x_unused)); | |
8103 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
8104 | .out(spare6_inv_8x_unused)); | |
8105 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
8106 | .in01(1'b1), | |
8107 | .in10(1'b1), | |
8108 | .in11(1'b1), | |
8109 | .out(spare6_aoi22_4x_unused)); | |
8110 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
8111 | .out(spare6_buf_8x_unused)); | |
8112 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
8113 | .in01(1'b1), | |
8114 | .in10(1'b1), | |
8115 | .in11(1'b1), | |
8116 | .out(spare6_oai22_4x_unused)); | |
8117 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
8118 | .out(spare6_inv_16x_unused)); | |
8119 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
8120 | .in1(1'b1), | |
8121 | .out(spare6_nand2_16x_unused)); | |
8122 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
8123 | .in1(1'b0), | |
8124 | .in2(1'b0), | |
8125 | .out(spare6_nor3_4x_unused)); | |
8126 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
8127 | .in1(1'b1), | |
8128 | .out(spare6_nand2_8x_unused)); | |
8129 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
8130 | .out(spare6_buf_16x_unused)); | |
8131 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
8132 | .in1(1'b0), | |
8133 | .out(spare6_nor2_16x_unused)); | |
8134 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
8135 | .out(spare6_inv_32x_unused)); | |
8136 | ||
8137 | cl_u1_buf_32x spare7_buf_32x (.in(1'b1), | |
8138 | .out(spare7_buf_32x_unused)); | |
8139 | cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1), | |
8140 | .in1(1'b1), | |
8141 | .in2(1'b1), | |
8142 | .out(spare7_nand3_8x_unused)); | |
8143 | cl_u1_inv_8x spare7_inv_8x (.in(1'b1), | |
8144 | .out(spare7_inv_8x_unused)); | |
8145 | cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1), | |
8146 | .in01(1'b1), | |
8147 | .in10(1'b1), | |
8148 | .in11(1'b1), | |
8149 | .out(spare7_aoi22_4x_unused)); | |
8150 | cl_u1_buf_8x spare7_buf_8x (.in(1'b1), | |
8151 | .out(spare7_buf_8x_unused)); | |
8152 | cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1), | |
8153 | .in01(1'b1), | |
8154 | .in10(1'b1), | |
8155 | .in11(1'b1), | |
8156 | .out(spare7_oai22_4x_unused)); | |
8157 | cl_u1_inv_16x spare7_inv_16x (.in(1'b1), | |
8158 | .out(spare7_inv_16x_unused)); | |
8159 | cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1), | |
8160 | .in1(1'b1), | |
8161 | .out(spare7_nand2_16x_unused)); | |
8162 | cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0), | |
8163 | .in1(1'b0), | |
8164 | .in2(1'b0), | |
8165 | .out(spare7_nor3_4x_unused)); | |
8166 | cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1), | |
8167 | .in1(1'b1), | |
8168 | .out(spare7_nand2_8x_unused)); | |
8169 | cl_u1_buf_16x spare7_buf_16x (.in(1'b1), | |
8170 | .out(spare7_buf_16x_unused)); | |
8171 | cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0), | |
8172 | .in1(1'b0), | |
8173 | .out(spare7_nor2_16x_unused)); | |
8174 | cl_u1_inv_32x spare7_inv_32x (.in(1'b1), | |
8175 | .out(spare7_inv_32x_unused)); | |
8176 | ||
8177 | cl_u1_buf_32x spare8_buf_32x (.in(1'b1), | |
8178 | .out(spare8_buf_32x_unused)); | |
8179 | cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1), | |
8180 | .in1(1'b1), | |
8181 | .in2(1'b1), | |
8182 | .out(spare8_nand3_8x_unused)); | |
8183 | cl_u1_inv_8x spare8_inv_8x (.in(1'b1), | |
8184 | .out(spare8_inv_8x_unused)); | |
8185 | cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1), | |
8186 | .in01(1'b1), | |
8187 | .in10(1'b1), | |
8188 | .in11(1'b1), | |
8189 | .out(spare8_aoi22_4x_unused)); | |
8190 | cl_u1_buf_8x spare8_buf_8x (.in(1'b1), | |
8191 | .out(spare8_buf_8x_unused)); | |
8192 | cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1), | |
8193 | .in01(1'b1), | |
8194 | .in10(1'b1), | |
8195 | .in11(1'b1), | |
8196 | .out(spare8_oai22_4x_unused)); | |
8197 | cl_u1_inv_16x spare8_inv_16x (.in(1'b1), | |
8198 | .out(spare8_inv_16x_unused)); | |
8199 | cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1), | |
8200 | .in1(1'b1), | |
8201 | .out(spare8_nand2_16x_unused)); | |
8202 | cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0), | |
8203 | .in1(1'b0), | |
8204 | .in2(1'b0), | |
8205 | .out(spare8_nor3_4x_unused)); | |
8206 | cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1), | |
8207 | .in1(1'b1), | |
8208 | .out(spare8_nand2_8x_unused)); | |
8209 | cl_u1_buf_16x spare8_buf_16x (.in(1'b1), | |
8210 | .out(spare8_buf_16x_unused)); | |
8211 | cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0), | |
8212 | .in1(1'b0), | |
8213 | .out(spare8_nor2_16x_unused)); | |
8214 | cl_u1_inv_32x spare8_inv_32x (.in(1'b1), | |
8215 | .out(spare8_inv_32x_unused)); | |
8216 | ||
8217 | ||
8218 | ||
8219 | endmodule | |
8220 | ||
8221 | ||
8222 | ||
8223 | ||
8224 | ||
8225 | ||
8226 | // any PARAMS parms go into naming of macro | |
8227 | ||
8228 | module tcu_sigmux_ctl_msff_ctl_macro__scanreverse_1__width_9 ( | |
8229 | din, | |
8230 | l1clk, | |
8231 | scan_in, | |
8232 | siclk, | |
8233 | soclk, | |
8234 | dout, | |
8235 | scan_out); | |
8236 | wire [8:0] fdin; | |
8237 | wire [0:7] so; | |
8238 | ||
8239 | input [8:0] din; | |
8240 | input l1clk; | |
8241 | input scan_in; | |
8242 | ||
8243 | ||
8244 | input siclk; | |
8245 | input soclk; | |
8246 | ||
8247 | output [8:0] dout; | |
8248 | output scan_out; | |
8249 | assign fdin[8:0] = din[8:0]; | |
8250 | ||
8251 | ||
8252 | ||
8253 | ||
8254 | ||
8255 | ||
8256 | dff #(9) d0_0 ( | |
8257 | .l1clk(l1clk), | |
8258 | .siclk(siclk), | |
8259 | .soclk(soclk), | |
8260 | .d(fdin[8:0]), | |
8261 | .si({so[0:7],scan_in}), | |
8262 | .so({scan_out,so[0:7]}), | |
8263 | .q(dout[8:0]) | |
8264 | ); | |
8265 | ||
8266 | ||
8267 | ||
8268 | ||
8269 | ||
8270 | ||
8271 | ||
8272 | ||
8273 | ||
8274 | ||
8275 | ||
8276 | ||
8277 | endmodule | |
8278 | ||
8279 | ||
8280 | ||
8281 | ||
8282 | ||
8283 | ||
8284 | ||
8285 |