Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / tds / rtl / tds_l2l1clk_io2x.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tds_l2l1clk_io2x.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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///////////////////////////////////////////////////////////////////////////////
//   tds_l2l1clk_io
///////////////////////////////////////////////////////////////////////////////

module tds_l2l1clk_io2x ( 
	l1clk,
	aclk,
	bclk,
	scan_out,
	pce_ov,
	aclk_wmr,
	wmr_protect,
	wmr_,
	por_,
	cmp_slow_sync_en,
	slow_cmp_sync_en,
	tcu_clk_stop,
	tcu_pce_ov,
	rst_wmr_protect,
	rst_wmr_,
	rst_por_,
//        ccu_cmp_slow_sync_en,
//        ccu_slow_cmp_sync_en,
	tcu_div_bypass,
	ccu_div_ph,
	cluster_div_en,
	gclk,
	cluster_arst_l,
	clk_ext,
	ccu_serdes_dtm,
	tcu_aclk,
	tcu_bclk,
	scan_en,
	scan_in
);

 
// ************************** 
// port declaration 
// ************************** 

// clock & test out
output	l1clk;	// assume we do not need aclk, bclk outputs
output	aclk;	// buffered version of aclk
output	bclk;	// buffered version of bclk
output	scan_out;		// unused as of today - feb 10, 05
output  aclk_wmr;

// pipelined out
output	pce_ov;				// pce override to l1 header
output	wmr_protect;		// warm reset protect
output	wmr_;				// warm reset (active low) 
output	por_;				// power-on-reset 
output	cmp_slow_sync_en;	// cmp->slow clk sync pulse
output	slow_cmp_sync_en;	// slow->cmp clk sync pulse

// ctrl in (for pipelining)
input	tcu_clk_stop;
input	tcu_pce_ov;
input	rst_wmr_protect;		
input	rst_wmr_;		
input	rst_por_;
// input   ccu_cmp_slow_sync_en;
// input   ccu_slow_cmp_sync_en;
// ctrl in (for clock gen) 
input	tcu_div_bypass;		// bypasses clk divider to mux in ext clk
input	ccu_div_ph;			// phase signal from ccu (div/4 or div/2)
input   cluster_div_en;		// if enabled, l2clk is divided down 

// clock & test in
input	gclk;			// global clk - this is either cmp or dr
input	cluster_arst_l;
input 	ccu_serdes_dtm;
input	clk_ext;		// external clk muxed in for ioclk bypass 
input	scan_en;		// unused as of today - feb 10, 05
input	scan_in;		// unused as of today - feb 10, 05
input	tcu_aclk;				
input	tcu_bclk;


// ************************** 
// wire declaration 
// ************************** 
wire	io2xl2clk;	
wire	aclk;
wire	bclk;
wire	scan_out;
wire	aclk_wmr;	
wire	pce_ov;
wire	wmr_protect;
wire	wmr_;
wire	por_;
wire	cmp_slow_sync_en;
wire	slow_cmp_sync_en;
wire	tcu_clk_stop;
wire	tcu_pce_ov;
wire	rst_wmr_protect;
wire	rst_wmr_;
wire	rst_por_;
// wire    ccu_cmp_slow_sync_en;
// wire    ccu_slow_cmp_sync_en;
wire	tcu_div_bypass;
wire	ccu_div_ph;
wire	cluster_div_en;
wire	gclk;
wire	cluster_arst_l;
wire	clk_ext;
wire	ccu_serdes_dtm;
wire	scan_en;				
wire	scan_in;				
wire	tcu_aclk;				
wire	tcu_bclk;

// ************************** 
// instantiations
// ************************** 
 clkgen_tds_io2x clkgen_tds_io2x ( 

   .l2clk(io2xl2clk), 
   .aclk(aclk), 
   .bclk(bclk),
   .scan_out(scan_out),
   .pce_ov(pce_ov),
   .aclk_wmr(aclk_wmr),
   .wmr_protect(wmr_protect),
   .wmr_(wmr_),
   .por_(por_),
   .cmp_slow_sync_en(cmp_slow_sync_en),
   .slow_cmp_sync_en(slow_cmp_sync_en),
   .tcu_clk_stop(tcu_clk_stop),
   .tcu_pce_ov(tcu_pce_ov),
   .rst_wmr_protect(rst_wmr_protect),
   .rst_wmr_(rst_wmr_),
   .rst_por_(rst_por_),
//   .ccu_cmp_slow_sync_en(ccu_cmp_slow_sync_en),
//   .ccu_slow_cmp_sync_en(ccu_slow_cmp_sync_en),
   .ccu_cmp_slow_sync_en(1'b0),
   .ccu_slow_cmp_sync_en(1'b0),
   .tcu_div_bypass(tcu_div_bypass),
   .ccu_div_ph(ccu_div_ph),
   .cluster_div_en(cluster_div_en),
   .gclk(gclk),
   .cluster_arst_l(cluster_arst_l),

   .clk_ext(clk_ext),
   .ccu_serdes_dtm(ccu_serdes_dtm),

   .tcu_aclk(tcu_aclk),
   .tcu_bclk(tcu_bclk),
   .scan_en(scan_en),
   .scan_in(scan_in) );


 cl_a1_l1hdr_8x tds_l1clk_1 ( .l2clk(io2xl2clk), .se(scan_en), .pce(1'b1),
      .pce_ov(pce_ov), .stop(tcu_clk_stop), .l1clk(l1clk) );


endmodule