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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_rtl_ext.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mux2e ( dout, in0, in1, sel ); | |
36 | ||
37 | parameter SIZE = 1; | |
38 | ||
39 | output [SIZE-1:0] dout; | |
40 | input [SIZE-1:0] in0; | |
41 | input [SIZE-1:0] in1; | |
42 | input sel; | |
43 | ||
44 | reg [SIZE-1:0] dout; | |
45 | ||
46 | always @ ( sel or in0 or in1 ) | |
47 | begin | |
48 | case ( sel ) | |
49 | 1'b0: dout = in0; | |
50 | 1'b1: dout = in1; | |
51 | ||
52 | default: | |
53 | dout = { SIZE { 1'bx } }; | |
54 | endcase // case( sel ) | |
55 | end // always @ ( sel or in0 or in1 ) | |
56 | ||
57 | endmodule // mux2e | |
58 | ||
59 | ||
60 | module mux3 ( dout, in0, in1, in2, | |
61 | sel0, sel1, sel2, muxtst ); | |
62 | ||
63 | parameter SIZE = 1; | |
64 | ||
65 | output [SIZE-1:0] dout; | |
66 | input [SIZE-1:0] in0; | |
67 | input [SIZE-1:0] in1; | |
68 | input [SIZE-1:0] in2; | |
69 | input sel0; | |
70 | input sel1; | |
71 | input sel2; | |
72 | input muxtst; | |
73 | ||
74 | wire [3:0] sel = { muxtst, sel2, sel1, sel0 }; | |
75 | ||
76 | reg [SIZE-1:0] dout; | |
77 | ||
78 | `ifdef MUXOHTEST | |
79 | //0in one_hot -var sel[2:0] -message "mux3 selects not one-hot!" | |
80 | `endif | |
81 | ||
82 | always @ ( sel or in0 or in1 or in2 ) | |
83 | casex ( sel ) | |
84 | 4'bx001: dout = in0; | |
85 | 4'bx010: dout = in1; | |
86 | 4'bx100: dout = in2; | |
87 | 4'b0000: dout = { SIZE {1'b1 }}; | |
88 | ||
89 | default: | |
90 | dout = { SIZE { 1'bx } }; | |
91 | endcase // case( sel ) | |
92 | ||
93 | endmodule // mux3 | |
94 | ||
95 | ||
96 | module mux4 ( dout, in0, in1, in2, in3, | |
97 | sel0, sel1, sel2, sel3, muxtst ); | |
98 | ||
99 | parameter SIZE = 1; | |
100 | ||
101 | output [SIZE-1:0] dout; | |
102 | input [SIZE-1:0] in0; | |
103 | input [SIZE-1:0] in1; | |
104 | input [SIZE-1:0] in2; | |
105 | input [SIZE-1:0] in3; | |
106 | input sel0; | |
107 | input sel1; | |
108 | input sel2; | |
109 | input sel3; | |
110 | input muxtst; | |
111 | ||
112 | wire [4:0] sel = { muxtst, sel3, sel2, sel1, sel0 }; | |
113 | ||
114 | reg [SIZE-1:0] dout; | |
115 | ||
116 | `ifdef MUXOHTEST | |
117 | //0in one_hot -var sel[3:0] -message "mux4 selects not one-hot!" | |
118 | `endif | |
119 | ||
120 | always @ ( sel or in0 or in1 or in2 or in3 ) | |
121 | casex ( sel ) | |
122 | 5'bx0001: dout = in0; | |
123 | 5'bx0010: dout = in1; | |
124 | 5'bx0100: dout = in2; | |
125 | 5'bx1000: dout = in3; | |
126 | 5'b00000: dout = { SIZE { 1'b1 } }; | |
127 | ||
128 | default: | |
129 | dout = { SIZE { 1'bx } }; | |
130 | endcase // case( sel ) | |
131 | ||
132 | ||
133 | endmodule // mux4 | |
134 | ||
135 | ||
136 | module mux5 ( dout, in0, in1, in2, in3, in4, | |
137 | sel0, sel1, sel2, sel3, sel4, muxtst ); | |
138 | ||
139 | parameter SIZE = 1; | |
140 | ||
141 | output [SIZE-1:0] dout; | |
142 | input [SIZE-1:0] in0; | |
143 | input [SIZE-1:0] in1; | |
144 | input [SIZE-1:0] in2; | |
145 | input [SIZE-1:0] in3; | |
146 | input [SIZE-1:0] in4; | |
147 | input sel0; | |
148 | input sel1; | |
149 | input sel2; | |
150 | input sel3; | |
151 | input sel4; | |
152 | input muxtst; | |
153 | ||
154 | wire [5:0] sel = { muxtst, sel4, sel3, sel2, sel1, sel0 }; | |
155 | ||
156 | reg [SIZE-1:0] dout; | |
157 | ||
158 | `ifdef MUXOHTEST | |
159 | //0in one_hot -var sel[4:0] -message "mux5 selects not one-hot!" | |
160 | `endif | |
161 | ||
162 | always @ ( sel or in0 or in1 or in2 or in3 or in4 ) | |
163 | casex ( sel ) | |
164 | 6'bx00001: dout = in0; | |
165 | 6'bx00010: dout = in1; | |
166 | 6'bx00100: dout = in2; | |
167 | 6'bx01000: dout = in3; | |
168 | 6'bx10000: dout = in4; | |
169 | 6'b000000: dout = { SIZE { 1'b1 }}; | |
170 | ||
171 | default: | |
172 | dout = { SIZE { 1'bx } }; | |
173 | endcase // case( sel ) | |
174 | ||
175 | endmodule // mux5 | |
176 | ||
177 | ||
178 | module mux6 ( dout, in0, in1, in2, in3, in4, in5, | |
179 | sel0, sel1, sel2, sel3, sel4, sel5, muxtst ); | |
180 | ||
181 | parameter SIZE = 1; | |
182 | ||
183 | output [SIZE-1:0] dout; | |
184 | input [SIZE-1:0] in0; | |
185 | input [SIZE-1:0] in1; | |
186 | input [SIZE-1:0] in2; | |
187 | input [SIZE-1:0] in3; | |
188 | input [SIZE-1:0] in4; | |
189 | input [SIZE-1:0] in5; | |
190 | input sel0; | |
191 | input sel1; | |
192 | input sel2; | |
193 | input sel3; | |
194 | input sel4; | |
195 | input sel5; | |
196 | input muxtst; | |
197 | ||
198 | wire [6:0] sel = { muxtst, sel5, | |
199 | sel4, sel3, sel2, sel1, sel0 }; | |
200 | ||
201 | reg [SIZE-1:0] dout; | |
202 | ||
203 | `ifdef MUXOHTEST | |
204 | //0in one_hot -var sel[5:0] -message "mux6 selects not one-hot!" | |
205 | `endif | |
206 | ||
207 | always @ ( sel or in0 or in1 or in2 or in3 or in4 or | |
208 | in5 ) | |
209 | casex ( sel ) | |
210 | 7'bx000001: dout = in0; | |
211 | 7'bx000010: dout = in1; | |
212 | 7'bx000100: dout = in2; | |
213 | 7'bx001000: dout = in3; | |
214 | 7'bx010000: dout = in4; | |
215 | 7'bx100000: dout = in5; | |
216 | 7'b0000000: dout = { SIZE { 1'b1 } }; | |
217 | ||
218 | default: | |
219 | dout = { SIZE { 1'bx } }; | |
220 | endcase // case( sel ) | |
221 | ||
222 | endmodule // mux6 | |
223 | ||
224 | ||
225 | module mux7 ( dout, in0, in1, in2, in3, in4, in5, in6, | |
226 | sel0, sel1, sel2, sel3, sel4, sel5, sel6, muxtst ); | |
227 | ||
228 | parameter SIZE = 1; | |
229 | ||
230 | output [SIZE-1:0] dout; | |
231 | input [SIZE-1:0] in0; | |
232 | input [SIZE-1:0] in1; | |
233 | input [SIZE-1:0] in2; | |
234 | input [SIZE-1:0] in3; | |
235 | input [SIZE-1:0] in4; | |
236 | input [SIZE-1:0] in5; | |
237 | input [SIZE-1:0] in6; | |
238 | input sel0; | |
239 | input sel1; | |
240 | input sel2; | |
241 | input sel3; | |
242 | input sel4; | |
243 | input sel5; | |
244 | input sel6; | |
245 | input muxtst; | |
246 | ||
247 | wire [7:0] sel = { muxtst, sel6, sel5, | |
248 | sel4, sel3, sel2, sel1, sel0 }; | |
249 | reg [SIZE-1:0] dout; | |
250 | ||
251 | `ifdef MUXOHTEST | |
252 | //0in one_hot -var sel[6:0] -message "mux7 selects not one-hot!" | |
253 | `endif | |
254 | ||
255 | always @ ( sel or in0 or in1 or in2 or in3 or in4 or | |
256 | in5 or in6 ) | |
257 | casex ( sel ) | |
258 | 8'bx0000001: dout = in0; | |
259 | 8'bx0000010: dout = in1; | |
260 | 8'bx0000100: dout = in2; | |
261 | 8'bx0001000: dout = in3; | |
262 | 8'bx0010000: dout = in4; | |
263 | 8'bx0100000: dout = in5; | |
264 | 8'bx1000000: dout = in6; | |
265 | 8'b00000000: dout = { SIZE { 1'b1 } }; | |
266 | ||
267 | default: | |
268 | dout = { SIZE { 1'bx } }; | |
269 | endcase // case( sel ) | |
270 | ||
271 | endmodule // mux7 | |
272 | ||
273 | ||
274 | module mux8 ( dout, in0, in1, in2, in3, in4, in5, in6, in7, | |
275 | sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, muxtst ); | |
276 | ||
277 | parameter SIZE = 1; | |
278 | ||
279 | output [SIZE-1:0] dout; | |
280 | input [SIZE-1:0] in0; | |
281 | input [SIZE-1:0] in1; | |
282 | input [SIZE-1:0] in2; | |
283 | input [SIZE-1:0] in3; | |
284 | input [SIZE-1:0] in4; | |
285 | input [SIZE-1:0] in5; | |
286 | input [SIZE-1:0] in6; | |
287 | input [SIZE-1:0] in7; | |
288 | input sel0; | |
289 | input sel1; | |
290 | input sel2; | |
291 | input sel3; | |
292 | input sel4; | |
293 | input sel5; | |
294 | input sel6; | |
295 | input sel7; | |
296 | input muxtst; | |
297 | ||
298 | wire [8:0] sel = { muxtst, sel7, sel6, sel5, | |
299 | sel4, sel3, sel2, sel1, sel0 }; | |
300 | reg [SIZE-1:0] dout; | |
301 | ||
302 | `ifdef MUXOHTEST | |
303 | //0in one_hot -var sel[7:0] -message "mux8 selects not one-hot!" | |
304 | `endif | |
305 | ||
306 | always @ ( sel or in0 or in1 or in2 or in3 or in4 or | |
307 | in5 or in6 or in7 ) | |
308 | casex ( sel ) | |
309 | 9'bx00000001: dout = in0; | |
310 | 9'bx00000010: dout = in1; | |
311 | 9'bx00000100: dout = in2; | |
312 | 9'bx00001000: dout = in3; | |
313 | 9'bx00010000: dout = in4; | |
314 | 9'bx00100000: dout = in5; | |
315 | 9'bx01000000: dout = in6; | |
316 | 9'bx10000000: dout = in7; | |
317 | 9'b000000000: dout = { SIZE { 1'b1 } }; | |
318 | ||
319 | default: | |
320 | dout = { SIZE { 1'bx } }; | |
321 | endcase // case( sel ) | |
322 | ||
323 | endmodule // mux8 | |
324 | ||
325 | ||
326 | `ifdef FPGA | |
327 | `else | |
328 | module mux2s ( dout, in0, in1, | |
329 | sel0, sel1 ); | |
330 | ||
331 | parameter SIZE = 1; | |
332 | ||
333 | output [SIZE-1:0] dout; | |
334 | input [SIZE-1:0] in0; | |
335 | input [SIZE-1:0] in1; | |
336 | input sel0; | |
337 | input sel1; | |
338 | ||
339 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
340 | ( in1 & { SIZE { sel1 } } ) ); | |
341 | ||
342 | endmodule // mux2s | |
343 | `endif // `ifdef FPGA | |
344 | ||
345 | ||
346 | module mux3s ( dout, in0, in1, in2, | |
347 | sel0, sel1, sel2 ); | |
348 | ||
349 | parameter SIZE = 1; | |
350 | ||
351 | output [SIZE-1:0] dout; | |
352 | input [SIZE-1:0] in0; | |
353 | input [SIZE-1:0] in1; | |
354 | input [SIZE-1:0] in2; | |
355 | input sel0; | |
356 | input sel1; | |
357 | input sel2; | |
358 | ||
359 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
360 | ( in1 & { SIZE { sel1 } } ) | | |
361 | ( in2 & { SIZE { sel2 } } ) ); | |
362 | ||
363 | endmodule // mux3s | |
364 | ||
365 | ||
366 | `ifdef FPGA | |
367 | `else | |
368 | module mux4s ( dout, in0, in1, in2, in3, | |
369 | sel0, sel1, sel2, sel3 ); | |
370 | ||
371 | parameter SIZE = 1; | |
372 | ||
373 | output [SIZE-1:0] dout; | |
374 | input [SIZE-1:0] in0; | |
375 | input [SIZE-1:0] in1; | |
376 | input [SIZE-1:0] in2; | |
377 | input [SIZE-1:0] in3; | |
378 | input sel0; | |
379 | input sel1; | |
380 | input sel2; | |
381 | input sel3; | |
382 | ||
383 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
384 | ( in1 & { SIZE { sel1 } } ) | | |
385 | ( in2 & { SIZE { sel2 } } ) | | |
386 | ( in3 & { SIZE { sel3 } } ) ); | |
387 | ||
388 | endmodule // mux4s | |
389 | `endif // `ifdef FPGA | |
390 | ||
391 | ||
392 | module mux5s ( dout, in0, in1, in2, in3, in4, | |
393 | sel0, sel1, sel2, sel3, sel4 ); | |
394 | ||
395 | parameter SIZE = 1; | |
396 | ||
397 | output [SIZE-1:0] dout; | |
398 | input [SIZE-1:0] in0; | |
399 | input [SIZE-1:0] in1; | |
400 | input [SIZE-1:0] in2; | |
401 | input [SIZE-1:0] in3; | |
402 | input [SIZE-1:0] in4; | |
403 | input sel0; | |
404 | input sel1; | |
405 | input sel2; | |
406 | input sel3; | |
407 | input sel4; | |
408 | ||
409 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
410 | ( in1 & { SIZE { sel1 } } ) | | |
411 | ( in2 & { SIZE { sel2 } } ) | | |
412 | ( in3 & { SIZE { sel3 } } ) | | |
413 | ( in4 & { SIZE { sel4 } } ) ); | |
414 | ||
415 | endmodule // mux5s | |
416 | ||
417 | ||
418 | module mux6s ( dout, in0, in1, in2, in3, in4, in5, | |
419 | sel0, sel1, sel2, sel3, sel4, sel5 ); | |
420 | ||
421 | parameter SIZE = 1; | |
422 | ||
423 | output [SIZE-1:0] dout; | |
424 | input [SIZE-1:0] in0; | |
425 | input [SIZE-1:0] in1; | |
426 | input [SIZE-1:0] in2; | |
427 | input [SIZE-1:0] in3; | |
428 | input [SIZE-1:0] in4; | |
429 | input [SIZE-1:0] in5; | |
430 | input sel0; | |
431 | input sel1; | |
432 | input sel2; | |
433 | input sel3; | |
434 | input sel4; | |
435 | input sel5; | |
436 | ||
437 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
438 | ( in1 & { SIZE { sel1 } } ) | | |
439 | ( in2 & { SIZE { sel2 } } ) | | |
440 | ( in3 & { SIZE { sel3 } } ) | | |
441 | ( in4 & { SIZE { sel4 } } ) | | |
442 | ( in5 & { SIZE { sel5 } } ) ); | |
443 | ||
444 | endmodule // mux6s | |
445 | ||
446 | ||
447 | module mux7s ( dout, in0, in1, in2, in3, in4, in5, in6, | |
448 | sel0, sel1, sel2, sel3, sel4, sel5, sel6 ); | |
449 | ||
450 | parameter SIZE = 1; | |
451 | ||
452 | output [SIZE-1:0] dout; | |
453 | input [SIZE-1:0] in0; | |
454 | input [SIZE-1:0] in1; | |
455 | input [SIZE-1:0] in2; | |
456 | input [SIZE-1:0] in3; | |
457 | input [SIZE-1:0] in4; | |
458 | input [SIZE-1:0] in5; | |
459 | input [SIZE-1:0] in6; | |
460 | input sel0; | |
461 | input sel1; | |
462 | input sel2; | |
463 | input sel3; | |
464 | input sel4; | |
465 | input sel5; | |
466 | input sel6; | |
467 | ||
468 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
469 | ( in1 & { SIZE { sel1 } } ) | | |
470 | ( in2 & { SIZE { sel2 } } ) | | |
471 | ( in3 & { SIZE { sel3 } } ) | | |
472 | ( in4 & { SIZE { sel4 } } ) | | |
473 | ( in5 & { SIZE { sel5 } } ) | | |
474 | ( in6 & { SIZE { sel6 } } ) ); | |
475 | ||
476 | endmodule // mux7s | |
477 | ||
478 | ||
479 | `ifdef FPGA | |
480 | `else | |
481 | module mux8s ( dout, in0, in1, in2, in3, in4, in5, in6, in7, | |
482 | sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 ); | |
483 | ||
484 | parameter SIZE = 1; | |
485 | ||
486 | output [SIZE-1:0] dout; | |
487 | input [SIZE-1:0] in0; | |
488 | input [SIZE-1:0] in1; | |
489 | input [SIZE-1:0] in2; | |
490 | input [SIZE-1:0] in3; | |
491 | input [SIZE-1:0] in4; | |
492 | input [SIZE-1:0] in5; | |
493 | input [SIZE-1:0] in6; | |
494 | input [SIZE-1:0] in7; | |
495 | input sel0; | |
496 | input sel1; | |
497 | input sel2; | |
498 | input sel3; | |
499 | input sel4; | |
500 | input sel5; | |
501 | input sel6; | |
502 | input sel7; | |
503 | ||
504 | assign dout = ( ( in0 & { SIZE { sel0 } } ) | | |
505 | ( in1 & { SIZE { sel1 } } ) | | |
506 | ( in2 & { SIZE { sel2 } } ) | | |
507 | ( in3 & { SIZE { sel3 } } ) | | |
508 | ( in4 & { SIZE { sel4 } } ) | | |
509 | ( in5 & { SIZE { sel5 } } ) | | |
510 | ( in6 & { SIZE { sel6 } } ) | | |
511 | ( in7 & { SIZE { sel7 } } ) ); | |
512 | ||
513 | endmodule // mux8s | |
514 | `endif // `ifdef FPGA | |
515 | ||
516 | // There are inverted and non-inverted versions of this...different between power levels! | |
517 | // First the non-inverting | |
518 | module tisram_blb ( latout_l, d, l1clk); | |
519 | ||
520 | parameter SIZE = 1; | |
521 | ||
522 | ||
523 | output [SIZE-1:0] latout_l; | |
524 | ||
525 | input [SIZE-1:0] d; | |
526 | input l1clk; | |
527 | ||
528 | reg [SIZE-1:0] latout_l; | |
529 | ||
530 | `ifdef SCAN_MODE | |
531 | `else | |
532 | `ifdef INITLATZERO | |
533 | initial latout_l[SIZE-1:0] = {SIZE{1'b0}}; | |
534 | `endif | |
535 | `endif | |
536 | ||
537 | always @(l1clk or d) begin | |
538 | if (!l1clk) latout_l[SIZE-1:0] <= d[SIZE-1:0]; | |
539 | end | |
540 | ||
541 | endmodule | |
542 | ||
543 | // Now the inverting | |
544 | module tisram_blb_inv ( latout_l, d, l1clk); | |
545 | ||
546 | parameter SIZE = 1; | |
547 | ||
548 | ||
549 | output [SIZE-1:0] latout_l; | |
550 | ||
551 | input [SIZE-1:0] d; | |
552 | input l1clk; | |
553 | ||
554 | reg [SIZE-1:0] latout_l; | |
555 | ||
556 | `ifdef SCAN_MODE | |
557 | `else | |
558 | `ifdef INITLATZERO | |
559 | initial latout_l[SIZE-1:0] = {SIZE{1'b0}}; | |
560 | `endif | |
561 | `endif | |
562 | ||
563 | always @(l1clk or d) begin | |
564 | if (!l1clk) latout_l[SIZE-1:0] <= ~d[SIZE-1:0]; | |
565 | end | |
566 | ||
567 | endmodule | |
568 | ||
569 | module tisram_bla (q_a, d_b, l1clk); | |
570 | ||
571 | parameter SIZE = 1; | |
572 | ||
573 | output [SIZE-1:0] q_a; | |
574 | input [SIZE-1:0] d_b; | |
575 | input l1clk; | |
576 | ||
577 | reg [SIZE-1:0] q_a; | |
578 | ||
579 | `ifdef SCAN_MODE | |
580 | `else | |
581 | `ifdef INITLATZERO | |
582 | initial q_a[SIZE-1:0] = {SIZE{1'b0}}; | |
583 | `endif | |
584 | `endif | |
585 | ||
586 | always @(l1clk or d_b) begin | |
587 | if (l1clk==1'b1) | |
588 | q_a[SIZE-1:0] <= d_b[SIZE-1:0]; | |
589 | end | |
590 | ||
591 | endmodule | |
592 | ||
593 | module msffi ( q_l, so, d, l1clk, si, siclk, soclk ); | |
594 | // RFM 05-14-2004 | |
595 | // Level sensitive in SCAN_MODE | |
596 | // Edge triggered when not in SCAN_MODE | |
597 | ||
598 | ||
599 | parameter SIZE = 1; | |
600 | ||
601 | output [SIZE-1:0] q_l; | |
602 | output [SIZE-1:0] so; | |
603 | ||
604 | input [SIZE-1:0] d; | |
605 | input l1clk; | |
606 | input [SIZE-1:0] si; | |
607 | input siclk; | |
608 | input soclk; | |
609 | ||
610 | reg [SIZE-1:0] q; | |
611 | reg [SIZE-1:0] q_l; | |
612 | ||
613 | wire [SIZE-1:0] so; | |
614 | wire l1clk, siclk, soclk; | |
615 | `ifdef SCAN_MODE | |
616 | ||
617 | `ifdef FAST_FLUSH | |
618 | always @(posedge l1clk or posedge siclk ) begin | |
619 | if (siclk) begin | |
620 | q[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
621 | end else begin | |
622 | q[SIZE-1:0] <= d[SIZE-1:0]; | |
623 | end | |
624 | end | |
625 | ||
626 | `else | |
627 | ||
628 | reg [SIZE-1:0] l1; | |
629 | ||
630 | always @(l1clk or siclk or soclk or d or si) | |
631 | begin | |
632 | if (!l1clk && !siclk) l1[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
633 | else if ( l1clk && siclk) l1[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
634 | else if (!l1clk && siclk) l1[SIZE-1:0] <= {SIZE{1'bx}}; // Conflict between data and scan | |
635 | ||
636 | else if ( l1clk && !siclk && !soclk) q[SIZE-1:0] <= l1[SIZE-1:0]; // Load slave with master data | |
637 | if ( l1clk && siclk && !soclk) q[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
638 | end | |
639 | ||
640 | `endif // FAST_FLUSH | |
641 | ||
642 | `else | |
643 | wire [SIZE-1:0] si_unused; | |
644 | wire siclk_unused; | |
645 | wire soclk_unused; | |
646 | assign si_unused[SIZE-1:0] = si[SIZE-1:0]; | |
647 | assign siclk_unused = siclk; | |
648 | assign soclk_unused = soclk; | |
649 | ||
650 | ||
651 | `ifdef INITLATZERO | |
652 | initial q[SIZE-1:0] = {SIZE{1'b0}}; | |
653 | initial q_l[SIZE-1:0] = {SIZE{1'b1}}; | |
654 | `endif | |
655 | ||
656 | always @(posedge l1clk) | |
657 | begin | |
658 | if (!siclk && !soclk) q[SIZE-1:0] <= d[SIZE-1:0]; | |
659 | else q[SIZE-1:0] <= {SIZE{1'bx}}; | |
660 | end | |
661 | `endif | |
662 | ||
663 | always @ (q) q_l=~q; | |
664 | ||
665 | assign so[SIZE-1:0] = q[SIZE-1:0]; | |
666 | ||
667 | endmodule // dff | |
668 | ||
669 | module msffi_dp ( q_l, so, d, l1clk, si, siclk, soclk ); | |
670 | // RFM 05-14-2004 | |
671 | // Level sensitive in SCAN_MODE | |
672 | // Edge triggered when not in SCAN_MODE | |
673 | ||
674 | ||
675 | parameter SIZE = 1; | |
676 | ||
677 | output [SIZE-1:0] q_l; | |
678 | output [SIZE-1:0] so; | |
679 | ||
680 | input [SIZE-1:0] d; | |
681 | input l1clk; | |
682 | input [SIZE-1:0] si; | |
683 | input siclk; | |
684 | input soclk; | |
685 | ||
686 | reg [SIZE-1:0] q; | |
687 | reg [SIZE-1:0] q_l; | |
688 | ||
689 | wire [SIZE-1:0] so; | |
690 | wire l1clk, siclk, soclk; | |
691 | `ifdef SCAN_MODE | |
692 | ||
693 | `ifdef FAST_FLUSH | |
694 | always @(posedge l1clk or posedge siclk ) begin | |
695 | if (siclk) begin | |
696 | q[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
697 | end else begin | |
698 | q[SIZE-1:0] <= d[SIZE-1:0]; | |
699 | end | |
700 | end | |
701 | ||
702 | `else | |
703 | ||
704 | reg [SIZE-1:0] l1; | |
705 | ||
706 | always @(l1clk or siclk or soclk or d or si) | |
707 | begin | |
708 | if (!l1clk && !siclk) l1[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
709 | else if ( l1clk && siclk) l1[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
710 | else if (!l1clk && siclk) l1[SIZE-1:0] <= {SIZE{1'bx}}; // Conflict between data and scan | |
711 | ||
712 | else if ( l1clk && !siclk && !soclk) q[SIZE-1:0] <= l1[SIZE-1:0]; // Load slave with master data | |
713 | if ( l1clk && siclk && !soclk) q[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
714 | end | |
715 | ||
716 | `endif // FAST_FLUSH | |
717 | ||
718 | `else | |
719 | wire [SIZE-1:0] si_unused; | |
720 | wire siclk_unused; | |
721 | wire soclk_unused; | |
722 | assign si_unused[SIZE-1:0] = si[SIZE-1:0]; | |
723 | assign siclk_unused = siclk; | |
724 | assign soclk_unused = soclk; | |
725 | ||
726 | ||
727 | `ifdef INITLATZERO | |
728 | // dp macro inits to 0! | |
729 | initial q[SIZE-1:0] = {SIZE{1'b0}}; | |
730 | initial q_l[SIZE-1:0] = {SIZE{1'b1}}; | |
731 | `endif | |
732 | ||
733 | always @(posedge l1clk) | |
734 | begin | |
735 | if (!siclk && !soclk) q[SIZE-1:0] <= d[SIZE-1:0]; | |
736 | else q[SIZE-1:0] <= {SIZE{1'bx}}; | |
737 | end | |
738 | `endif | |
739 | ||
740 | always @ (q) q_l=~q; | |
741 | ||
742 | // Fake inversion | |
743 | assign so[SIZE-1:0] = q[SIZE-1:0]; | |
744 | ||
745 | endmodule // msffi_dp | |
746 | ||
747 | module msffiz_dp ( q_l, so, d, l1clk, si, siclk, soclk ); | |
748 | // RFM 05-14-2004 | |
749 | // Level sensitive in SCAN_MODE | |
750 | // Edge triggered when not in SCAN_MODE | |
751 | ||
752 | ||
753 | parameter SIZE = 1; | |
754 | ||
755 | output [SIZE-1:0] q_l; | |
756 | output [SIZE-1:0] so; | |
757 | ||
758 | input [SIZE-1:0] d; | |
759 | input [SIZE-1:0] si; | |
760 | input l1clk; | |
761 | input siclk; | |
762 | input soclk; | |
763 | ||
764 | reg [SIZE-1:0] q_l; | |
765 | ||
766 | wire [SIZE-1:0] so; | |
767 | wire l1clk, siclk, soclk; | |
768 | ||
769 | `ifdef SCAN_MODE | |
770 | ||
771 | `ifdef FAST_FLUSH | |
772 | always @(posedge l1clk or posedge siclk ) begin | |
773 | if (siclk) begin | |
774 | q_l[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
775 | end else begin | |
776 | q_l[SIZE-1:0] <= ~d[SIZE-1:0]; | |
777 | end | |
778 | end | |
779 | ||
780 | `else | |
781 | ||
782 | reg [SIZE-1:0] l1; | |
783 | ||
784 | always @(l1clk or siclk or soclk or d or si) | |
785 | begin | |
786 | if (!l1clk && !siclk) l1[SIZE-1:0] <= ~d[SIZE-1:0]; // Load master with data | |
787 | else if ( l1clk && siclk) l1[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
788 | else if (!l1clk && siclk) l1[SIZE-1:0] <= {SIZE {1'bx}}; // Conflict between data and scan | |
789 | ||
790 | else if ( l1clk && !siclk && !soclk) q_l[SIZE-1:0] <= l1[SIZE-1:0]; // Load slave with master data | |
791 | if ( l1clk && siclk && !soclk) q_l[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
792 | end | |
793 | ||
794 | `endif // FAST_FLUSH | |
795 | ||
796 | `else | |
797 | wire [SIZE-1:0] si_unused; | |
798 | wire siclk_unused; | |
799 | wire soclk_unused; | |
800 | assign si_unused[SIZE-1:0] = si[SIZE-1:0]; | |
801 | assign siclk_unused = siclk; | |
802 | assign soclk_unused = soclk; | |
803 | ||
804 | ||
805 | `ifdef INITLATZERO | |
806 | initial q_l[SIZE-1:0] = {SIZE {1'b0}}; | |
807 | `endif | |
808 | ||
809 | always @(posedge l1clk) | |
810 | begin | |
811 | if (!siclk && !soclk) q_l[SIZE-1:0] <= ~d[SIZE-1:0]; | |
812 | else q_l[SIZE-1:0] <= {SIZE {1'bx}}; | |
813 | end | |
814 | `endif | |
815 | ||
816 | assign so[SIZE-1:0] = q_l[SIZE-1:0]; | |
817 | ||
818 | ||
819 | endmodule // msffiz_dp | |
820 | ||
821 | module bs_cell2 (q, so, d, l1clk, si, siclk, soclk, updateclk, mode, muxd, highZ_N); | |
822 | ||
823 | parameter SIZE=1; | |
824 | ||
825 | output [SIZE-1:0] q; | |
826 | output [SIZE-1:0] so; | |
827 | ||
828 | input [SIZE-1:0] d, muxd; | |
829 | input l1clk; | |
830 | input [SIZE-1:0] si; | |
831 | input siclk; | |
832 | input soclk; | |
833 | ||
834 | input updateclk, mode, highZ_N; | |
835 | ||
836 | reg [SIZE-1:0] q; | |
837 | reg [SIZE-1:0] so; | |
838 | ||
839 | wire l1clk, siclk, soclk, updateclk; | |
840 | ||
841 | ||
842 | reg [SIZE-1:0] l1, qm; | |
843 | ||
844 | always @(l1clk or siclk or soclk or d or si) begin | |
845 | if (!l1clk && !siclk) l1[SIZE-1:0] <= d[SIZE-1:0]; | |
846 | if ( l1clk && siclk) l1[SIZE-1:0] <= si[SIZE-1:0]; | |
847 | if (!l1clk && siclk) l1[SIZE-1:0] <= {SIZE {1'bx}}; | |
848 | if ( l1clk && !soclk) so[SIZE-1:0] <= l1[SIZE-1:0]; | |
849 | if ( l1clk && siclk && !soclk) so[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
850 | end | |
851 | ||
852 | `ifdef INITLATZERO | |
853 | initial qm[SIZE-1:0] = {SIZE {1'b0}}; | |
854 | `endif | |
855 | ||
856 | always @(updateclk or l1) begin | |
857 | if (updateclk) qm[SIZE-1:0] <=l1[SIZE-1:0]; | |
858 | end | |
859 | ||
860 | always@(mode or muxd or qm or highZ_N) begin | |
861 | if (mode==0) q[SIZE-1:0] = (qm[SIZE-1:0] && {SIZE {highZ_N}}); | |
862 | else q[SIZE-1:0] = muxd[SIZE-1:0]; | |
863 | end | |
864 | ||
865 | endmodule | |
866 | ||
867 | module scm_msff_lat ( latout, q, q_l, so, d, l1clk, si, siclk, soclk); | |
868 | ||
869 | parameter SIZE = 1; | |
870 | ||
871 | output [SIZE-1:0] latout; | |
872 | output [SIZE-1:0] so; | |
873 | output [SIZE-1:0] q; | |
874 | output [SIZE-1:0] q_l; | |
875 | input [SIZE-1:0] d; | |
876 | input l1clk; | |
877 | input [SIZE-1:0] si; | |
878 | input siclk; | |
879 | input soclk; | |
880 | ||
881 | ||
882 | wire [SIZE-1:0] so; | |
883 | reg [SIZE-1:0] m, s; | |
884 | ||
885 | `ifdef SCAN_MODE | |
886 | `ifdef FAST_FLUSH | |
887 | always @(l1clk or siclk or d ) begin // vcs optimized code | |
888 | ||
889 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
890 | else if ( l1clk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
891 | else if (l1clk && siclk) begin // flush reset | |
892 | m[SIZE-1:0] <= {SIZE {1'b0}}; | |
893 | s[SIZE-1:0] <= {SIZE {1'b0}}; | |
894 | end | |
895 | end | |
896 | // `ifdef FAST_FLUSH | |
897 | // always @(posedge l1clk or posedge siclk ) begin | |
898 | // if (siclk) begin | |
899 | // m[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
900 | // s[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
901 | // end else begin | |
902 | // m[SIZE-1:0] <= d[SIZE-1:0]; | |
903 | // s[SIZE-1:0] <= d[SIZE-1:0]; | |
904 | // end | |
905 | // end | |
906 | ||
907 | `else | |
908 | ||
909 | always @(l1clk or siclk or soclk or d or si) begin | |
910 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
911 | else if ( l1clk && siclk) m[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
912 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE {1'bx}}; // Conflict between data and scan | |
913 | ||
914 | if ( l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
915 | else if (l1clk && siclk && !soclk) s[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
916 | end | |
917 | ||
918 | `endif // FAST_FLUSH | |
919 | ||
920 | `else | |
921 | wire [SIZE-1:0] si_unused = si; | |
922 | `ifdef INITLATZERO | |
923 | initial m[SIZE-1:0] = {SIZE {1'b0}}; | |
924 | initial s[SIZE-1:0] = {SIZE {1'b0}}; | |
925 | `endif | |
926 | ||
927 | always @(l1clk or d or si or siclk) begin | |
928 | if(siclk==0 && l1clk==0) m[SIZE-1:0] = d[SIZE-1:0]; | |
929 | else if(siclk && !l1clk) m[SIZE-1:0] = {SIZE {1'bx}}; | |
930 | if(siclk && l1clk) m[SIZE-1:0] = si[SIZE-1:0]; | |
931 | if(l1clk && !soclk) s[SIZE-1:0] = m[SIZE-1:0]; | |
932 | end | |
933 | ||
934 | `endif | |
935 | ||
936 | assign latout[SIZE-1:0] = m[SIZE-1:0]; | |
937 | assign so[SIZE-1:0] = s[SIZE-1:0]; | |
938 | assign q[SIZE-1:0] = s[SIZE-1:0]; | |
939 | assign q_l[SIZE-1:0] = ~s[SIZE-1:0]; | |
940 | ||
941 | endmodule // scm_msff_lat | |
942 | ||
943 | module tisram_msff ( latout, latout_l, so, d, l1clk, si, siclk, soclk ); | |
944 | ||
945 | parameter SIZE = 1; | |
946 | ||
947 | output [SIZE-1:0] latout; | |
948 | output [SIZE-1:0] latout_l; | |
949 | output [SIZE-1:0] so; | |
950 | ||
951 | input [SIZE-1:0] d; | |
952 | input l1clk; | |
953 | input [SIZE-1:0] si; | |
954 | input siclk; | |
955 | input soclk; | |
956 | ||
957 | wire [SIZE-1:0] latout, latout_l, so; | |
958 | reg [SIZE-1:0] m, s; | |
959 | ||
960 | `ifdef SCAN_MODE | |
961 | ||
962 | always @(l1clk or siclk or soclk or d or si) begin | |
963 | ||
964 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
965 | else if ( l1clk && siclk) m[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
966 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE {1'bx}}; // Conflict between data and scan | |
967 | ||
968 | if ( l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
969 | else if (l1clk && siclk && !soclk) s[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
970 | end | |
971 | ||
972 | `else | |
973 | wire [SIZE-1:0] si_unused = si; | |
974 | wire soclk_unused = soclk; | |
975 | ||
976 | `ifdef INITLATZERO | |
977 | initial m[SIZE-1:0] = {SIZE {1'b0}}; | |
978 | initial s[SIZE-1:0] = {SIZE {1'b0}}; | |
979 | `endif | |
980 | ||
981 | always @(l1clk or d or si or siclk) begin | |
982 | if(siclk==0 && l1clk==0) m[SIZE-1:0] <= d[SIZE-1:0]; | |
983 | if(siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}}; | |
984 | else if(siclk && l1clk) m[SIZE-1:0] <= si[SIZE-1:0]; | |
985 | end | |
986 | `endif | |
987 | ||
988 | assign latout[SIZE-1:0] = m[SIZE-1:0]; | |
989 | assign latout_l[SIZE-1:0] = ~m[SIZE-1:0]; | |
990 | assign so[SIZE-1:0] = s[SIZE-1:0]; | |
991 | ||
992 | endmodule // | |
993 | ||
994 | module blat ( latout, so, d, l1clk, si, siclk, soclk ); | |
995 | ||
996 | parameter SIZE = 1; | |
997 | ||
998 | output [SIZE-1:0] latout; | |
999 | output [SIZE-1:0] so; | |
1000 | ||
1001 | input [SIZE-1:0] d; | |
1002 | input l1clk; | |
1003 | input [SIZE-1:0] si; | |
1004 | input siclk; | |
1005 | input soclk; | |
1006 | ||
1007 | wire [SIZE-1:0] latout, so; | |
1008 | reg [SIZE-1:0] m, s; | |
1009 | ||
1010 | `ifdef SCAN_MODE | |
1011 | `ifdef FAST_FLUSH | |
1012 | always @(posedge l1clk or posedge siclk ) begin | |
1013 | if (siclk) begin | |
1014 | m[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1015 | s[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1016 | end else begin | |
1017 | m[SIZE-1:0] <= d[SIZE-1:0]; | |
1018 | s[SIZE-1:0] <= d[SIZE-1:0]; | |
1019 | end | |
1020 | end | |
1021 | ||
1022 | `else | |
1023 | ||
1024 | always @(l1clk or siclk or soclk or d or si) begin | |
1025 | ||
1026 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
1027 | else if ( l1clk && siclk) m[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
1028 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE {1'bx}}; // Conflict between data and scan | |
1029 | ||
1030 | if ( l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
1031 | else if (l1clk && siclk && !soclk) s[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
1032 | end | |
1033 | ||
1034 | `endif // FAST_FLUSH | |
1035 | ||
1036 | `else | |
1037 | wire [SIZE-1:0] si_unused = si; | |
1038 | wire soclk_unused = soclk; | |
1039 | ||
1040 | `ifdef INITLATZERO | |
1041 | initial m[SIZE-1:0] = {SIZE {1'b0}}; | |
1042 | initial s[SIZE-1:0] = {SIZE {1'b0}}; | |
1043 | `endif | |
1044 | ||
1045 | always @(l1clk or d or si or siclk) begin | |
1046 | if(siclk==0 && l1clk==0) m[SIZE-1:0] <= d[SIZE-1:0]; | |
1047 | if(siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}}; | |
1048 | else if(siclk && l1clk) m[SIZE-1:0] <= si[SIZE-1:0]; | |
1049 | end | |
1050 | `endif | |
1051 | ||
1052 | assign latout[SIZE-1:0] = m[SIZE-1:0]; | |
1053 | assign so[SIZE-1:0] = s[SIZE-1:0]; | |
1054 | ||
1055 | endmodule // | |
1056 | ||
1057 | ||
1058 | module dlat ( latout, latout_l, so, d, l1clk, si, siclk, soclk ); | |
1059 | ||
1060 | parameter SIZE = 1; | |
1061 | ||
1062 | ||
1063 | output [SIZE-1:0] latout; | |
1064 | output [SIZE-1:0] latout_l; | |
1065 | output [SIZE-1:0] so; | |
1066 | ||
1067 | input [SIZE-1:0] d; | |
1068 | input l1clk; | |
1069 | input [SIZE-1:0] si; | |
1070 | input siclk; | |
1071 | input soclk; | |
1072 | ||
1073 | wire [SIZE-1:0] latout, latout_l, so; | |
1074 | reg [SIZE-1:0] m, s; | |
1075 | ||
1076 | `ifdef SCAN_MODE | |
1077 | `ifdef FAST_FLUSH | |
1078 | always @(posedge l1clk or posedge siclk ) begin | |
1079 | if (siclk) begin | |
1080 | m[SIZE-1:0] <= {SIZE{1'b1}}; //pseudo flush reset | |
1081 | s[SIZE-1:0] <= {SIZE{1'b1}}; //pseudo flush reset | |
1082 | end else begin | |
1083 | m[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1084 | s[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1085 | end | |
1086 | end | |
1087 | ||
1088 | `else | |
1089 | ||
1090 | always @(l1clk or siclk or soclk or d or si) begin | |
1091 | ||
1092 | if (!l1clk && !siclk) m[SIZE-1:0] <= ~d[SIZE-1:0]; // Load master with data | |
1093 | else if ( l1clk && siclk) m[SIZE-1:0] <= ~si[SIZE-1:0]; // Load master with scan or flush | |
1094 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE {1'bx}}; // Conflict between data and scan | |
1095 | ||
1096 | if ( l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
1097 | else if (l1clk && !soclk && siclk) s[SIZE-1:0] <= ~si[SIZE-1:0]; // Flush | |
1098 | end | |
1099 | ||
1100 | `endif // FAST_FLUSH | |
1101 | ||
1102 | assign so[SIZE-1:0] = ~s[SIZE-1:0]; | |
1103 | ||
1104 | `else | |
1105 | wire [SIZE-1:0] si_unused = si[SIZE-1:0]; | |
1106 | wire soclk_unused = soclk; | |
1107 | ||
1108 | `ifdef INITLATZERO | |
1109 | initial m[SIZE-1:0] = {SIZE{1'b1}}; | |
1110 | initial s[SIZE-1:0] = {SIZE{1'b1}}; | |
1111 | `endif | |
1112 | ||
1113 | always @(l1clk or d or si or siclk) begin | |
1114 | if (!l1clk && !siclk) m[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1115 | else if ( l1clk && siclk) m[SIZE-1:0] <= ~si[SIZE-1:0]; | |
1116 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE {1'bx}}; | |
1117 | end | |
1118 | ||
1119 | // Don't model slave...since is a don't care for normal sim | |
1120 | // below is a hack since we don't really care about s, so use m | |
1121 | assign so[SIZE-1:0] = ~m[SIZE-1:0]; | |
1122 | `endif | |
1123 | ||
1124 | assign latout[SIZE-1:0] = ~m[SIZE-1:0]; | |
1125 | assign latout_l[SIZE-1:0] = m[SIZE-1:0]; | |
1126 | ||
1127 | endmodule | |
1128 | ||
1129 | ||
1130 | ||
1131 | module dlata ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk ); | |
1132 | ||
1133 | parameter SIZE = 1; | |
1134 | ||
1135 | output [SIZE-1:0] latout; | |
1136 | output [SIZE-1:0] latout_l; | |
1137 | output [SIZE-1:0] so; | |
1138 | output [SIZE-1:0] q; | |
1139 | output [SIZE-1:0] q_l; | |
1140 | input [SIZE-1:0] d; | |
1141 | input l1clk; | |
1142 | input [SIZE-1:0] si; | |
1143 | input siclk; | |
1144 | input soclk; | |
1145 | ||
1146 | wire [SIZE-1:0] so, latout, latout_l; | |
1147 | reg [SIZE-1:0] m, s; | |
1148 | ||
1149 | `ifdef SCAN_MODE | |
1150 | `ifdef FAST_FLUSH | |
1151 | always @(posedge l1clk or posedge siclk ) begin | |
1152 | if (siclk) begin | |
1153 | m[SIZE-1:0] <= {SIZE{1'b1}}; //pseudo flush reset | |
1154 | s[SIZE-1:0] <= {SIZE{1'b1}}; //pseudo flush reset | |
1155 | end else begin | |
1156 | m[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1157 | s[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1158 | end | |
1159 | end | |
1160 | ||
1161 | `else | |
1162 | ||
1163 | always @(l1clk or siclk or soclk or d or si) begin | |
1164 | ||
1165 | if (!l1clk && !siclk) m[SIZE-1:0] <= ~d[SIZE-1:0]; // Load master with data | |
1166 | else if ( l1clk && siclk) m[SIZE-1:0] <= ~si[SIZE-1:0]; // Load master with scan or flush | |
1167 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE{1'bx}}; // Conflict between data and scan | |
1168 | ||
1169 | if (l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
1170 | else if (l1clk && !soclk && siclk) s[SIZE-1:0] <= ~si[SIZE-1:0]; // Flush | |
1171 | end | |
1172 | ||
1173 | `endif // FAST_FLUSH | |
1174 | ||
1175 | `else | |
1176 | // wire [SIZE-1:0] si_unused = si[SIZE-1:0]; | |
1177 | ||
1178 | `ifdef INITLATZERO | |
1179 | initial m[SIZE-1:0] = {SIZE{1'b1}}; | |
1180 | initial s[SIZE-1:0] = {SIZE{1'b1}}; | |
1181 | `endif | |
1182 | ||
1183 | always @(l1clk or d or si or siclk) begin | |
1184 | if (!siclk && !l1clk) m[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1185 | else if ( siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}}; | |
1186 | else if ( siclk && l1clk) m[SIZE-1:0] <= ~si[SIZE-1:0]; | |
1187 | if ( l1clk && !soclk) s[SIZE-1:0] <= m[SIZE-1:0]; | |
1188 | end | |
1189 | ||
1190 | // always @(l1clk or d or siclk or si) begin | |
1191 | // if (l1clk == 0) begin | |
1192 | // if (siclk == 0) begin | |
1193 | // m[SIZE-1:0] <= ~d[SIZE-1:0]; | |
1194 | // end | |
1195 | // else begin | |
1196 | // m[SIZE-1:0] <= {SIZE{1'bx}}; | |
1197 | // end | |
1198 | // end | |
1199 | // else begin // l1clk == 1 | |
1200 | // if (!soclk) s[SIZE-1:0] <= m[SIZE-1:0]; | |
1201 | // end | |
1202 | // end | |
1203 | ||
1204 | `endif | |
1205 | ||
1206 | assign latout[SIZE-1:0] = ~m[SIZE-1:0] & {SIZE {l1clk}}; | |
1207 | assign latout_l[SIZE-1:0] = m[SIZE-1:0] & {SIZE {l1clk}}; | |
1208 | assign so[SIZE-1:0] = ~s[SIZE-1:0]; | |
1209 | assign q[SIZE-1:0] = ~s[SIZE-1:0]; | |
1210 | assign q_l[SIZE-1:0] = s[SIZE-1:0]; | |
1211 | ||
1212 | ||
1213 | endmodule | |
1214 | ||
1215 | module new_dlata ( and_clk, mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk ); | |
1216 | ||
1217 | parameter SIZE = 1; | |
1218 | ||
1219 | output [SIZE-1:0] mq; | |
1220 | output [SIZE-1:0] mq_l; | |
1221 | output [SIZE-1:0] so; | |
1222 | output [SIZE-1:0] q; | |
1223 | output [SIZE-1:0] q_l; | |
1224 | input [SIZE-1:0] d; | |
1225 | input l1clk; | |
1226 | input and_clk; | |
1227 | input [SIZE-1:0] si; | |
1228 | input siclk; | |
1229 | input soclk; | |
1230 | ||
1231 | wire [SIZE-1:0] mq, mq_l, q, q_l, so; | |
1232 | reg [SIZE-1:0] m, s; | |
1233 | ||
1234 | `ifdef SCAN_MODE | |
1235 | `ifdef FAST_FLUSH | |
1236 | always @(l1clk or siclk or d ) begin // vcs optimized code | |
1237 | ||
1238 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
1239 | else if ( l1clk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
1240 | else if ( l1clk && siclk) begin // flush reset | |
1241 | m[SIZE-1:0] <= {SIZE{1'b0}}; | |
1242 | s[SIZE-1:0] <= {SIZE{1'b0}}; | |
1243 | end | |
1244 | end | |
1245 | // `ifdef FAST_FLUSH | |
1246 | // always @(posedge l1clk or posedge siclk ) begin | |
1247 | // if (siclk) begin | |
1248 | // m[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1249 | // s[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1250 | // end else begin | |
1251 | // m[SIZE-1:0] <= d[SIZE-1:0]; | |
1252 | // s[SIZE-1:0] <= d[SIZE-1:0]; | |
1253 | // end | |
1254 | // end | |
1255 | ||
1256 | `else | |
1257 | ||
1258 | always @(l1clk or siclk or soclk or d or si) begin | |
1259 | ||
1260 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
1261 | else if ( l1clk && siclk) m[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
1262 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE{1'bx}}; // Conflict between data and scan | |
1263 | ||
1264 | if (l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
1265 | else if (l1clk && !soclk && siclk) s[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
1266 | end | |
1267 | ||
1268 | `endif // FAST_FLUSH | |
1269 | ||
1270 | `else | |
1271 | // wire [SIZE-1:0] si_unused = si[SIZE-1:0]; | |
1272 | ||
1273 | `ifdef INITLATZERO | |
1274 | initial m[SIZE-1:0] = {SIZE{1'b0}}; | |
1275 | initial s[SIZE-1:0] = {SIZE{1'b0}}; | |
1276 | `endif | |
1277 | ||
1278 | always @(l1clk or d or si or siclk) begin | |
1279 | if (!siclk && !l1clk) m[SIZE-1:0] <= d[SIZE-1:0]; | |
1280 | else if ( siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}}; | |
1281 | else if ( siclk && l1clk) m[SIZE-1:0] <= si[SIZE-1:0]; | |
1282 | if ( l1clk && !soclk) s[SIZE-1:0] <= m[SIZE-1:0]; | |
1283 | end | |
1284 | ||
1285 | `endif | |
1286 | ||
1287 | `ifdef MODEL_AND | |
1288 | assign mq[SIZE-1:0] = m[SIZE-1:0] & {SIZE {(and_clk & l1clk)}}; | |
1289 | assign mq_l[SIZE-1:0] = ~m[SIZE-1:0] & {SIZE {(and_clk & l1clk)}}; | |
1290 | `else | |
1291 | wire and_clk_unused = and_clk; | |
1292 | assign mq[SIZE-1:0] = m[SIZE-1:0]; | |
1293 | assign mq_l[SIZE-1:0] = ~m[SIZE-1:0]; | |
1294 | `endif | |
1295 | ||
1296 | assign so[SIZE-1:0] = s[SIZE-1:0]; | |
1297 | assign q[SIZE-1:0] = s[SIZE-1:0]; | |
1298 | assign q_l[SIZE-1:0] = ~s[SIZE-1:0]; | |
1299 | ||
1300 | endmodule | |
1301 | ||
1302 | module new_dlat ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk ); | |
1303 | ||
1304 | parameter SIZE = 1; | |
1305 | ||
1306 | output [SIZE-1:0] latout; | |
1307 | output [SIZE-1:0] latout_l; | |
1308 | output [SIZE-1:0] so; | |
1309 | output [SIZE-1:0] q; | |
1310 | output [SIZE-1:0] q_l; | |
1311 | input [SIZE-1:0] d; | |
1312 | input l1clk; | |
1313 | input [SIZE-1:0] si; | |
1314 | input siclk; | |
1315 | input soclk; | |
1316 | ||
1317 | wire [SIZE-1:0] mq, mq_l, q, q_l, so; | |
1318 | reg [SIZE-1:0] m, s; | |
1319 | ||
1320 | `ifdef SCAN_MODE | |
1321 | `ifdef FAST_FLUSH | |
1322 | always @(posedge l1clk or posedge siclk ) begin | |
1323 | if (siclk) begin | |
1324 | m[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1325 | s[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1326 | end else begin | |
1327 | m[SIZE-1:0] <= d[SIZE-1:0]; | |
1328 | s[SIZE-1:0] <= d[SIZE-1:0]; | |
1329 | end | |
1330 | end | |
1331 | ||
1332 | `else | |
1333 | ||
1334 | always @(l1clk or siclk or soclk or d or si) begin | |
1335 | ||
1336 | if (!l1clk && !siclk) m[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
1337 | else if ( l1clk && siclk) m[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
1338 | else if (!l1clk && siclk) m[SIZE-1:0] <= {SIZE{1'bx}}; // Conflict between data and scan | |
1339 | ||
1340 | if (l1clk && !soclk && !siclk) s[SIZE-1:0] <= m[SIZE-1:0]; // Load slave with master data | |
1341 | else if (l1clk && !soclk && siclk) s[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
1342 | end | |
1343 | ||
1344 | `endif // FAST_FLUSH | |
1345 | ||
1346 | `else | |
1347 | // wire [SIZE-1:0] si_unused = si[SIZE-1:0]; | |
1348 | ||
1349 | `ifdef INITLATZERO | |
1350 | initial m[SIZE-1:0] = {SIZE{1'b0}}; | |
1351 | initial s[SIZE-1:0] = {SIZE{1'b0}}; | |
1352 | `endif | |
1353 | ||
1354 | always @(l1clk or d or si or siclk) begin | |
1355 | if (!siclk && !l1clk) m[SIZE-1:0] <= d[SIZE-1:0]; | |
1356 | else if ( siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}}; | |
1357 | else if ( siclk && l1clk) m[SIZE-1:0] <= si[SIZE-1:0]; | |
1358 | if ( l1clk && !soclk) s[SIZE-1:0] <= m[SIZE-1:0]; | |
1359 | end | |
1360 | ||
1361 | `endif | |
1362 | ||
1363 | `ifdef MODEL_AND | |
1364 | assign latout[SIZE-1:0] = m[SIZE-1:0] & {SIZE {l1clk}}; | |
1365 | assign latout_l[SIZE-1:0] = ~m[SIZE-1:0] & {SIZE {l1clk}}; | |
1366 | `else | |
1367 | assign latout[SIZE-1:0] = m[SIZE-1:0]; | |
1368 | assign latout_l[SIZE-1:0] = ~m[SIZE-1:0]; | |
1369 | `endif | |
1370 | ||
1371 | assign so[SIZE-1:0] = s[SIZE-1:0]; | |
1372 | assign q[SIZE-1:0] = s[SIZE-1:0]; | |
1373 | assign q_l[SIZE-1:0] = ~s[SIZE-1:0]; | |
1374 | ||
1375 | endmodule | |
1376 | ||
1377 | module ccx_mac_a (l1clk0,l1clk1,siclk,soclk,grant_x,data_a,data_x_l,qsel0_buf,shift_buf,si,so); | |
1378 | ||
1379 | parameter SIZE = 10; | |
1380 | ||
1381 | input l1clk0; | |
1382 | input l1clk1; | |
1383 | input siclk; | |
1384 | input soclk; | |
1385 | input grant_x; | |
1386 | input [SIZE-1:0] data_a; | |
1387 | ||
1388 | input qsel0_buf; | |
1389 | input shift_buf; | |
1390 | ||
1391 | output [SIZE-1:0] data_x_l; | |
1392 | ||
1393 | input si; | |
1394 | output so; | |
1395 | ||
1396 | wire [SIZE-1:0] msff1_so,msff1_si,msff0_so,msff0_si; | |
1397 | wire [SIZE-1:0] q1; | |
1398 | wire [SIZE-1:0] q0; | |
1399 | wire [SIZE-1:0] q0_in; | |
1400 | ||
1401 | ||
1402 | dff #(SIZE) msff1 | |
1403 | ( | |
1404 | .l1clk(l1clk1), | |
1405 | .siclk(siclk), | |
1406 | .soclk(soclk), | |
1407 | .d(data_a[SIZE-1:0]), | |
1408 | .si(msff1_si[SIZE-1:0]), | |
1409 | .so(msff1_so[SIZE-1:0]), | |
1410 | .q(q1[SIZE-1:0]) | |
1411 | ); | |
1412 | ||
1413 | assign q0_in[SIZE-1:0] = ({SIZE{qsel0_buf}} & data_a[SIZE-1:0]) | | |
1414 | ({SIZE{shift_buf}} & q1[SIZE-1:0]); | |
1415 | ||
1416 | ||
1417 | dff #(SIZE) msff0 | |
1418 | ( | |
1419 | .l1clk(l1clk0), | |
1420 | .siclk(siclk), | |
1421 | .soclk(soclk), | |
1422 | .d(q0_in[SIZE-1:0]), | |
1423 | .si(msff0_si[SIZE-1:0]), | |
1424 | .so(msff0_so[SIZE-1:0]), | |
1425 | .q(q0[SIZE-1:0]) | |
1426 | ); | |
1427 | ||
1428 | assign data_x_l[SIZE-1:0] = ~(q0[SIZE-1:0] & {SIZE{grant_x}}); | |
1429 | ||
1430 | //assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si}; | |
1431 | //assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]}; | |
1432 | //assign so = msff0_so[SIZE-1]; | |
1433 | ||
1434 | //assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si}; | |
1435 | //assign msff1_si[9:5] = {msff0_so[SIZE-2:5],si}; | |
1436 | //assign msff1_si[0] = msff0_so[SIZE-1]; | |
1437 | //assign msff1_si[4:1] = msff0_so[3:0]; | |
1438 | //assign so = msff0_so[4]; | |
1439 | ||
1440 | assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:5],si,msff0_so[3:0],msff0_so[SIZE-1]}; | |
1441 | assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]}; | |
1442 | assign so = msff0_so[4]; | |
1443 | ||
1444 | endmodule | |
1445 | ||
1446 | module ccx_mac_b (l1clk0,l1clk1,siclk,soclk,grant_x,data_a,data_prev_x_l,data_x_l,qsel0_buf,shift_buf,si,so); | |
1447 | ||
1448 | parameter SIZE = 10; | |
1449 | ||
1450 | input l1clk0; | |
1451 | input l1clk1; | |
1452 | input siclk; | |
1453 | input soclk; | |
1454 | input grant_x; | |
1455 | input [SIZE-1:0] data_a; | |
1456 | input [SIZE-1:0] data_prev_x_l; | |
1457 | ||
1458 | input qsel0_buf; | |
1459 | input shift_buf; | |
1460 | ||
1461 | output [SIZE-1:0] data_x_l; | |
1462 | ||
1463 | input si; | |
1464 | output so; | |
1465 | ||
1466 | wire [SIZE-1:0] msff1_so,msff1_si,msff0_so,msff0_si; | |
1467 | wire [SIZE-1:0] q1; | |
1468 | wire [SIZE-1:0] q0; | |
1469 | wire [SIZE-1:0] q0_in,x4,x5; | |
1470 | ||
1471 | ||
1472 | dff #(SIZE) msff1 | |
1473 | ( | |
1474 | .l1clk(l1clk1), | |
1475 | .siclk(siclk), | |
1476 | .soclk(soclk), | |
1477 | .d(data_a[SIZE-1:0]), | |
1478 | .si(msff1_si[SIZE-1:0]), | |
1479 | .so(msff1_so[SIZE-1:0]), | |
1480 | .q(q1[SIZE-1:0]) | |
1481 | ); | |
1482 | ||
1483 | assign q0_in[SIZE-1:0] = ({SIZE{qsel0_buf}} & data_a[SIZE-1:0]) | | |
1484 | ({SIZE{shift_buf}} & q1[SIZE-1:0]); | |
1485 | ||
1486 | ||
1487 | dff #(SIZE) msff0 | |
1488 | ( | |
1489 | .l1clk(l1clk0), | |
1490 | .siclk(siclk), | |
1491 | .soclk(soclk), | |
1492 | .d(q0_in[SIZE-1:0]), | |
1493 | .si(msff0_si[SIZE-1:0]), | |
1494 | .so(msff0_so[SIZE-1:0]), | |
1495 | .q(q0[SIZE-1:0]) | |
1496 | ); | |
1497 | ||
1498 | assign x4[SIZE-1:0] = ~(q0[SIZE-1:0] & {SIZE{grant_x}}); | |
1499 | assign x5[SIZE-1:0] = ~(x4[SIZE-1:0] & data_prev_x_l[SIZE-1:0]); | |
1500 | assign data_x_l[SIZE-1:0] = ~x5[SIZE-1:0]; | |
1501 | ||
1502 | //assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si}; | |
1503 | //assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]}; | |
1504 | //assign so = msff0_so[SIZE-1]; | |
1505 | ||
1506 | assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:5],si,msff0_so[3:0],msff0_so[SIZE-1]}; | |
1507 | assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]}; | |
1508 | assign so = msff0_so[4]; | |
1509 | ||
1510 | endmodule | |
1511 | ||
1512 | module ccx_mac_c (l1clk0,l1clk1,siclk,soclk,grant_x,data_a,data_crit_x_l,data_ncrit_x_l,data_x_l,qsel0_buf,shift_buf,si,so); | |
1513 | ||
1514 | parameter SIZE = 10; | |
1515 | ||
1516 | input l1clk0; | |
1517 | input l1clk1; | |
1518 | input siclk; | |
1519 | input soclk; | |
1520 | input grant_x; | |
1521 | input [SIZE-1:0] data_a; | |
1522 | input [SIZE-1:0] data_crit_x_l; | |
1523 | input [SIZE-1:0] data_ncrit_x_l; | |
1524 | ||
1525 | input qsel0_buf; | |
1526 | input shift_buf; | |
1527 | ||
1528 | output [SIZE-1:0] data_x_l; | |
1529 | ||
1530 | input si; | |
1531 | output so; | |
1532 | ||
1533 | wire [SIZE-1:0] msff1_so,msff1_si,msff0_so,msff0_si; | |
1534 | wire [SIZE-1:0] q1; | |
1535 | wire [SIZE-1:0] q0; | |
1536 | wire [SIZE-1:0] q0_in,x4,x5; | |
1537 | ||
1538 | ||
1539 | dff #(SIZE) msff1 | |
1540 | ( | |
1541 | .l1clk(l1clk1), | |
1542 | .siclk(siclk), | |
1543 | .soclk(soclk), | |
1544 | .d(data_a[SIZE-1:0]), | |
1545 | .si(msff1_si[SIZE-1:0]), | |
1546 | .so(msff1_so[SIZE-1:0]), | |
1547 | .q(q1[SIZE-1:0]) | |
1548 | ); | |
1549 | ||
1550 | assign q0_in[SIZE-1:0] = ({SIZE{qsel0_buf}} & data_a[SIZE-1:0]) | | |
1551 | ({SIZE{shift_buf}} & q1[SIZE-1:0]); | |
1552 | ||
1553 | ||
1554 | dff #(SIZE) msff0 | |
1555 | ( | |
1556 | .l1clk(l1clk0), | |
1557 | .siclk(siclk), | |
1558 | .soclk(soclk), | |
1559 | .d(q0_in[SIZE-1:0]), | |
1560 | .si(msff0_si[SIZE-1:0]), | |
1561 | .so(msff0_so[SIZE-1:0]), | |
1562 | .q(q0[SIZE-1:0]) | |
1563 | ); | |
1564 | ||
1565 | assign x4[SIZE-1:0] = ~(q0[SIZE-1:0] & {SIZE{grant_x}}); | |
1566 | assign x5[SIZE-1:0] = ~(x4[SIZE-1:0] & data_crit_x_l[SIZE-1:0] & data_ncrit_x_l[SIZE-1:0]); | |
1567 | assign data_x_l[SIZE-1:0] = ~x5[SIZE-1:0]; | |
1568 | ||
1569 | //assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si}; | |
1570 | //assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]}; | |
1571 | //assign so = msff0_so[SIZE-1]; | |
1572 | ||
1573 | assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:5],si,msff0_so[3:0],msff0_so[SIZE-1]}; | |
1574 | assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]}; | |
1575 | assign so = msff0_so[4]; | |
1576 | ||
1577 | endmodule | |
1578 | ||
1579 | // new FAST_FLUSH | |
1580 | // new dff from RM with init to zero in scan section | |
1581 | ||
1582 | `ifdef FPGA | |
1583 | `else | |
1584 | module dff ( q, so, d, l1clk, si, siclk, soclk ); | |
1585 | // RFM 05-14-2004 | |
1586 | // Level sensitive in SCAN_MODE | |
1587 | // Edge triggered when not in SCAN_MODE | |
1588 | // 4-25-2005 added initlatzero to scan_mode | |
1589 | ||
1590 | ||
1591 | parameter SIZE = 1; | |
1592 | ||
1593 | output [SIZE-1:0] q; | |
1594 | output [SIZE-1:0] so; | |
1595 | ||
1596 | input [SIZE-1:0] d; | |
1597 | input l1clk; | |
1598 | input [SIZE-1:0] si; | |
1599 | input siclk; | |
1600 | input soclk; | |
1601 | ||
1602 | reg [SIZE-1:0] q; | |
1603 | wire [SIZE-1:0] so; | |
1604 | wire l1clk, siclk, soclk; | |
1605 | ||
1606 | `ifdef SCAN_MODE | |
1607 | ||
1608 | reg [SIZE-1:0] l1; | |
1609 | ||
1610 | `ifdef INITLATZERO | |
1611 | initial l1[SIZE-1:0] = {SIZE{1'b0}}; | |
1612 | initial q[SIZE-1:0] = {SIZE{1'b0}}; | |
1613 | `endif | |
1614 | ||
1615 | `ifdef FAST_FLUSH | |
1616 | always @(posedge l1clk or posedge siclk ) begin | |
1617 | if (siclk) begin | |
1618 | q[SIZE-1:0] <= {SIZE{1'b0}}; //pseudo flush reset | |
1619 | end else begin | |
1620 | q[SIZE-1:0] <= d[SIZE-1:0]; | |
1621 | end | |
1622 | end | |
1623 | `else | |
1624 | always @(l1clk or siclk or soclk or d or si) | |
1625 | begin | |
1626 | if (!l1clk && !siclk) l1[SIZE-1:0] <= d[SIZE-1:0]; // Load master with data | |
1627 | else if ( l1clk && siclk) l1[SIZE-1:0] <= si[SIZE-1:0]; // Load master with scan or flush | |
1628 | else if (!l1clk && siclk) l1[SIZE-1:0] <= {SIZE{1'bx}}; // Conflict between data and scan | |
1629 | ||
1630 | else if ( l1clk && !siclk && !soclk) q[SIZE-1:0] <= l1[SIZE-1:0]; // Load slave with master data | |
1631 | if ( l1clk && siclk && !soclk) q[SIZE-1:0] <= si[SIZE-1:0]; // Flush | |
1632 | end | |
1633 | `endif | |
1634 | ||
1635 | `else | |
1636 | wire [SIZE-1:0] si_unused; | |
1637 | wire siclk_unused; | |
1638 | wire soclk_unused; | |
1639 | assign si_unused[SIZE-1:0] = si[SIZE-1:0]; | |
1640 | assign siclk_unused = siclk; | |
1641 | assign soclk_unused = soclk; | |
1642 | ||
1643 | ||
1644 | `ifdef INITLATZERO | |
1645 | initial q[SIZE-1:0] = {SIZE{1'b0}}; | |
1646 | `endif | |
1647 | ||
1648 | always @(posedge l1clk) | |
1649 | begin | |
1650 | if (!siclk && !soclk) q[SIZE-1:0] <= d[SIZE-1:0]; | |
1651 | else q[SIZE-1:0] <= {SIZE{1'bx}}; | |
1652 | end | |
1653 | `endif | |
1654 | ||
1655 | assign so[SIZE-1:0] = q[SIZE-1:0]; | |
1656 | ||
1657 | endmodule // dff | |
1658 | `endif // `ifdef FPGA | |
1659 | ||
1660 | ||
1661 | ||
1662 | module dff_jtag ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk ); | |
1663 | ||
1664 | // modified 2/15/05 gfg as per Shawn | |
1665 | ||
1666 | parameter SIZE = 1; | |
1667 | ||
1668 | output [SIZE-1:0] q; | |
1669 | output [SIZE-1:0] so; | |
1670 | ||
1671 | input [SIZE-1:0] d; | |
1672 | input l1clk; | |
1673 | input [SIZE-1:0] si; | |
1674 | input siclk; | |
1675 | input soclk; | |
1676 | input reset; | |
1677 | input updateclk; | |
1678 | ||
1679 | reg [SIZE-1:0] q; | |
1680 | reg [SIZE-1:0] so; | |
1681 | reg [SIZE-1:0] l1; | |
1682 | wire l1clk, siclk, soclk, updateclk; | |
1683 | ||
1684 | always @(l1clk or siclk or soclk or d or si or reset) | |
1685 | begin | |
1686 | if (!l1clk && !siclk) l1[SIZE-1:0] <= d[SIZE-1:0]; | |
1687 | else if ( l1clk && siclk) l1[SIZE-1:0] <= si[SIZE-1:0]; | |
1688 | else if (!l1clk && siclk) l1[SIZE-1:0] <= {SIZE{1'bx}}; | |
1689 | if ( reset ) so[SIZE-1:0] <= {SIZE{1'b0}}; | |
1690 | if ( l1clk && !siclk && !soclk && !reset) so[SIZE-1:0] <= l1[SIZE-1:0]; | |
1691 | if ( l1clk && siclk && !soclk && !reset) so[SIZE-1:0] <= si[SIZE-1:0]; | |
1692 | end | |
1693 | ||
1694 | `ifdef INITLATZERO | |
1695 | initial q[SIZE-1:0] = {SIZE{1'b0}}; | |
1696 | `endif | |
1697 | ||
1698 | always@(updateclk or reset or l1) | |
1699 | begin | |
1700 | if(reset) q[SIZE-1:0] <= {SIZE{1'b0}}; | |
1701 | else if(updateclk) q[SIZE-1:0] <= l1[SIZE-1:0]; | |
1702 | end | |
1703 | ||
1704 | endmodule // dff_jtag | |
1705 | ||
1706 | ||
1707 | // parameterized sim sections for the common sunv macros besides muxes and flops | |
1708 | ||
1709 | module and2 (out, in0, in1); | |
1710 | parameter SIZE=1; | |
1711 | ||
1712 | ||
1713 | output [SIZE-1:0] out; | |
1714 | input [SIZE-1:0] in0; | |
1715 | input [SIZE-1:0] in1; | |
1716 | ||
1717 | ||
1718 | assign out[SIZE-1:0] = in0[SIZE-1:0] & in1[SIZE-1:0]; | |
1719 | ||
1720 | endmodule | |
1721 | ||
1722 | `ifdef FPGA | |
1723 | `else | |
1724 | module and3 (out, in0, in1, in2); | |
1725 | parameter SIZE=1; | |
1726 | ||
1727 | ||
1728 | output [SIZE-1:0] out; | |
1729 | input [SIZE-1:0] in0; | |
1730 | input [SIZE-1:0] in1; | |
1731 | input [SIZE-1:0] in2; | |
1732 | ||
1733 | ||
1734 | assign out[SIZE-1:0] = in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0]; | |
1735 | ||
1736 | endmodule | |
1737 | ||
1738 | module and4 (out, in0, in1, in2, in3); | |
1739 | parameter SIZE=1; | |
1740 | ||
1741 | ||
1742 | output [SIZE-1:0] out; | |
1743 | input [SIZE-1:0] in0; | |
1744 | input [SIZE-1:0] in1; | |
1745 | input [SIZE-1:0] in2; | |
1746 | input [SIZE-1:0] in3; | |
1747 | ||
1748 | ||
1749 | assign out[SIZE-1:0] = in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0]; | |
1750 | ||
1751 | endmodule | |
1752 | ||
1753 | module nand2 (out, in0, in1); | |
1754 | parameter SIZE=1; | |
1755 | ||
1756 | ||
1757 | output [SIZE-1:0] out; | |
1758 | input [SIZE-1:0] in0; | |
1759 | input [SIZE-1:0] in1; | |
1760 | ||
1761 | ||
1762 | assign out[SIZE-1:0] = ~(in0[SIZE-1:0] & in1[SIZE-1:0]); | |
1763 | ||
1764 | endmodule | |
1765 | ||
1766 | module nand3 (out, in0, in1, in2); | |
1767 | parameter SIZE=1; | |
1768 | ||
1769 | ||
1770 | output [SIZE-1:0] out; | |
1771 | input [SIZE-1:0] in0; | |
1772 | input [SIZE-1:0] in1; | |
1773 | input [SIZE-1:0] in2; | |
1774 | ||
1775 | ||
1776 | assign out[SIZE-1:0] = ~(in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0]); | |
1777 | ||
1778 | endmodule | |
1779 | ||
1780 | `endif // `ifdef FPGA | |
1781 | ||
1782 | module nand4 (out, in0, in1, in2, in3); | |
1783 | parameter SIZE=1; | |
1784 | ||
1785 | ||
1786 | output [SIZE-1:0] out; | |
1787 | input [SIZE-1:0] in0; | |
1788 | input [SIZE-1:0] in1; | |
1789 | input [SIZE-1:0] in2; | |
1790 | input [SIZE-1:0] in3; | |
1791 | ||
1792 | ||
1793 | assign out[SIZE-1:0] = ~(in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0]); | |
1794 | ||
1795 | endmodule | |
1796 | ||
1797 | module or2 (out, in0, in1); | |
1798 | parameter SIZE=1; | |
1799 | ||
1800 | ||
1801 | output [SIZE-1:0] out; | |
1802 | input [SIZE-1:0] in0; | |
1803 | input [SIZE-1:0] in1; | |
1804 | ||
1805 | ||
1806 | assign out[SIZE-1:0] = in0[SIZE-1:0] | in1[SIZE-1:0]; | |
1807 | ||
1808 | endmodule | |
1809 | ||
1810 | module or3 (out, in0, in1, in2); | |
1811 | parameter SIZE=1; | |
1812 | ||
1813 | ||
1814 | output [SIZE-1:0] out; | |
1815 | input [SIZE-1:0] in0; | |
1816 | input [SIZE-1:0] in1; | |
1817 | input [SIZE-1:0] in2; | |
1818 | ||
1819 | ||
1820 | assign out[SIZE-1:0] = in0[SIZE-1:0] | in1[SIZE-1:0] | in2[SIZE-1:0]; | |
1821 | ||
1822 | endmodule | |
1823 | ||
1824 | `ifdef FPGA | |
1825 | `else | |
1826 | module nor2 (out, in0, in1); | |
1827 | parameter SIZE=1; | |
1828 | ||
1829 | ||
1830 | output [SIZE-1:0] out; | |
1831 | input [SIZE-1:0] in0; | |
1832 | input [SIZE-1:0] in1; | |
1833 | ||
1834 | ||
1835 | assign out[SIZE-1:0] = ~(in0[SIZE-1:0] | in1[SIZE-1:0]); | |
1836 | ||
1837 | endmodule | |
1838 | ||
1839 | module nor3 (out, in0, in1, in2); | |
1840 | parameter SIZE=1; | |
1841 | ||
1842 | ||
1843 | output [SIZE-1:0] out; | |
1844 | input [SIZE-1:0] in0; | |
1845 | input [SIZE-1:0] in1; | |
1846 | input [SIZE-1:0] in2; | |
1847 | ||
1848 | ||
1849 | assign out[SIZE-1:0] = ~(in0[SIZE-1:0] | in1[SIZE-1:0] | in2[SIZE-1:0]); | |
1850 | ||
1851 | endmodule | |
1852 | ||
1853 | `endif // `ifdef FPGA | |
1854 | ||
1855 | module xor2 ( out, in0, in1 ); | |
1856 | ||
1857 | parameter SIZE = 1; | |
1858 | ||
1859 | input [SIZE-1:0] in0, in1; | |
1860 | output [SIZE-1:0] out; | |
1861 | ||
1862 | assign out = in0 ^ in1 ; | |
1863 | ||
1864 | endmodule // xor2 | |
1865 | ||
1866 | ||
1867 | module xor3 (out, in0, in1, in2); | |
1868 | parameter SIZE=1; | |
1869 | ||
1870 | ||
1871 | output [SIZE-1:0] out; | |
1872 | input [SIZE-1:0] in0; | |
1873 | input [SIZE-1:0] in1; | |
1874 | input [SIZE-1:0] in2; | |
1875 | ||
1876 | ||
1877 | assign out[SIZE-1:0] = in0[SIZE-1:0] ^ in1[SIZE-1:0] ^ in2[SIZE-1:0]; | |
1878 | ||
1879 | endmodule | |
1880 | ||
1881 | module xnor2 ( out, in0, in1 ); | |
1882 | ||
1883 | parameter SIZE = 1; | |
1884 | ||
1885 | input [SIZE-1:0] in0, in1; | |
1886 | output [SIZE-1:0] out; | |
1887 | ||
1888 | assign out = ~(in0 ^ in1) ; | |
1889 | ||
1890 | endmodule // xnor2 | |
1891 | ||
1892 | module xnor3 (out, in0, in1, in2); | |
1893 | parameter SIZE=1; | |
1894 | ||
1895 | ||
1896 | output [SIZE-1:0] out; | |
1897 | input [SIZE-1:0] in0; | |
1898 | input [SIZE-1:0] in1; | |
1899 | input [SIZE-1:0] in2; | |
1900 | ||
1901 | ||
1902 | assign out[SIZE-1:0] = ~(in0[SIZE-1:0] ^ in1[SIZE-1:0] ^ in2[SIZE-1:0]); | |
1903 | ||
1904 | endmodule | |
1905 | ||
1906 | `ifdef FPGA | |
1907 | `else | |
1908 | ||
1909 | module buff (out, in); | |
1910 | parameter SIZE=1; | |
1911 | ||
1912 | ||
1913 | output [SIZE-1:0] out; | |
1914 | input [SIZE-1:0] in; | |
1915 | ||
1916 | assign out[SIZE-1:0] = in[SIZE-1:0]; | |
1917 | ||
1918 | ||
1919 | endmodule | |
1920 | ||
1921 | module inv (out, in); | |
1922 | parameter SIZE=1; | |
1923 | ||
1924 | ||
1925 | output [SIZE-1:0] out; | |
1926 | input [SIZE-1:0] in; | |
1927 | ||
1928 | assign out[SIZE-1:0] = ~in[SIZE-1:0]; | |
1929 | endmodule | |
1930 | ||
1931 | `endif // `ifdef FPGA | |
1932 | ||
1933 | ||
1934 | ||
1935 | ||
1936 | module cla(out, cout, in0, in1, cin); | |
1937 | parameter SIZE=1; | |
1938 | ||
1939 | output [SIZE-1:0] out; | |
1940 | output cout; | |
1941 | input [SIZE-1:0] in0; | |
1942 | input [SIZE-1:0] in1; | |
1943 | input cin; | |
1944 | ||
1945 | ||
1946 | assign {cout,out[SIZE-1:0]} = ({1'b0,in0[SIZE-1:0]} + {1'b0,in1[SIZE-1:0]} + {{SIZE{1'b0}},cin}); | |
1947 | ||
1948 | endmodule | |
1949 | ||
1950 | module incr(out, cout, in, cin); | |
1951 | parameter SIZE=1; | |
1952 | ||
1953 | output [SIZE-1:0] out; | |
1954 | output cout; | |
1955 | input [SIZE-1:0] in; | |
1956 | input cin; | |
1957 | ||
1958 | assign {cout,out[SIZE-1:0]} = ({1'b0,in[SIZE-1:0]} + {{SIZE{1'b0}},cin}); | |
1959 | ||
1960 | endmodule | |
1961 | ||
1962 | module cmp(out, in0, in1); | |
1963 | parameter SIZE=1; | |
1964 | ||
1965 | output out; | |
1966 | input [SIZE-1:0] in0; | |
1967 | input [SIZE-1:0] in1; | |
1968 | ||
1969 | assign out = (in0[SIZE-1:0] == in1[SIZE-1:0]); | |
1970 | ||
1971 | endmodule | |
1972 | ||
1973 | module zero(out, in); | |
1974 | parameter SIZE=1; | |
1975 | ||
1976 | output out; | |
1977 | input [SIZE-1:0] in; | |
1978 | ||
1979 | assign out = (in[SIZE-1:0] == {SIZE{1'b0}}); | |
1980 | ||
1981 | endmodule | |
1982 | ||
1983 | ||
1984 | module prty(out, in); | |
1985 | parameter SIZE=1; | |
1986 | ||
1987 | output out; | |
1988 | input [SIZE-1:0] in; | |
1989 | ||
1990 | assign out = ^in[SIZE-1:0]; | |
1991 | ||
1992 | endmodule | |
1993 | ||
1994 | ||
1995 | module csa32(sum, carry, in0, in1, in2); | |
1996 | parameter SIZE=1; | |
1997 | ||
1998 | input [SIZE-1:0] in0; | |
1999 | input [SIZE-1:0] in1; | |
2000 | input [SIZE-1:0] in2; | |
2001 | output [SIZE-1:0] carry; | |
2002 | output [SIZE-1:0] sum; | |
2003 | ||
2004 | assign carry[SIZE-1:0] = ((in0[SIZE-1:0] & in1[SIZE-1:0] ) | | |
2005 | (in0[SIZE-1:0] & in2[SIZE-1:0] ) | | |
2006 | (in1[SIZE-1:0] & in2[SIZE-1:0])); | |
2007 | ||
2008 | assign sum[SIZE-1:0] = (in0[SIZE-1:0] ^ in1[SIZE-1:0] ^ in2[SIZE-1:0]); | |
2009 | ||
2010 | ||
2011 | endmodule | |
2012 | ||
2013 | ||
2014 | module csa42(sum, carry, cout, cin, in0, in1, in2, in3); | |
2015 | parameter SIZE=1; | |
2016 | ||
2017 | input [SIZE-1:0] in0; | |
2018 | input [SIZE-1:0] in1; | |
2019 | input [SIZE-1:0] in2; | |
2020 | input [SIZE-1:0] in3; | |
2021 | input cin; | |
2022 | output cout; | |
2023 | output [SIZE-1:0] carry; | |
2024 | output [SIZE-1:0] sum; | |
2025 | ||
2026 | ||
2027 | wire [SIZE-1:0] i0_xor_i1 = (in0[SIZE-1:0] ^ in1[SIZE-1:0]); | |
2028 | ||
2029 | wire [SIZE-1:0] co = ((in0[SIZE-1:0] & in1[SIZE-1:0]) | | |
2030 | (in0[SIZE-1:0] & in2[SIZE-1:0]) | | |
2031 | (in1[SIZE-1:0] & in2[SIZE-1:0])); | |
2032 | ||
2033 | assign cout = co[SIZE-1]; | |
2034 | ||
2035 | wire [SIZE:0] cint = { co[SIZE-1:0], cin }; | |
2036 | ||
2037 | wire cint_unused; | |
2038 | ||
2039 | assign cint_unused = cint[SIZE]; | |
2040 | ||
2041 | ||
2042 | assign carry[SIZE-1:0] = ((~i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2043 | (~i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & ~in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2044 | (~i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0] ) | | |
2045 | ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & ~in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2046 | ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & in3[SIZE-1:0] ) | | |
2047 | ( i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0] & cint[SIZE-1:0])); | |
2048 | ||
2049 | ||
2050 | assign sum[SIZE-1:0] = ((~i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & ~in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2051 | (~i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & in3[SIZE-1:0] & ~cint[SIZE-1:0]) | | |
2052 | (~i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & ~in3[SIZE-1:0] & ~cint[SIZE-1:0]) | | |
2053 | (~i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2054 | ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & ~in3[SIZE-1:0] & ~cint[SIZE-1:0]) | | |
2055 | ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2056 | ( i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & ~in3[SIZE-1:0] & cint[SIZE-1:0]) | | |
2057 | ( i0_xor_i1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0] & ~cint[SIZE-1:0])); | |
2058 | ||
2059 | endmodule // csa42 | |
2060 | ||
2061 | module andmux8(out, in7,in6,in5,in4,in3,in2,in1,in0, | |
2062 | en7,en6,en5,en4,en3,en2,en1,en0, | |
2063 | sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0); | |
2064 | ||
2065 | parameter SIZE=1; | |
2066 | ||
2067 | output [SIZE-1:0] out; | |
2068 | input [SIZE-1:0] in7; | |
2069 | input [SIZE-1:0] in6; | |
2070 | input [SIZE-1:0] in5; | |
2071 | input [SIZE-1:0] in4; | |
2072 | input [SIZE-1:0] in3; | |
2073 | input [SIZE-1:0] in2; | |
2074 | input [SIZE-1:0] in1; | |
2075 | input [SIZE-1:0] in0; | |
2076 | input [SIZE-1:0] en7; | |
2077 | input [SIZE-1:0] en6; | |
2078 | input [SIZE-1:0] en5; | |
2079 | input [SIZE-1:0] en4; | |
2080 | input [SIZE-1:0] en3; | |
2081 | input [SIZE-1:0] en2; | |
2082 | input [SIZE-1:0] en1; | |
2083 | input [SIZE-1:0] en0; | |
2084 | input sel7; | |
2085 | input sel6; | |
2086 | input sel5; | |
2087 | input sel4; | |
2088 | input sel3; | |
2089 | input sel2; | |
2090 | input sel1; | |
2091 | input sel0; | |
2092 | ||
2093 | assign out = ({SIZE{sel0}} & in0 & en0) | | |
2094 | ({SIZE{sel1}} & in1 & en1) | | |
2095 | ({SIZE{sel2}} & in2 & en2) | | |
2096 | ({SIZE{sel3}} & in3 & en3) | | |
2097 | ({SIZE{sel4}} & in4 & en4) | | |
2098 | ({SIZE{sel5}} & in5 & en5) | | |
2099 | ({SIZE{sel6}} & in6 & en6) | | |
2100 | ({SIZE{sel7}} & in7 & en7); | |
2101 | ||
2102 | endmodule | |
2103 |