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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_u1gb.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_u1gb_aoi12_12x ( | |
36 | out, | |
37 | in10, | |
38 | in00, | |
39 | in01 ); | |
40 | ||
41 | output out; | |
42 | input in10; | |
43 | input in00; | |
44 | input in01; | |
45 | ||
46 | `ifdef LIB | |
47 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
48 | `endif | |
49 | ||
50 | endmodule | |
51 | // -------------------------------------------------- | |
52 | // File: cl_u1gb_aoi12_16x.behV | |
53 | // Auto generated verilog module by HnBCellAuto | |
54 | // | |
55 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
56 | // By: balmiki | |
57 | // -------------------------------------------------- | |
58 | // | |
59 | module cl_u1gb_aoi12_16x ( | |
60 | out, | |
61 | in10, | |
62 | in00, | |
63 | in01 ); | |
64 | ||
65 | output out; | |
66 | input in10; | |
67 | input in00; | |
68 | input in01; | |
69 | ||
70 | `ifdef LIB | |
71 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
72 | `endif | |
73 | ||
74 | endmodule | |
75 | // -------------------------------------------------- | |
76 | // File: cl_u1gb_aoi12_1x.behV | |
77 | // Auto generated verilog module by HnBCellAuto | |
78 | // | |
79 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST | |
80 | // By: balmiki | |
81 | // -------------------------------------------------- | |
82 | // | |
83 | module cl_u1gb_aoi12_1x ( | |
84 | out, | |
85 | in10, | |
86 | in00, | |
87 | in01 ); | |
88 | ||
89 | output out; | |
90 | input in10; | |
91 | input in00; | |
92 | input in01; | |
93 | ||
94 | `ifdef LIB | |
95 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
96 | `endif | |
97 | ||
98 | endmodule | |
99 | // -------------------------------------------------- | |
100 | // File: cl_u1gb_aoi12_2x.behV | |
101 | // Auto generated verilog module by HnBCellAuto | |
102 | // | |
103 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
104 | // By: balmiki | |
105 | // -------------------------------------------------- | |
106 | // | |
107 | module cl_u1gb_aoi12_2x ( | |
108 | out, | |
109 | in10, | |
110 | in00, | |
111 | in01 ); | |
112 | ||
113 | output out; | |
114 | input in10; | |
115 | input in00; | |
116 | input in01; | |
117 | ||
118 | `ifdef LIB | |
119 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
120 | `endif | |
121 | ||
122 | endmodule | |
123 | // -------------------------------------------------- | |
124 | // File: cl_u1gb_aoi12_4x.behV | |
125 | // Auto generated verilog module by HnBCellAuto | |
126 | // | |
127 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
128 | // By: balmiki | |
129 | // -------------------------------------------------- | |
130 | // | |
131 | module cl_u1gb_aoi12_4x ( | |
132 | out, | |
133 | in10, | |
134 | in00, | |
135 | in01 ); | |
136 | ||
137 | output out; | |
138 | input in10; | |
139 | input in00; | |
140 | input in01; | |
141 | ||
142 | `ifdef LIB | |
143 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
144 | `endif | |
145 | ||
146 | endmodule | |
147 | // -------------------------------------------------- | |
148 | // File: cl_u1gb_aoi12_8x.behV | |
149 | // Auto generated verilog module by HnBCellAuto | |
150 | // | |
151 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
152 | // By: balmiki | |
153 | // -------------------------------------------------- | |
154 | // | |
155 | module cl_u1gb_aoi12_8x ( | |
156 | out, | |
157 | in10, | |
158 | in00, | |
159 | in01 ); | |
160 | ||
161 | output out; | |
162 | input in10; | |
163 | input in00; | |
164 | input in01; | |
165 | ||
166 | `ifdef LIB | |
167 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
168 | `endif | |
169 | ||
170 | endmodule | |
171 | // -------------------------------------------------- | |
172 | // File: cl_u1gb_aoi21_12x.behV | |
173 | // Auto generated verilog module by HnBCellAuto | |
174 | // | |
175 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
176 | // By: balmiki | |
177 | // -------------------------------------------------- | |
178 | // | |
179 | module cl_u1gb_aoi21_12x ( | |
180 | out, | |
181 | in10, | |
182 | in11, | |
183 | in00 ); | |
184 | ||
185 | output out; | |
186 | input in10; | |
187 | input in11; | |
188 | input in00; | |
189 | ||
190 | `ifdef LIB | |
191 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
192 | `endif | |
193 | ||
194 | endmodule | |
195 | // -------------------------------------------------- | |
196 | // File: cl_u1gb_aoi21_16x.behV | |
197 | // Auto generated verilog module by HnBCellAuto | |
198 | // | |
199 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
200 | // By: balmiki | |
201 | // -------------------------------------------------- | |
202 | // | |
203 | module cl_u1gb_aoi21_16x ( | |
204 | out, | |
205 | in10, | |
206 | in11, | |
207 | in00 ); | |
208 | ||
209 | output out; | |
210 | input in10; | |
211 | input in11; | |
212 | input in00; | |
213 | ||
214 | `ifdef LIB | |
215 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
216 | `endif | |
217 | ||
218 | endmodule | |
219 | // -------------------------------------------------- | |
220 | // File: cl_u1gb_aoi21_1x.behV | |
221 | // Auto generated verilog module by HnBCellAuto | |
222 | // | |
223 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
224 | // By: balmiki | |
225 | // -------------------------------------------------- | |
226 | // | |
227 | module cl_u1gb_aoi21_1x ( | |
228 | out, | |
229 | in10, | |
230 | in11, | |
231 | in00 ); | |
232 | ||
233 | output out; | |
234 | input in10; | |
235 | input in11; | |
236 | input in00; | |
237 | ||
238 | `ifdef LIB | |
239 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
240 | `endif | |
241 | ||
242 | endmodule | |
243 | // -------------------------------------------------- | |
244 | // File: cl_u1gb_aoi21_2x.behV | |
245 | // Auto generated verilog module by HnBCellAuto | |
246 | // | |
247 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
248 | // By: balmiki | |
249 | // -------------------------------------------------- | |
250 | // | |
251 | module cl_u1gb_aoi21_2x ( | |
252 | out, | |
253 | in10, | |
254 | in11, | |
255 | in00 ); | |
256 | ||
257 | output out; | |
258 | input in10; | |
259 | input in11; | |
260 | input in00; | |
261 | ||
262 | `ifdef LIB | |
263 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
264 | `endif | |
265 | ||
266 | endmodule | |
267 | // -------------------------------------------------- | |
268 | // File: cl_u1gb_aoi21_4x.behV | |
269 | // Auto generated verilog module by HnBCellAuto | |
270 | // | |
271 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
272 | // By: balmiki | |
273 | // -------------------------------------------------- | |
274 | // | |
275 | module cl_u1gb_aoi21_4x ( | |
276 | out, | |
277 | in10, | |
278 | in11, | |
279 | in00 ); | |
280 | ||
281 | output out; | |
282 | input in10; | |
283 | input in11; | |
284 | input in00; | |
285 | ||
286 | `ifdef LIB | |
287 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
288 | `endif | |
289 | ||
290 | endmodule | |
291 | // -------------------------------------------------- | |
292 | // File: cl_u1gb_aoi21_8x.behV | |
293 | // Auto generated verilog module by HnBCellAuto | |
294 | // | |
295 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
296 | // By: balmiki | |
297 | // -------------------------------------------------- | |
298 | // | |
299 | module cl_u1gb_aoi21_8x ( | |
300 | out, | |
301 | in10, | |
302 | in11, | |
303 | in00 ); | |
304 | ||
305 | output out; | |
306 | input in10; | |
307 | input in11; | |
308 | input in00; | |
309 | ||
310 | `ifdef LIB | |
311 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
312 | `endif | |
313 | ||
314 | endmodule | |
315 | // -------------------------------------------------- | |
316 | // File: cl_u1gb_aoi22_12x.behV | |
317 | // Auto generated verilog module by HnBCellAuto | |
318 | // | |
319 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
320 | // By: balmiki | |
321 | // -------------------------------------------------- | |
322 | // | |
323 | module cl_u1gb_aoi22_12x ( | |
324 | out, | |
325 | in10, | |
326 | in11, | |
327 | in00, | |
328 | in01 ); | |
329 | ||
330 | output out; | |
331 | input in10; | |
332 | input in11; | |
333 | input in00; | |
334 | input in01; | |
335 | ||
336 | `ifdef LIB | |
337 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
338 | `endif | |
339 | ||
340 | endmodule | |
341 | ||
342 | // -------------------------------------------------- | |
343 | // File: cl_u1gb_aoi22_1x.behV | |
344 | // Auto generated verilog module by HnBCellAuto | |
345 | // | |
346 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT | |
347 | // By: balmiki | |
348 | // -------------------------------------------------- | |
349 | // | |
350 | module cl_u1gb_aoi22_1x ( | |
351 | out, | |
352 | in10, | |
353 | in11, | |
354 | in00, | |
355 | in01 ); | |
356 | ||
357 | output out; | |
358 | input in10; | |
359 | input in11; | |
360 | input in00; | |
361 | input in01; | |
362 | ||
363 | `ifdef LIB | |
364 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
365 | `endif | |
366 | ||
367 | endmodule | |
368 | // -------------------------------------------------- | |
369 | // File: cl_u1gb_aoi22_2x.behV | |
370 | // Auto generated verilog module by HnBCellAuto | |
371 | // | |
372 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
373 | // By: balmiki | |
374 | // -------------------------------------------------- | |
375 | // | |
376 | module cl_u1gb_aoi22_2x ( | |
377 | out, | |
378 | in10, | |
379 | in11, | |
380 | in00, | |
381 | in01 ); | |
382 | ||
383 | output out; | |
384 | input in10; | |
385 | input in11; | |
386 | input in00; | |
387 | input in01; | |
388 | ||
389 | `ifdef LIB | |
390 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
391 | `endif | |
392 | ||
393 | endmodule | |
394 | // -------------------------------------------------- | |
395 | // File: cl_u1gb_aoi22_4x.behV | |
396 | // Auto generated verilog module by HnBCellAuto | |
397 | // | |
398 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
399 | // By: balmiki | |
400 | // -------------------------------------------------- | |
401 | // | |
402 | module cl_u1gb_aoi22_4x ( | |
403 | out, | |
404 | in10, | |
405 | in11, | |
406 | in00, | |
407 | in01 ); | |
408 | ||
409 | output out; | |
410 | input in10; | |
411 | input in11; | |
412 | input in00; | |
413 | input in01; | |
414 | ||
415 | `ifdef LIB | |
416 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
417 | `endif | |
418 | ||
419 | endmodule | |
420 | // -------------------------------------------------- | |
421 | // File: cl_u1gb_aoi22_8x.behV | |
422 | // Auto generated verilog module by HnBCellAuto | |
423 | // | |
424 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
425 | // By: balmiki | |
426 | // -------------------------------------------------- | |
427 | // | |
428 | module cl_u1gb_aoi22_8x ( | |
429 | out, | |
430 | in10, | |
431 | in11, | |
432 | in00, | |
433 | in01 ); | |
434 | ||
435 | output out; | |
436 | input in10; | |
437 | input in11; | |
438 | input in00; | |
439 | input in01; | |
440 | ||
441 | `ifdef LIB | |
442 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
443 | `endif | |
444 | ||
445 | endmodule | |
446 | ||
447 | ||
448 | // -------------------------------------------------- | |
449 | // File: cl_u1gb_aoi33_1x.behV | |
450 | // Auto generated verilog module by HnBCellAuto | |
451 | // | |
452 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST | |
453 | // By: balmiki | |
454 | // -------------------------------------------------- | |
455 | // | |
456 | module cl_u1gb_aoi33_1x ( | |
457 | out, | |
458 | in10, | |
459 | in11, | |
460 | in12, | |
461 | in00, | |
462 | in01, | |
463 | in02 ); | |
464 | ||
465 | output out; | |
466 | input in10; | |
467 | input in11; | |
468 | input in12; | |
469 | input in00; | |
470 | input in01; | |
471 | input in02; | |
472 | ||
473 | `ifdef LIB | |
474 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
475 | `endif | |
476 | ||
477 | endmodule | |
478 | // -------------------------------------------------- | |
479 | // File: cl_u1gb_aoi33_2x.behV | |
480 | // Auto generated verilog module by HnBCellAuto | |
481 | // | |
482 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
483 | // By: balmiki | |
484 | // -------------------------------------------------- | |
485 | // | |
486 | module cl_u1gb_aoi33_2x ( | |
487 | out, | |
488 | in10, | |
489 | in11, | |
490 | in12, | |
491 | in00, | |
492 | in01, | |
493 | in02 ); | |
494 | ||
495 | output out; | |
496 | input in10; | |
497 | input in11; | |
498 | input in12; | |
499 | input in00; | |
500 | input in01; | |
501 | input in02; | |
502 | ||
503 | `ifdef LIB | |
504 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
505 | `endif | |
506 | ||
507 | endmodule | |
508 | // -------------------------------------------------- | |
509 | // File: cl_u1gb_aoi33_4x.behV | |
510 | // Auto generated verilog module by HnBCellAuto | |
511 | // | |
512 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
513 | // By: balmiki | |
514 | // -------------------------------------------------- | |
515 | // | |
516 | module cl_u1gb_aoi33_4x ( | |
517 | out, | |
518 | in10, | |
519 | in11, | |
520 | in12, | |
521 | in00, | |
522 | in01, | |
523 | in02 ); | |
524 | ||
525 | output out; | |
526 | input in10; | |
527 | input in11; | |
528 | input in12; | |
529 | input in00; | |
530 | input in01; | |
531 | input in02; | |
532 | ||
533 | `ifdef LIB | |
534 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
535 | `endif | |
536 | ||
537 | endmodule | |
538 | // -------------------------------------------------- | |
539 | // File: cl_u1gb_aoi33_8x.behV | |
540 | // Auto generated verilog module by HnBCellAuto | |
541 | // | |
542 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
543 | // By: balmiki | |
544 | // -------------------------------------------------- | |
545 | // | |
546 | module cl_u1gb_aoi33_8x ( | |
547 | out, | |
548 | in10, | |
549 | in11, | |
550 | in12, | |
551 | in00, | |
552 | in01, | |
553 | in02 ); | |
554 | ||
555 | output out; | |
556 | input in10; | |
557 | input in11; | |
558 | input in12; | |
559 | input in00; | |
560 | input in01; | |
561 | input in02; | |
562 | ||
563 | `ifdef LIB | |
564 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
565 | `endif | |
566 | ||
567 | endmodule | |
568 | ||
569 | ||
570 | module cl_u1gb_buf_12x ( | |
571 | in, | |
572 | out | |
573 | ); | |
574 | input in; | |
575 | output out; | |
576 | ||
577 | `ifdef LIB | |
578 | //assign out = in; | |
579 | buf (out, in); | |
580 | `endif | |
581 | ||
582 | endmodule | |
583 | module cl_u1gb_buf_16x ( | |
584 | in, | |
585 | out | |
586 | ); | |
587 | input in; | |
588 | output out; | |
589 | ||
590 | `ifdef LIB | |
591 | //assign out = in; | |
592 | buf (out, in); | |
593 | `endif | |
594 | ||
595 | endmodule | |
596 | module cl_u1gb_buf_1x ( | |
597 | in, | |
598 | out | |
599 | ); | |
600 | input in; | |
601 | output out; | |
602 | ||
603 | `ifdef LIB | |
604 | //assign out = in; | |
605 | buf (out, in); | |
606 | `endif | |
607 | ||
608 | endmodule | |
609 | module cl_u1gb_buf_20x ( | |
610 | in, | |
611 | out | |
612 | ); | |
613 | input in; | |
614 | output out; | |
615 | ||
616 | `ifdef LIB | |
617 | //assign out = in; | |
618 | buf (out, in); | |
619 | `endif | |
620 | ||
621 | endmodule | |
622 | module cl_u1gb_buf_24x ( | |
623 | in, | |
624 | out | |
625 | ); | |
626 | input in; | |
627 | output out; | |
628 | ||
629 | `ifdef LIB | |
630 | //assign out = in; | |
631 | buf (out, in); | |
632 | `endif | |
633 | ||
634 | endmodule | |
635 | module cl_u1gb_buf_28x ( | |
636 | in, | |
637 | out | |
638 | ); | |
639 | input in; | |
640 | output out; | |
641 | ||
642 | `ifdef LIB | |
643 | //assign out = in; | |
644 | buf (out, in); | |
645 | `endif | |
646 | ||
647 | endmodule | |
648 | module cl_u1gb_buf_2x ( | |
649 | in, | |
650 | out | |
651 | ); | |
652 | input in; | |
653 | output out; | |
654 | ||
655 | `ifdef LIB | |
656 | //assign out = in; | |
657 | buf (out, in); | |
658 | `endif | |
659 | ||
660 | endmodule | |
661 | module cl_u1gb_buf_32x ( | |
662 | in, | |
663 | out | |
664 | ); | |
665 | input in; | |
666 | output out; | |
667 | ||
668 | `ifdef LIB | |
669 | //assign out = in; | |
670 | buf (out, in); | |
671 | `endif | |
672 | ||
673 | endmodule | |
674 | module cl_u1gb_buf_36x ( | |
675 | in, | |
676 | out | |
677 | ); | |
678 | input in; | |
679 | output out; | |
680 | ||
681 | `ifdef LIB | |
682 | //assign out = in; | |
683 | buf (out, in); | |
684 | `endif | |
685 | ||
686 | endmodule | |
687 | module cl_u1gb_buf_40x ( | |
688 | in, | |
689 | out | |
690 | ); | |
691 | input in; | |
692 | output out; | |
693 | ||
694 | `ifdef LIB | |
695 | //assign out = in; | |
696 | buf (out, in); | |
697 | `endif | |
698 | ||
699 | endmodule | |
700 | module cl_u1gb_buf_44x ( | |
701 | in, | |
702 | out | |
703 | ); | |
704 | input in; | |
705 | output out; | |
706 | ||
707 | `ifdef LIB | |
708 | //assign out = in; | |
709 | buf (out, in); | |
710 | `endif | |
711 | ||
712 | endmodule | |
713 | module cl_u1gb_buf_48x ( | |
714 | in, | |
715 | out | |
716 | ); | |
717 | input in; | |
718 | output out; | |
719 | ||
720 | `ifdef LIB | |
721 | //assign out = in; | |
722 | buf (out, in); | |
723 | `endif | |
724 | ||
725 | endmodule | |
726 | module cl_u1gb_buf_4x ( | |
727 | in, | |
728 | out | |
729 | ); | |
730 | input in; | |
731 | output out; | |
732 | ||
733 | `ifdef LIB | |
734 | //assign out = in; | |
735 | buf (out, in); | |
736 | `endif | |
737 | ||
738 | endmodule | |
739 | module cl_u1gb_buf_56x ( | |
740 | in, | |
741 | out | |
742 | ); | |
743 | input in; | |
744 | output out; | |
745 | ||
746 | `ifdef LIB | |
747 | //assign out = in; | |
748 | buf (out, in); | |
749 | `endif | |
750 | ||
751 | endmodule | |
752 | module cl_u1gb_buf_64x ( | |
753 | in, | |
754 | out | |
755 | ); | |
756 | input in; | |
757 | output out; | |
758 | ||
759 | `ifdef LIB | |
760 | //assign out = in; | |
761 | buf (out, in); | |
762 | `endif | |
763 | ||
764 | endmodule | |
765 | module cl_u1gb_buf_6x ( | |
766 | in, | |
767 | out | |
768 | ); | |
769 | input in; | |
770 | output out; | |
771 | ||
772 | `ifdef LIB | |
773 | //assign out = in; | |
774 | buf (out, in); | |
775 | `endif | |
776 | ||
777 | endmodule | |
778 | module cl_u1gb_buf_8x ( | |
779 | in, | |
780 | out | |
781 | ); | |
782 | input in; | |
783 | output out; | |
784 | ||
785 | `ifdef LIB | |
786 | //assign out = in; | |
787 | buf (out, in); | |
788 | `endif | |
789 | ||
790 | endmodule | |
791 | ||
792 | ||
793 | module cl_u1gb_inv_12x ( | |
794 | in, | |
795 | out | |
796 | ); | |
797 | input in; | |
798 | output out; | |
799 | ||
800 | `ifdef LIB | |
801 | //assign out = ~in; | |
802 | not (out, in); | |
803 | `endif | |
804 | ||
805 | endmodule | |
806 | module cl_u1gb_inv_16x ( | |
807 | in, | |
808 | out | |
809 | ); | |
810 | input in; | |
811 | output out; | |
812 | ||
813 | `ifdef LIB | |
814 | //assign out = ~in; | |
815 | not (out, in); | |
816 | `endif | |
817 | ||
818 | endmodule | |
819 | module cl_u1gb_inv_1x ( | |
820 | in, | |
821 | out | |
822 | ); | |
823 | input in; | |
824 | output out; | |
825 | ||
826 | `ifdef LIB | |
827 | //assign out = ~in; | |
828 | not (out, in); | |
829 | `endif | |
830 | ||
831 | endmodule | |
832 | module cl_u1gb_inv_20x ( | |
833 | in, | |
834 | out | |
835 | ); | |
836 | input in; | |
837 | output out; | |
838 | ||
839 | `ifdef LIB | |
840 | //assign out = ~in; | |
841 | not (out, in); | |
842 | `endif | |
843 | ||
844 | endmodule | |
845 | module cl_u1gb_inv_24x ( | |
846 | in, | |
847 | out | |
848 | ); | |
849 | input in; | |
850 | output out; | |
851 | ||
852 | `ifdef LIB | |
853 | //assign out = ~in; | |
854 | not (out, in); | |
855 | `endif | |
856 | ||
857 | endmodule | |
858 | module cl_u1gb_inv_28x ( | |
859 | in, | |
860 | out | |
861 | ); | |
862 | input in; | |
863 | output out; | |
864 | ||
865 | `ifdef LIB | |
866 | //assign out = ~in; | |
867 | not (out, in); | |
868 | `endif | |
869 | ||
870 | endmodule | |
871 | module cl_u1gb_inv_2x ( | |
872 | in, | |
873 | out | |
874 | ); | |
875 | input in; | |
876 | output out; | |
877 | ||
878 | `ifdef LIB | |
879 | //assign out = ~in; | |
880 | not (out, in); | |
881 | `endif | |
882 | ||
883 | endmodule | |
884 | module cl_u1gb_inv_32x ( | |
885 | in, | |
886 | out | |
887 | ); | |
888 | input in; | |
889 | output out; | |
890 | ||
891 | `ifdef LIB | |
892 | //assign out = ~in; | |
893 | not (out, in); | |
894 | `endif | |
895 | ||
896 | endmodule | |
897 | module cl_u1gb_inv_36x ( | |
898 | in, | |
899 | out | |
900 | ); | |
901 | input in; | |
902 | output out; | |
903 | ||
904 | `ifdef LIB | |
905 | //assign out = ~in; | |
906 | not (out, in); | |
907 | `endif | |
908 | ||
909 | endmodule | |
910 | module cl_u1gb_inv_40x ( | |
911 | in, | |
912 | out | |
913 | ); | |
914 | input in; | |
915 | output out; | |
916 | ||
917 | `ifdef LIB | |
918 | //assign out = ~in; | |
919 | not (out, in); | |
920 | `endif | |
921 | ||
922 | endmodule | |
923 | module cl_u1gb_inv_44x ( | |
924 | in, | |
925 | out | |
926 | ); | |
927 | input in; | |
928 | output out; | |
929 | ||
930 | `ifdef LIB | |
931 | //assign out = ~in; | |
932 | not (out, in); | |
933 | `endif | |
934 | ||
935 | endmodule | |
936 | module cl_u1gb_inv_48x ( | |
937 | in, | |
938 | out | |
939 | ); | |
940 | input in; | |
941 | output out; | |
942 | ||
943 | `ifdef LIB | |
944 | //assign out = ~in; | |
945 | not (out, in); | |
946 | `endif | |
947 | ||
948 | endmodule | |
949 | module cl_u1gb_inv_4x ( | |
950 | in, | |
951 | out | |
952 | ); | |
953 | input in; | |
954 | output out; | |
955 | ||
956 | `ifdef LIB | |
957 | //assign out = ~in; | |
958 | not (out, in); | |
959 | `endif | |
960 | ||
961 | endmodule | |
962 | module cl_u1gb_inv_56x ( | |
963 | in, | |
964 | out | |
965 | ); | |
966 | input in; | |
967 | output out; | |
968 | ||
969 | `ifdef LIB | |
970 | //assign out = ~in; | |
971 | not (out, in); | |
972 | `endif | |
973 | ||
974 | endmodule | |
975 | module cl_u1gb_inv_64x ( | |
976 | in, | |
977 | out | |
978 | ); | |
979 | input in; | |
980 | output out; | |
981 | ||
982 | `ifdef LIB | |
983 | //assign out = ~in; | |
984 | not (out, in); | |
985 | `endif | |
986 | ||
987 | endmodule | |
988 | module cl_u1gb_inv_6x ( | |
989 | in, | |
990 | out | |
991 | ); | |
992 | input in; | |
993 | output out; | |
994 | ||
995 | `ifdef LIB | |
996 | //assign out = ~in; | |
997 | not (out, in); | |
998 | `endif | |
999 | ||
1000 | endmodule | |
1001 | module cl_u1gb_inv_8x ( | |
1002 | in, | |
1003 | out | |
1004 | ); | |
1005 | input in; | |
1006 | output out; | |
1007 | ||
1008 | `ifdef LIB | |
1009 | //assign out = ~in; | |
1010 | not (out, in); | |
1011 | `endif | |
1012 | ||
1013 | endmodule | |
1014 | module cl_u1gb_nand2_12x ( | |
1015 | in0, | |
1016 | in1, | |
1017 | out | |
1018 | ); | |
1019 | input in0; | |
1020 | input in1; | |
1021 | output out; | |
1022 | ||
1023 | `ifdef LIB | |
1024 | assign out = ~(in0 & in1); | |
1025 | `endif | |
1026 | ||
1027 | endmodule | |
1028 | module cl_u1gb_nand2_16x ( | |
1029 | in0, | |
1030 | in1, | |
1031 | out | |
1032 | ); | |
1033 | input in0; | |
1034 | input in1; | |
1035 | output out; | |
1036 | ||
1037 | `ifdef LIB | |
1038 | assign out = ~(in0 & in1); | |
1039 | `endif | |
1040 | ||
1041 | endmodule | |
1042 | module cl_u1gb_nand2_1x ( | |
1043 | in0, | |
1044 | in1, | |
1045 | out | |
1046 | ); | |
1047 | input in0; | |
1048 | input in1; | |
1049 | output out; | |
1050 | ||
1051 | `ifdef LIB | |
1052 | assign out = ~(in0 & in1); | |
1053 | `endif | |
1054 | ||
1055 | endmodule | |
1056 | module cl_u1gb_nand2_20x ( | |
1057 | in0, | |
1058 | in1, | |
1059 | out | |
1060 | ); | |
1061 | input in0; | |
1062 | input in1; | |
1063 | output out; | |
1064 | ||
1065 | `ifdef LIB | |
1066 | assign out = ~(in0 & in1); | |
1067 | `endif | |
1068 | ||
1069 | endmodule | |
1070 | module cl_u1gb_nand2_24x ( | |
1071 | in0, | |
1072 | in1, | |
1073 | out | |
1074 | ); | |
1075 | input in0; | |
1076 | input in1; | |
1077 | output out; | |
1078 | ||
1079 | `ifdef LIB | |
1080 | assign out = ~(in0 & in1); | |
1081 | `endif | |
1082 | ||
1083 | endmodule | |
1084 | module cl_u1gb_nand2_28x ( | |
1085 | in0, | |
1086 | in1, | |
1087 | out | |
1088 | ); | |
1089 | input in0; | |
1090 | input in1; | |
1091 | output out; | |
1092 | ||
1093 | `ifdef LIB | |
1094 | assign out = ~(in0 & in1); | |
1095 | `endif | |
1096 | ||
1097 | endmodule | |
1098 | module cl_u1gb_nand2_2x ( | |
1099 | in0, | |
1100 | in1, | |
1101 | out | |
1102 | ); | |
1103 | input in0; | |
1104 | input in1; | |
1105 | output out; | |
1106 | ||
1107 | `ifdef LIB | |
1108 | assign out = ~(in0 & in1); | |
1109 | `endif | |
1110 | ||
1111 | endmodule | |
1112 | module cl_u1gb_nand2_32x ( | |
1113 | in0, | |
1114 | in1, | |
1115 | out | |
1116 | ); | |
1117 | input in0; | |
1118 | input in1; | |
1119 | output out; | |
1120 | ||
1121 | `ifdef LIB | |
1122 | assign out = ~(in0 & in1); | |
1123 | `endif | |
1124 | ||
1125 | endmodule | |
1126 | module cl_u1gb_nand2_4x ( | |
1127 | in0, | |
1128 | in1, | |
1129 | out | |
1130 | ); | |
1131 | input in0; | |
1132 | input in1; | |
1133 | output out; | |
1134 | ||
1135 | `ifdef LIB | |
1136 | assign out = ~(in0 & in1); | |
1137 | `endif | |
1138 | ||
1139 | endmodule | |
1140 | module cl_u1gb_nand2_6x ( | |
1141 | in0, | |
1142 | in1, | |
1143 | out | |
1144 | ); | |
1145 | input in0; | |
1146 | input in1; | |
1147 | output out; | |
1148 | ||
1149 | `ifdef LIB | |
1150 | assign out = ~(in0 & in1); | |
1151 | `endif | |
1152 | ||
1153 | endmodule | |
1154 | module cl_u1gb_nand2_8x ( | |
1155 | in0, | |
1156 | in1, | |
1157 | out | |
1158 | ); | |
1159 | input in0; | |
1160 | input in1; | |
1161 | output out; | |
1162 | ||
1163 | `ifdef LIB | |
1164 | assign out = ~(in0 & in1); | |
1165 | `endif | |
1166 | ||
1167 | endmodule | |
1168 | module cl_u1gb_nand3_12x ( | |
1169 | in0, | |
1170 | in1, | |
1171 | in2, | |
1172 | out | |
1173 | ); | |
1174 | input in0; | |
1175 | input in1; | |
1176 | input in2; | |
1177 | output out; | |
1178 | ||
1179 | `ifdef LIB | |
1180 | assign out = ~(in0 & in1 & in2); | |
1181 | `endif | |
1182 | ||
1183 | endmodule | |
1184 | module cl_u1gb_nand3_16x ( | |
1185 | in0, | |
1186 | in1, | |
1187 | in2, | |
1188 | out | |
1189 | ); | |
1190 | input in0; | |
1191 | input in1; | |
1192 | input in2; | |
1193 | output out; | |
1194 | ||
1195 | `ifdef LIB | |
1196 | assign out = ~(in0 & in1 & in2); | |
1197 | `endif | |
1198 | ||
1199 | endmodule | |
1200 | module cl_u1gb_nand3_1x ( | |
1201 | in0, | |
1202 | in1, | |
1203 | in2, | |
1204 | out | |
1205 | ); | |
1206 | input in0; | |
1207 | input in1; | |
1208 | input in2; | |
1209 | output out; | |
1210 | ||
1211 | `ifdef LIB | |
1212 | assign out = ~(in0 & in1 & in2); | |
1213 | `endif | |
1214 | ||
1215 | endmodule | |
1216 | module cl_u1gb_nand3_20x ( | |
1217 | in0, | |
1218 | in1, | |
1219 | in2, | |
1220 | out | |
1221 | ); | |
1222 | input in0; | |
1223 | input in1; | |
1224 | input in2; | |
1225 | output out; | |
1226 | ||
1227 | `ifdef LIB | |
1228 | assign out = ~(in0 & in1 & in2); | |
1229 | `endif | |
1230 | ||
1231 | endmodule | |
1232 | module cl_u1gb_nand3_24x ( | |
1233 | in0, | |
1234 | in1, | |
1235 | in2, | |
1236 | out | |
1237 | ); | |
1238 | input in0; | |
1239 | input in1; | |
1240 | input in2; | |
1241 | output out; | |
1242 | ||
1243 | `ifdef LIB | |
1244 | assign out = ~(in0 & in1 & in2); | |
1245 | `endif | |
1246 | ||
1247 | endmodule | |
1248 | ||
1249 | module cl_u1gb_nand3_2x ( | |
1250 | in0, | |
1251 | in1, | |
1252 | in2, | |
1253 | out | |
1254 | ); | |
1255 | input in0; | |
1256 | input in1; | |
1257 | input in2; | |
1258 | output out; | |
1259 | ||
1260 | `ifdef LIB | |
1261 | assign out = ~(in0 & in1 & in2); | |
1262 | `endif | |
1263 | ||
1264 | endmodule | |
1265 | ||
1266 | module cl_u1gb_nand3_4x ( | |
1267 | in0, | |
1268 | in1, | |
1269 | in2, | |
1270 | out | |
1271 | ); | |
1272 | input in0; | |
1273 | input in1; | |
1274 | input in2; | |
1275 | output out; | |
1276 | ||
1277 | `ifdef LIB | |
1278 | assign out = ~(in0 & in1 & in2); | |
1279 | `endif | |
1280 | ||
1281 | endmodule | |
1282 | module cl_u1gb_nand3_6x ( | |
1283 | in0, | |
1284 | in1, | |
1285 | in2, | |
1286 | out | |
1287 | ); | |
1288 | input in0; | |
1289 | input in1; | |
1290 | input in2; | |
1291 | output out; | |
1292 | ||
1293 | `ifdef LIB | |
1294 | assign out = ~(in0 & in1 & in2); | |
1295 | `endif | |
1296 | ||
1297 | endmodule | |
1298 | module cl_u1gb_nand3_8x ( | |
1299 | in0, | |
1300 | in1, | |
1301 | in2, | |
1302 | out | |
1303 | ); | |
1304 | input in0; | |
1305 | input in1; | |
1306 | input in2; | |
1307 | output out; | |
1308 | ||
1309 | `ifdef LIB | |
1310 | assign out = ~(in0 & in1 & in2); | |
1311 | `endif | |
1312 | ||
1313 | endmodule | |
1314 | module cl_u1gb_nand4_12x ( | |
1315 | in0, | |
1316 | in1, | |
1317 | in2, | |
1318 | in3, | |
1319 | out | |
1320 | ); | |
1321 | input in0; | |
1322 | input in1; | |
1323 | input in2; | |
1324 | input in3; | |
1325 | output out; | |
1326 | ||
1327 | `ifdef LIB | |
1328 | assign out = ~(in0 & in1 & in2 & in3); | |
1329 | `endif | |
1330 | ||
1331 | endmodule | |
1332 | module cl_u1gb_nand4_16x ( | |
1333 | in0, | |
1334 | in1, | |
1335 | in2, | |
1336 | in3, | |
1337 | out | |
1338 | ); | |
1339 | input in0; | |
1340 | input in1; | |
1341 | input in2; | |
1342 | input in3; | |
1343 | output out; | |
1344 | ||
1345 | `ifdef LIB | |
1346 | assign out = ~(in0 & in1 & in2 & in3); | |
1347 | `endif | |
1348 | ||
1349 | endmodule | |
1350 | module cl_u1gb_nand4_1x ( | |
1351 | in0, | |
1352 | in1, | |
1353 | in2, | |
1354 | in3, | |
1355 | out | |
1356 | ); | |
1357 | input in0; | |
1358 | input in1; | |
1359 | input in2; | |
1360 | input in3; | |
1361 | output out; | |
1362 | ||
1363 | `ifdef LIB | |
1364 | assign out = ~(in0 & in1 & in2 & in3); | |
1365 | `endif | |
1366 | ||
1367 | endmodule | |
1368 | ||
1369 | ||
1370 | module cl_u1gb_nand4_2x ( | |
1371 | in0, | |
1372 | in1, | |
1373 | in2, | |
1374 | in3, | |
1375 | out | |
1376 | ); | |
1377 | input in0; | |
1378 | input in1; | |
1379 | input in2; | |
1380 | input in3; | |
1381 | output out; | |
1382 | ||
1383 | `ifdef LIB | |
1384 | assign out = ~(in0 & in1 & in2 & in3); | |
1385 | `endif | |
1386 | ||
1387 | endmodule | |
1388 | ||
1389 | module cl_u1gb_nand4_4x ( | |
1390 | in0, | |
1391 | in1, | |
1392 | in2, | |
1393 | in3, | |
1394 | out | |
1395 | ); | |
1396 | input in0; | |
1397 | input in1; | |
1398 | input in2; | |
1399 | input in3; | |
1400 | output out; | |
1401 | ||
1402 | `ifdef LIB | |
1403 | assign out = ~(in0 & in1 & in2 & in3); | |
1404 | `endif | |
1405 | ||
1406 | endmodule | |
1407 | module cl_u1gb_nand4_6x ( | |
1408 | in0, | |
1409 | in1, | |
1410 | in2, | |
1411 | in3, | |
1412 | out | |
1413 | ); | |
1414 | input in0; | |
1415 | input in1; | |
1416 | input in2; | |
1417 | input in3; | |
1418 | output out; | |
1419 | ||
1420 | `ifdef LIB | |
1421 | assign out = ~(in0 & in1 & in2 & in3); | |
1422 | `endif | |
1423 | ||
1424 | endmodule | |
1425 | module cl_u1gb_nand4_8x ( | |
1426 | in0, | |
1427 | in1, | |
1428 | in2, | |
1429 | in3, | |
1430 | out | |
1431 | ); | |
1432 | input in0; | |
1433 | input in1; | |
1434 | input in2; | |
1435 | input in3; | |
1436 | output out; | |
1437 | ||
1438 | `ifdef LIB | |
1439 | assign out = ~(in0 & in1 & in2 & in3); | |
1440 | `endif | |
1441 | ||
1442 | endmodule | |
1443 | module cl_u1gb_nor2_12x ( | |
1444 | in0, | |
1445 | in1, | |
1446 | out | |
1447 | ); | |
1448 | input in0; | |
1449 | input in1; | |
1450 | output out; | |
1451 | ||
1452 | `ifdef LIB | |
1453 | assign out = ~(in0 | in1); | |
1454 | `endif | |
1455 | ||
1456 | endmodule | |
1457 | module cl_u1gb_nor2_16x ( | |
1458 | in0, | |
1459 | in1, | |
1460 | out | |
1461 | ); | |
1462 | input in0; | |
1463 | input in1; | |
1464 | output out; | |
1465 | ||
1466 | `ifdef LIB | |
1467 | assign out = ~(in0 | in1); | |
1468 | `endif | |
1469 | ||
1470 | endmodule | |
1471 | module cl_u1gb_nor2_1x ( | |
1472 | in0, | |
1473 | in1, | |
1474 | out | |
1475 | ); | |
1476 | input in0; | |
1477 | input in1; | |
1478 | output out; | |
1479 | ||
1480 | `ifdef LIB | |
1481 | assign out = ~(in0 | in1); | |
1482 | `endif | |
1483 | ||
1484 | endmodule | |
1485 | module cl_u1gb_nor2_2x ( | |
1486 | in0, | |
1487 | in1, | |
1488 | out | |
1489 | ); | |
1490 | input in0; | |
1491 | input in1; | |
1492 | output out; | |
1493 | ||
1494 | `ifdef LIB | |
1495 | assign out = ~(in0 | in1); | |
1496 | `endif | |
1497 | ||
1498 | endmodule | |
1499 | module cl_u1gb_nor2_4x ( | |
1500 | in0, | |
1501 | in1, | |
1502 | out | |
1503 | ); | |
1504 | input in0; | |
1505 | input in1; | |
1506 | output out; | |
1507 | ||
1508 | `ifdef LIB | |
1509 | assign out = ~(in0 | in1); | |
1510 | `endif | |
1511 | ||
1512 | endmodule | |
1513 | module cl_u1gb_nor2_6x ( | |
1514 | in0, | |
1515 | in1, | |
1516 | out | |
1517 | ); | |
1518 | input in0; | |
1519 | input in1; | |
1520 | output out; | |
1521 | ||
1522 | `ifdef LIB | |
1523 | assign out = ~(in0 | in1); | |
1524 | `endif | |
1525 | ||
1526 | endmodule | |
1527 | module cl_u1gb_nor2_8x ( | |
1528 | in0, | |
1529 | in1, | |
1530 | out | |
1531 | ); | |
1532 | input in0; | |
1533 | input in1; | |
1534 | output out; | |
1535 | ||
1536 | `ifdef LIB | |
1537 | assign out = ~(in0 | in1); | |
1538 | `endif | |
1539 | ||
1540 | endmodule | |
1541 | module cl_u1gb_nor3_1x ( | |
1542 | in0, | |
1543 | in1, | |
1544 | in2, | |
1545 | out | |
1546 | ); | |
1547 | input in0; | |
1548 | input in1; | |
1549 | input in2; | |
1550 | output out; | |
1551 | ||
1552 | `ifdef LIB | |
1553 | assign out = ~(in0 | in1 | in2); | |
1554 | `endif | |
1555 | ||
1556 | endmodule | |
1557 | module cl_u1gb_nor3_2x ( | |
1558 | in0, | |
1559 | in1, | |
1560 | in2, | |
1561 | out | |
1562 | ); | |
1563 | input in0; | |
1564 | input in1; | |
1565 | input in2; | |
1566 | output out; | |
1567 | ||
1568 | `ifdef LIB | |
1569 | assign out = ~(in0 | in1 | in2); | |
1570 | `endif | |
1571 | ||
1572 | endmodule | |
1573 | module cl_u1gb_nor3_4x ( | |
1574 | in0, | |
1575 | in1, | |
1576 | in2, | |
1577 | out | |
1578 | ); | |
1579 | input in0; | |
1580 | input in1; | |
1581 | input in2; | |
1582 | output out; | |
1583 | ||
1584 | `ifdef LIB | |
1585 | assign out = ~(in0 | in1 | in2); | |
1586 | `endif | |
1587 | ||
1588 | endmodule | |
1589 | // -------------------------------------------------- | |
1590 | // File: cl_u1gb_oai12_12x.behV | |
1591 | // Auto generated verilog module by HnBCellAuto | |
1592 | // | |
1593 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1594 | // By: balmiki | |
1595 | // -------------------------------------------------- | |
1596 | // | |
1597 | module cl_u1gb_oai12_12x ( | |
1598 | out, | |
1599 | in10, | |
1600 | in00, | |
1601 | in01 ); | |
1602 | ||
1603 | output out; | |
1604 | input in10; | |
1605 | input in00; | |
1606 | input in01; | |
1607 | ||
1608 | `ifdef LIB | |
1609 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1610 | `endif | |
1611 | ||
1612 | endmodule | |
1613 | // -------------------------------------------------- | |
1614 | // File: cl_u1gb_oai12_16x.behV | |
1615 | // Auto generated verilog module by HnBCellAuto | |
1616 | // | |
1617 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1618 | // By: balmiki | |
1619 | // -------------------------------------------------- | |
1620 | // | |
1621 | module cl_u1gb_oai12_16x ( | |
1622 | out, | |
1623 | in10, | |
1624 | in00, | |
1625 | in01 ); | |
1626 | ||
1627 | output out; | |
1628 | input in10; | |
1629 | input in00; | |
1630 | input in01; | |
1631 | ||
1632 | `ifdef LIB | |
1633 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1634 | `endif | |
1635 | ||
1636 | endmodule | |
1637 | // -------------------------------------------------- | |
1638 | // File: cl_u1gb_oai12_1x.behV | |
1639 | // Auto generated verilog module by HnBCellAuto | |
1640 | // | |
1641 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1642 | // By: balmiki | |
1643 | // -------------------------------------------------- | |
1644 | // | |
1645 | module cl_u1gb_oai12_1x ( | |
1646 | out, | |
1647 | in10, | |
1648 | in00, | |
1649 | in01 ); | |
1650 | ||
1651 | output out; | |
1652 | input in10; | |
1653 | input in00; | |
1654 | input in01; | |
1655 | ||
1656 | `ifdef LIB | |
1657 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1658 | `endif | |
1659 | ||
1660 | endmodule | |
1661 | // -------------------------------------------------- | |
1662 | // File: cl_u1gb_oai12_2x.behV | |
1663 | // Auto generated verilog module by HnBCellAuto | |
1664 | // | |
1665 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1666 | // By: balmiki | |
1667 | // -------------------------------------------------- | |
1668 | // | |
1669 | module cl_u1gb_oai12_2x ( | |
1670 | out, | |
1671 | in10, | |
1672 | in00, | |
1673 | in01 ); | |
1674 | ||
1675 | output out; | |
1676 | input in10; | |
1677 | input in00; | |
1678 | input in01; | |
1679 | ||
1680 | `ifdef LIB | |
1681 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1682 | `endif | |
1683 | ||
1684 | endmodule | |
1685 | // -------------------------------------------------- | |
1686 | // File: cl_u1gb_oai12_4x.behV | |
1687 | // Auto generated verilog module by HnBCellAuto | |
1688 | // | |
1689 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1690 | // By: balmiki | |
1691 | // -------------------------------------------------- | |
1692 | // | |
1693 | module cl_u1gb_oai12_4x ( | |
1694 | out, | |
1695 | in10, | |
1696 | in00, | |
1697 | in01 ); | |
1698 | ||
1699 | output out; | |
1700 | input in10; | |
1701 | input in00; | |
1702 | input in01; | |
1703 | ||
1704 | `ifdef LIB | |
1705 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1706 | `endif | |
1707 | ||
1708 | endmodule | |
1709 | // -------------------------------------------------- | |
1710 | // File: cl_u1gb_oai12_8x.behV | |
1711 | // Auto generated verilog module by HnBCellAuto | |
1712 | // | |
1713 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1714 | // By: balmiki | |
1715 | // -------------------------------------------------- | |
1716 | // | |
1717 | module cl_u1gb_oai12_8x ( | |
1718 | out, | |
1719 | in10, | |
1720 | in00, | |
1721 | in01 ); | |
1722 | ||
1723 | output out; | |
1724 | input in10; | |
1725 | input in00; | |
1726 | input in01; | |
1727 | ||
1728 | `ifdef LIB | |
1729 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1730 | `endif | |
1731 | ||
1732 | endmodule | |
1733 | // -------------------------------------------------- | |
1734 | // File: cl_u1gb_oai21_12x.behV | |
1735 | // Auto generated verilog module by HnBCellAuto | |
1736 | // | |
1737 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1738 | // By: balmiki | |
1739 | // -------------------------------------------------- | |
1740 | // | |
1741 | module cl_u1gb_oai21_12x ( | |
1742 | out, | |
1743 | in10, | |
1744 | in11, | |
1745 | in00 ); | |
1746 | ||
1747 | output out; | |
1748 | input in10; | |
1749 | input in11; | |
1750 | input in00; | |
1751 | ||
1752 | `ifdef LIB | |
1753 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1754 | `endif | |
1755 | ||
1756 | endmodule | |
1757 | // -------------------------------------------------- | |
1758 | // File: cl_u1gb_oai21_16x.behV | |
1759 | // Auto generated verilog module by HnBCellAuto | |
1760 | // | |
1761 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1762 | // By: balmiki | |
1763 | // -------------------------------------------------- | |
1764 | // | |
1765 | module cl_u1gb_oai21_16x ( | |
1766 | out, | |
1767 | in10, | |
1768 | in11, | |
1769 | in00 ); | |
1770 | ||
1771 | output out; | |
1772 | input in10; | |
1773 | input in11; | |
1774 | input in00; | |
1775 | ||
1776 | `ifdef LIB | |
1777 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1778 | `endif | |
1779 | ||
1780 | endmodule | |
1781 | // -------------------------------------------------- | |
1782 | // File: cl_u1gb_oai21_1x.behV | |
1783 | // Auto generated verilog module by HnBCellAuto | |
1784 | // | |
1785 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST | |
1786 | // By: balmiki | |
1787 | // -------------------------------------------------- | |
1788 | // | |
1789 | module cl_u1gb_oai21_1x ( | |
1790 | out, | |
1791 | in10, | |
1792 | in11, | |
1793 | in00 ); | |
1794 | ||
1795 | output out; | |
1796 | input in10; | |
1797 | input in11; | |
1798 | input in00; | |
1799 | ||
1800 | `ifdef LIB | |
1801 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1802 | `endif | |
1803 | ||
1804 | endmodule | |
1805 | // -------------------------------------------------- | |
1806 | // File: cl_u1gb_oai21_2x.behV | |
1807 | // Auto generated verilog module by HnBCellAuto | |
1808 | // | |
1809 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1810 | // By: balmiki | |
1811 | // -------------------------------------------------- | |
1812 | // | |
1813 | module cl_u1gb_oai21_2x ( | |
1814 | out, | |
1815 | in10, | |
1816 | in11, | |
1817 | in00 ); | |
1818 | ||
1819 | output out; | |
1820 | input in10; | |
1821 | input in11; | |
1822 | input in00; | |
1823 | ||
1824 | `ifdef LIB | |
1825 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1826 | `endif | |
1827 | ||
1828 | endmodule | |
1829 | // -------------------------------------------------- | |
1830 | // File: cl_u1gb_oai21_4x.behV | |
1831 | // Auto generated verilog module by HnBCellAuto | |
1832 | // | |
1833 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1834 | // By: balmiki | |
1835 | // -------------------------------------------------- | |
1836 | // | |
1837 | module cl_u1gb_oai21_4x ( | |
1838 | out, | |
1839 | in10, | |
1840 | in11, | |
1841 | in00 ); | |
1842 | ||
1843 | output out; | |
1844 | input in10; | |
1845 | input in11; | |
1846 | input in00; | |
1847 | ||
1848 | `ifdef LIB | |
1849 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1850 | `endif | |
1851 | ||
1852 | endmodule | |
1853 | // -------------------------------------------------- | |
1854 | // File: cl_u1gb_oai21_8x.behV | |
1855 | // Auto generated verilog module by HnBCellAuto | |
1856 | // | |
1857 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1858 | // By: balmiki | |
1859 | // -------------------------------------------------- | |
1860 | // | |
1861 | module cl_u1gb_oai21_8x ( | |
1862 | out, | |
1863 | in10, | |
1864 | in11, | |
1865 | in00 ); | |
1866 | ||
1867 | output out; | |
1868 | input in10; | |
1869 | input in11; | |
1870 | input in00; | |
1871 | ||
1872 | `ifdef LIB | |
1873 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1874 | `endif | |
1875 | ||
1876 | endmodule | |
1877 | // -------------------------------------------------- | |
1878 | // File: cl_u1gb_oai22_12x.behV | |
1879 | // Auto generated verilog module by HnBCellAuto | |
1880 | // | |
1881 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1882 | // By: balmiki | |
1883 | // -------------------------------------------------- | |
1884 | // | |
1885 | module cl_u1gb_oai22_12x ( | |
1886 | out, | |
1887 | in10, | |
1888 | in11, | |
1889 | in00, | |
1890 | in01 ); | |
1891 | ||
1892 | output out; | |
1893 | input in10; | |
1894 | input in11; | |
1895 | input in00; | |
1896 | input in01; | |
1897 | ||
1898 | `ifdef LIB | |
1899 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1900 | `endif | |
1901 | ||
1902 | endmodule | |
1903 | // -------------------------------------------------- | |
1904 | // File: cl_u1gb_oai22_16x.behV | |
1905 | // Auto generated verilog module by HnBCellAuto | |
1906 | // | |
1907 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1908 | // By: balmiki | |
1909 | // -------------------------------------------------- | |
1910 | // | |
1911 | module cl_u1gb_oai22_16x ( | |
1912 | out, | |
1913 | in10, | |
1914 | in11, | |
1915 | in00, | |
1916 | in01 ); | |
1917 | ||
1918 | output out; | |
1919 | input in10; | |
1920 | input in11; | |
1921 | input in00; | |
1922 | input in01; | |
1923 | ||
1924 | `ifdef LIB | |
1925 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1926 | `endif | |
1927 | ||
1928 | endmodule | |
1929 | // -------------------------------------------------- | |
1930 | // File: cl_u1gb_oai22_1x.behV | |
1931 | // Auto generated verilog module by HnBCellAuto | |
1932 | // | |
1933 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1934 | // By: balmiki | |
1935 | // -------------------------------------------------- | |
1936 | // | |
1937 | module cl_u1gb_oai22_1x ( | |
1938 | out, | |
1939 | in10, | |
1940 | in11, | |
1941 | in00, | |
1942 | in01 ); | |
1943 | ||
1944 | output out; | |
1945 | input in10; | |
1946 | input in11; | |
1947 | input in00; | |
1948 | input in01; | |
1949 | ||
1950 | `ifdef LIB | |
1951 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1952 | `endif | |
1953 | ||
1954 | endmodule | |
1955 | // -------------------------------------------------- | |
1956 | // File: cl_u1gb_oai22_2x.behV | |
1957 | // Auto generated verilog module by HnBCellAuto | |
1958 | // | |
1959 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
1960 | // By: balmiki | |
1961 | // -------------------------------------------------- | |
1962 | // | |
1963 | module cl_u1gb_oai22_2x ( | |
1964 | out, | |
1965 | in10, | |
1966 | in11, | |
1967 | in00, | |
1968 | in01 ); | |
1969 | ||
1970 | output out; | |
1971 | input in10; | |
1972 | input in11; | |
1973 | input in00; | |
1974 | input in01; | |
1975 | ||
1976 | `ifdef LIB | |
1977 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1978 | `endif | |
1979 | ||
1980 | endmodule | |
1981 | // -------------------------------------------------- | |
1982 | // File: cl_u1gb_oai22_4x.behV | |
1983 | // Auto generated verilog module by HnBCellAuto | |
1984 | // | |
1985 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
1986 | // By: balmiki | |
1987 | // -------------------------------------------------- | |
1988 | // | |
1989 | module cl_u1gb_oai22_4x ( | |
1990 | out, | |
1991 | in10, | |
1992 | in11, | |
1993 | in00, | |
1994 | in01 ); | |
1995 | ||
1996 | output out; | |
1997 | input in10; | |
1998 | input in11; | |
1999 | input in00; | |
2000 | input in01; | |
2001 | ||
2002 | `ifdef LIB | |
2003 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
2004 | `endif | |
2005 | ||
2006 | endmodule | |
2007 | // -------------------------------------------------- | |
2008 | // File: cl_u1gb_oai22_8x.behV | |
2009 | // Auto generated verilog module by HnBCellAuto | |
2010 | // | |
2011 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
2012 | // By: balmiki | |
2013 | // -------------------------------------------------- | |
2014 | // | |
2015 | module cl_u1gb_oai22_8x ( | |
2016 | out, | |
2017 | in10, | |
2018 | in11, | |
2019 | in00, | |
2020 | in01 ); | |
2021 | ||
2022 | output out; | |
2023 | input in10; | |
2024 | input in11; | |
2025 | input in00; | |
2026 | input in01; | |
2027 | ||
2028 | `ifdef LIB | |
2029 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
2030 | `endif | |
2031 | ||
2032 | endmodule | |
2033 | module cl_u1gb_xnor2_16x ( | |
2034 | in0, | |
2035 | in1, | |
2036 | out | |
2037 | ); | |
2038 | input in0; | |
2039 | input in1; | |
2040 | output out; | |
2041 | ||
2042 | `ifdef LIB | |
2043 | assign out = ~(in0 ^ in1); | |
2044 | `endif | |
2045 | ||
2046 | endmodule | |
2047 | ||
2048 | module cl_u1gb_xnor2_1x ( | |
2049 | in0, | |
2050 | in1, | |
2051 | out | |
2052 | ); | |
2053 | input in0; | |
2054 | input in1; | |
2055 | output out; | |
2056 | ||
2057 | `ifdef LIB | |
2058 | assign out = ~(in0 ^ in1); | |
2059 | `endif | |
2060 | ||
2061 | endmodule | |
2062 | module cl_u1gb_xnor2_2x ( | |
2063 | in0, | |
2064 | in1, | |
2065 | out | |
2066 | ); | |
2067 | input in0; | |
2068 | input in1; | |
2069 | output out; | |
2070 | ||
2071 | `ifdef LIB | |
2072 | assign out = ~(in0 ^ in1); | |
2073 | `endif | |
2074 | ||
2075 | endmodule | |
2076 | module cl_u1gb_xnor2_4x ( | |
2077 | in0, | |
2078 | in1, | |
2079 | out | |
2080 | ); | |
2081 | input in0; | |
2082 | input in1; | |
2083 | output out; | |
2084 | ||
2085 | `ifdef LIB | |
2086 | assign out = ~(in0 ^ in1); | |
2087 | `endif | |
2088 | ||
2089 | endmodule | |
2090 | module cl_u1gb_xnor2_6x ( | |
2091 | in0, | |
2092 | in1, | |
2093 | out | |
2094 | ); | |
2095 | input in0; | |
2096 | input in1; | |
2097 | output out; | |
2098 | ||
2099 | `ifdef LIB | |
2100 | assign out = ~(in0 ^ in1); | |
2101 | `endif | |
2102 | ||
2103 | endmodule | |
2104 | module cl_u1gb_xnor2_8x ( | |
2105 | in0, | |
2106 | in1, | |
2107 | out | |
2108 | ); | |
2109 | input in0; | |
2110 | input in1; | |
2111 | output out; | |
2112 | ||
2113 | `ifdef LIB | |
2114 | assign out = ~(in0 ^ in1); | |
2115 | `endif | |
2116 | ||
2117 | endmodule | |
2118 | ||
2119 | module cl_u1gb_xnor3_16x ( | |
2120 | in0, | |
2121 | in1, | |
2122 | in2, | |
2123 | out | |
2124 | ); | |
2125 | input in0; | |
2126 | input in1; | |
2127 | input in2; | |
2128 | output out; | |
2129 | ||
2130 | `ifdef LIB | |
2131 | assign out = ~(in0 ^ in1 ^ in2); | |
2132 | `endif | |
2133 | ||
2134 | ||
2135 | ||
2136 | endmodule | |
2137 | module cl_u1gb_xnor3_1x ( | |
2138 | in0, | |
2139 | in1, | |
2140 | in2, | |
2141 | out | |
2142 | ); | |
2143 | input in0; | |
2144 | input in1; | |
2145 | input in2; | |
2146 | output out; | |
2147 | ||
2148 | `ifdef LIB | |
2149 | assign out = ~(in0 ^ in1 ^ in2); | |
2150 | `endif | |
2151 | ||
2152 | ||
2153 | ||
2154 | endmodule | |
2155 | module cl_u1gb_xnor3_2x ( | |
2156 | in0, | |
2157 | in1, | |
2158 | in2, | |
2159 | out | |
2160 | ); | |
2161 | input in0; | |
2162 | input in1; | |
2163 | input in2; | |
2164 | output out; | |
2165 | ||
2166 | `ifdef LIB | |
2167 | assign out = ~(in0 ^ in1 ^ in2); | |
2168 | `endif | |
2169 | ||
2170 | ||
2171 | ||
2172 | endmodule | |
2173 | module cl_u1gb_xnor3_4x ( | |
2174 | in0, | |
2175 | in1, | |
2176 | in2, | |
2177 | out | |
2178 | ); | |
2179 | input in0; | |
2180 | input in1; | |
2181 | input in2; | |
2182 | output out; | |
2183 | ||
2184 | `ifdef LIB | |
2185 | assign out = ~(in0 ^ in1 ^ in2); | |
2186 | `endif | |
2187 | ||
2188 | ||
2189 | ||
2190 | endmodule | |
2191 | module cl_u1gb_xnor3_6x ( | |
2192 | in0, | |
2193 | in1, | |
2194 | in2, | |
2195 | out | |
2196 | ); | |
2197 | input in0; | |
2198 | input in1; | |
2199 | input in2; | |
2200 | output out; | |
2201 | ||
2202 | `ifdef LIB | |
2203 | assign out = ~(in0 ^ in1 ^ in2); | |
2204 | `endif | |
2205 | ||
2206 | ||
2207 | ||
2208 | endmodule | |
2209 | module cl_u1gb_xnor3_8x ( | |
2210 | in0, | |
2211 | in1, | |
2212 | in2, | |
2213 | out | |
2214 | ); | |
2215 | input in0; | |
2216 | input in1; | |
2217 | input in2; | |
2218 | output out; | |
2219 | ||
2220 | `ifdef LIB | |
2221 | assign out = ~(in0 ^ in1 ^ in2); | |
2222 | `endif | |
2223 | ||
2224 | ||
2225 | ||
2226 | endmodule | |
2227 | module cl_u1gb_xor2_16x ( | |
2228 | in0, | |
2229 | in1, | |
2230 | out | |
2231 | ); | |
2232 | input in0; | |
2233 | input in1; | |
2234 | output out; | |
2235 | ||
2236 | `ifdef LIB | |
2237 | assign out = in0 ^ in1; | |
2238 | `endif | |
2239 | ||
2240 | endmodule | |
2241 | ||
2242 | module cl_u1gb_xor2_1x ( | |
2243 | in0, | |
2244 | in1, | |
2245 | out | |
2246 | ); | |
2247 | input in0; | |
2248 | input in1; | |
2249 | output out; | |
2250 | ||
2251 | `ifdef LIB | |
2252 | assign out = in0 ^ in1; | |
2253 | `endif | |
2254 | ||
2255 | endmodule | |
2256 | module cl_u1gb_xor2_2x ( | |
2257 | in0, | |
2258 | in1, | |
2259 | out | |
2260 | ); | |
2261 | input in0; | |
2262 | input in1; | |
2263 | output out; | |
2264 | ||
2265 | `ifdef LIB | |
2266 | assign out = in0 ^ in1; | |
2267 | `endif | |
2268 | ||
2269 | endmodule | |
2270 | module cl_u1gb_xor2_4x ( | |
2271 | in0, | |
2272 | in1, | |
2273 | out | |
2274 | ); | |
2275 | input in0; | |
2276 | input in1; | |
2277 | output out; | |
2278 | ||
2279 | `ifdef LIB | |
2280 | assign out = in0 ^ in1; | |
2281 | `endif | |
2282 | ||
2283 | endmodule | |
2284 | module cl_u1gb_xor2_6x ( | |
2285 | in0, | |
2286 | in1, | |
2287 | out | |
2288 | ); | |
2289 | input in0; | |
2290 | input in1; | |
2291 | output out; | |
2292 | ||
2293 | `ifdef LIB | |
2294 | assign out = in0 ^ in1; | |
2295 | `endif | |
2296 | ||
2297 | endmodule | |
2298 | module cl_u1gb_xor2_8x ( | |
2299 | in0, | |
2300 | in1, | |
2301 | out | |
2302 | ); | |
2303 | input in0; | |
2304 | input in1; | |
2305 | output out; | |
2306 | ||
2307 | `ifdef LIB | |
2308 | assign out = in0 ^ in1; | |
2309 | `endif | |
2310 | ||
2311 | endmodule | |
2312 | module cl_u1gb_xor3_16x ( | |
2313 | in0, | |
2314 | in1, | |
2315 | in2, | |
2316 | out | |
2317 | ); | |
2318 | input in0; | |
2319 | input in1; | |
2320 | input in2; | |
2321 | output out; | |
2322 | ||
2323 | `ifdef LIB | |
2324 | assign out = in0 ^ in1 ^ in2; | |
2325 | `endif | |
2326 | ||
2327 | ||
2328 | endmodule | |
2329 | ||
2330 | module cl_u1gb_xor3_1x ( | |
2331 | in0, | |
2332 | in1, | |
2333 | in2, | |
2334 | out | |
2335 | ); | |
2336 | input in0; | |
2337 | input in1; | |
2338 | input in2; | |
2339 | output out; | |
2340 | ||
2341 | `ifdef LIB | |
2342 | assign out = in0 ^ in1 ^ in2; | |
2343 | `endif | |
2344 | ||
2345 | ||
2346 | endmodule | |
2347 | module cl_u1gb_xor3_2x ( | |
2348 | in0, | |
2349 | in1, | |
2350 | in2, | |
2351 | out | |
2352 | ); | |
2353 | input in0; | |
2354 | input in1; | |
2355 | input in2; | |
2356 | output out; | |
2357 | ||
2358 | `ifdef LIB | |
2359 | assign out = in0 ^ in1 ^ in2; | |
2360 | `endif | |
2361 | ||
2362 | ||
2363 | endmodule | |
2364 | module cl_u1gb_xor3_4x ( | |
2365 | in0, | |
2366 | in1, | |
2367 | in2, | |
2368 | out | |
2369 | ); | |
2370 | input in0; | |
2371 | input in1; | |
2372 | input in2; | |
2373 | output out; | |
2374 | ||
2375 | `ifdef LIB | |
2376 | assign out = in0 ^ in1 ^ in2; | |
2377 | `endif | |
2378 | ||
2379 | ||
2380 | endmodule | |
2381 | module cl_u1gb_xor3_6x ( | |
2382 | in0, | |
2383 | in1, | |
2384 | in2, | |
2385 | out | |
2386 | ); | |
2387 | input in0; | |
2388 | input in1; | |
2389 | input in2; | |
2390 | output out; | |
2391 | ||
2392 | `ifdef LIB | |
2393 | assign out = in0 ^ in1 ^ in2; | |
2394 | `endif | |
2395 | ||
2396 | ||
2397 | endmodule | |
2398 | module cl_u1gb_xor3_8x ( | |
2399 | in0, | |
2400 | in1, | |
2401 | in2, | |
2402 | out | |
2403 | ); | |
2404 | input in0; | |
2405 | input in1; | |
2406 | input in2; | |
2407 | output out; | |
2408 | ||
2409 | `ifdef LIB | |
2410 | assign out = in0 ^ in1 ^ in2; | |
2411 | `endif | |
2412 | ||
2413 | ||
2414 | endmodule | |
2415 | ||
2416 | module cl_u1gb_rep_32x ( | |
2417 | in, | |
2418 | out | |
2419 | ); | |
2420 | input in; | |
2421 | output out; | |
2422 | ||
2423 | `ifdef LIB | |
2424 | //assign out = in; | |
2425 | buf (out, in); | |
2426 | `endif | |
2427 | ||
2428 | endmodule | |
2429 | module cl_u1gb_rep_40x ( | |
2430 | in, | |
2431 | out | |
2432 | ); | |
2433 | input in; | |
2434 | output out; | |
2435 | ||
2436 | `ifdef LIB | |
2437 | //assign out = in; | |
2438 | buf (out, in); | |
2439 | `endif | |
2440 | ||
2441 | endmodule | |
2442 | module cl_u1gb_rep_24x ( | |
2443 | in, | |
2444 | out | |
2445 | ); | |
2446 | input in; | |
2447 | output out; | |
2448 | ||
2449 | `ifdef LIB | |
2450 | //assign out = in; | |
2451 | buf (out, in); | |
2452 | `endif | |
2453 | ||
2454 | endmodule | |
2455 | module cl_u1gb_rep_16x ( | |
2456 | in, | |
2457 | out | |
2458 | ); | |
2459 | input in; | |
2460 | output out; | |
2461 | ||
2462 | `ifdef LIB | |
2463 | //assign out = in; | |
2464 | buf (out, in); | |
2465 | `endif | |
2466 | ||
2467 | endmodule | |
2468 | module cl_u1gb_rep_8x ( | |
2469 | in, | |
2470 | out | |
2471 | ); | |
2472 | input in; | |
2473 | output out; | |
2474 | ||
2475 | `ifdef LIB | |
2476 | //assign out = in; | |
2477 | buf (out, in); | |
2478 | `endif | |
2479 | ||
2480 | endmodule | |
2481 | module cl_u1gb_rep_48x ( | |
2482 | in, | |
2483 | out | |
2484 | ); | |
2485 | input in; | |
2486 | output out; | |
2487 | ||
2488 | `ifdef LIB | |
2489 | //assign out = in; | |
2490 | buf (out, in); | |
2491 | `endif | |
2492 | ||
2493 | endmodule | |
2494 | ||
2495 | ||
2496 |