projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: n2_com_cm_64x64_cust.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module n2_com_cm_64x64_cust ( | |
| 36 | row_hit, | |
| 37 | rd_data0, | |
| 38 | rd_data1, | |
| 39 | rd_data2, | |
| 40 | rd_data3, | |
| 41 | cam_en, | |
| 42 | force_hit, | |
| 43 | inv_mask0, | |
| 44 | inv_mask1, | |
| 45 | inv_mask2, | |
| 46 | inv_mask3, | |
| 47 | scan_in, | |
| 48 | scan_out, | |
| 49 | tcu_se_scancollar_in, | |
| 50 | l2clk, | |
| 51 | rd_en, | |
| 52 | rw_addr0, | |
| 53 | rw_addr1, | |
| 54 | rw_addr2, | |
| 55 | rw_addr3, | |
| 56 | rst_warm_0, | |
| 57 | rst_warm_1, | |
| 58 | wr_en, | |
| 59 | tcu_array_wr_inhibit, | |
| 60 | wr_data0, | |
| 61 | wr_data1, | |
| 62 | wr_data2, | |
| 63 | wr_data3, | |
| 64 | tcu_pce_ov, | |
| 65 | pce, | |
| 66 | tcu_aclk, | |
| 67 | tcu_bclk, | |
| 68 | tcu_scan_en, | |
| 69 | tcu_array_bypass); | |
| 70 | wire se; | |
| 71 | ||
| 72 | ||
| 73 | output [63:0] row_hit; | |
| 74 | ||
| 75 | output [15:0] rd_data0; // From panel0 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 76 | output [15:0] rd_data1; // From panel1 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 77 | output [15:0] rd_data2; // From panel2 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 78 | output [15:0] rd_data3; // From panel3 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 79 | ||
| 80 | input [3:0] cam_en; | |
| 81 | input [3:0] force_hit; | |
| 82 | ||
| 83 | input [7:0] inv_mask0; // To panel0 of dcm_panel.v | |
| 84 | input [7:0] inv_mask1; // To panel1 of dcm_panel.v | |
| 85 | input [7:0] inv_mask2; // To panel2 of dcm_panel.v | |
| 86 | input [7:0] inv_mask3; // To panel3 of dcm_panel.v | |
| 87 | ||
| 88 | input scan_in; | |
| 89 | output scan_out; | |
| 90 | input tcu_se_scancollar_in; | |
| 91 | ||
| 92 | input l2clk; // To panel0 of dcm_panel.v, ... | |
| 93 | ||
| 94 | input [3:0] rd_en ; // To panel0 of dcm_panel.v | |
| 95 | ||
| 96 | input [5:0] rw_addr0; // To panel0 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 97 | input [5:0] rw_addr1; // To panel1 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 98 | input [5:0] rw_addr2; // To panel2 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 99 | input [5:0] rw_addr3; // To panel3 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 100 | ||
| 101 | input rst_warm_0; | |
| 102 | input rst_warm_1; | |
| 103 | ||
| 104 | input [3:0] wr_en; // To panel0 of dcm_panel.v | |
| 105 | input tcu_array_wr_inhibit; // used to disable writes during SCAN. | |
| 106 | ||
| 107 | input [15:0] wr_data0; // To panel0 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 108 | input [15:0] wr_data1; // To panel1 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 109 | input [15:0] wr_data2; // To panel2 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 110 | input [15:0] wr_data3; // To panel3 of dcm_panel.v, BS and SR 11/18/03 Reverse Directory change | |
| 111 | ||
| 112 | input tcu_pce_ov; | |
| 113 | input pce; | |
| 114 | input tcu_aclk; | |
| 115 | input tcu_bclk; | |
| 116 | input tcu_scan_en; | |
| 117 | input tcu_array_bypass; // array bypass for DFT | |
| 118 | ||
| 119 | // JDL 05/17/07 | |
| 120 | // synopsys translate_off | |
| 121 | ||
| 122 | ||
| 123 | wire [63:0] lkup_hit0, lkup_hit1, lkup_hit2, lkup_hit3; | |
| 124 | wire [63:0] bank1_hit; | |
| 125 | wire [63:0] bank0_hit; | |
| 126 | ||
| 127 | ||
| 128 | ||
| 129 | // scan chain connections //// | |
| 130 | wire stop; | |
| 131 | wire [2:0] siclk; | |
| 132 | wire [2:0] soclk; | |
| 133 | //assign siclk[0] = tcu_aclk; | |
| 134 | //assign soclk[0] = tcu_bclk; | |
| 135 | //assign siclk[1] = tcu_aclk; | |
| 136 | //assign soclk[1] = tcu_bclk; | |
| 137 | //assign siclk[2] = tcu_aclk; | |
| 138 | //assign soclk[2] = tcu_bclk; | |
| 139 | wire pce_ov = tcu_pce_ov; | |
| 140 | assign stop = 1'b0; | |
| 141 | //assign pce_ov = tcu_pce_ov; | |
| 142 | ||
| 143 | //------------------------------------------------------------------------ | |
| 144 | // instantiate clock headers | |
| 145 | //------------------------------------------------------------------------ | |
| 146 | wire [1:0] collar_clk; | |
| 147 | wire in_clk; | |
| 148 | wire aclk = tcu_aclk; | |
| 149 | wire bclk = tcu_bclk; | |
| 150 | assign se = tcu_se_scancollar_in; // TEMP | |
| 151 | ||
| 152 | //0in fire -message "cam_en and wr_en active at the same time" -active (cam_en[0] & wr_en[0]) -group mbist_mode | |
| 153 | //0in fire -message "cam_en and wr_en active at the same time" -active (cam_en[1] & wr_en[1]) -group mbist_mode | |
| 154 | //0in fire -message "cam_en and wr_en active at the same time" -active (cam_en[2] & wr_en[2]) -group mbist_mode | |
| 155 | //0in fire -message "cam_en and wr_en active at the same time" -active (cam_en[3] & wr_en[3]) -group mbist_mode | |
| 156 | ||
| 157 | ||
| 158 | //0in fire -message "rd_en and wr_en active at the same time" -active (rd_en[3] & wr_en[3]) -group mbist_mode | |
| 159 | //0in fire -message "rd_en and wr_en active at the same time" -active (rd_en[2] & wr_en[2]) -group mbist_mode | |
| 160 | //0in fire -message "rd_en and wr_en active at the same time" -active (rd_en[1] & wr_en[1]) -group mbist_mode | |
| 161 | //0in fire -message "rd_en and wr_en active at the same time" -active (rd_en[0] & wr_en[0]) -group mbist_mode | |
| 162 | ||
| 163 | cl_dp1_l1hdr_8x clk_hdr_ctrl ( | |
| 164 | .l2clk(l2clk), | |
| 165 | .pce (pce), | |
| 166 | .l1clk(collar_clk[0]), | |
| 167 | .siclk_out(siclk[0]), | |
| 168 | .soclk_out(soclk[0]), | |
| 169 | .se(se), | |
| 170 | .pce_ov(pce_ov), | |
| 171 | .stop(stop), | |
| 172 | .aclk(aclk), | |
| 173 | .bclk(bclk) | |
| 174 | ); | |
| 175 | ||
| 176 | cl_dp1_l1hdr_8x clk_hdr_data ( | |
| 177 | .l2clk(l2clk), | |
| 178 | .pce (pce), | |
| 179 | .l1clk(collar_clk[1]), | |
| 180 | .siclk_out(siclk[1]), | |
| 181 | .soclk_out(soclk[1]), | |
| 182 | .se(se), | |
| 183 | .pce_ov(pce_ov), | |
| 184 | .stop(stop), | |
| 185 | .aclk(aclk), | |
| 186 | .bclk(bclk) | |
| 187 | ); | |
| 188 | ||
| 189 | cl_dp1_l1hdr_8x clk_hdr_inputs ( | |
| 190 | .l2clk(l2clk), | |
| 191 | .pce (pce), | |
| 192 | .l1clk(in_clk), | |
| 193 | .siclk_out(siclk[2]), | |
| 194 | .soclk_out(soclk[2]), | |
| 195 | .se(tcu_scan_en), | |
| 196 | .pce_ov(pce_ov), | |
| 197 | .stop(stop), | |
| 198 | .aclk(aclk), | |
| 199 | .bclk(bclk) | |
| 200 | ); | |
| 201 | ||
| 202 | //// Input Flops ///// | |
| 203 | ||
| 204 | wire [15:0] wr_data0_array,wr_data0_so; | |
| 205 | wire [15:0] wr_data1_array,wr_data1_so; | |
| 206 | wire [15:0] wr_data2_array,wr_data2_so; | |
| 207 | wire [15:0] wr_data3_array,wr_data3_so; | |
| 208 | wire nc; | |
| 209 | wire [3:0] wr_en_array,rd_en_array,cam_en_array; | |
| 210 | wire [3:0] cam_en_so,wr_en_so,rd_en_so; | |
| 211 | wire [7:0] inv_mask0_array,inv_mask0_so; | |
| 212 | wire [7:0] inv_mask1_array,inv_mask1_so; | |
| 213 | wire [7:0] inv_mask2_array,inv_mask2_so; | |
| 214 | wire [7:0] inv_mask3_array,inv_mask3_so; | |
| 215 | wire [1:0] rst_warm_0_array,rst_warm_0_so; | |
| 216 | wire [1:0] rst_warm_1_array,rst_warm_1_so; | |
| 217 | wire [5:0] rw_addr0_array,rw_addr0_so; | |
| 218 | wire [5:0] rw_addr1_array,rw_addr1_so; | |
| 219 | wire [5:0] rw_addr2_array,rw_addr2_so; | |
| 220 | wire [5:0] rw_addr3_array,rw_addr3_so; | |
| 221 | wire [3:0] force_hit_array,force_hit_so; | |
| 222 | wire [140:1] q, q_l; | |
| 223 | ||
| 224 | cl_sc1_msff_8x wr_data0_so_15 ( .si(scan_in), .so(wr_data0_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[15]), .q(wr_data0_array[15]) ); | |
| 225 | cl_sc1_msff_8x wr_data0_so_13 ( .si(wr_data0_so[15]), .so(wr_data0_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[13]), .q(wr_data0_array[13]) ); | |
| 226 | cl_sc1_msff_8x wr_data0_so_0 ( .si(wr_data0_so[13]), .so(wr_data0_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[0]), .q(wr_data0_array[0]) ); | |
| 227 | cl_sc1_msff_8x wr_data0_so_1 ( .si(wr_data0_so[0]), .so(wr_data0_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[1]), .q(wr_data0_array[1]) ); | |
| 228 | cl_sc1_msff_8x wr_data0_so_2 ( .si(wr_data0_so[1]), .so(wr_data0_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[2]), .q(wr_data0_array[2]) ); | |
| 229 | cl_sc1_msff_8x wr_data0_so_3 ( .si(wr_data0_so[2]), .so(wr_data0_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[3]), .q(wr_data0_array[3]) ); | |
| 230 | cl_sc1_msff_8x wr_data0_so_4 ( .si(wr_data0_so[3]), .so(wr_data0_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[4]), .q(wr_data0_array[4]) ); | |
| 231 | ||
| 232 | cl_mc1_scm_msff_lat_4x ff_cam_en_0 ( .si(wr_data0_so[4]), .so(cam_en_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(cam_en[0]), .latout(cam_en_array[0]), .q(q[1]), .q_l(q_l[1]) ); | |
| 233 | ||
| 234 | cl_sc1_msff_8x wr_data0_so_5 ( .si(cam_en_so[0]), .so(wr_data0_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[5]), .q(wr_data0_array[5]) ); | |
| 235 | cl_sc1_msff_8x wr_data0_so_6 ( .si(wr_data0_so[5]), .so(wr_data0_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[6]), .q(wr_data0_array[6]) ); | |
| 236 | cl_sc1_msff_8x wr_data0_so_7 ( .si(wr_data0_so[6]), .so(wr_data0_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[7]), .q(wr_data0_array[7]) ); | |
| 237 | cl_sc1_msff_8x wr_data0_so_8 ( .si(wr_data0_so[7]), .so(wr_data0_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[8]), .q(wr_data0_array[8]) ); | |
| 238 | cl_sc1_msff_8x wr_data0_so_9 ( .si(wr_data0_so[8]), .so(wr_data0_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[9]), .q(wr_data0_array[9]) ); | |
| 239 | cl_sc1_msff_8x wr_data0_so_10 ( .si(wr_data0_so[9]), .so(wr_data0_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[10]), .q(wr_data0_array[10]) ); | |
| 240 | cl_sc1_msff_8x wr_data0_so_11 ( .si(wr_data0_so[10]), .so(wr_data0_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[11]), .q(wr_data0_array[11]) ); | |
| 241 | cl_sc1_msff_8x wr_data0_so_12 ( .si(wr_data0_so[11]), .so(wr_data0_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[12]), .q(wr_data0_array[12]) ); | |
| 242 | cl_sc1_msff_8x wr_data0_so_14 ( .si(wr_data0_so[12]), .so(wr_data0_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data0[14]), .q(wr_data0_array[14]) ); | |
| 243 | ||
| 244 | cl_mc1_scm_msff_lat_4x ff_rd_en_0 ( .si(wr_data0_so[14]), .so(rd_en_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_en[0]), .latout(rd_en_array[0]), .q(q[2]), .q_l(q_l[2]) ); | |
| 245 | cl_mc1_scm_msff_lat_4x ff_wr_en_0 ( .si(rd_en_so[0]), .so(wr_en_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_en[0]), .latout(wr_en_array[0]), .q(q[3]), .q_l(q_l[3]) ); | |
| 246 | ||
| 247 | cl_mc1_scm_msff_lat_4x inv_mask0_so_0 ( .si(wr_en_so[0]), .so(inv_mask0_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[0]), .latout(inv_mask0_array[0]), .q(q[4]), .q_l(q_l[4]) ); | |
| 248 | cl_mc1_scm_msff_lat_4x inv_mask0_so_1 ( .si(inv_mask0_so[0]), .so(inv_mask0_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[1]), .latout(inv_mask0_array[1]), .q(q[5]), .q_l(q_l[5]) ); | |
| 249 | cl_mc1_scm_msff_lat_4x inv_mask0_so_2 ( .si(inv_mask0_so[1]), .so(inv_mask0_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[2]), .latout(inv_mask0_array[2]), .q(q[6]), .q_l(q_l[6]) ); | |
| 250 | cl_mc1_scm_msff_lat_4x inv_mask0_so_3 ( .si(inv_mask0_so[2]), .so(inv_mask0_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[3]), .latout(inv_mask0_array[3]), .q(q[7]), .q_l(q_l[7]) ); | |
| 251 | cl_mc1_scm_msff_lat_4x inv_mask0_so_4 ( .si(inv_mask0_so[3]), .so(inv_mask0_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[4]), .latout(inv_mask0_array[4]), .q(q[8]), .q_l(q_l[8]) ); | |
| 252 | cl_mc1_scm_msff_lat_4x inv_mask0_so_5 ( .si(inv_mask0_so[4]), .so(inv_mask0_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[5]), .latout(inv_mask0_array[5]), .q(q[9]), .q_l(q_l[9]) ); | |
| 253 | cl_mc1_scm_msff_lat_4x inv_mask0_so_6 ( .si(inv_mask0_so[5]), .so(inv_mask0_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[6]), .latout(inv_mask0_array[6]), .q(q[10]), .q_l(q_l[10]) ); | |
| 254 | cl_mc1_scm_msff_lat_4x inv_mask0_so_7 ( .si(inv_mask0_so[6]), .so(inv_mask0_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask0[7]), .latout(inv_mask0_array[7]), .q(q[11]), .q_l(q_l[11]) ); | |
| 255 | ||
| 256 | cl_mc1_scm_msff_lat_4x rw_addr0_so_0 ( .si(inv_mask0_so[7]), .so(rw_addr0_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr0[0]), .latout(rw_addr0_array[0]), .q(q[12]), .q_l(q_l[12]) ); | |
| 257 | cl_mc1_scm_msff_lat_4x rw_addr0_so_1 ( .si(rw_addr0_so[0]), .so(rw_addr0_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr0[1]), .latout(rw_addr0_array[1]), .q(q[13]), .q_l(q_l[13]) ); | |
| 258 | cl_mc1_scm_msff_lat_4x rw_addr0_so_2 ( .si(rw_addr0_so[1]), .so(rw_addr0_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr0[2]), .latout(rw_addr0_array[2]), .q(q[14]), .q_l(q_l[14]) ); | |
| 259 | cl_mc1_scm_msff_lat_4x rw_addr0_so_3 ( .si(rw_addr0_so[2]), .so(rw_addr0_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr0[3]), .latout(rw_addr0_array[3]), .q(q[15]), .q_l(q_l[15]) ); | |
| 260 | cl_mc1_scm_msff_lat_4x rw_addr0_so_4 ( .si(rw_addr0_so[3]), .so(rw_addr0_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr0[4]), .latout(rw_addr0_array[4]), .q(q[16]), .q_l(q_l[16]) ); | |
| 261 | cl_mc1_scm_msff_lat_4x rw_addr0_so_5 ( .si(rw_addr0_so[4]), .so(rw_addr0_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr0[5]), .latout(rw_addr0_array[5]), .q(q[17]), .q_l(q_l[17]) ); | |
| 262 | ||
| 263 | cl_mc1_scm_msff_lat_4x rst_warm0_0 ( .si(rw_addr0_so[5]), .so(rst_warm_0_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rst_warm_0), .latout(rst_warm_0_array[0]), .q(q[18]), .q_l(q_l[18]) ); | |
| 264 | cl_mc1_scm_msff_lat_4x ff_force_hit_0 ( .si(rst_warm_0_so[0]), .so(force_hit_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(force_hit[0]), .latout(force_hit_array[0]), .q(q[19]), .q_l(q_l[19]) ); | |
| 265 | ||
| 266 | ||
| 267 | cl_sc1_msff_8x wr_data1_so_15 ( .si(force_hit_so[0]), .so(wr_data1_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[15]), .q(wr_data1_array[15]) ); | |
| 268 | cl_sc1_msff_8x wr_data1_so_13 ( .si(wr_data1_so[15]), .so(wr_data1_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[13]), .q(wr_data1_array[13]) ); | |
| 269 | cl_sc1_msff_8x wr_data1_so_0 ( .si(wr_data1_so[13]), .so(wr_data1_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[0]), .q(wr_data1_array[0]) ); | |
| 270 | cl_sc1_msff_8x wr_data1_so_1 ( .si(wr_data1_so[0]), .so(wr_data1_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[1]), .q(wr_data1_array[1]) ); | |
| 271 | cl_sc1_msff_8x wr_data1_so_2 ( .si(wr_data1_so[1]), .so(wr_data1_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[2]), .q(wr_data1_array[2]) ); | |
| 272 | cl_sc1_msff_8x wr_data1_so_3 ( .si(wr_data1_so[2]), .so(wr_data1_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[3]), .q(wr_data1_array[3]) ); | |
| 273 | cl_sc1_msff_8x wr_data1_so_4 ( .si(wr_data1_so[3]), .so(wr_data1_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[4]), .q(wr_data1_array[4]) ); | |
| 274 | ||
| 275 | cl_mc1_scm_msff_lat_4x ff_cam_en_1 ( .si(wr_data1_so[4]), .so(cam_en_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(cam_en[1]), .latout(cam_en_array[1]), .q(q[20]), .q_l(q_l[20]) ); | |
| 276 | ||
| 277 | cl_sc1_msff_8x wr_data1_so_5 ( .si(cam_en_so[1]), .so(wr_data1_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[5]), .q(wr_data1_array[5]) ); | |
| 278 | cl_sc1_msff_8x wr_data1_so_6 ( .si(wr_data1_so[5]), .so(wr_data1_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[6]), .q(wr_data1_array[6]) ); | |
| 279 | cl_sc1_msff_8x wr_data1_so_7 ( .si(wr_data1_so[6]), .so(wr_data1_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[7]), .q(wr_data1_array[7]) ); | |
| 280 | cl_sc1_msff_8x wr_data1_so_8 ( .si(wr_data1_so[7]), .so(wr_data1_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[8]), .q(wr_data1_array[8]) ); | |
| 281 | cl_sc1_msff_8x wr_data1_so_9 ( .si(wr_data1_so[8]), .so(wr_data1_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[9]), .q(wr_data1_array[9]) ); | |
| 282 | cl_sc1_msff_8x wr_data1_so_10 ( .si(wr_data1_so[9]), .so(wr_data1_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[10]), .q(wr_data1_array[10]) ); | |
| 283 | cl_sc1_msff_8x wr_data1_so_11 ( .si(wr_data1_so[10]), .so(wr_data1_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[11]), .q(wr_data1_array[11]) ); | |
| 284 | cl_sc1_msff_8x wr_data1_so_12 ( .si(wr_data1_so[11]), .so(wr_data1_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[12]), .q(wr_data1_array[12]) ); | |
| 285 | cl_sc1_msff_8x wr_data1_so_14 ( .si(wr_data1_so[12]), .so(wr_data1_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data1[14]), .q(wr_data1_array[14]) ); | |
| 286 | ||
| 287 | cl_mc1_scm_msff_lat_4x ff_rd_en_1 ( .si(wr_data1_so[14]), .so(rd_en_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_en[1]), .latout(rd_en_array[1]), .q(q[21]), .q_l(q_l[21]) ); | |
| 288 | cl_mc1_scm_msff_lat_4x ff_wr_en_1 ( .si(rd_en_so[1]), .so(wr_en_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_en[1]), .latout(wr_en_array[1]), .q(q[22]), .q_l(q_l[22]) ); | |
| 289 | ||
| 290 | cl_mc1_scm_msff_lat_4x inv_mask1_so_0 ( .si(wr_en_so[1]), .so(inv_mask1_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[0]), .latout(inv_mask1_array[0]), .q(q[23]), .q_l(q_l[23]) ); | |
| 291 | cl_mc1_scm_msff_lat_4x inv_mask1_so_1 ( .si(inv_mask1_so[0]), .so(inv_mask1_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[1]), .latout(inv_mask1_array[1]), .q(q[24]), .q_l(q_l[24]) ); | |
| 292 | cl_mc1_scm_msff_lat_4x inv_mask1_so_2 ( .si(inv_mask1_so[1]), .so(inv_mask1_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[2]), .latout(inv_mask1_array[2]), .q(q[25]), .q_l(q_l[25]) ); | |
| 293 | cl_mc1_scm_msff_lat_4x inv_mask1_so_3 ( .si(inv_mask1_so[2]), .so(inv_mask1_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[3]), .latout(inv_mask1_array[3]), .q(q[26]), .q_l(q_l[26]) ); | |
| 294 | cl_mc1_scm_msff_lat_4x inv_mask1_so_4 ( .si(inv_mask1_so[3]), .so(inv_mask1_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[4]), .latout(inv_mask1_array[4]), .q(q[27]), .q_l(q_l[27]) ); | |
| 295 | cl_mc1_scm_msff_lat_4x inv_mask1_so_5 ( .si(inv_mask1_so[4]), .so(inv_mask1_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[5]), .latout(inv_mask1_array[5]), .q(q[28]), .q_l(q_l[28]) ); | |
| 296 | cl_mc1_scm_msff_lat_4x inv_mask1_so_6 ( .si(inv_mask1_so[5]), .so(inv_mask1_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[6]), .latout(inv_mask1_array[6]), .q(q[29]), .q_l(q_l[29]) ); | |
| 297 | cl_mc1_scm_msff_lat_4x inv_mask1_so_7 ( .si(inv_mask1_so[6]), .so(inv_mask1_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask1[7]), .latout(inv_mask1_array[7]), .q(q[30]), .q_l(q_l[30]) ); | |
| 298 | ||
| 299 | cl_mc1_scm_msff_lat_4x rw_addr1_so_0 ( .si(inv_mask1_so[7]), .so(rw_addr1_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr1[0]), .latout(rw_addr1_array[0]), .q(q[31]), .q_l(q_l[31]) ); | |
| 300 | cl_mc1_scm_msff_lat_4x rw_addr1_so_1 ( .si(rw_addr1_so[0]), .so(rw_addr1_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr1[1]), .latout(rw_addr1_array[1]), .q(q[32]), .q_l(q_l[32]) ); | |
| 301 | cl_mc1_scm_msff_lat_4x rw_addr1_so_2 ( .si(rw_addr1_so[1]), .so(rw_addr1_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr1[2]), .latout(rw_addr1_array[2]), .q(q[33]), .q_l(q_l[33]) ); | |
| 302 | cl_mc1_scm_msff_lat_4x rw_addr1_so_3 ( .si(rw_addr1_so[2]), .so(rw_addr1_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr1[3]), .latout(rw_addr1_array[3]), .q(q[34]), .q_l(q_l[34]) ); | |
| 303 | cl_mc1_scm_msff_lat_4x rw_addr1_so_4 ( .si(rw_addr1_so[3]), .so(rw_addr1_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr1[4]), .latout(rw_addr1_array[4]), .q(q[35]), .q_l(q_l[35]) ); | |
| 304 | cl_mc1_scm_msff_lat_4x rw_addr1_so_5 ( .si(rw_addr1_so[4]), .so(rw_addr1_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr1[5]), .latout(rw_addr1_array[5]), .q(q[36]), .q_l(q_l[36]) ); | |
| 305 | ||
| 306 | cl_mc1_scm_msff_lat_4x rst_warm0_1 ( .si(rw_addr1_so[5]), .so(rst_warm_0_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rst_warm_0), .latout(rst_warm_0_array[1]), .q(q[37]), .q_l(q_l[37]) ); | |
| 307 | cl_mc1_scm_msff_lat_4x ff_force_hit_1 ( .si(rst_warm_0_so[1]), .so(force_hit_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(force_hit[1]), .latout(force_hit_array[1]), .q(q[38]), .q_l(q_l[38]) ); | |
| 308 | ||
| 309 | ||
| 310 | cl_sc1_msff_8x wr_data2_so_15 ( .si(force_hit_so[1]), .so(wr_data2_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[15]), .q(wr_data2_array[15]) ); | |
| 311 | cl_sc1_msff_8x wr_data2_so_13 ( .si(wr_data2_so[15]), .so(wr_data2_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[13]), .q(wr_data2_array[13]) ); | |
| 312 | cl_sc1_msff_8x wr_data2_so_0 ( .si(wr_data2_so[13]), .so(wr_data2_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[0]), .q(wr_data2_array[0]) ); | |
| 313 | cl_sc1_msff_8x wr_data2_so_1 ( .si(wr_data2_so[0]), .so(wr_data2_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[1]), .q(wr_data2_array[1]) ); | |
| 314 | cl_sc1_msff_8x wr_data2_so_2 ( .si(wr_data2_so[1]), .so(wr_data2_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[2]), .q(wr_data2_array[2]) ); | |
| 315 | cl_sc1_msff_8x wr_data2_so_3 ( .si(wr_data2_so[2]), .so(wr_data2_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[3]), .q(wr_data2_array[3]) ); | |
| 316 | cl_sc1_msff_8x wr_data2_so_4 ( .si(wr_data2_so[3]), .so(wr_data2_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[4]), .q(wr_data2_array[4]) ); | |
| 317 | ||
| 318 | cl_mc1_scm_msff_lat_4x ff_cam_en_2 ( .si(wr_data2_so[4]), .so(cam_en_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(cam_en[2]), .latout(cam_en_array[2]), .q(q[39]), .q_l(q_l[39]) ); | |
| 319 | ||
| 320 | cl_sc1_msff_8x wr_data2_so_5 ( .si(cam_en_so[2]), .so(wr_data2_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[5]), .q(wr_data2_array[5]) ); | |
| 321 | cl_sc1_msff_8x wr_data2_so_6 ( .si(wr_data2_so[5]), .so(wr_data2_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[6]), .q(wr_data2_array[6]) ); | |
| 322 | cl_sc1_msff_8x wr_data2_so_7 ( .si(wr_data2_so[6]), .so(wr_data2_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[7]), .q(wr_data2_array[7]) ); | |
| 323 | cl_sc1_msff_8x wr_data2_so_8 ( .si(wr_data2_so[7]), .so(wr_data2_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[8]), .q(wr_data2_array[8]) ); | |
| 324 | cl_sc1_msff_8x wr_data2_so_9 ( .si(wr_data2_so[8]), .so(wr_data2_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[9]), .q(wr_data2_array[9]) ); | |
| 325 | cl_sc1_msff_8x wr_data2_so_10 ( .si(wr_data2_so[9]), .so(wr_data2_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[10]), .q(wr_data2_array[10]) ); | |
| 326 | cl_sc1_msff_8x wr_data2_so_11 ( .si(wr_data2_so[10]), .so(wr_data2_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[11]), .q(wr_data2_array[11]) ); | |
| 327 | cl_sc1_msff_8x wr_data2_so_12 ( .si(wr_data2_so[11]), .so(wr_data2_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[12]), .q(wr_data2_array[12]) ); | |
| 328 | cl_sc1_msff_8x wr_data2_so_14 ( .si(wr_data2_so[12]), .so(wr_data2_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data2[14]), .q(wr_data2_array[14]) ); | |
| 329 | ||
| 330 | cl_mc1_scm_msff_lat_4x ff_rd_en_2 ( .si(wr_data2_so[14]), .so(rd_en_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_en[2]), .latout(rd_en_array[2]), .q(q[40]), .q_l(q_l[40]) ); | |
| 331 | cl_mc1_scm_msff_lat_4x ff_wr_en_2 ( .si(rd_en_so[2]), .so(wr_en_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_en[2]), .latout(wr_en_array[2]), .q(q[41]), .q_l(q_l[41]) ); | |
| 332 | ||
| 333 | cl_mc1_scm_msff_lat_4x inv_mask2_so_0 ( .si(wr_en_so[2]), .so(inv_mask2_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[0]), .latout(inv_mask2_array[0]), .q(q[42]), .q_l(q_l[42]) ); | |
| 334 | cl_mc1_scm_msff_lat_4x inv_mask2_so_1 ( .si(inv_mask2_so[0]), .so(inv_mask2_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[1]), .latout(inv_mask2_array[1]), .q(q[43]), .q_l(q_l[43]) ); | |
| 335 | cl_mc1_scm_msff_lat_4x inv_mask2_so_2 ( .si(inv_mask2_so[1]), .so(inv_mask2_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[2]), .latout(inv_mask2_array[2]), .q(q[44]), .q_l(q_l[44]) ); | |
| 336 | cl_mc1_scm_msff_lat_4x inv_mask2_so_3 ( .si(inv_mask2_so[2]), .so(inv_mask2_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[3]), .latout(inv_mask2_array[3]), .q(q[45]), .q_l(q_l[45]) ); | |
| 337 | cl_mc1_scm_msff_lat_4x inv_mask2_so_4 ( .si(inv_mask2_so[3]), .so(inv_mask2_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[4]), .latout(inv_mask2_array[4]), .q(q[46]), .q_l(q_l[46]) ); | |
| 338 | cl_mc1_scm_msff_lat_4x inv_mask2_so_5 ( .si(inv_mask2_so[4]), .so(inv_mask2_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[5]), .latout(inv_mask2_array[5]), .q(q[47]), .q_l(q_l[47]) ); | |
| 339 | cl_mc1_scm_msff_lat_4x inv_mask2_so_6 ( .si(inv_mask2_so[5]), .so(inv_mask2_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[6]), .latout(inv_mask2_array[6]), .q(q[48]), .q_l(q_l[48]) ); | |
| 340 | cl_mc1_scm_msff_lat_4x inv_mask2_so_7 ( .si(inv_mask2_so[6]), .so(inv_mask2_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask2[7]), .latout(inv_mask2_array[7]), .q(q[49]), .q_l(q_l[49]) ); | |
| 341 | ||
| 342 | cl_mc1_scm_msff_lat_4x rw_addr2_so_0 ( .si(inv_mask2_so[7]), .so(rw_addr2_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr2[0]), .latout(rw_addr2_array[0]), .q(q[50]), .q_l(q_l[50]) ); | |
| 343 | cl_mc1_scm_msff_lat_4x rw_addr2_so_1 ( .si(rw_addr2_so[0]), .so(rw_addr2_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr2[1]), .latout(rw_addr2_array[1]), .q(q[51]), .q_l(q_l[51]) ); | |
| 344 | cl_mc1_scm_msff_lat_4x rw_addr2_so_2 ( .si(rw_addr2_so[1]), .so(rw_addr2_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr2[2]), .latout(rw_addr2_array[2]), .q(q[52]), .q_l(q_l[52]) ); | |
| 345 | cl_mc1_scm_msff_lat_4x rw_addr2_so_3 ( .si(rw_addr2_so[2]), .so(rw_addr2_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr2[3]), .latout(rw_addr2_array[3]), .q(q[53]), .q_l(q_l[53]) ); | |
| 346 | cl_mc1_scm_msff_lat_4x rw_addr2_so_4 ( .si(rw_addr2_so[3]), .so(rw_addr2_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr2[4]), .latout(rw_addr2_array[4]), .q(q[54]), .q_l(q_l[54]) ); | |
| 347 | cl_mc1_scm_msff_lat_4x rw_addr2_so_5 ( .si(rw_addr2_so[4]), .so(rw_addr2_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr2[5]), .latout(rw_addr2_array[5]), .q(q[55]), .q_l(q_l[55]) ); | |
| 348 | ||
| 349 | cl_mc1_scm_msff_lat_4x rst_warm1_0 ( .si(rw_addr2_so[5]), .so(rst_warm_1_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rst_warm_1), .latout(rst_warm_1_array[0]), .q(q[56]), .q_l(q_l[56]) ); | |
| 350 | cl_mc1_scm_msff_lat_4x ff_force_hit_2 ( .si(rst_warm_1_so[0]), .so(force_hit_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(force_hit[2]), .latout(force_hit_array[2]), .q(q[57]), .q_l(q_l[57]) ); | |
| 351 | ||
| 352 | ||
| 353 | cl_sc1_msff_8x wr_data3_so_15 ( .si(force_hit_so[2]), .so(wr_data3_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[15]), .q(wr_data3_array[15]) ); | |
| 354 | cl_sc1_msff_8x wr_data3_so_13 ( .si(wr_data3_so[15]), .so(wr_data3_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[13]), .q(wr_data3_array[13]) ); | |
| 355 | cl_sc1_msff_8x wr_data3_so_0 ( .si(wr_data3_so[13]), .so(wr_data3_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[0]), .q(wr_data3_array[0]) ); | |
| 356 | cl_sc1_msff_8x wr_data3_so_1 ( .si(wr_data3_so[0]), .so(wr_data3_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[1]), .q(wr_data3_array[1]) ); | |
| 357 | cl_sc1_msff_8x wr_data3_so_2 ( .si(wr_data3_so[1]), .so(wr_data3_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[2]), .q(wr_data3_array[2]) ); | |
| 358 | cl_sc1_msff_8x wr_data3_so_3 ( .si(wr_data3_so[2]), .so(wr_data3_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[3]), .q(wr_data3_array[3]) ); | |
| 359 | cl_sc1_msff_8x wr_data3_so_4 ( .si(wr_data3_so[3]), .so(wr_data3_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[4]), .q(wr_data3_array[4]) ); | |
| 360 | ||
| 361 | cl_mc1_scm_msff_lat_4x ff_cam_en_3 ( .si(wr_data3_so[4]), .so(cam_en_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(cam_en[3]), .latout(cam_en_array[3]), .q(q[58]), .q_l(q_l[58]) ); | |
| 362 | ||
| 363 | cl_sc1_msff_8x wr_data3_so_5 ( .si(cam_en_so[3]), .so(wr_data3_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[5]), .q(wr_data3_array[5]) ); | |
| 364 | cl_sc1_msff_8x wr_data3_so_6 ( .si(wr_data3_so[5]), .so(wr_data3_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[6]), .q(wr_data3_array[6]) ); | |
| 365 | cl_sc1_msff_8x wr_data3_so_7 ( .si(wr_data3_so[6]), .so(wr_data3_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[7]), .q(wr_data3_array[7]) ); | |
| 366 | cl_sc1_msff_8x wr_data3_so_8 ( .si(wr_data3_so[7]), .so(wr_data3_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[8]), .q(wr_data3_array[8]) ); | |
| 367 | cl_sc1_msff_8x wr_data3_so_9 ( .si(wr_data3_so[8]), .so(wr_data3_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[9]), .q(wr_data3_array[9]) ); | |
| 368 | cl_sc1_msff_8x wr_data3_so_10 ( .si(wr_data3_so[9]), .so(wr_data3_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[10]), .q(wr_data3_array[10]) ); | |
| 369 | cl_sc1_msff_8x wr_data3_so_11 ( .si(wr_data3_so[10]), .so(wr_data3_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[11]), .q(wr_data3_array[11]) ); | |
| 370 | cl_sc1_msff_8x wr_data3_so_12 ( .si(wr_data3_so[11]), .so(wr_data3_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[12]), .q(wr_data3_array[12]) ); | |
| 371 | cl_sc1_msff_8x wr_data3_so_14 ( .si(wr_data3_so[12]), .so(wr_data3_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(wr_data3[14]), .q(wr_data3_array[14]) ); | |
| 372 | ||
| 373 | cl_mc1_scm_msff_lat_4x ff_rd_en_3 ( .si(wr_data3_so[14]), .so(rd_en_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_en[3]), .latout(rd_en_array[3]), .q(q[59]), .q_l(q_l[59]) ); | |
| 374 | cl_mc1_scm_msff_lat_4x ff_wr_en_3 ( .si(rd_en_so[3]), .so(wr_en_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_en[3]), .latout(wr_en_array[3]), .q(q[60]), .q_l(q_l[60]) ); | |
| 375 | ||
| 376 | cl_mc1_scm_msff_lat_4x inv_mask3_so_0 ( .si(wr_en_so[3]), .so(inv_mask3_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[0]), .latout(inv_mask3_array[0]), .q(q[61]), .q_l(q_l[61]) ); | |
| 377 | cl_mc1_scm_msff_lat_4x inv_mask3_so_1 ( .si(inv_mask3_so[0]), .so(inv_mask3_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[1]), .latout(inv_mask3_array[1]), .q(q[62]), .q_l(q_l[62]) ); | |
| 378 | cl_mc1_scm_msff_lat_4x inv_mask3_so_2 ( .si(inv_mask3_so[1]), .so(inv_mask3_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[2]), .latout(inv_mask3_array[2]), .q(q[63]), .q_l(q_l[63]) ); | |
| 379 | cl_mc1_scm_msff_lat_4x inv_mask3_so_3 ( .si(inv_mask3_so[2]), .so(inv_mask3_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[3]), .latout(inv_mask3_array[3]), .q(q[64]), .q_l(q_l[64]) ); | |
| 380 | cl_mc1_scm_msff_lat_4x inv_mask3_so_4 ( .si(inv_mask3_so[3]), .so(inv_mask3_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[4]), .latout(inv_mask3_array[4]), .q(q[65]), .q_l(q_l[65]) ); | |
| 381 | cl_mc1_scm_msff_lat_4x inv_mask3_so_5 ( .si(inv_mask3_so[4]), .so(inv_mask3_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[5]), .latout(inv_mask3_array[5]), .q(q[66]), .q_l(q_l[66]) ); | |
| 382 | cl_mc1_scm_msff_lat_4x inv_mask3_so_6 ( .si(inv_mask3_so[5]), .so(inv_mask3_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[6]), .latout(inv_mask3_array[6]), .q(q[67]), .q_l(q_l[67]) ); | |
| 383 | cl_mc1_scm_msff_lat_4x inv_mask3_so_7 ( .si(inv_mask3_so[6]), .so(inv_mask3_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(inv_mask3[7]), .latout(inv_mask3_array[7]), .q(q[68]), .q_l(q_l[68]) ); | |
| 384 | ||
| 385 | cl_mc1_scm_msff_lat_4x rw_addr3_so_0 ( .si(inv_mask3_so[7]), .so(rw_addr3_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr3[0]), .latout(rw_addr3_array[0]), .q(q[69]), .q_l(q_l[69]) ); | |
| 386 | cl_mc1_scm_msff_lat_4x rw_addr3_so_1 ( .si(rw_addr3_so[0]), .so(rw_addr3_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr3[1]), .latout(rw_addr3_array[1]), .q(q[70]), .q_l(q_l[70]) ); | |
| 387 | cl_mc1_scm_msff_lat_4x rw_addr3_so_2 ( .si(rw_addr3_so[1]), .so(rw_addr3_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr3[2]), .latout(rw_addr3_array[2]), .q(q[71]), .q_l(q_l[71]) ); | |
| 388 | cl_mc1_scm_msff_lat_4x rw_addr3_so_3 ( .si(rw_addr3_so[2]), .so(rw_addr3_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr3[3]), .latout(rw_addr3_array[3]), .q(q[72]), .q_l(q_l[72]) ); | |
| 389 | cl_mc1_scm_msff_lat_4x rw_addr3_so_4 ( .si(rw_addr3_so[3]), .so(rw_addr3_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr3[4]), .latout(rw_addr3_array[4]), .q(q[73]), .q_l(q_l[73]) ); | |
| 390 | cl_mc1_scm_msff_lat_4x rw_addr3_so_5 ( .si(rw_addr3_so[4]), .so(rw_addr3_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rw_addr3[5]), .latout(rw_addr3_array[5]), .q(q[74]), .q_l(q_l[74]) ); | |
| 391 | ||
| 392 | cl_mc1_scm_msff_lat_4x rst_warm1_1 ( .si(rw_addr3_so[5]), .so(rst_warm_1_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rst_warm_1), .latout(rst_warm_1_array[1]), .q(q[75]), .q_l(q_l[75]) ); | |
| 393 | cl_mc1_scm_msff_lat_4x ff_force_hit_3 ( .si(rst_warm_1_so[1]), .so(force_hit_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(force_hit[3]), .latout(force_hit_array[3]), .q(q[76]), .q_l(q_l[76]) ); | |
| 394 | ||
| 395 | assign scan_out = force_hit_so[3]; | |
| 396 | ||
| 397 | dcm_panel_cust panel0( | |
| 398 | // Outputs | |
| 399 | .lkup_hit (lkup_hit0[63:0]), | |
| 400 | .rd_data (rd_data0[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 401 | // Inputs | |
| 402 | .tcu_aclk (1'b0), | |
| 403 | .tcu_bclk (1'b0), | |
| 404 | .tcu_pce_ov (tcu_pce_ov), | |
| 405 | .pce (pce), | |
| 406 | .tcu_array_bypass (tcu_array_bypass), | |
| 407 | .rd_en (rd_en_array[0]), | |
| 408 | .wr_en (wr_en_array[0]), | |
| 409 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
| 410 | .force_hit (force_hit_array[0]), | |
| 411 | .cam_en (cam_en_array[0]), | |
| 412 | .wr_data (wr_data0_array[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 413 | .rw_addr (rw_addr0_array[5:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 414 | .inv_mask (inv_mask0_array[7:0]), | |
| 415 | .l2clk (in_clk), | |
| 416 | .rst_warm (rst_warm_0_array[0]), | |
| 417 | .tcu_se_scancollar_in (tcu_se_scancollar_in)); | |
| 418 | ||
| 419 | assign bank0_hit = lkup_hit0 | lkup_hit1 ; | |
| 420 | ||
| 421 | dcm_panel_cust panel1( | |
| 422 | // Outputs | |
| 423 | .lkup_hit (lkup_hit1[63:0]), | |
| 424 | .rd_data (rd_data1[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 425 | // Inputs | |
| 426 | .tcu_aclk (1'b0), | |
| 427 | .tcu_bclk (1'b0), | |
| 428 | .tcu_pce_ov (tcu_pce_ov), | |
| 429 | .pce (pce), | |
| 430 | .tcu_array_bypass (tcu_array_bypass), | |
| 431 | .rd_en (rd_en_array[1]), | |
| 432 | .wr_en (wr_en_array[1]), | |
| 433 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
| 434 | .force_hit (force_hit_array[1]), | |
| 435 | .cam_en (cam_en_array[1]), | |
| 436 | .wr_data (wr_data1_array[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 437 | .rw_addr (rw_addr1_array[5:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 438 | .inv_mask (inv_mask1_array[7:0]), | |
| 439 | .l2clk (in_clk), | |
| 440 | .rst_warm (rst_warm_0_array[1]), | |
| 441 | .tcu_se_scancollar_in (tcu_se_scancollar_in)); | |
| 442 | ||
| 443 | ||
| 444 | assign row_hit = bank1_hit | bank0_hit ; | |
| 445 | ||
| 446 | ||
| 447 | dcm_panel_cust panel2( | |
| 448 | // Outputs | |
| 449 | .lkup_hit (lkup_hit2[63:0]), | |
| 450 | .rd_data (rd_data2[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 451 | // Inputs | |
| 452 | .tcu_aclk (1'b0), | |
| 453 | .tcu_bclk (1'b0), | |
| 454 | .tcu_pce_ov (tcu_pce_ov), | |
| 455 | .pce (pce), | |
| 456 | .tcu_array_bypass (tcu_array_bypass), | |
| 457 | .rd_en (rd_en_array[2]), | |
| 458 | .wr_en (wr_en_array[2]), | |
| 459 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
| 460 | .force_hit (force_hit_array[2]), | |
| 461 | .cam_en (cam_en_array[2]), | |
| 462 | .wr_data (wr_data2_array[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 463 | .rw_addr (rw_addr2_array[5:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 464 | .inv_mask (inv_mask2_array[7:0]), | |
| 465 | .l2clk (in_clk), | |
| 466 | .rst_warm (rst_warm_1_array[0]), | |
| 467 | .tcu_se_scancollar_in(tcu_se_scancollar_in)); | |
| 468 | ||
| 469 | assign bank1_hit = lkup_hit2 | lkup_hit3 ; | |
| 470 | ||
| 471 | dcm_panel_cust panel3( | |
| 472 | // Outputs | |
| 473 | .lkup_hit (lkup_hit3[63:0]), | |
| 474 | .rd_data (rd_data3[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 475 | // Inputs | |
| 476 | .tcu_aclk (1'b0), | |
| 477 | .tcu_bclk (1'b0), | |
| 478 | .tcu_pce_ov (tcu_pce_ov), | |
| 479 | .pce (pce), | |
| 480 | .tcu_array_bypass (tcu_array_bypass), | |
| 481 | .rd_en (rd_en_array[3]), | |
| 482 | .wr_en (wr_en_array[3]), | |
| 483 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), | |
| 484 | .force_hit (force_hit_array[3]), | |
| 485 | .cam_en (cam_en_array[3]), | |
| 486 | .wr_data (wr_data3_array[15:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 487 | .rw_addr (rw_addr3_array[5:0]), // BS and SR 11/18/03 Reverse Directory change | |
| 488 | .inv_mask (inv_mask3_array[7:0]), | |
| 489 | .l2clk (in_clk), | |
| 490 | .rst_warm (rst_warm_1_array[1]), | |
| 491 | .tcu_se_scancollar_in (tcu_se_scancollar_in)); | |
| 492 | ||
| 493 | // synopsys translate_on | |
| 494 | ||
| 495 | endmodule | |
| 496 | ||
| 497 | ||
| 498 | //////////////////////////////////////////////////////////////////////// | |
| 499 | // Local header file includes / local defines | |
| 500 | // A directory panel is 32 bits wide and 64 entries deep. | |
| 501 | // The lkup_hit combines the match lines for an even and odd entry pair | |
| 502 | // and hence is only 32 bits wide. | |
| 503 | //////////////////////////////////////////////////////////////////////// | |
| 504 | ||
| 505 | module dcm_panel_cust ( | |
| 506 | rd_en, | |
| 507 | wr_en, | |
| 508 | tcu_array_wr_inhibit, | |
| 509 | cam_en, | |
| 510 | force_hit, | |
| 511 | wr_data, | |
| 512 | rw_addr, | |
| 513 | inv_mask, | |
| 514 | l2clk, | |
| 515 | rst_warm, | |
| 516 | tcu_se_scancollar_in, | |
| 517 | tcu_pce_ov, | |
| 518 | pce, | |
| 519 | tcu_aclk, | |
| 520 | tcu_bclk, | |
| 521 | tcu_array_bypass, | |
| 522 | lkup_hit, | |
| 523 | rd_data); | |
| 524 | wire ff_valid_scanin; | |
| 525 | wire tcu_se_scancollar_in_unused; | |
| 526 | wire tcu_pce_ov_unused; | |
| 527 | wire pce_unused; | |
| 528 | wire ff_valid_scanout_unused; | |
| 529 | ||
| 530 | ||
| 531 | ||
| 532 | wire tcu_array_bypass_n; | |
| 533 | wire [62:0] ff_valid__so; | |
| 534 | ||
| 535 | ||
| 536 | // Read inputs | |
| 537 | input rd_en; | |
| 538 | input wr_en; | |
| 539 | input tcu_array_wr_inhibit; | |
| 540 | input cam_en; | |
| 541 | input force_hit; | |
| 542 | ||
| 543 | input [15:0] wr_data; // { parity, valid, addr<4>,addr<17:9>, L2 way[3:0]} , BS and SR 11/18/03 Reverse Directory change | |
| 544 | ||
| 545 | // shared inputs | |
| 546 | input [5:0] rw_addr; // BS and SR 11/18/03 Reverse Directory change | |
| 547 | input [7:0] inv_mask; | |
| 548 | ||
| 549 | input l2clk; | |
| 550 | input rst_warm; | |
| 551 | input tcu_se_scancollar_in; | |
| 552 | input tcu_pce_ov; | |
| 553 | input pce; | |
| 554 | input tcu_aclk; | |
| 555 | input tcu_bclk; | |
| 556 | input tcu_array_bypass; // array bypass for DFT | |
| 557 | ||
| 558 | output [63:0] lkup_hit; | |
| 559 | output [15:0] rd_data; // { valid,parity, addr<17:9>, L2 way<3:0> } , BS and SR 11/18/03 Reverse Directory change | |
| 560 | ||
| 561 | wire [63:0] inval_mask_d; | |
| 562 | wire [31:0] inval_mask_d1; | |
| 563 | wire [15:0] rd_data_array; | |
| 564 | wire [63:0] lkup_hit_array; | |
| 565 | wire [63:0] valid_bit; | |
| 566 | wire [63:0] valid; | |
| 567 | wire [140:1] mq_l, q, q_l; | |
| 568 | ||
| 569 | assign ff_valid_scanin = 1'b0; | |
| 570 | ||
| 571 | assign tcu_se_scancollar_in_unused = tcu_se_scancollar_in; | |
| 572 | assign tcu_pce_ov_unused = tcu_pce_ov; | |
| 573 | assign pce_unused = pce; | |
| 574 | ||
| 575 | cl_mc1_scm_msff_lat_4x ff_valid_0 ( .si(ff_valid_scanin), .so(ff_valid__so[0]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[0]), .latout(valid_bit[0]), .q(q[77]), .q_l(q_l[77]) ); | |
| 576 | cl_mc1_scm_msff_lat_4x ff_valid_1 ( .si(ff_valid__so[0]), .so(ff_valid__so[1]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[1]), .latout(valid_bit[1]), .q(q[78]), .q_l(q_l[78]) ); | |
| 577 | cl_mc1_scm_msff_lat_4x ff_valid_2 ( .si(ff_valid__so[1]), .so(ff_valid__so[2]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[2]), .latout(valid_bit[2]), .q(q[79]), .q_l(q_l[79]) ); | |
| 578 | cl_mc1_scm_msff_lat_4x ff_valid_3 ( .si(ff_valid__so[2]), .so(ff_valid__so[3]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[3]), .latout(valid_bit[3]), .q(q[80]), .q_l(q_l[80]) ); | |
| 579 | cl_mc1_scm_msff_lat_4x ff_valid_4 ( .si(ff_valid__so[3]), .so(ff_valid__so[4]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[4]), .latout(valid_bit[4]), .q(q[81]), .q_l(q_l[81]) ); | |
| 580 | cl_mc1_scm_msff_lat_4x ff_valid_5 ( .si(ff_valid__so[4]), .so(ff_valid__so[5]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[5]), .latout(valid_bit[5]), .q(q[82]), .q_l(q_l[82]) ); | |
| 581 | cl_mc1_scm_msff_lat_4x ff_valid_6 ( .si(ff_valid__so[5]), .so(ff_valid__so[6]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[6]), .latout(valid_bit[6]), .q(q[83]), .q_l(q_l[83]) ); | |
| 582 | cl_mc1_scm_msff_lat_4x ff_valid_7 ( .si(ff_valid__so[6]), .so(ff_valid__so[7]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[7]), .latout(valid_bit[7]), .q(q[84]), .q_l(q_l[84]) ); | |
| 583 | cl_mc1_scm_msff_lat_4x ff_valid_8 ( .si(ff_valid__so[7]), .so(ff_valid__so[8]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[8]), .latout(valid_bit[8]), .q(q[85]), .q_l(q_l[85]) ); | |
| 584 | cl_mc1_scm_msff_lat_4x ff_valid_9 ( .si(ff_valid__so[8]), .so(ff_valid__so[9]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[9]), .latout(valid_bit[9]), .q(q[86]), .q_l(q_l[86]) ); | |
| 585 | cl_mc1_scm_msff_lat_4x ff_valid_10 ( .si(ff_valid__so[9]), .so(ff_valid__so[10]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[10]), .latout(valid_bit[10]), .q(q[87]), .q_l(q_l[87]) ); | |
| 586 | cl_mc1_scm_msff_lat_4x ff_valid_11 ( .si(ff_valid__so[10]), .so(ff_valid__so[11]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[11]), .latout(valid_bit[11]), .q(q[88]), .q_l(q_l[88]) ); | |
| 587 | cl_mc1_scm_msff_lat_4x ff_valid_12 ( .si(ff_valid__so[11]), .so(ff_valid__so[12]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[12]), .latout(valid_bit[12]), .q(q[89]), .q_l(q_l[89]) ); | |
| 588 | cl_mc1_scm_msff_lat_4x ff_valid_13 ( .si(ff_valid__so[12]), .so(ff_valid__so[13]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[13]), .latout(valid_bit[13]), .q(q[90]), .q_l(q_l[90]) ); | |
| 589 | cl_mc1_scm_msff_lat_4x ff_valid_14 ( .si(ff_valid__so[13]), .so(ff_valid__so[14]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[14]), .latout(valid_bit[14]), .q(q[91]), .q_l(q_l[91]) ); | |
| 590 | cl_mc1_scm_msff_lat_4x ff_valid_15 ( .si(ff_valid__so[14]), .so(ff_valid__so[15]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[15]), .latout(valid_bit[15]), .q(q[92]), .q_l(q_l[92]) ); | |
| 591 | cl_mc1_scm_msff_lat_4x ff_valid_16 ( .si(ff_valid__so[15]), .so(ff_valid__so[16]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[16]), .latout(valid_bit[16]), .q(q[93]), .q_l(q_l[93]) ); | |
| 592 | cl_mc1_scm_msff_lat_4x ff_valid_17 ( .si(ff_valid__so[16]), .so(ff_valid__so[17]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[17]), .latout(valid_bit[17]), .q(q[94]), .q_l(q_l[94]) ); | |
| 593 | cl_mc1_scm_msff_lat_4x ff_valid_18 ( .si(ff_valid__so[17]), .so(ff_valid__so[18]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[18]), .latout(valid_bit[18]), .q(q[95]), .q_l(q_l[95]) ); | |
| 594 | cl_mc1_scm_msff_lat_4x ff_valid_19 ( .si(ff_valid__so[18]), .so(ff_valid__so[19]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[19]), .latout(valid_bit[19]), .q(q[96]), .q_l(q_l[96]) ); | |
| 595 | cl_mc1_scm_msff_lat_4x ff_valid_20 ( .si(ff_valid__so[19]), .so(ff_valid__so[20]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[20]), .latout(valid_bit[20]), .q(q[97]), .q_l(q_l[97]) ); | |
| 596 | cl_mc1_scm_msff_lat_4x ff_valid_21 ( .si(ff_valid__so[20]), .so(ff_valid__so[21]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[21]), .latout(valid_bit[21]), .q(q[98]), .q_l(q_l[98]) ); | |
| 597 | cl_mc1_scm_msff_lat_4x ff_valid_22 ( .si(ff_valid__so[21]), .so(ff_valid__so[22]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[22]), .latout(valid_bit[22]), .q(q[99]), .q_l(q_l[99]) ); | |
| 598 | cl_mc1_scm_msff_lat_4x ff_valid_23 ( .si(ff_valid__so[22]), .so(ff_valid__so[23]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[23]), .latout(valid_bit[23]), .q(q[100]), .q_l(q_l[100]) ); | |
| 599 | cl_mc1_scm_msff_lat_4x ff_valid_24 ( .si(ff_valid__so[23]), .so(ff_valid__so[24]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[24]), .latout(valid_bit[24]), .q(q[101]), .q_l(q_l[101]) ); | |
| 600 | cl_mc1_scm_msff_lat_4x ff_valid_25 ( .si(ff_valid__so[24]), .so(ff_valid__so[25]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[25]), .latout(valid_bit[25]), .q(q[102]), .q_l(q_l[102]) ); | |
| 601 | cl_mc1_scm_msff_lat_4x ff_valid_26 ( .si(ff_valid__so[25]), .so(ff_valid__so[26]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[26]), .latout(valid_bit[26]), .q(q[103]), .q_l(q_l[103]) ); | |
| 602 | cl_mc1_scm_msff_lat_4x ff_valid_27 ( .si(ff_valid__so[26]), .so(ff_valid__so[27]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[27]), .latout(valid_bit[27]), .q(q[104]), .q_l(q_l[104]) ); | |
| 603 | cl_mc1_scm_msff_lat_4x ff_valid_28 ( .si(ff_valid__so[27]), .so(ff_valid__so[28]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[28]), .latout(valid_bit[28]), .q(q[105]), .q_l(q_l[105]) ); | |
| 604 | cl_mc1_scm_msff_lat_4x ff_valid_29 ( .si(ff_valid__so[28]), .so(ff_valid__so[29]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[29]), .latout(valid_bit[29]), .q(q[106]), .q_l(q_l[106]) ); | |
| 605 | cl_mc1_scm_msff_lat_4x ff_valid_30 ( .si(ff_valid__so[29]), .so(ff_valid__so[30]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[30]), .latout(valid_bit[30]), .q(q[107]), .q_l(q_l[107]) ); | |
| 606 | cl_mc1_scm_msff_lat_4x ff_valid_31 ( .si(ff_valid__so[30]), .so(ff_valid__so[31]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[31]), .latout(valid_bit[31]), .q(q[108]), .q_l(q_l[108]) ); | |
| 607 | cl_mc1_scm_msff_lat_4x ff_valid_32 ( .si(ff_valid__so[31]), .so(ff_valid__so[32]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[32]), .latout(valid_bit[32]), .q(q[109]), .q_l(q_l[109]) ); | |
| 608 | cl_mc1_scm_msff_lat_4x ff_valid_33 ( .si(ff_valid__so[32]), .so(ff_valid__so[33]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[33]), .latout(valid_bit[33]), .q(q[110]), .q_l(q_l[110]) ); | |
| 609 | cl_mc1_scm_msff_lat_4x ff_valid_34 ( .si(ff_valid__so[33]), .so(ff_valid__so[34]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[34]), .latout(valid_bit[34]), .q(q[111]), .q_l(q_l[111]) ); | |
| 610 | cl_mc1_scm_msff_lat_4x ff_valid_35 ( .si(ff_valid__so[34]), .so(ff_valid__so[35]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[35]), .latout(valid_bit[35]), .q(q[112]), .q_l(q_l[112]) ); | |
| 611 | cl_mc1_scm_msff_lat_4x ff_valid_36 ( .si(ff_valid__so[35]), .so(ff_valid__so[36]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[36]), .latout(valid_bit[36]), .q(q[113]), .q_l(q_l[113]) ); | |
| 612 | cl_mc1_scm_msff_lat_4x ff_valid_37 ( .si(ff_valid__so[36]), .so(ff_valid__so[37]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[37]), .latout(valid_bit[37]), .q(q[114]), .q_l(q_l[114]) ); | |
| 613 | cl_mc1_scm_msff_lat_4x ff_valid_38 ( .si(ff_valid__so[37]), .so(ff_valid__so[38]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[38]), .latout(valid_bit[38]), .q(q[115]), .q_l(q_l[115]) ); | |
| 614 | cl_mc1_scm_msff_lat_4x ff_valid_39 ( .si(ff_valid__so[38]), .so(ff_valid__so[39]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[39]), .latout(valid_bit[39]), .q(q[116]), .q_l(q_l[116]) ); | |
| 615 | cl_mc1_scm_msff_lat_4x ff_valid_40 ( .si(ff_valid__so[39]), .so(ff_valid__so[40]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[40]), .latout(valid_bit[40]), .q(q[117]), .q_l(q_l[117]) ); | |
| 616 | cl_mc1_scm_msff_lat_4x ff_valid_41 ( .si(ff_valid__so[40]), .so(ff_valid__so[41]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[41]), .latout(valid_bit[41]), .q(q[118]), .q_l(q_l[118]) ); | |
| 617 | cl_mc1_scm_msff_lat_4x ff_valid_42 ( .si(ff_valid__so[41]), .so(ff_valid__so[42]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[42]), .latout(valid_bit[42]), .q(q[119]), .q_l(q_l[119]) ); | |
| 618 | cl_mc1_scm_msff_lat_4x ff_valid_43 ( .si(ff_valid__so[42]), .so(ff_valid__so[43]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[43]), .latout(valid_bit[43]), .q(q[120]), .q_l(q_l[120]) ); | |
| 619 | cl_mc1_scm_msff_lat_4x ff_valid_44 ( .si(ff_valid__so[43]), .so(ff_valid__so[44]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[44]), .latout(valid_bit[44]), .q(q[121]), .q_l(q_l[121]) ); | |
| 620 | cl_mc1_scm_msff_lat_4x ff_valid_45 ( .si(ff_valid__so[44]), .so(ff_valid__so[45]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[45]), .latout(valid_bit[45]), .q(q[122]), .q_l(q_l[122]) ); | |
| 621 | cl_mc1_scm_msff_lat_4x ff_valid_46 ( .si(ff_valid__so[45]), .so(ff_valid__so[46]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[46]), .latout(valid_bit[46]), .q(q[123]), .q_l(q_l[123]) ); | |
| 622 | cl_mc1_scm_msff_lat_4x ff_valid_47 ( .si(ff_valid__so[46]), .so(ff_valid__so[47]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[47]), .latout(valid_bit[47]), .q(q[124]), .q_l(q_l[124]) ); | |
| 623 | cl_mc1_scm_msff_lat_4x ff_valid_48 ( .si(ff_valid__so[47]), .so(ff_valid__so[48]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[48]), .latout(valid_bit[48]), .q(q[125]), .q_l(q_l[125]) ); | |
| 624 | cl_mc1_scm_msff_lat_4x ff_valid_49 ( .si(ff_valid__so[48]), .so(ff_valid__so[49]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[49]), .latout(valid_bit[49]), .q(q[126]), .q_l(q_l[126]) ); | |
| 625 | cl_mc1_scm_msff_lat_4x ff_valid_50 ( .si(ff_valid__so[49]), .so(ff_valid__so[50]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[50]), .latout(valid_bit[50]), .q(q[127]), .q_l(q_l[127]) ); | |
| 626 | cl_mc1_scm_msff_lat_4x ff_valid_51 ( .si(ff_valid__so[50]), .so(ff_valid__so[51]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[51]), .latout(valid_bit[51]), .q(q[128]), .q_l(q_l[128]) ); | |
| 627 | cl_mc1_scm_msff_lat_4x ff_valid_52 ( .si(ff_valid__so[51]), .so(ff_valid__so[52]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[52]), .latout(valid_bit[52]), .q(q[129]), .q_l(q_l[129]) ); | |
| 628 | cl_mc1_scm_msff_lat_4x ff_valid_53 ( .si(ff_valid__so[52]), .so(ff_valid__so[53]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[53]), .latout(valid_bit[53]), .q(q[130]), .q_l(q_l[130]) ); | |
| 629 | cl_mc1_scm_msff_lat_4x ff_valid_54 ( .si(ff_valid__so[53]), .so(ff_valid__so[54]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[54]), .latout(valid_bit[54]), .q(q[131]), .q_l(q_l[131]) ); | |
| 630 | cl_mc1_scm_msff_lat_4x ff_valid_55 ( .si(ff_valid__so[54]), .so(ff_valid__so[55]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[55]), .latout(valid_bit[55]), .q(q[132]), .q_l(q_l[132]) ); | |
| 631 | cl_mc1_scm_msff_lat_4x ff_valid_56 ( .si(ff_valid__so[55]), .so(ff_valid__so[56]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[56]), .latout(valid_bit[56]), .q(q[133]), .q_l(q_l[133]) ); | |
| 632 | cl_mc1_scm_msff_lat_4x ff_valid_57 ( .si(ff_valid__so[56]), .so(ff_valid__so[57]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[57]), .latout(valid_bit[57]), .q(q[134]), .q_l(q_l[134]) ); | |
| 633 | cl_mc1_scm_msff_lat_4x ff_valid_58 ( .si(ff_valid__so[57]), .so(ff_valid__so[58]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[58]), .latout(valid_bit[58]), .q(q[135]), .q_l(q_l[135]) ); | |
| 634 | cl_mc1_scm_msff_lat_4x ff_valid_59 ( .si(ff_valid__so[58]), .so(ff_valid__so[59]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[59]), .latout(valid_bit[59]), .q(q[136]), .q_l(q_l[136]) ); | |
| 635 | cl_mc1_scm_msff_lat_4x ff_valid_60 ( .si(ff_valid__so[59]), .so(ff_valid__so[60]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[60]), .latout(valid_bit[60]), .q(q[137]), .q_l(q_l[137]) ); | |
| 636 | cl_mc1_scm_msff_lat_4x ff_valid_61 ( .si(ff_valid__so[60]), .so(ff_valid__so[61]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[61]), .latout(valid_bit[61]), .q(q[138]), .q_l(q_l[138]) ); | |
| 637 | cl_mc1_scm_msff_lat_4x ff_valid_62 ( .si(ff_valid__so[61]), .so(ff_valid__so[62]), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[62]), .latout(valid_bit[62]), .q(q[139]), .q_l(q_l[139]) ); | |
| 638 | cl_mc1_scm_msff_lat_4x ff_valid_63 ( .si(ff_valid__so[62]), .so(ff_valid_scanout_unused), .l1clk(l2clk), .siclk(tcu_aclk), .soclk(tcu_bclk), .d(valid[63]), .latout(valid_bit[63]), .q(q[140]), .q_l(q_l[140]) ); | |
| 639 | ||
| 640 | ||
| 641 | // Inval mask is generated on a per cpu basis. | |
| 642 | ||
| 643 | assign inval_mask_d1[3:0] = {4{inv_mask[0]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 644 | assign inval_mask_d1[7:4] = {4{inv_mask[1]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 645 | assign inval_mask_d1[11:8] = {4{inv_mask[2]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 646 | assign inval_mask_d1[15:12] = {4{inv_mask[3]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 647 | assign inval_mask_d1[19:16] = {4{inv_mask[4]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 648 | assign inval_mask_d1[23:20] = {4{inv_mask[5]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 649 | assign inval_mask_d1[27:24] = {4{inv_mask[6]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 650 | assign inval_mask_d1[31:28] = {4{inv_mask[7]}} ; // BS and SR 11/18/03 Reverse Directory change | |
| 651 | ||
| 652 | assign inval_mask_d[63:0] = {inval_mask_d1,inval_mask_d1}; | |
| 653 | ||
| 654 | ||
| 655 | // MEM Array // | |
| 656 | ||
| 657 | ||
| 658 | dc_panel_array array ( | |
| 659 | .l2clk(l2clk), | |
| 660 | // .rst_l(rst_l), | |
| 661 | .wr_en(wr_en), | |
| 662 | .rd_en(rd_en), | |
| 663 | .cam_en(cam_en), | |
| 664 | .rw_addr(rw_addr[5:0]), | |
| 665 | .wr_data(wr_data[15:0]), | |
| 666 | .rst_warm(rst_warm), | |
| 667 | .force_hit(force_hit), | |
| 668 | .write_disable(tcu_array_wr_inhibit), | |
| 669 | .inval_mask(inval_mask_d[63:0]), | |
| 670 | .valid_bit(valid_bit[63:0]), | |
| 671 | .lkup_hit(lkup_hit[63:0]), | |
| 672 | .rd_data(rd_data[15:0]), | |
| 673 | .valid(valid[63:0]), | |
| 674 | .bypass(tcu_array_bypass) | |
| 675 | ); | |
| 676 | ||
| 677 | endmodule | |
| 678 | ||
| 679 | ||
| 680 | ||
| 681 | // | |
| 682 | // ADDRESS BIT 4 as REGISTER ARRAY | |
| 683 | /// | |
| 684 | ||
| 685 | ||
| 686 | module dc_panel_array ( | |
| 687 | l2clk, | |
| 688 | wr_en, | |
| 689 | rd_en, | |
| 690 | cam_en, | |
| 691 | rst_warm, | |
| 692 | write_disable, | |
| 693 | force_hit, | |
| 694 | rw_addr, | |
| 695 | inval_mask, | |
| 696 | wr_data, | |
| 697 | valid_bit, | |
| 698 | bypass, | |
| 699 | valid, | |
| 700 | rd_data, | |
| 701 | lkup_hit); | |
| 702 | wire [12:0] addr_array_0; | |
| 703 | wire [12:0] addr_array_1; | |
| 704 | wire [12:0] addr_array_2; | |
| 705 | wire [12:0] addr_array_3; | |
| 706 | wire [12:0] addr_array_4; | |
| 707 | wire [12:0] addr_array_5; | |
| 708 | wire [12:0] addr_array_6; | |
| 709 | wire [12:0] addr_array_7; | |
| 710 | wire [12:0] addr_array_8; | |
| 711 | wire [12:0] addr_array_9; | |
| 712 | wire [12:0] addr_array_10; | |
| 713 | wire [12:0] addr_array_11; | |
| 714 | wire [12:0] addr_array_12; | |
| 715 | wire [12:0] addr_array_13; | |
| 716 | wire [12:0] addr_array_14; | |
| 717 | wire [12:0] addr_array_15; | |
| 718 | wire [12:0] addr_array_16; | |
| 719 | wire [12:0] addr_array_17; | |
| 720 | wire [12:0] addr_array_18; | |
| 721 | wire [12:0] addr_array_19; | |
| 722 | wire [12:0] addr_array_20; | |
| 723 | wire [12:0] addr_array_21; | |
| 724 | wire [12:0] addr_array_22; | |
| 725 | wire [12:0] addr_array_23; | |
| 726 | wire [12:0] addr_array_24; | |
| 727 | wire [12:0] addr_array_25; | |
| 728 | wire [12:0] addr_array_26; | |
| 729 | wire [12:0] addr_array_27; | |
| 730 | wire [12:0] addr_array_28; | |
| 731 | wire [12:0] addr_array_29; | |
| 732 | wire [12:0] addr_array_30; | |
| 733 | wire [12:0] addr_array_31; | |
| 734 | wire [12:0] addr_array_32; | |
| 735 | wire [12:0] addr_array_33; | |
| 736 | wire [12:0] addr_array_34; | |
| 737 | wire [12:0] addr_array_35; | |
| 738 | wire [12:0] addr_array_36; | |
| 739 | wire [12:0] addr_array_37; | |
| 740 | wire [12:0] addr_array_38; | |
| 741 | wire [12:0] addr_array_39; | |
| 742 | wire [12:0] addr_array_40; | |
| 743 | wire [12:0] addr_array_41; | |
| 744 | wire [12:0] addr_array_42; | |
| 745 | wire [12:0] addr_array_43; | |
| 746 | wire [12:0] addr_array_44; | |
| 747 | wire [12:0] addr_array_45; | |
| 748 | wire [12:0] addr_array_46; | |
| 749 | wire [12:0] addr_array_47; | |
| 750 | wire [12:0] addr_array_48; | |
| 751 | wire [12:0] addr_array_49; | |
| 752 | wire [12:0] addr_array_50; | |
| 753 | wire [12:0] addr_array_51; | |
| 754 | wire [12:0] addr_array_52; | |
| 755 | wire [12:0] addr_array_53; | |
| 756 | wire [12:0] addr_array_54; | |
| 757 | wire [12:0] addr_array_55; | |
| 758 | wire [12:0] addr_array_56; | |
| 759 | wire [12:0] addr_array_57; | |
| 760 | wire [12:0] addr_array_58; | |
| 761 | wire [12:0] addr_array_59; | |
| 762 | wire [12:0] addr_array_60; | |
| 763 | wire [12:0] addr_array_61; | |
| 764 | wire [12:0] addr_array_62; | |
| 765 | wire [12:0] addr_array_63; | |
| 766 | ||
| 767 | input l2clk; | |
| 768 | input wr_en; | |
| 769 | input rd_en; | |
| 770 | input cam_en; | |
| 771 | input rst_warm; | |
| 772 | input write_disable; | |
| 773 | input force_hit; | |
| 774 | input [5:0] rw_addr; | |
| 775 | input [63:0] inval_mask; | |
| 776 | input [15:0] wr_data; | |
| 777 | input [63:0] valid_bit; | |
| 778 | input bypass; | |
| 779 | output [63:0] valid; | |
| 780 | output [15:0] rd_data; | |
| 781 | output [63:0] lkup_hit; | |
| 782 | ||
| 783 | ||
| 784 | // | |
| 785 | // Registers and wires | |
| 786 | // | |
| 787 | ||
| 788 | integer i,j; | |
| 789 | ||
| 790 | reg [12:0] addr_array[63:0] ; // BS and SR 11/18/03 Reverse Directory change | |
| 791 | reg [63:0] addr_bit4; // Restructuring directories | |
| 792 | reg [63:0] valid ; | |
| 793 | reg [63:0] parity ; | |
| 794 | reg [15:0] rd_data; // BS and SR 11/18/03 Reverse Directory change | |
| 795 | reg [63:0] lkup_hit; | |
| 796 | reg [63:0] cam_hit; | |
| 797 | reg [63:0] cam_hit0; | |
| 798 | reg [63:0] cam_hit1; | |
| 799 | reg [63:0] new_valid; | |
| 800 | ||
| 801 | `ifndef NOINITMEM | |
| 802 | /////////////////////////////////////// | |
| 803 | // Initialize the cam/arrays. // | |
| 804 | /////////////////////////////////////// | |
| 805 | integer n; | |
| 806 | initial begin | |
| 807 | for (n = 0; n < 64; n = n + 1) begin | |
| 808 | addr_array[n] = {13{1'b0}}; | |
| 809 | addr_bit4[n] = 1'b0; | |
| 810 | valid[n] = 1'b0; | |
| 811 | parity[n] = 1'b0; | |
| 812 | end | |
| 813 | end | |
| 814 | `endif | |
| 815 | ||
| 816 | assign addr_array_0 = addr_array[0]; | |
| 817 | assign addr_array_1 = addr_array[1]; | |
| 818 | assign addr_array_2 = addr_array[2]; | |
| 819 | assign addr_array_3 = addr_array[3]; | |
| 820 | assign addr_array_4 = addr_array[4]; | |
| 821 | assign addr_array_5 = addr_array[5]; | |
| 822 | assign addr_array_6 = addr_array[6]; | |
| 823 | assign addr_array_7 = addr_array[7]; | |
| 824 | assign addr_array_8 = addr_array[8]; | |
| 825 | assign addr_array_9 = addr_array[9]; | |
| 826 | assign addr_array_10 = addr_array[10]; | |
| 827 | assign addr_array_11 = addr_array[11]; | |
| 828 | assign addr_array_12 = addr_array[12]; | |
| 829 | assign addr_array_13 = addr_array[13]; | |
| 830 | assign addr_array_14 = addr_array[14]; | |
| 831 | assign addr_array_15 = addr_array[15]; | |
| 832 | assign addr_array_16 = addr_array[16]; | |
| 833 | assign addr_array_17 = addr_array[17]; | |
| 834 | assign addr_array_18 = addr_array[18]; | |
| 835 | assign addr_array_19 = addr_array[19]; | |
| 836 | assign addr_array_20 = addr_array[20]; | |
| 837 | assign addr_array_21 = addr_array[21]; | |
| 838 | assign addr_array_22 = addr_array[22]; | |
| 839 | assign addr_array_23 = addr_array[23]; | |
| 840 | assign addr_array_24 = addr_array[24]; | |
| 841 | assign addr_array_25 = addr_array[25]; | |
| 842 | assign addr_array_26 = addr_array[26]; | |
| 843 | assign addr_array_27 = addr_array[27]; | |
| 844 | assign addr_array_28 = addr_array[28]; | |
| 845 | assign addr_array_29 = addr_array[29]; | |
| 846 | assign addr_array_30 = addr_array[30]; | |
| 847 | assign addr_array_31 = addr_array[31]; | |
| 848 | ||
| 849 | assign addr_array_32 = addr_array[32]; | |
| 850 | assign addr_array_33 = addr_array[33]; | |
| 851 | assign addr_array_34 = addr_array[34]; | |
| 852 | assign addr_array_35 = addr_array[35]; | |
| 853 | assign addr_array_36 = addr_array[36]; | |
| 854 | assign addr_array_37 = addr_array[37]; | |
| 855 | assign addr_array_38 = addr_array[38]; | |
| 856 | assign addr_array_39 = addr_array[39]; | |
| 857 | assign addr_array_40 = addr_array[40]; | |
| 858 | assign addr_array_41 = addr_array[41]; | |
| 859 | assign addr_array_42 = addr_array[42]; | |
| 860 | assign addr_array_43 = addr_array[43]; | |
| 861 | assign addr_array_44 = addr_array[44]; | |
| 862 | assign addr_array_45 = addr_array[45]; | |
| 863 | assign addr_array_46 = addr_array[46]; | |
| 864 | assign addr_array_47 = addr_array[47]; | |
| 865 | assign addr_array_48 = addr_array[48]; | |
| 866 | assign addr_array_49 = addr_array[49]; | |
| 867 | assign addr_array_50 = addr_array[50]; | |
| 868 | assign addr_array_51 = addr_array[51]; | |
| 869 | assign addr_array_52 = addr_array[52]; | |
| 870 | assign addr_array_53 = addr_array[53]; | |
| 871 | assign addr_array_54 = addr_array[54]; | |
| 872 | assign addr_array_55 = addr_array[55]; | |
| 873 | assign addr_array_56 = addr_array[56]; | |
| 874 | assign addr_array_57 = addr_array[57]; | |
| 875 | assign addr_array_58 = addr_array[58]; | |
| 876 | assign addr_array_59 = addr_array[59]; | |
| 877 | assign addr_array_60 = addr_array[60]; | |
| 878 | assign addr_array_61 = addr_array[61]; | |
| 879 | assign addr_array_62 = addr_array[62]; | |
| 880 | assign addr_array_63 = addr_array[63]; | |
| 881 | ||
| 882 | ||
| 883 | // CAM OPERATION | |
| 884 | // PH 1 CAM | |
| 885 | ||
| 886 | always @( cam_en or inval_mask or wr_data or valid_bit or force_hit or addr_bit4 | |
| 887 | or l2clk or bypass or write_disable or rst_warm or | |
| 888 | addr_array_0 or addr_array_1 or addr_array_2 or addr_array_3 or addr_array_4 or | |
| 889 | addr_array_5 or addr_array_6 or addr_array_7 or addr_array_8 or addr_array_9 or | |
| 890 | addr_array_10 or addr_array_11 or addr_array_12 or addr_array_13 or addr_array_14 or | |
| 891 | addr_array_15 or addr_array_16 or addr_array_17 or addr_array_18 or addr_array_19 or | |
| 892 | addr_array_20 or addr_array_21 or addr_array_22 or addr_array_23 or addr_array_24 or | |
| 893 | addr_array_25 or addr_array_26 or addr_array_27 or addr_array_28 or addr_array_29 or | |
| 894 | addr_array_30 or addr_array_31 or addr_array_32 or addr_array_33 or addr_array_34 or | |
| 895 | addr_array_35 or addr_array_36 or addr_array_37 or addr_array_38 or addr_array_39 or | |
| 896 | addr_array_40 or addr_array_41 or addr_array_42 or addr_array_43 or addr_array_44 or | |
| 897 | addr_array_45 or addr_array_46 or addr_array_47 or addr_array_48 or addr_array_49 or | |
| 898 | addr_array_50 or addr_array_51 or addr_array_52 or addr_array_53 or addr_array_54 or | |
| 899 | addr_array_55 or addr_array_56 or addr_array_57 or addr_array_58 or addr_array_59 or | |
| 900 | addr_array_60 or addr_array_61 or addr_array_62 or addr_array_63 ) | |
| 901 | ||
| 902 | begin | |
| 903 | // CAM | |
| 904 | ||
| 905 | if (bypass) | |
| 906 | begin | |
| 907 | lkup_hit <= 64'b0; // RACE FIX | |
| 908 | end | |
| 909 | else if(l2clk & rst_warm) | |
| 910 | begin | |
| 911 | lkup_hit <= 64'b0; // RAACE FIX | |
| 912 | end | |
| 913 | ||
| 914 | else | |
| 915 | if(l2clk & cam_en & ~write_disable) | |
| 916 | begin | |
| 917 | ||
| 918 | ||
| 919 | ||
| 920 | cam_hit0[0] = ( wr_data[12:0] == addr_array_0[12:0] ); | |
| 921 | cam_hit1[0] = (( wr_data[13] == addr_bit4[0] ) | force_hit); | |
| 922 | cam_hit[0] = (cam_hit0[0] & cam_hit1[0]) & valid_bit[0]; | |
| 923 | new_valid[0] = valid_bit[0] & ~( cam_hit[0] & inval_mask[0]); | |
| 924 | ||
| 925 | ||
| 926 | cam_hit0[1] = ( wr_data[12:0] == addr_array_1[12:0] ); | |
| 927 | cam_hit1[1] = (( wr_data[13] == addr_bit4[1] ) | force_hit); | |
| 928 | cam_hit[1] = (cam_hit0[1] & cam_hit1[1]) & valid_bit[1]; | |
| 929 | new_valid[1] = valid_bit[1] & ~( cam_hit[1] & inval_mask[1]); | |
| 930 | ||
| 931 | ||
| 932 | cam_hit0[2] = ( wr_data[12:0] == addr_array_2[12:0] ); | |
| 933 | cam_hit1[2] = (( wr_data[13] == addr_bit4[2] ) | force_hit); | |
| 934 | cam_hit[2] = (cam_hit0[2] & cam_hit1[2]) & valid_bit[2]; | |
| 935 | new_valid[2] = valid_bit[2] & ~( cam_hit[2] & inval_mask[2]); | |
| 936 | ||
| 937 | ||
| 938 | cam_hit0[3] = ( wr_data[12:0] == addr_array_3[12:0] ); | |
| 939 | cam_hit1[3] = (( wr_data[13] == addr_bit4[3] ) | force_hit); | |
| 940 | cam_hit[3] = (cam_hit0[3] & cam_hit1[3]) & valid_bit[3]; | |
| 941 | new_valid[3] = valid_bit[3] & ~( cam_hit[3] & inval_mask[3]); | |
| 942 | ||
| 943 | ||
| 944 | cam_hit0[4] = ( wr_data[12:0] == addr_array_4[12:0] ); | |
| 945 | cam_hit1[4] = (( wr_data[13] == addr_bit4[4] ) | force_hit); | |
| 946 | cam_hit[4] = (cam_hit0[4] & cam_hit1[4]) & valid_bit[4]; | |
| 947 | new_valid[4] = valid_bit[4] & ~( cam_hit[4] & inval_mask[4]); | |
| 948 | ||
| 949 | ||
| 950 | cam_hit0[5] = ( wr_data[12:0] == addr_array_5[12:0] ); | |
| 951 | cam_hit1[5] = (( wr_data[13] == addr_bit4[5] ) | force_hit); | |
| 952 | cam_hit[5] = (cam_hit0[5] & cam_hit1[5]) & valid_bit[5]; | |
| 953 | new_valid[5] = valid_bit[5] & ~( cam_hit[5] & inval_mask[5]); | |
| 954 | ||
| 955 | ||
| 956 | cam_hit0[6] = ( wr_data[12:0] == addr_array_6[12:0] ); | |
| 957 | cam_hit1[6] = (( wr_data[13] == addr_bit4[6] ) | force_hit); | |
| 958 | cam_hit[6] = (cam_hit0[6] & cam_hit1[6]) & valid_bit[6]; | |
| 959 | new_valid[6] = valid_bit[6] & ~( cam_hit[6] & inval_mask[6]); | |
| 960 | ||
| 961 | ||
| 962 | cam_hit0[7] = ( wr_data[12:0] == addr_array_7[12:0] ); | |
| 963 | cam_hit1[7] = (( wr_data[13] == addr_bit4[7] ) | force_hit); | |
| 964 | cam_hit[7] = (cam_hit0[7] & cam_hit1[7]) & valid_bit[7]; | |
| 965 | new_valid[7] = valid_bit[7] & ~( cam_hit[7] & inval_mask[7]); | |
| 966 | ||
| 967 | ||
| 968 | cam_hit0[8] = ( wr_data[12:0] == addr_array_8[12:0] ); | |
| 969 | cam_hit1[8] = (( wr_data[13] == addr_bit4[8] ) | force_hit); | |
| 970 | cam_hit[8] = (cam_hit0[8] & cam_hit1[8]) & valid_bit[8]; | |
| 971 | new_valid[8] = valid_bit[8] & ~( cam_hit[8] & inval_mask[8]); | |
| 972 | ||
| 973 | ||
| 974 | cam_hit0[9] = ( wr_data[12:0] == addr_array_9[12:0] ); | |
| 975 | cam_hit1[9] = (( wr_data[13] == addr_bit4[9] ) | force_hit); | |
| 976 | cam_hit[9] = (cam_hit0[9] & cam_hit1[9]) & valid_bit[9]; | |
| 977 | new_valid[9] = valid_bit[9] & ~( cam_hit[9] & inval_mask[9]); | |
| 978 | ||
| 979 | ||
| 980 | cam_hit0[10] = ( wr_data[12:0] == addr_array_10[12:0] ); | |
| 981 | cam_hit1[10] = (( wr_data[13] == addr_bit4[10] ) | force_hit); | |
| 982 | cam_hit[10] = (cam_hit0[10] & cam_hit1[10]) & valid_bit[10]; | |
| 983 | new_valid[10] = valid_bit[10] & ~( cam_hit[10] & inval_mask[10]); | |
| 984 | ||
| 985 | ||
| 986 | cam_hit0[11] = ( wr_data[12:0] == addr_array_11[12:0] ); | |
| 987 | cam_hit1[11] = (( wr_data[13] == addr_bit4[11] ) | force_hit); | |
| 988 | cam_hit[11] = (cam_hit0[11] & cam_hit1[11]) & valid_bit[11]; | |
| 989 | new_valid[11] = valid_bit[11] & ~( cam_hit[11] & inval_mask[11]); | |
| 990 | ||
| 991 | ||
| 992 | cam_hit0[12] = ( wr_data[12:0] == addr_array_12[12:0] ); | |
| 993 | cam_hit1[12] = (( wr_data[13] == addr_bit4[12] ) | force_hit); | |
| 994 | cam_hit[12] = (cam_hit0[12] & cam_hit1[12]) & valid_bit[12]; | |
| 995 | new_valid[12] = valid_bit[12] & ~( cam_hit[12] & inval_mask[12]); | |
| 996 | ||
| 997 | ||
| 998 | cam_hit0[13] = ( wr_data[12:0] == addr_array_13[12:0] ); | |
| 999 | cam_hit1[13] = (( wr_data[13] == addr_bit4[13] ) | force_hit); | |
| 1000 | cam_hit[13] = (cam_hit0[13] & cam_hit1[13]) & valid_bit[13]; | |
| 1001 | new_valid[13] = valid_bit[13] & ~( cam_hit[13] & inval_mask[13]); | |
| 1002 | ||
| 1003 | ||
| 1004 | cam_hit0[14] = ( wr_data[12:0] == addr_array_14[12:0] ); | |
| 1005 | cam_hit1[14] = (( wr_data[13] == addr_bit4[14] ) | force_hit); | |
| 1006 | cam_hit[14] = (cam_hit0[14] & cam_hit1[14]) & valid_bit[14]; | |
| 1007 | new_valid[14] = valid_bit[14] & ~( cam_hit[14] & inval_mask[14]); | |
| 1008 | ||
| 1009 | ||
| 1010 | cam_hit0[15] = ( wr_data[12:0] == addr_array_15[12:0] ); | |
| 1011 | cam_hit1[15] = (( wr_data[13] == addr_bit4[15] ) | force_hit); | |
| 1012 | cam_hit[15] = (cam_hit0[15] & cam_hit1[15]) & valid_bit[15]; | |
| 1013 | new_valid[15] = valid_bit[15] & ~( cam_hit[15] & inval_mask[15]); | |
| 1014 | ||
| 1015 | ||
| 1016 | cam_hit0[16] = ( wr_data[12:0] == addr_array_16[12:0] ); | |
| 1017 | cam_hit1[16] = (( wr_data[13] == addr_bit4[16] ) | force_hit); | |
| 1018 | cam_hit[16] = (cam_hit0[16] & cam_hit1[16]) & valid_bit[16]; | |
| 1019 | new_valid[16] = valid_bit[16] & ~( cam_hit[16] & inval_mask[16]); | |
| 1020 | ||
| 1021 | ||
| 1022 | cam_hit0[17] = ( wr_data[12:0] == addr_array_17[12:0] ); | |
| 1023 | cam_hit1[17] = (( wr_data[13] == addr_bit4[17] ) | force_hit); | |
| 1024 | cam_hit[17] = (cam_hit0[17] & cam_hit1[17]) & valid_bit[17]; | |
| 1025 | new_valid[17] = valid_bit[17] & ~( cam_hit[17] & inval_mask[17]); | |
| 1026 | ||
| 1027 | ||
| 1028 | cam_hit0[18] = ( wr_data[12:0] == addr_array_18[12:0] ); | |
| 1029 | cam_hit1[18] = (( wr_data[13] == addr_bit4[18] ) | force_hit); | |
| 1030 | cam_hit[18] = (cam_hit0[18] & cam_hit1[18]) & valid_bit[18]; | |
| 1031 | new_valid[18] = valid_bit[18] & ~( cam_hit[18] & inval_mask[18]); | |
| 1032 | ||
| 1033 | ||
| 1034 | cam_hit0[19] = ( wr_data[12:0] == addr_array_19[12:0] ); | |
| 1035 | cam_hit1[19] = (( wr_data[13] == addr_bit4[19] ) | force_hit); | |
| 1036 | cam_hit[19] = (cam_hit0[19] & cam_hit1[19]) & valid_bit[19]; | |
| 1037 | new_valid[19] = valid_bit[19] & ~( cam_hit[19] & inval_mask[19]); | |
| 1038 | ||
| 1039 | ||
| 1040 | cam_hit0[20] = ( wr_data[12:0] == addr_array_20[12:0] ); | |
| 1041 | cam_hit1[20] = (( wr_data[13] == addr_bit4[20] ) | force_hit); | |
| 1042 | cam_hit[20] = (cam_hit0[20] & cam_hit1[20]) & valid_bit[20]; | |
| 1043 | new_valid[20] = valid_bit[20] & ~( cam_hit[20] & inval_mask[20]); | |
| 1044 | ||
| 1045 | ||
| 1046 | cam_hit0[21] = ( wr_data[12:0] == addr_array_21[12:0] ); | |
| 1047 | cam_hit1[21] = (( wr_data[13] == addr_bit4[21] ) | force_hit); | |
| 1048 | cam_hit[21] = (cam_hit0[21] & cam_hit1[21]) & valid_bit[21]; | |
| 1049 | new_valid[21] = valid_bit[21] & ~( cam_hit[21] & inval_mask[21]); | |
| 1050 | ||
| 1051 | ||
| 1052 | cam_hit0[22] = ( wr_data[12:0] == addr_array_22[12:0] ); | |
| 1053 | cam_hit1[22] = (( wr_data[13] == addr_bit4[22] ) | force_hit); | |
| 1054 | cam_hit[22] = (cam_hit0[22] & cam_hit1[22]) & valid_bit[22]; | |
| 1055 | new_valid[22] = valid_bit[22] & ~( cam_hit[22] & inval_mask[22]); | |
| 1056 | ||
| 1057 | ||
| 1058 | cam_hit0[23] = ( wr_data[12:0] == addr_array_23[12:0] ); | |
| 1059 | cam_hit1[23] = (( wr_data[13] == addr_bit4[23] ) | force_hit); | |
| 1060 | cam_hit[23] = (cam_hit0[23] & cam_hit1[23]) & valid_bit[23]; | |
| 1061 | new_valid[23] = valid_bit[23] & ~( cam_hit[23] & inval_mask[23]); | |
| 1062 | ||
| 1063 | ||
| 1064 | cam_hit0[24] = ( wr_data[12:0] == addr_array_24[12:0] ); | |
| 1065 | cam_hit1[24] = (( wr_data[13] == addr_bit4[24] ) | force_hit); | |
| 1066 | cam_hit[24] = (cam_hit0[24] & cam_hit1[24]) & valid_bit[24]; | |
| 1067 | new_valid[24] = valid_bit[24] & ~( cam_hit[24] & inval_mask[24]); | |
| 1068 | ||
| 1069 | ||
| 1070 | cam_hit0[25] = ( wr_data[12:0] == addr_array_25[12:0] ); | |
| 1071 | cam_hit1[25] = (( wr_data[13] == addr_bit4[25] ) | force_hit); | |
| 1072 | cam_hit[25] = (cam_hit0[25] & cam_hit1[25]) & valid_bit[25]; | |
| 1073 | new_valid[25] = valid_bit[25] & ~( cam_hit[25] & inval_mask[25]); | |
| 1074 | ||
| 1075 | ||
| 1076 | cam_hit0[26] = ( wr_data[12:0] == addr_array_26[12:0] ); | |
| 1077 | cam_hit1[26] = (( wr_data[13] == addr_bit4[26] ) | force_hit); | |
| 1078 | cam_hit[26] = (cam_hit0[26] & cam_hit1[26]) & valid_bit[26]; | |
| 1079 | new_valid[26] = valid_bit[26] & ~( cam_hit[26] & inval_mask[26]); | |
| 1080 | ||
| 1081 | ||
| 1082 | cam_hit0[27] = ( wr_data[12:0] == addr_array_27[12:0] ); | |
| 1083 | cam_hit1[27] = (( wr_data[13] == addr_bit4[27] ) | force_hit); | |
| 1084 | cam_hit[27] = (cam_hit0[27] & cam_hit1[27]) & valid_bit[27]; | |
| 1085 | new_valid[27] = valid_bit[27] & ~( cam_hit[27] & inval_mask[27]); | |
| 1086 | ||
| 1087 | ||
| 1088 | cam_hit0[28] = ( wr_data[12:0] == addr_array_28[12:0] ); | |
| 1089 | cam_hit1[28] = (( wr_data[13] == addr_bit4[28] ) | force_hit); | |
| 1090 | cam_hit[28] = (cam_hit0[28] & cam_hit1[28]) & valid_bit[28]; | |
| 1091 | new_valid[28] = valid_bit[28] & ~( cam_hit[28] & inval_mask[28]); | |
| 1092 | ||
| 1093 | ||
| 1094 | cam_hit0[29] = ( wr_data[12:0] == addr_array_29[12:0] ); | |
| 1095 | cam_hit1[29] = (( wr_data[13] == addr_bit4[29] ) | force_hit); | |
| 1096 | cam_hit[29] = (cam_hit0[29] & cam_hit1[29]) & valid_bit[29]; | |
| 1097 | new_valid[29] = valid_bit[29] & ~( cam_hit[29] & inval_mask[29]); | |
| 1098 | ||
| 1099 | ||
| 1100 | cam_hit0[30] = ( wr_data[12:0] == addr_array_30[12:0] ); | |
| 1101 | cam_hit1[30] = (( wr_data[13] == addr_bit4[30] ) | force_hit); | |
| 1102 | cam_hit[30] = (cam_hit0[30] & cam_hit1[30]) & valid_bit[30]; | |
| 1103 | new_valid[30] = valid_bit[30] & ~( cam_hit[30] & inval_mask[30]); | |
| 1104 | ||
| 1105 | ||
| 1106 | cam_hit0[31] = ( wr_data[12:0] == addr_array_31[12:0] ); | |
| 1107 | cam_hit1[31] = (( wr_data[13] == addr_bit4[31] ) | force_hit); | |
| 1108 | cam_hit[31] = (cam_hit0[31] & cam_hit1[31]) & valid_bit[31]; | |
| 1109 | new_valid[31] = valid_bit[31] & ~( cam_hit[31] & inval_mask[31]); | |
| 1110 | ||
| 1111 | ||
| 1112 | cam_hit0[32] = ( wr_data[12:0] == addr_array_32[12:0] ); | |
| 1113 | cam_hit1[32] = (( wr_data[13] == addr_bit4[32] ) | force_hit); | |
| 1114 | cam_hit[32] = (cam_hit0[32] & cam_hit1[32]) & valid_bit[32]; | |
| 1115 | new_valid[32] = valid_bit[32] & ~( cam_hit[32] & inval_mask[32]); | |
| 1116 | ||
| 1117 | ||
| 1118 | cam_hit0[33] = ( wr_data[12:0] == addr_array_33[12:0] ); | |
| 1119 | cam_hit1[33] = (( wr_data[13] == addr_bit4[33] ) | force_hit); | |
| 1120 | cam_hit[33] = (cam_hit0[33] & cam_hit1[33]) & valid_bit[33]; | |
| 1121 | new_valid[33] = valid_bit[33] & ~( cam_hit[33] & inval_mask[33]); | |
| 1122 | ||
| 1123 | ||
| 1124 | cam_hit0[34] = ( wr_data[12:0] == addr_array_34[12:0] ); | |
| 1125 | cam_hit1[34] = (( wr_data[13] == addr_bit4[34] ) | force_hit); | |
| 1126 | cam_hit[34] = (cam_hit0[34] & cam_hit1[34]) & valid_bit[34]; | |
| 1127 | new_valid[34] = valid_bit[34] & ~( cam_hit[34] & inval_mask[34]); | |
| 1128 | ||
| 1129 | ||
| 1130 | cam_hit0[35] = ( wr_data[12:0] == addr_array_35[12:0] ); | |
| 1131 | cam_hit1[35] = (( wr_data[13] == addr_bit4[35] ) | force_hit); | |
| 1132 | cam_hit[35] = (cam_hit0[35] & cam_hit1[35]) & valid_bit[35]; | |
| 1133 | new_valid[35] = valid_bit[35] & ~( cam_hit[35] & inval_mask[35]); | |
| 1134 | ||
| 1135 | ||
| 1136 | cam_hit0[36] = ( wr_data[12:0] == addr_array_36[12:0] ); | |
| 1137 | cam_hit1[36] = (( wr_data[13] == addr_bit4[36] ) | force_hit); | |
| 1138 | cam_hit[36] = (cam_hit0[36] & cam_hit1[36]) & valid_bit[36]; | |
| 1139 | new_valid[36] = valid_bit[36] & ~( cam_hit[36] & inval_mask[36]); | |
| 1140 | ||
| 1141 | ||
| 1142 | cam_hit0[37] = ( wr_data[12:0] == addr_array_37[12:0] ); | |
| 1143 | cam_hit1[37] = (( wr_data[13] == addr_bit4[37] ) | force_hit); | |
| 1144 | cam_hit[37] = (cam_hit0[37] & cam_hit1[37]) & valid_bit[37]; | |
| 1145 | new_valid[37] = valid_bit[37] & ~( cam_hit[37] & inval_mask[37]); | |
| 1146 | ||
| 1147 | ||
| 1148 | cam_hit0[38] = ( wr_data[12:0] == addr_array_38[12:0] ); | |
| 1149 | cam_hit1[38] = (( wr_data[13] == addr_bit4[38] ) | force_hit); | |
| 1150 | cam_hit[38] = (cam_hit0[38] & cam_hit1[38]) & valid_bit[38]; | |
| 1151 | new_valid[38] = valid_bit[38] & ~( cam_hit[38] & inval_mask[38]); | |
| 1152 | ||
| 1153 | ||
| 1154 | cam_hit0[39] = ( wr_data[12:0] == addr_array_39[12:0] ); | |
| 1155 | cam_hit1[39] = (( wr_data[13] == addr_bit4[39] ) | force_hit); | |
| 1156 | cam_hit[39] = (cam_hit0[39] & cam_hit1[39]) & valid_bit[39]; | |
| 1157 | new_valid[39] = valid_bit[39] & ~( cam_hit[39] & inval_mask[39]); | |
| 1158 | ||
| 1159 | ||
| 1160 | cam_hit0[40] = ( wr_data[12:0] == addr_array_40[12:0] ); | |
| 1161 | cam_hit1[40] = (( wr_data[13] == addr_bit4[40] ) | force_hit); | |
| 1162 | cam_hit[40] = (cam_hit0[40] & cam_hit1[40]) & valid_bit[40]; | |
| 1163 | new_valid[40] = valid_bit[40] & ~( cam_hit[40] & inval_mask[40]); | |
| 1164 | ||
| 1165 | ||
| 1166 | cam_hit0[41] = ( wr_data[12:0] == addr_array_41[12:0] ); | |
| 1167 | cam_hit1[41] = (( wr_data[13] == addr_bit4[41] ) | force_hit); | |
| 1168 | cam_hit[41] = (cam_hit0[41] & cam_hit1[41]) & valid_bit[41]; | |
| 1169 | new_valid[41] = valid_bit[41] & ~( cam_hit[41] & inval_mask[41]); | |
| 1170 | ||
| 1171 | ||
| 1172 | cam_hit0[42] = ( wr_data[12:0] == addr_array_42[12:0] ); | |
| 1173 | cam_hit1[42] = (( wr_data[13] == addr_bit4[42] ) | force_hit); | |
| 1174 | cam_hit[42] = (cam_hit0[42] & cam_hit1[42]) & valid_bit[42]; | |
| 1175 | new_valid[42] = valid_bit[42] & ~( cam_hit[42] & inval_mask[42]); | |
| 1176 | ||
| 1177 | ||
| 1178 | cam_hit0[43] = ( wr_data[12:0] == addr_array_43[12:0] ); | |
| 1179 | cam_hit1[43] = (( wr_data[13] == addr_bit4[43] ) | force_hit); | |
| 1180 | cam_hit[43] = (cam_hit0[43] & cam_hit1[43]) & valid_bit[43]; | |
| 1181 | new_valid[43] = valid_bit[43] & ~( cam_hit[43] & inval_mask[43]); | |
| 1182 | ||
| 1183 | ||
| 1184 | cam_hit0[44] = ( wr_data[12:0] == addr_array_44[12:0] ); | |
| 1185 | cam_hit1[44] = (( wr_data[13] == addr_bit4[44] ) | force_hit); | |
| 1186 | cam_hit[44] = (cam_hit0[44] & cam_hit1[44]) & valid_bit[44]; | |
| 1187 | new_valid[44] = valid_bit[44] & ~( cam_hit[44] & inval_mask[44]); | |
| 1188 | ||
| 1189 | ||
| 1190 | cam_hit0[45] = ( wr_data[12:0] == addr_array_45[12:0] ); | |
| 1191 | cam_hit1[45] = (( wr_data[13] == addr_bit4[45] ) | force_hit); | |
| 1192 | cam_hit[45] = (cam_hit0[45] & cam_hit1[45]) & valid_bit[45]; | |
| 1193 | new_valid[45] = valid_bit[45] & ~( cam_hit[45] & inval_mask[45]); | |
| 1194 | ||
| 1195 | ||
| 1196 | cam_hit0[46] = ( wr_data[12:0] == addr_array_46[12:0] ); | |
| 1197 | cam_hit1[46] = (( wr_data[13] == addr_bit4[46] ) | force_hit); | |
| 1198 | cam_hit[46] = (cam_hit0[46] & cam_hit1[46]) & valid_bit[46]; | |
| 1199 | new_valid[46] = valid_bit[46] & ~( cam_hit[46] & inval_mask[46]); | |
| 1200 | ||
| 1201 | ||
| 1202 | cam_hit0[47] = ( wr_data[12:0] == addr_array_47[12:0] ); | |
| 1203 | cam_hit1[47] = (( wr_data[13] == addr_bit4[47] ) | force_hit); | |
| 1204 | cam_hit[47] = (cam_hit0[47] & cam_hit1[47]) & valid_bit[47]; | |
| 1205 | new_valid[47] = valid_bit[47] & ~( cam_hit[47] & inval_mask[47]); | |
| 1206 | ||
| 1207 | ||
| 1208 | cam_hit0[48] = ( wr_data[12:0] == addr_array_48[12:0] ); | |
| 1209 | cam_hit1[48] = (( wr_data[13] == addr_bit4[48] ) | force_hit); | |
| 1210 | cam_hit[48] = (cam_hit0[48] & cam_hit1[48]) & valid_bit[48]; | |
| 1211 | new_valid[48] = valid_bit[48] & ~( cam_hit[48] & inval_mask[48]); | |
| 1212 | ||
| 1213 | ||
| 1214 | cam_hit0[49] = ( wr_data[12:0] == addr_array_49[12:0] ); | |
| 1215 | cam_hit1[49] = (( wr_data[13] == addr_bit4[49] ) | force_hit); | |
| 1216 | cam_hit[49] = (cam_hit0[49] & cam_hit1[49]) & valid_bit[49]; | |
| 1217 | new_valid[49] = valid_bit[49] & ~( cam_hit[49] & inval_mask[49]); | |
| 1218 | ||
| 1219 | ||
| 1220 | cam_hit0[50] = ( wr_data[12:0] == addr_array_50[12:0] ); | |
| 1221 | cam_hit1[50] = (( wr_data[13] == addr_bit4[50] ) | force_hit); | |
| 1222 | cam_hit[50] = (cam_hit0[50] & cam_hit1[50]) & valid_bit[50]; | |
| 1223 | new_valid[50] = valid_bit[50] & ~( cam_hit[50] & inval_mask[50]); | |
| 1224 | ||
| 1225 | ||
| 1226 | cam_hit0[51] = ( wr_data[12:0] == addr_array_51[12:0] ); | |
| 1227 | cam_hit1[51] = (( wr_data[13] == addr_bit4[51] ) | force_hit); | |
| 1228 | cam_hit[51] = (cam_hit0[51] & cam_hit1[51]) & valid_bit[51]; | |
| 1229 | new_valid[51] = valid_bit[51] & ~( cam_hit[51] & inval_mask[51]); | |
| 1230 | ||
| 1231 | ||
| 1232 | cam_hit0[52] = ( wr_data[12:0] == addr_array_52[12:0] ); | |
| 1233 | cam_hit1[52] = (( wr_data[13] == addr_bit4[52] ) | force_hit); | |
| 1234 | cam_hit[52] = (cam_hit0[52] & cam_hit1[52]) & valid_bit[52]; | |
| 1235 | new_valid[52] = valid_bit[52] & ~( cam_hit[52] & inval_mask[52]); | |
| 1236 | ||
| 1237 | ||
| 1238 | cam_hit0[53] = ( wr_data[12:0] == addr_array_53[12:0] ); | |
| 1239 | cam_hit1[53] = (( wr_data[13] == addr_bit4[53] ) | force_hit); | |
| 1240 | cam_hit[53] = (cam_hit0[53] & cam_hit1[53]) & valid_bit[53]; | |
| 1241 | new_valid[53] = valid_bit[53] & ~( cam_hit[53] & inval_mask[53]); | |
| 1242 | ||
| 1243 | ||
| 1244 | cam_hit0[54] = ( wr_data[12:0] == addr_array_54[12:0] ); | |
| 1245 | cam_hit1[54] = (( wr_data[13] == addr_bit4[54] ) | force_hit); | |
| 1246 | cam_hit[54] = (cam_hit0[54] & cam_hit1[54]) & valid_bit[54]; | |
| 1247 | new_valid[54] = valid_bit[54] & ~( cam_hit[54] & inval_mask[54]); | |
| 1248 | ||
| 1249 | ||
| 1250 | cam_hit0[55] = ( wr_data[12:0] == addr_array_55[12:0] ); | |
| 1251 | cam_hit1[55] = (( wr_data[13] == addr_bit4[55] ) | force_hit); | |
| 1252 | cam_hit[55] = (cam_hit0[55] & cam_hit1[55]) & valid_bit[55]; | |
| 1253 | new_valid[55] = valid_bit[55] & ~( cam_hit[55] & inval_mask[55]); | |
| 1254 | ||
| 1255 | ||
| 1256 | cam_hit0[56] = ( wr_data[12:0] == addr_array_56[12:0] ); | |
| 1257 | cam_hit1[56] = (( wr_data[13] == addr_bit4[56] ) | force_hit); | |
| 1258 | cam_hit[56] = (cam_hit0[56] & cam_hit1[56]) & valid_bit[56]; | |
| 1259 | new_valid[56] = valid_bit[56] & ~( cam_hit[56] & inval_mask[56]); | |
| 1260 | ||
| 1261 | ||
| 1262 | cam_hit0[57] = ( wr_data[12:0] == addr_array_57[12:0] ); | |
| 1263 | cam_hit1[57] = (( wr_data[13] == addr_bit4[57] ) | force_hit); | |
| 1264 | cam_hit[57] = (cam_hit0[57] & cam_hit1[57]) & valid_bit[57]; | |
| 1265 | new_valid[57] = valid_bit[57] & ~( cam_hit[57] & inval_mask[57]); | |
| 1266 | ||
| 1267 | ||
| 1268 | cam_hit0[58] = ( wr_data[12:0] == addr_array_58[12:0] ); | |
| 1269 | cam_hit1[58] = (( wr_data[13] == addr_bit4[58] ) | force_hit); | |
| 1270 | cam_hit[58] = (cam_hit0[58] & cam_hit1[58]) & valid_bit[58]; | |
| 1271 | new_valid[58] = valid_bit[58] & ~( cam_hit[58] & inval_mask[58]); | |
| 1272 | ||
| 1273 | ||
| 1274 | cam_hit0[59] = ( wr_data[12:0] == addr_array_59[12:0] ); | |
| 1275 | cam_hit1[59] = (( wr_data[13] == addr_bit4[59] ) | force_hit); | |
| 1276 | cam_hit[59] = (cam_hit0[59] & cam_hit1[59]) & valid_bit[59]; | |
| 1277 | new_valid[59] = valid_bit[59] & ~( cam_hit[59] & inval_mask[59]); | |
| 1278 | ||
| 1279 | ||
| 1280 | cam_hit0[60] = ( wr_data[12:0] == addr_array_60[12:0] ); | |
| 1281 | cam_hit1[60] = (( wr_data[13] == addr_bit4[60] ) | force_hit); | |
| 1282 | cam_hit[60] = (cam_hit0[60] & cam_hit1[60]) & valid_bit[60]; | |
| 1283 | new_valid[60] = valid_bit[60] & ~( cam_hit[60] & inval_mask[60]); | |
| 1284 | ||
| 1285 | ||
| 1286 | cam_hit0[61] = ( wr_data[12:0] == addr_array_61[12:0] ); | |
| 1287 | cam_hit1[61] = (( wr_data[13] == addr_bit4[61] ) | force_hit); | |
| 1288 | cam_hit[61] = (cam_hit0[61] & cam_hit1[61]) & valid_bit[61]; | |
| 1289 | new_valid[61] = valid_bit[61] & ~( cam_hit[61] & inval_mask[61]); | |
| 1290 | ||
| 1291 | ||
| 1292 | cam_hit0[62] = ( wr_data[12:0] == addr_array_62[12:0] ); | |
| 1293 | cam_hit1[62] = (( wr_data[13] == addr_bit4[62] ) | force_hit); | |
| 1294 | cam_hit[62] = (cam_hit0[62] & cam_hit1[62]) & valid_bit[62]; | |
| 1295 | new_valid[62] = valid_bit[62] & ~( cam_hit[62] & inval_mask[62]); | |
| 1296 | ||
| 1297 | ||
| 1298 | cam_hit0[63] = ( wr_data[12:0] == addr_array_63[12:0] ); | |
| 1299 | cam_hit1[63] = (( wr_data[13] == addr_bit4[63] ) | force_hit); | |
| 1300 | cam_hit[63] = (cam_hit0[63] & cam_hit1[63]) & valid_bit[63]; | |
| 1301 | new_valid[63] = valid_bit[63] & ~( cam_hit[63] & inval_mask[63]); | |
| 1302 | ||
| 1303 | ||
| 1304 | ||
| 1305 | lkup_hit <= cam_hit; // RACE FIX | |
| 1306 | ||
| 1307 | ||
| 1308 | end | |
| 1309 | ||
| 1310 | else if(l2clk) | |
| 1311 | begin | |
| 1312 | lkup_hit <= 64'b0; // RACE FIX | |
| 1313 | new_valid <= valid_bit; | |
| 1314 | end | |
| 1315 | ||
| 1316 | end | |
| 1317 | ||
| 1318 | ||
| 1319 | //////////////////////////////////////////////////////////// | |
| 1320 | // READ/WRITE OPERATION | |
| 1321 | // Phase 1 RD | |
| 1322 | //////////////////////////////////////////////////////////// | |
| 1323 | ||
| 1324 | //initial | |
| 1325 | //begin | |
| 1326 | // addr_bit4 = 64'b0; | |
| 1327 | //end | |
| 1328 | ||
| 1329 | always @(l2clk or write_disable or rd_en or wr_en or cam_en or bypass or valid or rst_warm or wr_data ) | |
| 1330 | begin | |
| 1331 | if (bypass) | |
| 1332 | rd_data[15:0] <= wr_data[15:0]; | |
| 1333 | else if ((rst_warm & ~write_disable)) | |
| 1334 | begin | |
| 1335 | rd_data[15:0] <= 16'b0; | |
| 1336 | valid[63:0] <= 64'b0; | |
| 1337 | end | |
| 1338 | else if ((rst_warm & write_disable)) | |
| 1339 | begin | |
| 1340 | rd_data[15:0] <= 16'b0; | |
| 1341 | end | |
| 1342 | if(l2clk & rd_en & ~write_disable & ~bypass & ~rst_warm) // RD | |
| 1343 | begin | |
| 1344 | if(wr_en) | |
| 1345 | begin | |
| 1346 | rd_data <= 16'bx; | |
| 1347 | // should put in <fire -active wr_en -message "L2_DIR_ERR: read and write conflict" | |
| 1348 | end | |
| 1349 | else | |
| 1350 | begin | |
| 1351 | rd_data <= { valid[rw_addr], parity[rw_addr], addr_bit4[rw_addr], addr_array[rw_addr] }; | |
| 1352 | end | |
| 1353 | end // of if rd_en | |
| 1354 | ||
| 1355 | if(l2clk & wr_en & ~write_disable & ~bypass & ~rst_warm & ~cam_en) // WR | |
| 1356 | begin | |
| 1357 | if(rd_en) // RESET | |
| 1358 | begin | |
| 1359 | rd_data <= 16'bx; | |
| 1360 | addr_array[rw_addr] <= 13'bx; | |
| 1361 | addr_bit4[rw_addr] <= 1'bx; | |
| 1362 | parity[rw_addr] <= 1'bx; | |
| 1363 | valid[rw_addr] <= 1'bx; | |
| 1364 | end | |
| 1365 | else | |
| 1366 | begin | |
| 1367 | addr_array[rw_addr] <= wr_data[12:0] ; // BS and SR 11/18/03 Reverse Directory change | |
| 1368 | addr_bit4[rw_addr] <= wr_data[13] ; // BS and SR 11/18/03 Reverse Directory change | |
| 1369 | parity[rw_addr] <= wr_data[14] ; // BS and SR 11/18/03 Reverse Directory change | |
| 1370 | valid[rw_addr] <= wr_data[15] ; // BS and SR 11/18/03 Reverse Directory change | |
| 1371 | // should put in <fire -active cam_en -message "L2_DIR_ERR : cam/wr conflict" | |
| 1372 | end | |
| 1373 | end | |
| 1374 | // if(~l2clk & cam_en & ~write_disable) // CAM | |
| 1375 | if(~l2clk & ~write_disable) // CAM | |
| 1376 | begin | |
| 1377 | if (lkup_hit[0]) valid[0] <= new_valid[0]; | |
| 1378 | if (lkup_hit[1]) valid[1] <= new_valid[1]; | |
| 1379 | if (lkup_hit[2]) valid[2] <= new_valid[2]; | |
| 1380 | if (lkup_hit[3]) valid[3] <= new_valid[3]; | |
| 1381 | if (lkup_hit[4]) valid[4] <= new_valid[4]; | |
| 1382 | if (lkup_hit[5]) valid[5] <= new_valid[5]; | |
| 1383 | if (lkup_hit[6]) valid[6] <= new_valid[6]; | |
| 1384 | if (lkup_hit[7]) valid[7] <= new_valid[7]; | |
| 1385 | if (lkup_hit[8]) valid[8] <= new_valid[8]; | |
| 1386 | if (lkup_hit[9]) valid[9] <= new_valid[9]; | |
| 1387 | if (lkup_hit[10]) valid[10] <= new_valid[10]; | |
| 1388 | if (lkup_hit[11]) valid[11] <= new_valid[11]; | |
| 1389 | if (lkup_hit[12]) valid[12] <= new_valid[12]; | |
| 1390 | if (lkup_hit[13]) valid[13] <= new_valid[13]; | |
| 1391 | if (lkup_hit[14]) valid[14] <= new_valid[14]; | |
| 1392 | if (lkup_hit[15]) valid[15] <= new_valid[15]; | |
| 1393 | if (lkup_hit[16]) valid[16] <= new_valid[16]; | |
| 1394 | if (lkup_hit[17]) valid[17] <= new_valid[17]; | |
| 1395 | if (lkup_hit[18]) valid[18] <= new_valid[18]; | |
| 1396 | if (lkup_hit[19]) valid[19] <= new_valid[19]; | |
| 1397 | if (lkup_hit[20]) valid[20] <= new_valid[20]; | |
| 1398 | if (lkup_hit[21]) valid[21] <= new_valid[21]; | |
| 1399 | if (lkup_hit[22]) valid[22] <= new_valid[22]; | |
| 1400 | if (lkup_hit[23]) valid[23] <= new_valid[23]; | |
| 1401 | if (lkup_hit[24]) valid[24] <= new_valid[24]; | |
| 1402 | if (lkup_hit[25]) valid[25] <= new_valid[25]; | |
| 1403 | if (lkup_hit[26]) valid[26] <= new_valid[26]; | |
| 1404 | if (lkup_hit[27]) valid[27] <= new_valid[27]; | |
| 1405 | if (lkup_hit[28]) valid[28] <= new_valid[28]; | |
| 1406 | if (lkup_hit[29]) valid[29] <= new_valid[29]; | |
| 1407 | if (lkup_hit[30]) valid[30] <= new_valid[30]; | |
| 1408 | if (lkup_hit[31]) valid[31] <= new_valid[31]; | |
| 1409 | if (lkup_hit[32]) valid[32] <= new_valid[32]; | |
| 1410 | if (lkup_hit[33]) valid[33] <= new_valid[33]; | |
| 1411 | if (lkup_hit[34]) valid[34] <= new_valid[34]; | |
| 1412 | if (lkup_hit[35]) valid[35] <= new_valid[35]; | |
| 1413 | if (lkup_hit[36]) valid[36] <= new_valid[36]; | |
| 1414 | if (lkup_hit[37]) valid[37] <= new_valid[37]; | |
| 1415 | if (lkup_hit[38]) valid[38] <= new_valid[38]; | |
| 1416 | if (lkup_hit[39]) valid[39] <= new_valid[39]; | |
| 1417 | if (lkup_hit[40]) valid[40] <= new_valid[40]; | |
| 1418 | if (lkup_hit[41]) valid[41] <= new_valid[41]; | |
| 1419 | if (lkup_hit[42]) valid[42] <= new_valid[42]; | |
| 1420 | if (lkup_hit[43]) valid[43] <= new_valid[43]; | |
| 1421 | if (lkup_hit[44]) valid[44] <= new_valid[44]; | |
| 1422 | if (lkup_hit[45]) valid[45] <= new_valid[45]; | |
| 1423 | if (lkup_hit[46]) valid[46] <= new_valid[46]; | |
| 1424 | if (lkup_hit[47]) valid[47] <= new_valid[47]; | |
| 1425 | if (lkup_hit[48]) valid[48] <= new_valid[48]; | |
| 1426 | if (lkup_hit[49]) valid[49] <= new_valid[49]; | |
| 1427 | if (lkup_hit[50]) valid[50] <= new_valid[50]; | |
| 1428 | if (lkup_hit[51]) valid[51] <= new_valid[51]; | |
| 1429 | if (lkup_hit[52]) valid[52] <= new_valid[52]; | |
| 1430 | if (lkup_hit[53]) valid[53] <= new_valid[53]; | |
| 1431 | if (lkup_hit[54]) valid[54] <= new_valid[54]; | |
| 1432 | if (lkup_hit[55]) valid[55] <= new_valid[55]; | |
| 1433 | if (lkup_hit[56]) valid[56] <= new_valid[56]; | |
| 1434 | if (lkup_hit[57]) valid[57] <= new_valid[57]; | |
| 1435 | if (lkup_hit[58]) valid[58] <= new_valid[58]; | |
| 1436 | if (lkup_hit[59]) valid[59] <= new_valid[59]; | |
| 1437 | if (lkup_hit[60]) valid[60] <= new_valid[60]; | |
| 1438 | if (lkup_hit[61]) valid[61] <= new_valid[61]; | |
| 1439 | if (lkup_hit[62]) valid[62] <= new_valid[62]; | |
| 1440 | if (lkup_hit[63]) valid[63] <= new_valid[63]; | |
| 1441 | end | |
| 1442 | end | |
| 1443 | ||
| 1444 | endmodule | |
| 1445 |