projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: n2_mmu_cm_64x34s_cust.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module n2_mmu_cm_64x34s_cust ( | |
| 36 | // clocks, scan | |
| 37 | clk, | |
| 38 | scan_in, | |
| 39 | tcu_se_scancollar_in, | |
| 40 | tcu_scan_en, | |
| 41 | tcu_pce_ov, | |
| 42 | pce, | |
| 43 | tcu_aclk, | |
| 44 | tcu_bclk, | |
| 45 | tcu_array_wr_inhibit, | |
| 46 | scan_out, | |
| 47 | ||
| 48 | // ram control | |
| 49 | rd_addr, | |
| 50 | wr_addr, | |
| 51 | din, | |
| 52 | wr_en, | |
| 53 | rd_en, | |
| 54 | lkup_en, | |
| 55 | hld, | |
| 56 | key, | |
| 57 | hit, | |
| 58 | dout | |
| 59 | ||
| 60 | ); | |
| 61 | ||
| 62 | ||
| 63 | ||
| 64 | ||
| 65 | // clocks, scan | |
| 66 | input clk; // io clock | |
| 67 | input scan_in; // | |
| 68 | input tcu_se_scancollar_in; // | |
| 69 | input tcu_scan_en; // | |
| 70 | input tcu_pce_ov; // scan signals | |
| 71 | input pce; // clock enable | |
| 72 | input tcu_aclk; // | |
| 73 | input tcu_bclk; // | |
| 74 | input tcu_array_wr_inhibit; // | |
| 75 | output scan_out; // | |
| 76 | ||
| 77 | ||
| 78 | // | |
| 79 | input [5:0] rd_addr; // read address in | |
| 80 | input [5:0] wr_addr; // write address in | |
| 81 | input wr_en; // write enable | |
| 82 | input rd_en; // read enable | |
| 83 | input lkup_en; // CAM operation request | |
| 84 | input hld; // output holds its current value | |
| 85 | input [32:0] key; // look up address for CAM operation | |
| 86 | input [32:0] din; // data in | |
| 87 | output [32:0] dout; // data out | |
| 88 | output [63:0] hit; // results of CAM operation | |
| 89 | ||
| 90 | ||
| 91 | //------------------------------------------------------------------------ | |
| 92 | // scan chain connections | |
| 93 | //------------------------------------------------------------------------ | |
| 94 | // scan renames | |
| 95 | wire [1:0] siclk,soclk; | |
| 96 | wire se,wr_inhibit_array,and_clk; | |
| 97 | assign wr_inhibit_array = tcu_array_wr_inhibit; | |
| 98 | // end scan | |
| 99 | //------------------------------------------------------------------------ | |
| 100 | // instantiate clock headers | |
| 101 | //------------------------------------------------------------------------ | |
| 102 | wire [1:0] collar_clk; | |
| 103 | wire stop = 1'b0; | |
| 104 | wire aclk = tcu_aclk; | |
| 105 | wire bclk = tcu_bclk; | |
| 106 | assign se = tcu_se_scancollar_in; // TEMP | |
| 107 | ||
| 108 | cl_dp1_l1hdr_8x clk_hdr_ctrl ( | |
| 109 | .l2clk(clk), | |
| 110 | .pce (pce), | |
| 111 | .l1clk(collar_clk[0]), | |
| 112 | .siclk_out(siclk[0]), | |
| 113 | .soclk_out(soclk[0]), | |
| 114 | .se(se), | |
| 115 | .pce_ov(tcu_pce_ov), | |
| 116 | .stop(stop), | |
| 117 | .aclk(aclk), | |
| 118 | .bclk(bclk) | |
| 119 | ); | |
| 120 | ||
| 121 | cl_dp1_l1hdr_8x clk_hdr_data ( | |
| 122 | .l2clk(clk), | |
| 123 | .pce (pce), | |
| 124 | .l1clk(collar_clk[1]), | |
| 125 | .siclk_out(siclk[1]), | |
| 126 | .soclk_out(soclk[1]), | |
| 127 | .se(se), | |
| 128 | .pce_ov(tcu_pce_ov), | |
| 129 | .stop(stop), | |
| 130 | .aclk(aclk), | |
| 131 | .bclk(bclk) | |
| 132 | ); | |
| 133 | ||
| 134 | cl_dp1_l1hdr_8x clk_hdr_array ( | |
| 135 | .l2clk(clk), | |
| 136 | .pce (pce), | |
| 137 | .l1clk(and_clk), | |
| 138 | .siclk_out(), | |
| 139 | .soclk_out(), | |
| 140 | .se(tcu_scan_en), | |
| 141 | .pce_ov(tcu_pce_ov), | |
| 142 | .stop(stop), | |
| 143 | .aclk(aclk), | |
| 144 | .bclk(bclk) | |
| 145 | ); | |
| 146 | ||
| 147 | ||
| 148 | //------------------------------------------------------------------------ | |
| 149 | // input flops | |
| 150 | //------------------------------------------------------------------------ | |
| 151 | wire [5:0] rd_addr_array,rd_addr_so; | |
| 152 | wire [5:0] wr_addr_array,wr_addr_so; | |
| 153 | wire hld_array,wr_en_array,rd_en_array,lkup_en_array; | |
| 154 | wire hld_so,lkup_en_so; | |
| 155 | wire wr_en_so,rd_en_so; | |
| 156 | wire [32:0] din_array,din_so,key_array; | |
| 157 | wire [32:0] key_so; | |
| 158 | wire [63:0] hit_array; | |
| 159 | ||
| 160 | ||
| 161 | cl_sc1_msff_8x din_0 ( .si(scan_in), .so(din_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[0]), .q(din_array[0]) ); | |
| 162 | cl_sc1_msff_8x din_1 ( .si(din_so[0]), .so(din_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[1]), .q(din_array[1]) ); | |
| 163 | cl_sc1_msff_8x din_2 ( .si(din_so[1]), .so(din_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[2]), .q(din_array[2]) ); | |
| 164 | cl_sc1_msff_8x din_3 ( .si(din_so[2]), .so(din_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[3]), .q(din_array[3]) ); | |
| 165 | cl_sc1_msff_8x din_4 ( .si(din_so[3]), .so(din_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[4]), .q(din_array[4]) ); | |
| 166 | cl_sc1_msff_8x din_5 ( .si(din_so[4]), .so(din_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[5]), .q(din_array[5]) ); | |
| 167 | cl_sc1_msff_8x din_6 ( .si(din_so[5]), .so(din_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[6]), .q(din_array[6]) ); | |
| 168 | cl_sc1_msff_8x din_7 ( .si(din_so[6]), .so(din_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[7]), .q(din_array[7]) ); | |
| 169 | cl_sc1_msff_8x din_8 ( .si(din_so[7]), .so(din_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[8]), .q(din_array[8]) ); | |
| 170 | cl_sc1_msff_8x din_9 ( .si(din_so[8]), .so(din_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[9]), .q(din_array[9]) ); | |
| 171 | cl_sc1_msff_8x din_10 ( .si(din_so[9]), .so(din_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[10]), .q(din_array[10]) ); | |
| 172 | cl_sc1_msff_8x din_11 ( .si(din_so[10]), .so(din_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[11]), .q(din_array[11]) ); | |
| 173 | cl_sc1_msff_8x din_12 ( .si(din_so[11]), .so(din_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[12]), .q(din_array[12]) ); | |
| 174 | cl_sc1_msff_8x din_13 ( .si(din_so[12]), .so(din_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[13]), .q(din_array[13]) ); | |
| 175 | cl_sc1_msff_8x din_14 ( .si(din_so[13]), .so(din_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[14]), .q(din_array[14]) ); | |
| 176 | cl_sc1_msff_8x din_15 ( .si(din_so[14]), .so(din_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[15]), .q(din_array[15]) ); | |
| 177 | cl_sc1_msff_8x din_16 ( .si(din_so[15]), .so(din_so[16]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[16]), .q(din_array[16]) ); | |
| 178 | cl_sc1_msff_8x din_17 ( .si(din_so[16]), .so(din_so[17]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[17]), .q(din_array[17]) ); | |
| 179 | cl_sc1_msff_8x din_18 ( .si(din_so[17]), .so(din_so[18]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[18]), .q(din_array[18]) ); | |
| 180 | cl_sc1_msff_8x din_19 ( .si(din_so[18]), .so(din_so[19]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[19]), .q(din_array[19]) ); | |
| 181 | cl_sc1_msff_8x din_20 ( .si(din_so[19]), .so(din_so[20]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[20]), .q(din_array[20]) ); | |
| 182 | cl_sc1_msff_8x din_21 ( .si(din_so[20]), .so(din_so[21]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[21]), .q(din_array[21]) ); | |
| 183 | cl_sc1_msff_8x din_22 ( .si(din_so[21]), .so(din_so[22]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[22]), .q(din_array[22]) ); | |
| 184 | cl_sc1_msff_8x din_23 ( .si(din_so[22]), .so(din_so[23]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[23]), .q(din_array[23]) ); | |
| 185 | cl_sc1_msff_8x din_24 ( .si(din_so[23]), .so(din_so[24]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[24]), .q(din_array[24]) ); | |
| 186 | cl_sc1_msff_8x din_25 ( .si(din_so[24]), .so(din_so[25]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[25]), .q(din_array[25]) ); | |
| 187 | cl_sc1_msff_8x din_26 ( .si(din_so[25]), .so(din_so[26]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[26]), .q(din_array[26]) ); | |
| 188 | cl_sc1_msff_8x din_27 ( .si(din_so[26]), .so(din_so[27]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[27]), .q(din_array[27]) ); | |
| 189 | cl_sc1_msff_8x din_28 ( .si(din_so[27]), .so(din_so[28]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[28]), .q(din_array[28]) ); | |
| 190 | cl_sc1_msff_8x din_29 ( .si(din_so[28]), .so(din_so[29]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[29]), .q(din_array[29]) ); | |
| 191 | cl_sc1_msff_8x din_30 ( .si(din_so[29]), .so(din_so[30]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[30]), .q(din_array[30]) ); | |
| 192 | cl_sc1_msff_8x din_31 ( .si(din_so[30]), .so(din_so[31]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[31]), .q(din_array[31]) ); | |
| 193 | cl_sc1_msff_8x din_32 ( .si(din_so[31]), .so(din_so[32]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[32]), .q(din_array[32]) ); | |
| 194 | ||
| 195 | cl_mc1_scm_msff_lat_4x key_32 ( .si(din_so[32]), .so(key_so[32]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[32]), .latout(key_array[32]) ); | |
| 196 | cl_mc1_scm_msff_lat_4x key_31 ( .si(key_so[32]), .so(key_so[31]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[31]), .latout(key_array[31]) ); | |
| 197 | cl_mc1_scm_msff_lat_4x key_30 ( .si(key_so[31]), .so(key_so[30]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[30]), .latout(key_array[30]) ); | |
| 198 | cl_mc1_scm_msff_lat_4x key_29 ( .si(key_so[30]), .so(key_so[29]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[29]), .latout(key_array[29]) ); | |
| 199 | cl_mc1_scm_msff_lat_4x key_28 ( .si(key_so[29]), .so(key_so[28]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[28]), .latout(key_array[28]) ); | |
| 200 | ||
| 201 | cl_mc1_scm_msff_lat_4x ff_lkup_en ( .si(key_so[28]), .so(lkup_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(lkup_en), .latout(lkup_en_array) ); | |
| 202 | ||
| 203 | cl_mc1_scm_msff_lat_4x key_27 ( .si(lkup_en_so), .so(key_so[27]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[27]), .latout(key_array[27]) ); | |
| 204 | cl_mc1_scm_msff_lat_4x key_26 ( .si(key_so[27]), .so(key_so[26]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[26]), .latout(key_array[26]) ); | |
| 205 | cl_mc1_scm_msff_lat_4x key_25 ( .si(key_so[26]), .so(key_so[25]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[25]), .latout(key_array[25]) ); | |
| 206 | cl_mc1_scm_msff_lat_4x key_24 ( .si(key_so[25]), .so(key_so[24]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[24]), .latout(key_array[24]) ); | |
| 207 | cl_mc1_scm_msff_lat_4x key_23 ( .si(key_so[24]), .so(key_so[23]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[23]), .latout(key_array[23]) ); | |
| 208 | cl_mc1_scm_msff_lat_4x key_22 ( .si(key_so[23]), .so(key_so[22]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[22]), .latout(key_array[22]) ); | |
| 209 | cl_mc1_scm_msff_lat_4x key_21 ( .si(key_so[22]), .so(key_so[21]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[21]), .latout(key_array[21]) ); | |
| 210 | cl_mc1_scm_msff_lat_4x key_20 ( .si(key_so[21]), .so(key_so[20]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[20]), .latout(key_array[20]) ); | |
| 211 | cl_mc1_scm_msff_lat_4x key_19 ( .si(key_so[20]), .so(key_so[19]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[19]), .latout(key_array[19]) ); | |
| 212 | cl_mc1_scm_msff_lat_4x key_18 ( .si(key_so[19]), .so(key_so[18]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[18]), .latout(key_array[18]) ); | |
| 213 | cl_mc1_scm_msff_lat_4x key_17 ( .si(key_so[18]), .so(key_so[17]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[17]), .latout(key_array[17]) ); | |
| 214 | cl_mc1_scm_msff_lat_4x key_16 ( .si(key_so[17]), .so(key_so[16]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[16]), .latout(key_array[16]) ); | |
| 215 | cl_mc1_scm_msff_lat_4x key_15 ( .si(key_so[16]), .so(key_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[15]), .latout(key_array[15]) ); | |
| 216 | cl_mc1_scm_msff_lat_4x key_14 ( .si(key_so[15]), .so(key_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[14]), .latout(key_array[14]) ); | |
| 217 | cl_mc1_scm_msff_lat_4x key_13 ( .si(key_so[14]), .so(key_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[13]), .latout(key_array[13]) ); | |
| 218 | cl_mc1_scm_msff_lat_4x key_12 ( .si(key_so[13]), .so(key_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[12]), .latout(key_array[12]) ); | |
| 219 | cl_mc1_scm_msff_lat_4x key_11 ( .si(key_so[12]), .so(key_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[11]), .latout(key_array[11]) ); | |
| 220 | cl_mc1_scm_msff_lat_4x key_10 ( .si(key_so[11]), .so(key_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[10]), .latout(key_array[10]) ); | |
| 221 | cl_mc1_scm_msff_lat_4x key_9 ( .si(key_so[10]), .so(key_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[9]), .latout(key_array[9]) ); | |
| 222 | cl_mc1_scm_msff_lat_4x key_8 ( .si(key_so[9]), .so(key_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[8]), .latout(key_array[8]) ); | |
| 223 | cl_mc1_scm_msff_lat_4x key_7 ( .si(key_so[8]), .so(key_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[7]), .latout(key_array[7]) ); | |
| 224 | cl_mc1_scm_msff_lat_4x key_6 ( .si(key_so[7]), .so(key_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[6]), .latout(key_array[6]) ); | |
| 225 | cl_mc1_scm_msff_lat_4x key_5 ( .si(key_so[6]), .so(key_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[5]), .latout(key_array[5]) ); | |
| 226 | cl_mc1_scm_msff_lat_4x key_4 ( .si(key_so[5]), .so(key_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[4]), .latout(key_array[4]) ); | |
| 227 | cl_mc1_scm_msff_lat_4x key_3 ( .si(key_so[4]), .so(key_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[3]), .latout(key_array[3]) ); | |
| 228 | cl_mc1_scm_msff_lat_4x key_2 ( .si(key_so[3]), .so(key_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[2]), .latout(key_array[2]) ); | |
| 229 | cl_mc1_scm_msff_lat_4x key_1 ( .si(key_so[2]), .so(key_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[1]), .latout(key_array[1]) ); | |
| 230 | cl_mc1_scm_msff_lat_4x key_0 ( .si(key_so[1]), .so(key_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(key[0]), .latout(key_array[0]) ); | |
| 231 | ||
| 232 | cl_mc1_scm_msff_lat_4x ff_rd_en ( .si(key_so[0]), .so(rd_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_en), .latout(rd_en_array) ); | |
| 233 | ||
| 234 | cl_sc1_msff_8x ff_wr_en ( .si(rd_en_so), .so(wr_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_en), .q(wr_en_array) ); | |
| 235 | ||
| 236 | cl_mc1_scm_msff_lat_4x rd_addr_so_0 ( .si(wr_en_so), .so(rd_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_addr[0]), .latout(rd_addr_array[0]) ); | |
| 237 | cl_sc1_msff_8x wr_addr_so_0 ( .si(rd_addr_so[0]), .so(wr_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_addr[0]), .q(wr_addr_array[0]) ); | |
| 238 | cl_sc1_msff_8x wr_addr_so_1 ( .si(wr_addr_so[0]), .so(wr_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_addr[1]), .q(wr_addr_array[1]) ); | |
| 239 | cl_mc1_scm_msff_lat_4x rd_addr_so_1 ( .si(wr_addr_so[1]), .so(rd_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_addr[1]), .latout(rd_addr_array[1]) ); | |
| 240 | cl_mc1_scm_msff_lat_4x rd_addr_so_2 ( .si(rd_addr_so[1]), .so(rd_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_addr[2]), .latout(rd_addr_array[2]) ); | |
| 241 | cl_sc1_msff_8x wr_addr_so_2 ( .si(rd_addr_so[2]), .so(wr_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_addr[2]), .q(wr_addr_array[2]) ); | |
| 242 | cl_sc1_msff_8x wr_addr_so_3 ( .si(wr_addr_so[2]), .so(wr_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_addr[3]), .q(wr_addr_array[3]) ); | |
| 243 | cl_mc1_scm_msff_lat_4x rd_addr_so_3 ( .si(wr_addr_so[3]), .so(rd_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_addr[3]), .latout(rd_addr_array[3]) ); | |
| 244 | cl_mc1_scm_msff_lat_4x rd_addr_so_4 ( .si(rd_addr_so[3]), .so(rd_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_addr[4]), .latout(rd_addr_array[4]) ); | |
| 245 | cl_sc1_msff_8x wr_addr_so_4 ( .si(rd_addr_so[4]), .so(wr_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_addr[4]), .q(wr_addr_array[4]) ); | |
| 246 | cl_sc1_msff_8x wr_addr_so_5 ( .si(wr_addr_so[4]), .so(wr_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(wr_addr[5]), .q(wr_addr_array[5]) ); | |
| 247 | cl_mc1_scm_msff_lat_4x rd_addr_so_5 ( .si(wr_addr_so[5]), .so(rd_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(rd_addr[5]), .latout(rd_addr_array[5]) ); | |
| 248 | ||
| 249 | cl_mc1_scm_msff_lat_4x ff_hld ( .si(rd_addr_so[5]), .so(scan_out), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), .d(hld), .latout(hld_array) ); | |
| 250 | ||
| 251 | wire x1_,wr_array, rd_array; | |
| 252 | //assign rd_array = !wr_inhibit_array & rd_en_array; | |
| 253 | not rd2 (x1_,wr_inhibit_array); | |
| 254 | and rd1 (rd_array,rd_en_array,x1_); | |
| 255 | ||
| 256 | //assign wr_array = !wr_inhibit_array & wr_en_array; | |
| 257 | and wr1 (wr_array,wr_en_array,x1_); | |
| 258 | ||
| 259 | wire lkup_array; | |
| 260 | //assign lkup_array = !(wr_inhibit_array) & lkup_en_array; | |
| 261 | and lkup1 (lkup_array,lkup_en_array,x1_); | |
| 262 | ||
| 263 | wire inhibit_array; | |
| 264 | //assign inhibit_array = wr_inhibit_array | hld_array; | |
| 265 | or inhibit1 (inhibit_array,wr_inhibit_array,hld_array); | |
| 266 | ||
| 267 | ||
| 268 | //------------------------------------------------------------------------ | |
| 269 | // instantiate the clock-less ram | |
| 270 | //------------------------------------------------------------------------ | |
| 271 | wire [32:0] dout_array; | |
| 272 | n2_mmu_cm_64x34s_cust_array mmu_cam_vtb( | |
| 273 | .clk (and_clk), | |
| 274 | .l2clk (clk), | |
| 275 | .rd_addr_array (rd_addr_array[5:0]), | |
| 276 | .wr_addr_array (wr_addr_array[5:0]), | |
| 277 | .wr_array (wr_array), | |
| 278 | .rd_array (rd_array), | |
| 279 | .lkup_en_array (lkup_array), | |
| 280 | .hld_array (inhibit_array), | |
| 281 | .din_array (din_array[32:0]), | |
| 282 | .key_array (key_array[32:0]), | |
| 283 | .hit_array (hit_array[63:0]), | |
| 284 | .dout_array (dout_array[32:0]) | |
| 285 | ); | |
| 286 | ||
| 287 | assign dout[32:0] = dout_array[32:0]; | |
| 288 | assign hit = hit_array[63:0] ; | |
| 289 | ||
| 290 | ||
| 291 | ||
| 292 | endmodule //n2_mmu_cm_64x34s_cust | |
| 293 | ||
| 294 | ||
| 295 | ||
| 296 | module n2_mmu_cm_64x34s_cust_array ( | |
| 297 | ||
| 298 | // ram control | |
| 299 | clk, | |
| 300 | l2clk, | |
| 301 | rd_addr_array, | |
| 302 | wr_addr_array, | |
| 303 | wr_array, | |
| 304 | rd_array, | |
| 305 | lkup_en_array, | |
| 306 | hld_array, | |
| 307 | din_array, | |
| 308 | key_array, | |
| 309 | hit_array, | |
| 310 | dout_array | |
| 311 | ||
| 312 | ); | |
| 313 | ||
| 314 | ||
| 315 | ||
| 316 | ||
| 317 | // | |
| 318 | input clk,l2clk; // clk | |
| 319 | input [5:0] rd_addr_array; // read port address in | |
| 320 | input [5:0] wr_addr_array; // write port address in | |
| 321 | input wr_array; // write port enable | |
| 322 | input rd_array; // read port enable | |
| 323 | input lkup_en_array; // enable CAM operation | |
| 324 | input hld_array; // enable CAM operation | |
| 325 | input [32:0] din_array; // data in | |
| 326 | input [32:0] key_array; // value to CAM against | |
| 327 | output [32:0] dout_array; // data out | |
| 328 | output [63:0] hit_array; // results of CAM operation | |
| 329 | ||
| 330 | integer i; | |
| 331 | // ---------------------------------------------------------------------------- | |
| 332 | // Zero In Checkers | |
| 333 | // ---------------------------------------------------------------------------- | |
| 334 | // checker to verify on accesses's that no bits are x | |
| 335 | /* //BP 0in assert -var (((|rd_addr_array[6:0] ) == 1'bx) | |
| 336 | || ((|wr_addr_array[6:0] ) == 1'bx) | |
| 337 | || ((wr_en_array ) == 1'bx)) | |
| 338 | -active (rd_array | wr_array) | |
| 339 | -module dmu_ram128x132_array | |
| 340 | -name dmu_ram128x132_array_x | |
| 341 | */ | |
| 342 | // 0in kndr -var rd_addr_array | |
| 343 | // 0in kndr -var wr_addr_array | |
| 344 | // 0in kndr -var wr_array | |
| 345 | // 0in kndr -var rd_array | |
| 346 | // 0in kndr -var lkup_en_array | |
| 347 | // 0in kndr -var din_array -active (wr_array ) | |
| 348 | ||
| 349 | ||
| 350 | /* RAM Array: =128 - 1 -> 127 */ | |
| 351 | ||
| 352 | reg [32:0] tag [0:63]; | |
| 353 | reg [63:0] hit_array; | |
| 354 | reg [32:0] dout_array; | |
| 355 | ||
| 356 | // Initialize the arrays | |
| 357 | `ifndef NOINITMEM | |
| 358 | initial begin | |
| 359 | for (i=0; i<64; i=i+1) begin | |
| 360 | tag[i] = 33'b0; | |
| 361 | end | |
| 362 | hit_array = 64'b0; | |
| 363 | end | |
| 364 | `endif | |
| 365 | ||
| 366 | ||
| 367 | ||
| 368 | // ---------------------------------------------------------------------------- | |
| 369 | // Read the array | |
| 370 | // ---------------------------------------------------------------------------- | |
| 371 | //assign dout_array[131:0] = array_ram[rd_addr_array[6:0]]; | |
| 372 | reg read_flag; | |
| 373 | always @(clk or rd_addr_array or rd_array or wr_array or wr_addr_array or l2clk) begin | |
| 374 | read_flag <=0; | |
| 375 | if (clk & l2clk) begin | |
| 376 | if (rd_array) begin | |
| 377 | read_flag <=1; | |
| 378 | if (wr_array & (rd_addr_array == wr_addr_array)) begin | |
| 379 | dout_array[32:0] <= {33{1'bx}}; //0in <fire -severity 1 -message " got x's in dmu cam" -group mbist_mode | |
| 380 | end | |
| 381 | else begin | |
| 382 | dout_array <= tag[rd_addr_array[5:0]]; | |
| 383 | end | |
| 384 | end | |
| 385 | end | |
| 386 | end | |
| 387 | ||
| 388 | ||
| 389 | ||
| 390 | // ---------------------------------------------------------------------------- | |
| 391 | // Write the array, note: it is written when the clock is low | |
| 392 | // ---------------------------------------------------------------------------- | |
| 393 | reg write_flag; | |
| 394 | always @ ( clk or lkup_en_array or hld_array or l2clk or | |
| 395 | wr_addr_array or din_array or key_array or wr_array) begin | |
| 396 | write_flag<=0; | |
| 397 | if(~clk & ~l2clk) begin | |
| 398 | if (wr_array ) begin | |
| 399 | write_flag<=1; | |
| 400 | tag[wr_addr_array] <= din_array; | |
| 401 | end | |
| 402 | end | |
| 403 | ||
| 404 | if(clk & l2clk) begin | |
| 405 | for (i = 0; i < 64; i = i + 1) begin | |
| 406 | if (~hld_array ) begin | |
| 407 | hit_array[i] <= lkup_en_array & (key_array == tag[i]); | |
| 408 | end | |
| 409 | end | |
| 410 | end | |
| 411 | end | |
| 412 | ||
| 413 | ||
| 414 | ||
| 415 | endmodule // n2_mmu_cm_64x34s_cust_array | |
| 416 | ||
| 417 |