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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_niu_dp_256x152s_cust_l / n2_niu_dp_256x152s_cust / rtl / n2_niu_dp_256x152s_cust.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_niu_dp_256x152s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_niu_dp_256x152s_cust (
36 reset,
37 tcu_aclk,
38 tcu_bclk,
39 tcu_scan_en,
40 tcu_se_scancollar_in,
41 tcu_se_scancollar_out,
42 tcu_pce_ov,
43 pce,
44 tcu_array_wr_inhibit,
45 scan_in,
46 scan_out,
47 hdr_sram_rvalue,
48 hdr_sram_rid,
49 hdr_sram_wr_en,
50 hdr_sram_red_clr,
51 sram_hdr_read_data,
52 wr_adr,
53 wr_en,
54 rd_adr,
55 rd_en,
56 din,
57 dout,
58 l2clk_2x,
59 l2clk);
60wire bank_scanout;
61wire repair_en_b0;
62wire repair_en_b1;
63wire repair_en_b2;
64wire repair_en_b3;
65
66
67
68input reset;
69input tcu_aclk;
70input tcu_bclk;
71input tcu_scan_en;
72input tcu_se_scancollar_in;
73input tcu_se_scancollar_out;
74input tcu_pce_ov;
75input pce;
76input tcu_array_wr_inhibit;
77input scan_in;
78output scan_out;
79
80input [6:0] hdr_sram_rvalue;
81input [1:0] hdr_sram_rid;
82input hdr_sram_wr_en;
83input hdr_sram_red_clr;
84output [6:0] sram_hdr_read_data;
85
86input [7:0] wr_adr;
87input wr_en;
88input [7:0] rd_adr;
89input rd_en;
90input [151:0] din;
91output [151:0] dout;
92input l2clk_2x;
93input l2clk;
94
95wire [6:0] sram_hdr_read_data;
96wire [6:0] hdr_sram_rvalue;
97wire [7:0] wr_adr;
98wire [7:0] rd_adr;
99wire [151:0] din;
100wire [151:0] dout;
101
102
103wire [5:0] red_value_b0; // to subbank
104wire [5:0] red_value_b1;
105wire [5:0] red_value_b2;
106wire [5:0] red_value_b3;
107
108
109 n2_niu_dp_256x152s_bank niu_dp_256x152s_bank_0 (
110 .reset (reset),
111 .tcu_aclk (tcu_aclk),
112 .tcu_bclk (tcu_bclk),
113 .pce (pce),
114 .tcu_pce_ov (tcu_pce_ov),
115 .tcu_scan_en (tcu_scan_en),
116 .tcu_se_scancollar_in (tcu_se_scancollar_in),
117 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
118 .l2clk (l2clk),
119 .l2clk_2x (l2clk_2x),
120 .wr_adr (wr_adr),
121 .wr_en (wr_en),
122 .rd_adr (rd_adr),
123 .rd_en (rd_en),
124 .din (din),
125 .scan_in (scan_in),
126 .scan_out (bank_scanout),
127 .red_v_br (red_value_b0),
128 .red_v_bl (red_value_b1),
129 .red_v_tr (red_value_b2),
130 .red_v_tl (red_value_b3),
131 .red_en_br (repair_en_b0),
132 .red_en_bl (repair_en_b1),
133 .red_en_tr (repair_en_b2),
134 .red_en_tl (repair_en_b3),
135 .dout (dout)
136 );
137
138 n2_niu_dp_256x152s_repair niu_dp_256x152s_repair_0 (
139 .tcu_aclk (tcu_aclk),
140 .tcu_bclk (tcu_bclk),
141 .tcu_scan_en (tcu_scan_en),
142 .pce (pce),
143 .tcu_pce_ov (tcu_pce_ov),
144 .tcu_se_scancollar_in (tcu_se_scancollar_in),
145 .tcu_se_scancollar_out (tcu_se_scancollar_out),
146 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
147 .scan_in (bank_scanout),
148 .hdr_sram_rvalue (hdr_sram_rvalue),
149 .hdr_sram_rid (hdr_sram_rid),
150 .hdr_sram_wr_en (hdr_sram_wr_en),
151 .hdr_sram_red_clr (hdr_sram_red_clr),
152 .l2clk (l2clk),
153 .sram_hdr_read_data (sram_hdr_read_data),
154 .red_value_b0 (red_value_b0), // to subbank
155 .red_value_b1 (red_value_b1),
156 .red_value_b2 (red_value_b2),
157 .red_value_b3 (red_value_b3),
158 .repair_en_bk ({repair_en_b3,repair_en_b2,repair_en_b1,repair_en_b0}),
159 .scan_out (scan_out)
160 );
161
162
163
164endmodule
165
166
167
168module n2_niu_dp_256x152s_bank (
169 reset,
170 din,
171 wr_adr,
172 rd_adr,
173 rd_en,
174 wr_en,
175 tcu_aclk,
176 tcu_bclk,
177 pce,
178 tcu_pce_ov,
179 tcu_scan_en,
180 tcu_se_scancollar_in,
181 tcu_array_wr_inhibit,
182 l2clk,
183 l2clk_2x,
184 scan_in,
185 red_v_br,
186 red_v_bl,
187 red_v_tr,
188 red_v_tl,
189 red_en_br,
190 red_en_bl,
191 red_en_tr,
192 red_en_tl,
193 dout,
194 scan_out);
195wire l1clk_in_en;
196wire l1clk_in;
197wire l1clk_gate_en;
198wire l1clk_gate;
199wire [8:0] dff_wr_adr_m_scanout;
200wire [8:0] dff_rd_adr_m_scanout;
201wire dff_rd_en_m_scanin;
202wire dff_rd_en_m_scanout;
203wire dff_wr_en_m_scanin;
204wire dff_wr_en_m_scanout;
205wire test_mode;
206wire dff_test_mode_scanin;
207wire dff_test_mode_scanout;
208wire test_clk;
209wire dff_test_clk_scanin;
210wire dff_test_clk_scanout;
211wire do_A_read_2x_a;
212wire do_B_write_2x_a;
213wire [151:0] wdata_2x_b;
214
215
216input reset;
217input [151:0] din;
218input [7:0] wr_adr;
219input [7:0] rd_adr;
220input rd_en;
221input wr_en;
222input tcu_aclk;
223input tcu_bclk;
224input pce;
225input tcu_pce_ov;
226input tcu_scan_en;
227input tcu_se_scancollar_in;
228input tcu_array_wr_inhibit;
229input l2clk;
230input l2clk_2x;
231input scan_in;
232
233input [5:0] red_v_br;
234input [5:0] red_v_bl;
235input [5:0] red_v_tr;
236input [5:0] red_v_tl;
237input red_en_br;
238input red_en_bl;
239input red_en_tr;
240input red_en_tl;
241
242output [151:0] dout;
243output scan_out;
244
245
246
247wire [5:0] red_value_b0;
248wire [5:0] red_value_b1;
249wire [5:0] red_value_b2;
250wire [5:0] red_value_b3;
251wire [3:0] repair_en_bk;
252wire [151:0] dout; //
253
254
255// scan renames
256// end scan
257
258wire rd_en_a;
259wire wr_en_a;
260wire [151:0] wdata_b;
261wire [8:0] addr_a;
262
263wire wcs_a;
264
265wire [37:0] din_br;
266wire [37:0] din_tr;
267wire [37:0] din_bl;
268wire [37:0] din_tl;
269
270wire [151:0] rd_dout;
271
272wire [3:0] rd_en_column;
273wire [3:0] wt_en_column;
274
275wire [37:0] ary_rdout_br;
276wire [37:0] ary_rdout_tr;
277wire [37:0] ary_rdout_bl;
278wire [37:0] ary_rdout_tl;
279
280wire siclk, soclk;
281assign siclk = tcu_aclk;
282assign soclk = tcu_bclk;
283
284
285//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
286//================================================
287// l2 clock Domain: Clock headers
288//================================================
289//cl_sc1_l1hdr_8x l1ch_in (
290// .l1clk (l1clk_in),
291// .l2clk (l2clk),
292// .se (tcu_se_scancollar_in),
293// .pce (pce),
294// .pce_ov (tcu_pce_ov),
295// .stop (1'b0)
296// );
297
298//cl_sc1_l1hdr_8x l1ch_gate (
299// .l1clk (l1clk_gate),
300// .l2clk (l2clk),
301// .se (tcu_scan_en),
302// .pce (pce),
303// .pce_ov (tcu_pce_ov),
304// .stop (1'b0)
305// );
306
307///////////////////////////////////
308// decomposed l1hdr for l1clk_in
309///////////////////////////////////
310
311cl_mc1_l1enable_12x l1ch_in_l1en (
312 .l2clk (l2clk),
313 .pce (pce),
314 .pce_ov (tcu_pce_ov),
315 .l1en (l1clk_in_en)
316 );
317
318cl_mc1_l1driver_12x l1ch_in_l1drvr (
319 .se (tcu_se_scancollar_in),
320 .l1en (l1clk_in_en),
321 .l1clk (l1clk_in),
322 .l2clk(l2clk)
323 );
324
325///////////////////////////////////
326// decomposed l1hdr for l1clk_gate
327///////////////////////////////////
328
329cl_mc1_l1enable_12x l1ch_gate_l1en (
330 .l2clk (l2clk),
331 .pce (pce),
332 .pce_ov (tcu_pce_ov),
333 .l1en (l1clk_gate_en)
334 );
335
336cl_mc1_l1driver_12x l1ch_gate_l1drvr (
337 .se (tcu_scan_en),
338 .l1en (l1clk_gate_en),
339 .l1clk (l1clk_gate),
340 .l2clk(l2clk)
341 );
342
343
344
345//================================================
346// l2 clock Domain: Input flops
347//================================================
348
349// ------------ controls_ph.a register --------------
350/****************************************************
351//reg [8:0] rd_adr_m;
352//reg [8:0] wr_adr_m;
353//reg rd_en_m;
354//reg wr_en_m;
355//
356// always @(posedge l1clk_in) begin
357// rd_adr_m <= rd_adr;
358// wr_adr_m <= wr_adr;
359// rd_en_m <= rd_en;
360// wr_en_m <= wr_en;
361// end
362
363*****************************************************/
364wire [8:0] rd_adr_m;
365wire [8:0] wr_adr_m;
366wire rd_en_m;
367wire wr_en_m;
368wire reset_l;
369wire [151:0] din_m;
370wire [8:0] dff_wr_adr_m_scanin;
371wire [8:0] dff_rd_adr_m_scanin;
372
373assign reset_l = ~reset;
374
375// msff_ctl_macro dff_ctrls_m (width=(9*2+2), clr_=1) (
376// .scan_in (scan_in),
377// .scan_out (dff_ctrls_m_scanout),
378// .clr_ (reset_l),
379// .l1clk (l1clk_in),
380// .din ({rd_en, wr_en, rd_adr[8:0], wr_adr[8:0]}),
381// .dout ({rd_en_m,wr_en_m,rd_adr_m[8:0],wr_adr_m[8:0]}) );
382
383
384 cl_sc1_msff_syrst_4x wr_adr_m00 (.d(wr_adr[0]), .si(dff_wr_adr_m_scanin[0]), .q(wr_adr_m[0]), .so(dff_wr_adr_m_scanout[0]),
385 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
386 cl_sc1_msff_syrst_4x wr_adr_m01 (.d(wr_adr[1]), .si(dff_wr_adr_m_scanin[1]), .q(wr_adr_m[1]), .so(dff_wr_adr_m_scanout[1]),
387 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
388 cl_sc1_msff_syrst_4x wr_adr_m02 (.d(wr_adr[2]), .si(dff_wr_adr_m_scanin[2]), .q(wr_adr_m[2]), .so(dff_wr_adr_m_scanout[2]),
389 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
390 cl_sc1_msff_syrst_4x wr_adr_m03 (.d(wr_adr[3]), .si(dff_wr_adr_m_scanin[3]), .q(wr_adr_m[3]), .so(dff_wr_adr_m_scanout[3]),
391 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
392 cl_sc1_msff_syrst_4x wr_adr_m04 (.d(wr_adr[4]), .si(dff_wr_adr_m_scanin[4]), .q(wr_adr_m[4]), .so(dff_wr_adr_m_scanout[4]),
393 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
394 cl_sc1_msff_syrst_4x wr_adr_m05 (.d(wr_adr[5]), .si(dff_wr_adr_m_scanin[5]), .q(wr_adr_m[5]), .so(dff_wr_adr_m_scanout[5]),
395 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
396 cl_sc1_msff_syrst_4x wr_adr_m06 (.d(wr_adr[6]), .si(dff_wr_adr_m_scanin[6]), .q(wr_adr_m[6]), .so(dff_wr_adr_m_scanout[6]),
397 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
398 cl_sc1_msff_syrst_4x wr_adr_m07 (.d(wr_adr[7]), .si(dff_wr_adr_m_scanin[7]), .q(wr_adr_m[7]), .so(dff_wr_adr_m_scanout[7]),
399 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
400 cl_sc1_msff_syrst_4x wr_adr_m08 (.d(1'b0), .si(dff_wr_adr_m_scanin[8]), .q(wr_adr_m[8]), .so(dff_wr_adr_m_scanout[8]),
401 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
402
403 cl_sc1_msff_syrst_4x rd_adr_m00 (.d(rd_adr[0]), .si(dff_rd_adr_m_scanin[0]), .q(rd_adr_m[0]), .so(dff_rd_adr_m_scanout[0]),
404 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
405 cl_sc1_msff_syrst_4x rd_adr_m01 (.d(rd_adr[1]), .si(dff_rd_adr_m_scanin[1]), .q(rd_adr_m[1]), .so(dff_rd_adr_m_scanout[1]),
406 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
407 cl_sc1_msff_syrst_4x rd_adr_m02 (.d(rd_adr[2]), .si(dff_rd_adr_m_scanin[2]), .q(rd_adr_m[2]), .so(dff_rd_adr_m_scanout[2]),
408 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
409 cl_sc1_msff_syrst_4x rd_adr_m03 (.d(rd_adr[3]), .si(dff_rd_adr_m_scanin[3]), .q(rd_adr_m[3]), .so(dff_rd_adr_m_scanout[3]),
410 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
411 cl_sc1_msff_syrst_4x rd_adr_m04 (.d(rd_adr[4]), .si(dff_rd_adr_m_scanin[4]), .q(rd_adr_m[4]), .so(dff_rd_adr_m_scanout[4]),
412 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
413 cl_sc1_msff_syrst_4x rd_adr_m05 (.d(rd_adr[5]), .si(dff_rd_adr_m_scanin[5]), .q(rd_adr_m[5]), .so(dff_rd_adr_m_scanout[5]),
414 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
415 cl_sc1_msff_syrst_4x rd_adr_m06 (.d(rd_adr[6]), .si(dff_rd_adr_m_scanin[6]), .q(rd_adr_m[6]), .so(dff_rd_adr_m_scanout[6]),
416 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
417 cl_sc1_msff_syrst_4x rd_adr_m07 (.d(rd_adr[7]), .si(dff_rd_adr_m_scanin[7]), .q(rd_adr_m[7]), .so(dff_rd_adr_m_scanout[7]),
418 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
419 cl_sc1_msff_syrst_4x rd_adr_m08 (.d(1'b0), .si(dff_rd_adr_m_scanin[8]), .q(rd_adr_m[8]), .so(dff_rd_adr_m_scanout[8]),
420 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
421
422 cl_sc1_msff_syrst_4x rd_en_m0 (.d(rd_en), .si(dff_rd_en_m_scanin), .q(rd_en_m), .so(dff_rd_en_m_scanout),
423 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
424 cl_sc1_msff_syrst_4x wr_en_m0 (.d(wr_en), .si(dff_wr_en_m_scanin), .q(wr_en_m), .so(dff_wr_en_m_scanout),
425 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
426
427// ------------ write_data_ph.a register ------------
428//
429//reg [151:0] din_m;
430//
431//
432// always @(posedge l1clk_in) begin
433// din_m <= din;
434// end
435
436// msff_ctl_macro dff_wdata_m (width=152, clr_=1) (
437// .scan_in (dff_ctrls_m_scanout),
438// .scan_out (dff_wdata_m_scanout),
439// .clr_ (reset_l),
440// .l1clk (l1clk_in),
441// .din (din[151:0]),
442// .dout (din_m[151:0]) );
443
444
445wire [151:0] dff_wdata_m_scanin, dff_wdata_m_scanout;
446
447 cl_sc1_msff_syrst_4x din_m000 (.d(din[0]), .si(dff_wdata_m_scanin[0]), .q(din_m[0]), .so(dff_wdata_m_scanout[0]),
448 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
449 cl_sc1_msff_syrst_4x din_m001 (.d(din[1]), .si(dff_wdata_m_scanin[1]), .q(din_m[1]), .so(dff_wdata_m_scanout[1]),
450 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
451 cl_sc1_msff_syrst_4x din_m002 (.d(din[2]), .si(dff_wdata_m_scanin[2]), .q(din_m[2]), .so(dff_wdata_m_scanout[2]),
452 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
453 cl_sc1_msff_syrst_4x din_m003 (.d(din[3]), .si(dff_wdata_m_scanin[3]), .q(din_m[3]), .so(dff_wdata_m_scanout[3]),
454 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
455 cl_sc1_msff_syrst_4x din_m004 (.d(din[4]), .si(dff_wdata_m_scanin[4]), .q(din_m[4]), .so(dff_wdata_m_scanout[4]),
456 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
457 cl_sc1_msff_syrst_4x din_m005 (.d(din[5]), .si(dff_wdata_m_scanin[5]), .q(din_m[5]), .so(dff_wdata_m_scanout[5]),
458 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
459 cl_sc1_msff_syrst_4x din_m006 (.d(din[6]), .si(dff_wdata_m_scanin[6]), .q(din_m[6]), .so(dff_wdata_m_scanout[6]),
460 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
461 cl_sc1_msff_syrst_4x din_m007 (.d(din[7]), .si(dff_wdata_m_scanin[7]), .q(din_m[7]), .so(dff_wdata_m_scanout[7]),
462 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
463 cl_sc1_msff_syrst_4x din_m008 (.d(din[8]), .si(dff_wdata_m_scanin[8]), .q(din_m[8]), .so(dff_wdata_m_scanout[8]),
464 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
465 cl_sc1_msff_syrst_4x din_m009 (.d(din[9]), .si(dff_wdata_m_scanin[9]), .q(din_m[9]), .so(dff_wdata_m_scanout[9]),
466 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
467
468 cl_sc1_msff_syrst_4x din_m010 (.d(din[10]), .si(dff_wdata_m_scanin[10]), .q(din_m[10]), .so(dff_wdata_m_scanout[10]),
469 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
470 cl_sc1_msff_syrst_4x din_m011 (.d(din[11]), .si(dff_wdata_m_scanin[11]), .q(din_m[11]), .so(dff_wdata_m_scanout[11]),
471 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
472 cl_sc1_msff_syrst_4x din_m012 (.d(din[12]), .si(dff_wdata_m_scanin[12]), .q(din_m[12]), .so(dff_wdata_m_scanout[12]),
473 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
474 cl_sc1_msff_syrst_4x din_m013 (.d(din[13]), .si(dff_wdata_m_scanin[13]), .q(din_m[13]), .so(dff_wdata_m_scanout[13]),
475 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
476 cl_sc1_msff_syrst_4x din_m014 (.d(din[14]), .si(dff_wdata_m_scanin[14]), .q(din_m[14]), .so(dff_wdata_m_scanout[14]),
477 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
478 cl_sc1_msff_syrst_4x din_m015 (.d(din[15]), .si(dff_wdata_m_scanin[15]), .q(din_m[15]), .so(dff_wdata_m_scanout[15]),
479 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
480 cl_sc1_msff_syrst_4x din_m016 (.d(din[16]), .si(dff_wdata_m_scanin[16]), .q(din_m[16]), .so(dff_wdata_m_scanout[16]),
481 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
482 cl_sc1_msff_syrst_4x din_m017 (.d(din[17]), .si(dff_wdata_m_scanin[17]), .q(din_m[17]), .so(dff_wdata_m_scanout[17]),
483 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
484 cl_sc1_msff_syrst_4x din_m018 (.d(din[18]), .si(dff_wdata_m_scanin[18]), .q(din_m[18]), .so(dff_wdata_m_scanout[18]),
485 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
486 cl_sc1_msff_syrst_4x din_m019 (.d(din[19]), .si(dff_wdata_m_scanin[19]), .q(din_m[19]), .so(dff_wdata_m_scanout[19]),
487 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
488
489 cl_sc1_msff_syrst_4x din_m020 (.d(din[20]), .si(dff_wdata_m_scanin[20]), .q(din_m[20]), .so(dff_wdata_m_scanout[20]),
490 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
491 cl_sc1_msff_syrst_4x din_m021 (.d(din[21]), .si(dff_wdata_m_scanin[21]), .q(din_m[21]), .so(dff_wdata_m_scanout[21]),
492 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
493 cl_sc1_msff_syrst_4x din_m022 (.d(din[22]), .si(dff_wdata_m_scanin[22]), .q(din_m[22]), .so(dff_wdata_m_scanout[22]),
494 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
495 cl_sc1_msff_syrst_4x din_m023 (.d(din[23]), .si(dff_wdata_m_scanin[23]), .q(din_m[23]), .so(dff_wdata_m_scanout[23]),
496 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
497 cl_sc1_msff_syrst_4x din_m024 (.d(din[24]), .si(dff_wdata_m_scanin[24]), .q(din_m[24]), .so(dff_wdata_m_scanout[24]),
498 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
499 cl_sc1_msff_syrst_4x din_m025 (.d(din[25]), .si(dff_wdata_m_scanin[25]), .q(din_m[25]), .so(dff_wdata_m_scanout[25]),
500 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
501 cl_sc1_msff_syrst_4x din_m026 (.d(din[26]), .si(dff_wdata_m_scanin[26]), .q(din_m[26]), .so(dff_wdata_m_scanout[26]),
502 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
503 cl_sc1_msff_syrst_4x din_m027 (.d(din[27]), .si(dff_wdata_m_scanin[27]), .q(din_m[27]), .so(dff_wdata_m_scanout[27]),
504 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
505 cl_sc1_msff_syrst_4x din_m028 (.d(din[28]), .si(dff_wdata_m_scanin[28]), .q(din_m[28]), .so(dff_wdata_m_scanout[28]),
506 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
507 cl_sc1_msff_syrst_4x din_m029 (.d(din[29]), .si(dff_wdata_m_scanin[29]), .q(din_m[29]), .so(dff_wdata_m_scanout[29]),
508 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
509
510 cl_sc1_msff_syrst_4x din_m030 (.d(din[30]), .si(dff_wdata_m_scanin[30]), .q(din_m[30]), .so(dff_wdata_m_scanout[30]),
511 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
512 cl_sc1_msff_syrst_4x din_m031 (.d(din[31]), .si(dff_wdata_m_scanin[31]), .q(din_m[31]), .so(dff_wdata_m_scanout[31]),
513 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
514 cl_sc1_msff_syrst_4x din_m032 (.d(din[32]), .si(dff_wdata_m_scanin[32]), .q(din_m[32]), .so(dff_wdata_m_scanout[32]),
515 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
516 cl_sc1_msff_syrst_4x din_m033 (.d(din[33]), .si(dff_wdata_m_scanin[33]), .q(din_m[33]), .so(dff_wdata_m_scanout[33]),
517 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
518 cl_sc1_msff_syrst_4x din_m034 (.d(din[34]), .si(dff_wdata_m_scanin[34]), .q(din_m[34]), .so(dff_wdata_m_scanout[34]),
519 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
520 cl_sc1_msff_syrst_4x din_m035 (.d(din[35]), .si(dff_wdata_m_scanin[35]), .q(din_m[35]), .so(dff_wdata_m_scanout[35]),
521 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
522 cl_sc1_msff_syrst_4x din_m036 (.d(din[36]), .si(dff_wdata_m_scanin[36]), .q(din_m[36]), .so(dff_wdata_m_scanout[36]),
523 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
524 cl_sc1_msff_syrst_4x din_m037 (.d(din[37]), .si(dff_wdata_m_scanin[37]), .q(din_m[37]), .so(dff_wdata_m_scanout[37]),
525 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
526 cl_sc1_msff_syrst_4x din_m038 (.d(din[38]), .si(dff_wdata_m_scanin[38]), .q(din_m[38]), .so(dff_wdata_m_scanout[38]),
527 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
528 cl_sc1_msff_syrst_4x din_m039 (.d(din[39]), .si(dff_wdata_m_scanin[39]), .q(din_m[39]), .so(dff_wdata_m_scanout[39]),
529 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
530
531 cl_sc1_msff_syrst_4x din_m040 (.d(din[40]), .si(dff_wdata_m_scanin[40]), .q(din_m[40]), .so(dff_wdata_m_scanout[40]),
532 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
533 cl_sc1_msff_syrst_4x din_m041 (.d(din[41]), .si(dff_wdata_m_scanin[41]), .q(din_m[41]), .so(dff_wdata_m_scanout[41]),
534 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
535 cl_sc1_msff_syrst_4x din_m042 (.d(din[42]), .si(dff_wdata_m_scanin[42]), .q(din_m[42]), .so(dff_wdata_m_scanout[42]),
536 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
537 cl_sc1_msff_syrst_4x din_m043 (.d(din[43]), .si(dff_wdata_m_scanin[43]), .q(din_m[43]), .so(dff_wdata_m_scanout[43]),
538 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
539 cl_sc1_msff_syrst_4x din_m044 (.d(din[44]), .si(dff_wdata_m_scanin[44]), .q(din_m[44]), .so(dff_wdata_m_scanout[44]),
540 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
541 cl_sc1_msff_syrst_4x din_m045 (.d(din[45]), .si(dff_wdata_m_scanin[45]), .q(din_m[45]), .so(dff_wdata_m_scanout[45]),
542 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
543 cl_sc1_msff_syrst_4x din_m046 (.d(din[46]), .si(dff_wdata_m_scanin[46]), .q(din_m[46]), .so(dff_wdata_m_scanout[46]),
544 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
545 cl_sc1_msff_syrst_4x din_m047 (.d(din[47]), .si(dff_wdata_m_scanin[47]), .q(din_m[47]), .so(dff_wdata_m_scanout[47]),
546 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
547 cl_sc1_msff_syrst_4x din_m048 (.d(din[48]), .si(dff_wdata_m_scanin[48]), .q(din_m[48]), .so(dff_wdata_m_scanout[48]),
548 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
549 cl_sc1_msff_syrst_4x din_m049 (.d(din[49]), .si(dff_wdata_m_scanin[49]), .q(din_m[49]), .so(dff_wdata_m_scanout[49]),
550 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
551
552 cl_sc1_msff_syrst_4x din_m050 (.d(din[50]), .si(dff_wdata_m_scanin[50]), .q(din_m[50]), .so(dff_wdata_m_scanout[50]),
553 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
554 cl_sc1_msff_syrst_4x din_m051 (.d(din[51]), .si(dff_wdata_m_scanin[51]), .q(din_m[51]), .so(dff_wdata_m_scanout[51]),
555 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
556 cl_sc1_msff_syrst_4x din_m052 (.d(din[52]), .si(dff_wdata_m_scanin[52]), .q(din_m[52]), .so(dff_wdata_m_scanout[52]),
557 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
558 cl_sc1_msff_syrst_4x din_m053 (.d(din[53]), .si(dff_wdata_m_scanin[53]), .q(din_m[53]), .so(dff_wdata_m_scanout[53]),
559 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
560 cl_sc1_msff_syrst_4x din_m054 (.d(din[54]), .si(dff_wdata_m_scanin[54]), .q(din_m[54]), .so(dff_wdata_m_scanout[54]),
561 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
562 cl_sc1_msff_syrst_4x din_m055 (.d(din[55]), .si(dff_wdata_m_scanin[55]), .q(din_m[55]), .so(dff_wdata_m_scanout[55]),
563 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
564 cl_sc1_msff_syrst_4x din_m056 (.d(din[56]), .si(dff_wdata_m_scanin[56]), .q(din_m[56]), .so(dff_wdata_m_scanout[56]),
565 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
566 cl_sc1_msff_syrst_4x din_m057 (.d(din[57]), .si(dff_wdata_m_scanin[57]), .q(din_m[57]), .so(dff_wdata_m_scanout[57]),
567 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
568 cl_sc1_msff_syrst_4x din_m058 (.d(din[58]), .si(dff_wdata_m_scanin[58]), .q(din_m[58]), .so(dff_wdata_m_scanout[58]),
569 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
570 cl_sc1_msff_syrst_4x din_m059 (.d(din[59]), .si(dff_wdata_m_scanin[59]), .q(din_m[59]), .so(dff_wdata_m_scanout[59]),
571 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
572
573 cl_sc1_msff_syrst_4x din_m060 (.d(din[60]), .si(dff_wdata_m_scanin[60]), .q(din_m[60]), .so(dff_wdata_m_scanout[60]),
574 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
575 cl_sc1_msff_syrst_4x din_m061 (.d(din[61]), .si(dff_wdata_m_scanin[61]), .q(din_m[61]), .so(dff_wdata_m_scanout[61]),
576 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
577 cl_sc1_msff_syrst_4x din_m062 (.d(din[62]), .si(dff_wdata_m_scanin[62]), .q(din_m[62]), .so(dff_wdata_m_scanout[62]),
578 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
579 cl_sc1_msff_syrst_4x din_m063 (.d(din[63]), .si(dff_wdata_m_scanin[63]), .q(din_m[63]), .so(dff_wdata_m_scanout[63]),
580 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
581 cl_sc1_msff_syrst_4x din_m064 (.d(din[64]), .si(dff_wdata_m_scanin[64]), .q(din_m[64]), .so(dff_wdata_m_scanout[64]),
582 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
583 cl_sc1_msff_syrst_4x din_m065 (.d(din[65]), .si(dff_wdata_m_scanin[65]), .q(din_m[65]), .so(dff_wdata_m_scanout[65]),
584 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
585 cl_sc1_msff_syrst_4x din_m066 (.d(din[66]), .si(dff_wdata_m_scanin[66]), .q(din_m[66]), .so(dff_wdata_m_scanout[66]),
586 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
587 cl_sc1_msff_syrst_4x din_m067 (.d(din[67]), .si(dff_wdata_m_scanin[67]), .q(din_m[67]), .so(dff_wdata_m_scanout[67]),
588 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
589 cl_sc1_msff_syrst_4x din_m068 (.d(din[68]), .si(dff_wdata_m_scanin[68]), .q(din_m[68]), .so(dff_wdata_m_scanout[68]),
590 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
591 cl_sc1_msff_syrst_4x din_m069 (.d(din[69]), .si(dff_wdata_m_scanin[69]), .q(din_m[69]), .so(dff_wdata_m_scanout[69]),
592 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
593
594 cl_sc1_msff_syrst_4x din_m070 (.d(din[70]), .si(dff_wdata_m_scanin[70]), .q(din_m[70]), .so(dff_wdata_m_scanout[70]),
595 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
596 cl_sc1_msff_syrst_4x din_m071 (.d(din[71]), .si(dff_wdata_m_scanin[71]), .q(din_m[71]), .so(dff_wdata_m_scanout[71]),
597 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
598 cl_sc1_msff_syrst_4x din_m072 (.d(din[72]), .si(dff_wdata_m_scanin[72]), .q(din_m[72]), .so(dff_wdata_m_scanout[72]),
599 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
600 cl_sc1_msff_syrst_4x din_m073 (.d(din[73]), .si(dff_wdata_m_scanin[73]), .q(din_m[73]), .so(dff_wdata_m_scanout[73]),
601 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
602 cl_sc1_msff_syrst_4x din_m074 (.d(din[74]), .si(dff_wdata_m_scanin[74]), .q(din_m[74]), .so(dff_wdata_m_scanout[74]),
603 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
604 cl_sc1_msff_syrst_4x din_m075 (.d(din[75]), .si(dff_wdata_m_scanin[75]), .q(din_m[75]), .so(dff_wdata_m_scanout[75]),
605 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
606 cl_sc1_msff_syrst_4x din_m076 (.d(din[76]), .si(dff_wdata_m_scanin[76]), .q(din_m[76]), .so(dff_wdata_m_scanout[76]),
607 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
608 cl_sc1_msff_syrst_4x din_m077 (.d(din[77]), .si(dff_wdata_m_scanin[77]), .q(din_m[77]), .so(dff_wdata_m_scanout[77]),
609 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
610 cl_sc1_msff_syrst_4x din_m078 (.d(din[78]), .si(dff_wdata_m_scanin[78]), .q(din_m[78]), .so(dff_wdata_m_scanout[78]),
611 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
612 cl_sc1_msff_syrst_4x din_m079 (.d(din[79]), .si(dff_wdata_m_scanin[79]), .q(din_m[79]), .so(dff_wdata_m_scanout[79]),
613 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
614
615 cl_sc1_msff_syrst_4x din_m080 (.d(din[80]), .si(dff_wdata_m_scanin[80]), .q(din_m[80]), .so(dff_wdata_m_scanout[80]),
616 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
617 cl_sc1_msff_syrst_4x din_m081 (.d(din[81]), .si(dff_wdata_m_scanin[81]), .q(din_m[81]), .so(dff_wdata_m_scanout[81]),
618 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
619 cl_sc1_msff_syrst_4x din_m082 (.d(din[82]), .si(dff_wdata_m_scanin[82]), .q(din_m[82]), .so(dff_wdata_m_scanout[82]),
620 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
621 cl_sc1_msff_syrst_4x din_m083 (.d(din[83]), .si(dff_wdata_m_scanin[83]), .q(din_m[83]), .so(dff_wdata_m_scanout[83]),
622 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
623 cl_sc1_msff_syrst_4x din_m084 (.d(din[84]), .si(dff_wdata_m_scanin[84]), .q(din_m[84]), .so(dff_wdata_m_scanout[84]),
624 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
625 cl_sc1_msff_syrst_4x din_m085 (.d(din[85]), .si(dff_wdata_m_scanin[85]), .q(din_m[85]), .so(dff_wdata_m_scanout[85]),
626 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
627 cl_sc1_msff_syrst_4x din_m086 (.d(din[86]), .si(dff_wdata_m_scanin[86]), .q(din_m[86]), .so(dff_wdata_m_scanout[86]),
628 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
629 cl_sc1_msff_syrst_4x din_m087 (.d(din[87]), .si(dff_wdata_m_scanin[87]), .q(din_m[87]), .so(dff_wdata_m_scanout[87]),
630 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
631 cl_sc1_msff_syrst_4x din_m088 (.d(din[88]), .si(dff_wdata_m_scanin[88]), .q(din_m[88]), .so(dff_wdata_m_scanout[88]),
632 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
633 cl_sc1_msff_syrst_4x din_m089 (.d(din[89]), .si(dff_wdata_m_scanin[89]), .q(din_m[89]), .so(dff_wdata_m_scanout[89]),
634 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
635
636 cl_sc1_msff_syrst_4x din_m090 (.d(din[90]), .si(dff_wdata_m_scanin[90]), .q(din_m[90]), .so(dff_wdata_m_scanout[90]),
637 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
638 cl_sc1_msff_syrst_4x din_m091 (.d(din[91]), .si(dff_wdata_m_scanin[91]), .q(din_m[91]), .so(dff_wdata_m_scanout[91]),
639 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
640 cl_sc1_msff_syrst_4x din_m092 (.d(din[92]), .si(dff_wdata_m_scanin[92]), .q(din_m[92]), .so(dff_wdata_m_scanout[92]),
641 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
642 cl_sc1_msff_syrst_4x din_m093 (.d(din[93]), .si(dff_wdata_m_scanin[93]), .q(din_m[93]), .so(dff_wdata_m_scanout[93]),
643 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
644 cl_sc1_msff_syrst_4x din_m094 (.d(din[94]), .si(dff_wdata_m_scanin[94]), .q(din_m[94]), .so(dff_wdata_m_scanout[94]),
645 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
646 cl_sc1_msff_syrst_4x din_m095 (.d(din[95]), .si(dff_wdata_m_scanin[95]), .q(din_m[95]), .so(dff_wdata_m_scanout[95]),
647 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
648 cl_sc1_msff_syrst_4x din_m096 (.d(din[96]), .si(dff_wdata_m_scanin[96]), .q(din_m[96]), .so(dff_wdata_m_scanout[96]),
649 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
650 cl_sc1_msff_syrst_4x din_m097 (.d(din[97]), .si(dff_wdata_m_scanin[97]), .q(din_m[97]), .so(dff_wdata_m_scanout[97]),
651 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
652 cl_sc1_msff_syrst_4x din_m098 (.d(din[98]), .si(dff_wdata_m_scanin[98]), .q(din_m[98]), .so(dff_wdata_m_scanout[98]),
653 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
654 cl_sc1_msff_syrst_4x din_m099 (.d(din[99]), .si(dff_wdata_m_scanin[99]), .q(din_m[99]), .so(dff_wdata_m_scanout[99]),
655 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
656
657 cl_sc1_msff_syrst_4x din_m100 (.d(din[100]), .si(dff_wdata_m_scanin[100]), .q(din_m[100]), .so(dff_wdata_m_scanout[100]),
658 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
659 cl_sc1_msff_syrst_4x din_m101 (.d(din[101]), .si(dff_wdata_m_scanin[101]), .q(din_m[101]), .so(dff_wdata_m_scanout[101]),
660 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
661 cl_sc1_msff_syrst_4x din_m102 (.d(din[102]), .si(dff_wdata_m_scanin[102]), .q(din_m[102]), .so(dff_wdata_m_scanout[102]),
662 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
663 cl_sc1_msff_syrst_4x din_m103 (.d(din[103]), .si(dff_wdata_m_scanin[103]), .q(din_m[103]), .so(dff_wdata_m_scanout[103]),
664 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
665 cl_sc1_msff_syrst_4x din_m104 (.d(din[104]), .si(dff_wdata_m_scanin[104]), .q(din_m[104]), .so(dff_wdata_m_scanout[104]),
666 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
667 cl_sc1_msff_syrst_4x din_m105 (.d(din[105]), .si(dff_wdata_m_scanin[105]), .q(din_m[105]), .so(dff_wdata_m_scanout[105]),
668 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
669 cl_sc1_msff_syrst_4x din_m106 (.d(din[106]), .si(dff_wdata_m_scanin[106]), .q(din_m[106]), .so(dff_wdata_m_scanout[106]),
670 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
671 cl_sc1_msff_syrst_4x din_m107 (.d(din[107]), .si(dff_wdata_m_scanin[107]), .q(din_m[107]), .so(dff_wdata_m_scanout[107]),
672 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
673 cl_sc1_msff_syrst_4x din_m108 (.d(din[108]), .si(dff_wdata_m_scanin[108]), .q(din_m[108]), .so(dff_wdata_m_scanout[108]),
674 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
675 cl_sc1_msff_syrst_4x din_m109 (.d(din[109]), .si(dff_wdata_m_scanin[109]), .q(din_m[109]), .so(dff_wdata_m_scanout[109]),
676 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
677
678 cl_sc1_msff_syrst_4x din_m110 (.d(din[110]), .si(dff_wdata_m_scanin[110]), .q(din_m[110]), .so(dff_wdata_m_scanout[110]),
679 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
680 cl_sc1_msff_syrst_4x din_m111 (.d(din[111]), .si(dff_wdata_m_scanin[111]), .q(din_m[111]), .so(dff_wdata_m_scanout[111]),
681 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
682 cl_sc1_msff_syrst_4x din_m112 (.d(din[112]), .si(dff_wdata_m_scanin[112]), .q(din_m[112]), .so(dff_wdata_m_scanout[112]),
683 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
684 cl_sc1_msff_syrst_4x din_m113 (.d(din[113]), .si(dff_wdata_m_scanin[113]), .q(din_m[113]), .so(dff_wdata_m_scanout[113]),
685 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
686 cl_sc1_msff_syrst_4x din_m114 (.d(din[114]), .si(dff_wdata_m_scanin[114]), .q(din_m[114]), .so(dff_wdata_m_scanout[114]),
687 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
688 cl_sc1_msff_syrst_4x din_m115 (.d(din[115]), .si(dff_wdata_m_scanin[115]), .q(din_m[115]), .so(dff_wdata_m_scanout[115]),
689 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
690 cl_sc1_msff_syrst_4x din_m116 (.d(din[116]), .si(dff_wdata_m_scanin[116]), .q(din_m[116]), .so(dff_wdata_m_scanout[116]),
691 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
692 cl_sc1_msff_syrst_4x din_m117 (.d(din[117]), .si(dff_wdata_m_scanin[117]), .q(din_m[117]), .so(dff_wdata_m_scanout[117]),
693 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
694 cl_sc1_msff_syrst_4x din_m118 (.d(din[118]), .si(dff_wdata_m_scanin[118]), .q(din_m[118]), .so(dff_wdata_m_scanout[118]),
695 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
696 cl_sc1_msff_syrst_4x din_m119 (.d(din[119]), .si(dff_wdata_m_scanin[119]), .q(din_m[119]), .so(dff_wdata_m_scanout[119]),
697 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
698
699 cl_sc1_msff_syrst_4x din_m120 (.d(din[120]), .si(dff_wdata_m_scanin[120]), .q(din_m[120]), .so(dff_wdata_m_scanout[120]),
700 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
701 cl_sc1_msff_syrst_4x din_m121 (.d(din[121]), .si(dff_wdata_m_scanin[121]), .q(din_m[121]), .so(dff_wdata_m_scanout[121]),
702 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
703 cl_sc1_msff_syrst_4x din_m122 (.d(din[122]), .si(dff_wdata_m_scanin[122]), .q(din_m[122]), .so(dff_wdata_m_scanout[122]),
704 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
705 cl_sc1_msff_syrst_4x din_m123 (.d(din[123]), .si(dff_wdata_m_scanin[123]), .q(din_m[123]), .so(dff_wdata_m_scanout[123]),
706 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
707 cl_sc1_msff_syrst_4x din_m124 (.d(din[124]), .si(dff_wdata_m_scanin[124]), .q(din_m[124]), .so(dff_wdata_m_scanout[124]),
708 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
709 cl_sc1_msff_syrst_4x din_m125 (.d(din[125]), .si(dff_wdata_m_scanin[125]), .q(din_m[125]), .so(dff_wdata_m_scanout[125]),
710 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
711 cl_sc1_msff_syrst_4x din_m126 (.d(din[126]), .si(dff_wdata_m_scanin[126]), .q(din_m[126]), .so(dff_wdata_m_scanout[126]),
712 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
713 cl_sc1_msff_syrst_4x din_m127 (.d(din[127]), .si(dff_wdata_m_scanin[127]), .q(din_m[127]), .so(dff_wdata_m_scanout[127]),
714 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
715 cl_sc1_msff_syrst_4x din_m128 (.d(din[128]), .si(dff_wdata_m_scanin[128]), .q(din_m[128]), .so(dff_wdata_m_scanout[128]),
716 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
717 cl_sc1_msff_syrst_4x din_m129 (.d(din[129]), .si(dff_wdata_m_scanin[129]), .q(din_m[129]), .so(dff_wdata_m_scanout[129]),
718 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
719
720 cl_sc1_msff_syrst_4x din_m130 (.d(din[130]), .si(dff_wdata_m_scanin[130]), .q(din_m[130]), .so(dff_wdata_m_scanout[130]),
721 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
722 cl_sc1_msff_syrst_4x din_m131 (.d(din[131]), .si(dff_wdata_m_scanin[131]), .q(din_m[131]), .so(dff_wdata_m_scanout[131]),
723 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
724 cl_sc1_msff_syrst_4x din_m132 (.d(din[132]), .si(dff_wdata_m_scanin[132]), .q(din_m[132]), .so(dff_wdata_m_scanout[132]),
725 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
726 cl_sc1_msff_syrst_4x din_m133 (.d(din[133]), .si(dff_wdata_m_scanin[133]), .q(din_m[133]), .so(dff_wdata_m_scanout[133]),
727 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
728 cl_sc1_msff_syrst_4x din_m134 (.d(din[134]), .si(dff_wdata_m_scanin[134]), .q(din_m[134]), .so(dff_wdata_m_scanout[134]),
729 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
730 cl_sc1_msff_syrst_4x din_m135 (.d(din[135]), .si(dff_wdata_m_scanin[135]), .q(din_m[135]), .so(dff_wdata_m_scanout[135]),
731 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
732 cl_sc1_msff_syrst_4x din_m136 (.d(din[136]), .si(dff_wdata_m_scanin[136]), .q(din_m[136]), .so(dff_wdata_m_scanout[136]),
733 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
734 cl_sc1_msff_syrst_4x din_m137 (.d(din[137]), .si(dff_wdata_m_scanin[137]), .q(din_m[137]), .so(dff_wdata_m_scanout[137]),
735 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
736 cl_sc1_msff_syrst_4x din_m138 (.d(din[138]), .si(dff_wdata_m_scanin[138]), .q(din_m[138]), .so(dff_wdata_m_scanout[138]),
737 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
738 cl_sc1_msff_syrst_4x din_m139 (.d(din[139]), .si(dff_wdata_m_scanin[139]), .q(din_m[139]), .so(dff_wdata_m_scanout[139]),
739 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
740
741 cl_sc1_msff_syrst_4x din_m140 (.d(din[140]), .si(dff_wdata_m_scanin[140]), .q(din_m[140]), .so(dff_wdata_m_scanout[140]),
742 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
743 cl_sc1_msff_syrst_4x din_m141 (.d(din[141]), .si(dff_wdata_m_scanin[141]), .q(din_m[141]), .so(dff_wdata_m_scanout[141]),
744 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
745 cl_sc1_msff_syrst_4x din_m142 (.d(din[142]), .si(dff_wdata_m_scanin[142]), .q(din_m[142]), .so(dff_wdata_m_scanout[142]),
746 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
747 cl_sc1_msff_syrst_4x din_m143 (.d(din[143]), .si(dff_wdata_m_scanin[143]), .q(din_m[143]), .so(dff_wdata_m_scanout[143]),
748 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
749 cl_sc1_msff_syrst_4x din_m144 (.d(din[144]), .si(dff_wdata_m_scanin[144]), .q(din_m[144]), .so(dff_wdata_m_scanout[144]),
750 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
751 cl_sc1_msff_syrst_4x din_m145 (.d(din[145]), .si(dff_wdata_m_scanin[145]), .q(din_m[145]), .so(dff_wdata_m_scanout[145]),
752 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
753 cl_sc1_msff_syrst_4x din_m146 (.d(din[146]), .si(dff_wdata_m_scanin[146]), .q(din_m[146]), .so(dff_wdata_m_scanout[146]),
754 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
755 cl_sc1_msff_syrst_4x din_m147 (.d(din[147]), .si(dff_wdata_m_scanin[147]), .q(din_m[147]), .so(dff_wdata_m_scanout[147]),
756 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
757 cl_sc1_msff_syrst_4x din_m148 (.d(din[148]), .si(dff_wdata_m_scanin[148]), .q(din_m[148]), .so(dff_wdata_m_scanout[148]),
758 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
759 cl_sc1_msff_syrst_4x din_m149 (.d(din[149]), .si(dff_wdata_m_scanin[149]), .q(din_m[149]), .so(dff_wdata_m_scanout[149]),
760 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
761
762 cl_sc1_msff_syrst_4x din_m150 (.d(din[150]), .si(dff_wdata_m_scanin[150]), .q(din_m[150]), .so(dff_wdata_m_scanout[150]),
763 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
764 cl_sc1_msff_syrst_4x din_m151 (.d(din[151]), .si(dff_wdata_m_scanin[151]), .q(din_m[151]), .so(dff_wdata_m_scanout[151]),
765 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
766
767// ------------ test registers ------------
768
769 cl_sc1_msff_syrst_4x test_mode_reg (
770 .d (test_mode),
771 .reset (reset_l),
772 .si (dff_test_mode_scanin),
773 .q (test_mode),
774 .so (dff_test_mode_scanout),
775 .l1clk (l1clk_in),
776 .siclk (tcu_aclk),
777 .soclk (tcu_bclk) );
778
779 cl_sc1_msff_syrst_4x test_clk_reg (
780 .d (test_clk),
781 .reset (reset_l),
782 .si (dff_test_clk_scanin),
783 .q (test_clk),
784 .so (dff_test_clk_scanout),
785 .l1clk (l1clk_in),
786 .siclk (tcu_aclk),
787 .soclk (tcu_bclk) );
788
789wire l1clk_testclk;
790
791 assign l1clk_testclk = test_mode ? test_clk : l1clk_gate;
792
793
794//================================================
795// l2 clock Domain: Control signals
796//================================================
797wire do_B_write_m, l1clk_testclk_not, wr_inhibit_not, wr_en_and_clk;
798wire do_A_read_m, do_A_read_temp;
799wire [8:0] rw_addr_m, sc11, sc12;
800
801// assign do_B_write_m = wr_en_m && !l1clk_gate && !tcu_array_wr_inhibit;
802// assign do_A_read_m = rd_en_m && l1clk_gate && !tcu_array_wr_inhibit;
803// assign rw_addr_m = {9{do_B_write_m}} & wr_adr_m |
804// {9{do_A_read_m}} & rd_adr_m;
805
806 niu256_inv_macro__width_1 a1 (.dout(l1clk_testclk_not), .din(l1clk_testclk) );
807 niu256_inv_macro__width_1 a2 (.dout(wr_inhibit_not), .din(tcu_array_wr_inhibit) );
808 niu256_and_macro__width_1 a3 (.dout(wr_en_and_clk), .din0(wr_en_m), .din1(l1clk_testclk_not) );
809 niu256_and_macro__width_1 a4 (.dout(do_B_write_m), .din0(wr_en_and_clk), .din1(wr_inhibit_not) );
810
811 niu256_and_macro__width_1 b1 (.dout(do_A_read_temp), .din0(rd_en_m), .din1(l1clk_testclk) );
812 niu256_and_macro__width_1 b2 (.dout(do_A_read_m), .din0(wr_inhibit_not), .din1(do_A_read_temp) );
813
814 niu256_and_macro__width_9 c1 (.dout(sc11[8:0]), .din0({9{do_B_write_m}}),.din1(wr_adr_m[8:0]));
815 niu256_and_macro__width_9 c2 (.dout(sc12[8:0]), .din0({9{do_A_read_m}}), .din1(rd_adr_m[8:0]));
816 niu256_or_macro__width_9 c3 (.dout(rw_addr_m[8:0]),.din0(sc11[8:0]), .din1(sc12[8:0]));
817
818//================================================
819// l2x2 clock Domain: Clock headers
820//================================================
821
822wire l1clk_2x_free;
823
824cl_sc1_l1hdr_8x l1ch_2x_free (
825 .l2clk (l2clk_2x),
826 .pce (pce),
827 .pce_ov (tcu_pce_ov),
828 .l1clk (l1clk_2x_free),
829 .se (tcu_scan_en),
830 .stop (1'b0)
831 );
832
833
834
835//================================================
836// l2x2 clock Domain: Input Logic
837//================================================
838// ------------ controls_ph.a Latch @ posedge -------
839//reg do_B_write_2x_a;
840//reg do_A_read_2x_a;
841//reg [8:0] rw_addr_2x_a;
842//
843// always @(l1clk_2x_free or rw_addr_m or do_A_read_m or do_B_write_m) begin
844// if (l1clk_2x_free)
845// begin
846// rw_addr_2x_a = rw_addr_m;
847// do_A_read_2x_a = do_A_read_m;
848// do_B_write_2x_a = do_B_write_m;
849// end
850// else
851// begin
852// rw_addr_2x_a = rw_addr_2x_a;
853// do_A_read_2x_a = do_A_read_2x_a;
854// do_B_write_2x_a = do_B_write_2x_a;
855// end
856// end
857// ------------ controls_ph.b Latch @ negedge -------
858//reg [1:0] rd_addr_column_b;
859//reg [1:0] rd_addr_column_b1;
860//
861// always @(l1clk_2x_free or rd_en_a or rw_addr_2x_a) begin
862// if (!l1clk_2x_free && rd_en_a)
863// begin
864// rd_addr_column_b1 = rw_addr_2x_a[1:0];
865// end
866// else
867// begin
868// rd_addr_column_b1 = rd_addr_column_b1;
869// end
870// end
871//
872// always @(l1clk_2x_free) begin
873// rd_addr_column_b <= rd_addr_column_b1;
874// end
875
876// ------------ write_data_ph.b Flop @ negedge -----
877//reg [151:0] wdata_2x_b;
878//
879// always @(negedge l1clk_2x_free) begin
880// wdata_2x_b <= din_m;
881// end
882//
883
884wire [8:0] rw_addr_2x_a;
885wire [1:0] rd_addr_column_b;
886wire [1:0] rd_addr_column_b1;
887
888cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat0 (.latout(rw_addr_2x_a[0]), .d(rw_addr_m[0]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
889cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat1 (.latout(rw_addr_2x_a[1]), .d(rw_addr_m[1]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
890cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat2 (.latout(rw_addr_2x_a[2]), .d(rw_addr_m[2]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
891cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat3 (.latout(rw_addr_2x_a[3]), .d(rw_addr_m[3]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
892cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat4 (.latout(rw_addr_2x_a[4]), .d(rw_addr_m[4]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
893cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat5 (.latout(rw_addr_2x_a[5]), .d(rw_addr_m[5]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
894cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat6 (.latout(rw_addr_2x_a[6]), .d(rw_addr_m[6]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
895cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat7 (.latout(rw_addr_2x_a[7]), .d(rw_addr_m[7]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
896cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat8 (.latout(rw_addr_2x_a[8]), .d(rw_addr_m[8]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
897
898cl_mc1_scm_msff_lat_4x do_A_read_2x_a_lat (.latout(do_A_read_2x_a), .d(do_A_read_m), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
899cl_mc1_scm_msff_lat_4x do_B_write_2x_a_lat (.latout(do_B_write_2x_a), .d(do_B_write_m), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
900
901
902cl_mc1_scm_msff_lat_4x rd_addr_column_b1_lat0 (.latout(rd_addr_column_b1[0]), .d(rw_addr_2x_a[0]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
903cl_mc1_scm_msff_lat_4x rd_addr_column_b1_lat1 (.latout(rd_addr_column_b1[1]), .d(rw_addr_2x_a[1]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
904
905cl_mc1_scm_msff_lat_4x rd_addr_column_b_lat0 (.latout(rd_addr_column_b[0]), .d(rd_addr_column_b1[0]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
906cl_mc1_scm_msff_lat_4x rd_addr_column_b_lat1 (.latout(rd_addr_column_b[1]), .d(rd_addr_column_b1[1]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
907
908
909cl_sc1_msff_4x wdata_2x_b_reg0 (.d(din_m[0]), .si(1'b0), .q(wdata_2x_b[0]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
910cl_sc1_msff_4x wdata_2x_b_reg1 (.d(din_m[1]), .si(1'b0), .q(wdata_2x_b[1]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
911cl_sc1_msff_4x wdata_2x_b_reg2 (.d(din_m[2]), .si(1'b0), .q(wdata_2x_b[2]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
912cl_sc1_msff_4x wdata_2x_b_reg3 (.d(din_m[3]), .si(1'b0), .q(wdata_2x_b[3]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
913cl_sc1_msff_4x wdata_2x_b_reg4 (.d(din_m[4]), .si(1'b0), .q(wdata_2x_b[4]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
914cl_sc1_msff_4x wdata_2x_b_reg5 (.d(din_m[5]), .si(1'b0), .q(wdata_2x_b[5]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
915cl_sc1_msff_4x wdata_2x_b_reg6 (.d(din_m[6]), .si(1'b0), .q(wdata_2x_b[6]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
916cl_sc1_msff_4x wdata_2x_b_reg7 (.d(din_m[7]), .si(1'b0), .q(wdata_2x_b[7]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
917cl_sc1_msff_4x wdata_2x_b_reg8 (.d(din_m[8]), .si(1'b0), .q(wdata_2x_b[8]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
918cl_sc1_msff_4x wdata_2x_b_reg9 (.d(din_m[9]), .si(1'b0), .q(wdata_2x_b[9]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
919cl_sc1_msff_4x wdata_2x_b_reg10 (.d(din_m[10]), .si(1'b0), .q(wdata_2x_b[10]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
920cl_sc1_msff_4x wdata_2x_b_reg11 (.d(din_m[11]), .si(1'b0), .q(wdata_2x_b[11]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
921cl_sc1_msff_4x wdata_2x_b_reg12 (.d(din_m[12]), .si(1'b0), .q(wdata_2x_b[12]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
922cl_sc1_msff_4x wdata_2x_b_reg13 (.d(din_m[13]), .si(1'b0), .q(wdata_2x_b[13]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
923cl_sc1_msff_4x wdata_2x_b_reg14 (.d(din_m[14]), .si(1'b0), .q(wdata_2x_b[14]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
924cl_sc1_msff_4x wdata_2x_b_reg15 (.d(din_m[15]), .si(1'b0), .q(wdata_2x_b[15]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
925cl_sc1_msff_4x wdata_2x_b_reg16 (.d(din_m[16]), .si(1'b0), .q(wdata_2x_b[16]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
926cl_sc1_msff_4x wdata_2x_b_reg17 (.d(din_m[17]), .si(1'b0), .q(wdata_2x_b[17]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
927cl_sc1_msff_4x wdata_2x_b_reg18 (.d(din_m[18]), .si(1'b0), .q(wdata_2x_b[18]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
928cl_sc1_msff_4x wdata_2x_b_reg19 (.d(din_m[19]), .si(1'b0), .q(wdata_2x_b[19]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
929cl_sc1_msff_4x wdata_2x_b_reg20 (.d(din_m[20]), .si(1'b0), .q(wdata_2x_b[20]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
930cl_sc1_msff_4x wdata_2x_b_reg21 (.d(din_m[21]), .si(1'b0), .q(wdata_2x_b[21]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
931cl_sc1_msff_4x wdata_2x_b_reg22 (.d(din_m[22]), .si(1'b0), .q(wdata_2x_b[22]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
932cl_sc1_msff_4x wdata_2x_b_reg23 (.d(din_m[23]), .si(1'b0), .q(wdata_2x_b[23]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
933cl_sc1_msff_4x wdata_2x_b_reg24 (.d(din_m[24]), .si(1'b0), .q(wdata_2x_b[24]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
934cl_sc1_msff_4x wdata_2x_b_reg25 (.d(din_m[25]), .si(1'b0), .q(wdata_2x_b[25]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
935cl_sc1_msff_4x wdata_2x_b_reg26 (.d(din_m[26]), .si(1'b0), .q(wdata_2x_b[26]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
936cl_sc1_msff_4x wdata_2x_b_reg27 (.d(din_m[27]), .si(1'b0), .q(wdata_2x_b[27]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
937cl_sc1_msff_4x wdata_2x_b_reg28 (.d(din_m[28]), .si(1'b0), .q(wdata_2x_b[28]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
938cl_sc1_msff_4x wdata_2x_b_reg29 (.d(din_m[29]), .si(1'b0), .q(wdata_2x_b[29]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
939cl_sc1_msff_4x wdata_2x_b_reg30 (.d(din_m[30]), .si(1'b0), .q(wdata_2x_b[30]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
940cl_sc1_msff_4x wdata_2x_b_reg31 (.d(din_m[31]), .si(1'b0), .q(wdata_2x_b[31]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
941cl_sc1_msff_4x wdata_2x_b_reg32 (.d(din_m[32]), .si(1'b0), .q(wdata_2x_b[32]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
942cl_sc1_msff_4x wdata_2x_b_reg33 (.d(din_m[33]), .si(1'b0), .q(wdata_2x_b[33]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
943cl_sc1_msff_4x wdata_2x_b_reg34 (.d(din_m[34]), .si(1'b0), .q(wdata_2x_b[34]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
944cl_sc1_msff_4x wdata_2x_b_reg35 (.d(din_m[35]), .si(1'b0), .q(wdata_2x_b[35]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
945cl_sc1_msff_4x wdata_2x_b_reg36 (.d(din_m[36]), .si(1'b0), .q(wdata_2x_b[36]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
946cl_sc1_msff_4x wdata_2x_b_reg37 (.d(din_m[37]), .si(1'b0), .q(wdata_2x_b[37]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
947cl_sc1_msff_4x wdata_2x_b_reg38 (.d(din_m[38]), .si(1'b0), .q(wdata_2x_b[38]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
948cl_sc1_msff_4x wdata_2x_b_reg39 (.d(din_m[39]), .si(1'b0), .q(wdata_2x_b[39]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
949cl_sc1_msff_4x wdata_2x_b_reg40 (.d(din_m[40]), .si(1'b0), .q(wdata_2x_b[40]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
950cl_sc1_msff_4x wdata_2x_b_reg41 (.d(din_m[41]), .si(1'b0), .q(wdata_2x_b[41]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
951cl_sc1_msff_4x wdata_2x_b_reg42 (.d(din_m[42]), .si(1'b0), .q(wdata_2x_b[42]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
952cl_sc1_msff_4x wdata_2x_b_reg43 (.d(din_m[43]), .si(1'b0), .q(wdata_2x_b[43]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
953cl_sc1_msff_4x wdata_2x_b_reg44 (.d(din_m[44]), .si(1'b0), .q(wdata_2x_b[44]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
954cl_sc1_msff_4x wdata_2x_b_reg45 (.d(din_m[45]), .si(1'b0), .q(wdata_2x_b[45]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
955cl_sc1_msff_4x wdata_2x_b_reg46 (.d(din_m[46]), .si(1'b0), .q(wdata_2x_b[46]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
956cl_sc1_msff_4x wdata_2x_b_reg47 (.d(din_m[47]), .si(1'b0), .q(wdata_2x_b[47]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
957cl_sc1_msff_4x wdata_2x_b_reg48 (.d(din_m[48]), .si(1'b0), .q(wdata_2x_b[48]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
958cl_sc1_msff_4x wdata_2x_b_reg49 (.d(din_m[49]), .si(1'b0), .q(wdata_2x_b[49]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
959cl_sc1_msff_4x wdata_2x_b_reg50 (.d(din_m[50]), .si(1'b0), .q(wdata_2x_b[50]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
960cl_sc1_msff_4x wdata_2x_b_reg51 (.d(din_m[51]), .si(1'b0), .q(wdata_2x_b[51]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
961cl_sc1_msff_4x wdata_2x_b_reg52 (.d(din_m[52]), .si(1'b0), .q(wdata_2x_b[52]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
962cl_sc1_msff_4x wdata_2x_b_reg53 (.d(din_m[53]), .si(1'b0), .q(wdata_2x_b[53]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
963cl_sc1_msff_4x wdata_2x_b_reg54 (.d(din_m[54]), .si(1'b0), .q(wdata_2x_b[54]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
964cl_sc1_msff_4x wdata_2x_b_reg55 (.d(din_m[55]), .si(1'b0), .q(wdata_2x_b[55]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
965cl_sc1_msff_4x wdata_2x_b_reg56 (.d(din_m[56]), .si(1'b0), .q(wdata_2x_b[56]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
966cl_sc1_msff_4x wdata_2x_b_reg57 (.d(din_m[57]), .si(1'b0), .q(wdata_2x_b[57]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
967cl_sc1_msff_4x wdata_2x_b_reg58 (.d(din_m[58]), .si(1'b0), .q(wdata_2x_b[58]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
968cl_sc1_msff_4x wdata_2x_b_reg59 (.d(din_m[59]), .si(1'b0), .q(wdata_2x_b[59]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
969cl_sc1_msff_4x wdata_2x_b_reg60 (.d(din_m[60]), .si(1'b0), .q(wdata_2x_b[60]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
970cl_sc1_msff_4x wdata_2x_b_reg61 (.d(din_m[61]), .si(1'b0), .q(wdata_2x_b[61]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
971cl_sc1_msff_4x wdata_2x_b_reg62 (.d(din_m[62]), .si(1'b0), .q(wdata_2x_b[62]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
972cl_sc1_msff_4x wdata_2x_b_reg63 (.d(din_m[63]), .si(1'b0), .q(wdata_2x_b[63]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
973cl_sc1_msff_4x wdata_2x_b_reg64 (.d(din_m[64]), .si(1'b0), .q(wdata_2x_b[64]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
974cl_sc1_msff_4x wdata_2x_b_reg65 (.d(din_m[65]), .si(1'b0), .q(wdata_2x_b[65]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
975cl_sc1_msff_4x wdata_2x_b_reg66 (.d(din_m[66]), .si(1'b0), .q(wdata_2x_b[66]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
976cl_sc1_msff_4x wdata_2x_b_reg67 (.d(din_m[67]), .si(1'b0), .q(wdata_2x_b[67]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
977cl_sc1_msff_4x wdata_2x_b_reg68 (.d(din_m[68]), .si(1'b0), .q(wdata_2x_b[68]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
978cl_sc1_msff_4x wdata_2x_b_reg69 (.d(din_m[69]), .si(1'b0), .q(wdata_2x_b[69]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
979cl_sc1_msff_4x wdata_2x_b_reg70 (.d(din_m[70]), .si(1'b0), .q(wdata_2x_b[70]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
980cl_sc1_msff_4x wdata_2x_b_reg71 (.d(din_m[71]), .si(1'b0), .q(wdata_2x_b[71]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
981cl_sc1_msff_4x wdata_2x_b_reg72 (.d(din_m[72]), .si(1'b0), .q(wdata_2x_b[72]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
982cl_sc1_msff_4x wdata_2x_b_reg73 (.d(din_m[73]), .si(1'b0), .q(wdata_2x_b[73]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
983cl_sc1_msff_4x wdata_2x_b_reg74 (.d(din_m[74]), .si(1'b0), .q(wdata_2x_b[74]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
984cl_sc1_msff_4x wdata_2x_b_reg75 (.d(din_m[75]), .si(1'b0), .q(wdata_2x_b[75]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
985cl_sc1_msff_4x wdata_2x_b_reg76 (.d(din_m[76]), .si(1'b0), .q(wdata_2x_b[76]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
986cl_sc1_msff_4x wdata_2x_b_reg77 (.d(din_m[77]), .si(1'b0), .q(wdata_2x_b[77]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
987cl_sc1_msff_4x wdata_2x_b_reg78 (.d(din_m[78]), .si(1'b0), .q(wdata_2x_b[78]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
988cl_sc1_msff_4x wdata_2x_b_reg79 (.d(din_m[79]), .si(1'b0), .q(wdata_2x_b[79]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
989cl_sc1_msff_4x wdata_2x_b_reg80 (.d(din_m[80]), .si(1'b0), .q(wdata_2x_b[80]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
990cl_sc1_msff_4x wdata_2x_b_reg81 (.d(din_m[81]), .si(1'b0), .q(wdata_2x_b[81]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
991cl_sc1_msff_4x wdata_2x_b_reg82 (.d(din_m[82]), .si(1'b0), .q(wdata_2x_b[82]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
992cl_sc1_msff_4x wdata_2x_b_reg83 (.d(din_m[83]), .si(1'b0), .q(wdata_2x_b[83]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
993cl_sc1_msff_4x wdata_2x_b_reg84 (.d(din_m[84]), .si(1'b0), .q(wdata_2x_b[84]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
994cl_sc1_msff_4x wdata_2x_b_reg85 (.d(din_m[85]), .si(1'b0), .q(wdata_2x_b[85]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
995cl_sc1_msff_4x wdata_2x_b_reg86 (.d(din_m[86]), .si(1'b0), .q(wdata_2x_b[86]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
996cl_sc1_msff_4x wdata_2x_b_reg87 (.d(din_m[87]), .si(1'b0), .q(wdata_2x_b[87]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
997cl_sc1_msff_4x wdata_2x_b_reg88 (.d(din_m[88]), .si(1'b0), .q(wdata_2x_b[88]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
998cl_sc1_msff_4x wdata_2x_b_reg89 (.d(din_m[89]), .si(1'b0), .q(wdata_2x_b[89]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
999cl_sc1_msff_4x wdata_2x_b_reg90 (.d(din_m[90]), .si(1'b0), .q(wdata_2x_b[90]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1000cl_sc1_msff_4x wdata_2x_b_reg91 (.d(din_m[91]), .si(1'b0), .q(wdata_2x_b[91]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1001cl_sc1_msff_4x wdata_2x_b_reg92 (.d(din_m[92]), .si(1'b0), .q(wdata_2x_b[92]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1002cl_sc1_msff_4x wdata_2x_b_reg93 (.d(din_m[93]), .si(1'b0), .q(wdata_2x_b[93]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1003cl_sc1_msff_4x wdata_2x_b_reg94 (.d(din_m[94]), .si(1'b0), .q(wdata_2x_b[94]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1004cl_sc1_msff_4x wdata_2x_b_reg95 (.d(din_m[95]), .si(1'b0), .q(wdata_2x_b[95]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1005cl_sc1_msff_4x wdata_2x_b_reg96 (.d(din_m[96]), .si(1'b0), .q(wdata_2x_b[96]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1006cl_sc1_msff_4x wdata_2x_b_reg97 (.d(din_m[97]), .si(1'b0), .q(wdata_2x_b[97]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1007cl_sc1_msff_4x wdata_2x_b_reg98 (.d(din_m[98]), .si(1'b0), .q(wdata_2x_b[98]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1008cl_sc1_msff_4x wdata_2x_b_reg99 (.d(din_m[99]), .si(1'b0), .q(wdata_2x_b[99]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1009cl_sc1_msff_4x wdata_2x_b_reg100 (.d(din_m[100]), .si(1'b0), .q(wdata_2x_b[100]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1010cl_sc1_msff_4x wdata_2x_b_reg101 (.d(din_m[101]), .si(1'b0), .q(wdata_2x_b[101]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1011cl_sc1_msff_4x wdata_2x_b_reg102 (.d(din_m[102]), .si(1'b0), .q(wdata_2x_b[102]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1012cl_sc1_msff_4x wdata_2x_b_reg103 (.d(din_m[103]), .si(1'b0), .q(wdata_2x_b[103]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1013cl_sc1_msff_4x wdata_2x_b_reg104 (.d(din_m[104]), .si(1'b0), .q(wdata_2x_b[104]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1014cl_sc1_msff_4x wdata_2x_b_reg105 (.d(din_m[105]), .si(1'b0), .q(wdata_2x_b[105]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1015cl_sc1_msff_4x wdata_2x_b_reg106 (.d(din_m[106]), .si(1'b0), .q(wdata_2x_b[106]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1016cl_sc1_msff_4x wdata_2x_b_reg107 (.d(din_m[107]), .si(1'b0), .q(wdata_2x_b[107]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1017cl_sc1_msff_4x wdata_2x_b_reg108 (.d(din_m[108]), .si(1'b0), .q(wdata_2x_b[108]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1018cl_sc1_msff_4x wdata_2x_b_reg109 (.d(din_m[109]), .si(1'b0), .q(wdata_2x_b[109]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1019cl_sc1_msff_4x wdata_2x_b_reg110 (.d(din_m[110]), .si(1'b0), .q(wdata_2x_b[110]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1020cl_sc1_msff_4x wdata_2x_b_reg111 (.d(din_m[111]), .si(1'b0), .q(wdata_2x_b[111]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1021cl_sc1_msff_4x wdata_2x_b_reg112 (.d(din_m[112]), .si(1'b0), .q(wdata_2x_b[112]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1022cl_sc1_msff_4x wdata_2x_b_reg113 (.d(din_m[113]), .si(1'b0), .q(wdata_2x_b[113]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1023cl_sc1_msff_4x wdata_2x_b_reg114 (.d(din_m[114]), .si(1'b0), .q(wdata_2x_b[114]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1024cl_sc1_msff_4x wdata_2x_b_reg115 (.d(din_m[115]), .si(1'b0), .q(wdata_2x_b[115]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1025cl_sc1_msff_4x wdata_2x_b_reg116 (.d(din_m[116]), .si(1'b0), .q(wdata_2x_b[116]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1026cl_sc1_msff_4x wdata_2x_b_reg117 (.d(din_m[117]), .si(1'b0), .q(wdata_2x_b[117]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1027cl_sc1_msff_4x wdata_2x_b_reg118 (.d(din_m[118]), .si(1'b0), .q(wdata_2x_b[118]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1028cl_sc1_msff_4x wdata_2x_b_reg119 (.d(din_m[119]), .si(1'b0), .q(wdata_2x_b[119]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1029cl_sc1_msff_4x wdata_2x_b_reg120 (.d(din_m[120]), .si(1'b0), .q(wdata_2x_b[120]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1030cl_sc1_msff_4x wdata_2x_b_reg121 (.d(din_m[121]), .si(1'b0), .q(wdata_2x_b[121]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1031cl_sc1_msff_4x wdata_2x_b_reg122 (.d(din_m[122]), .si(1'b0), .q(wdata_2x_b[122]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1032cl_sc1_msff_4x wdata_2x_b_reg123 (.d(din_m[123]), .si(1'b0), .q(wdata_2x_b[123]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1033cl_sc1_msff_4x wdata_2x_b_reg124 (.d(din_m[124]), .si(1'b0), .q(wdata_2x_b[124]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1034cl_sc1_msff_4x wdata_2x_b_reg125 (.d(din_m[125]), .si(1'b0), .q(wdata_2x_b[125]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1035cl_sc1_msff_4x wdata_2x_b_reg126 (.d(din_m[126]), .si(1'b0), .q(wdata_2x_b[126]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1036cl_sc1_msff_4x wdata_2x_b_reg127 (.d(din_m[127]), .si(1'b0), .q(wdata_2x_b[127]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1037cl_sc1_msff_4x wdata_2x_b_reg128 (.d(din_m[128]), .si(1'b0), .q(wdata_2x_b[128]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1038cl_sc1_msff_4x wdata_2x_b_reg129 (.d(din_m[129]), .si(1'b0), .q(wdata_2x_b[129]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1039cl_sc1_msff_4x wdata_2x_b_reg130 (.d(din_m[130]), .si(1'b0), .q(wdata_2x_b[130]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1040cl_sc1_msff_4x wdata_2x_b_reg131 (.d(din_m[131]), .si(1'b0), .q(wdata_2x_b[131]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1041cl_sc1_msff_4x wdata_2x_b_reg132 (.d(din_m[132]), .si(1'b0), .q(wdata_2x_b[132]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1042cl_sc1_msff_4x wdata_2x_b_reg133 (.d(din_m[133]), .si(1'b0), .q(wdata_2x_b[133]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1043cl_sc1_msff_4x wdata_2x_b_reg134 (.d(din_m[134]), .si(1'b0), .q(wdata_2x_b[134]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1044cl_sc1_msff_4x wdata_2x_b_reg135 (.d(din_m[135]), .si(1'b0), .q(wdata_2x_b[135]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1045cl_sc1_msff_4x wdata_2x_b_reg136 (.d(din_m[136]), .si(1'b0), .q(wdata_2x_b[136]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1046cl_sc1_msff_4x wdata_2x_b_reg137 (.d(din_m[137]), .si(1'b0), .q(wdata_2x_b[137]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1047cl_sc1_msff_4x wdata_2x_b_reg138 (.d(din_m[138]), .si(1'b0), .q(wdata_2x_b[138]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1048cl_sc1_msff_4x wdata_2x_b_reg139 (.d(din_m[139]), .si(1'b0), .q(wdata_2x_b[139]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1049cl_sc1_msff_4x wdata_2x_b_reg140 (.d(din_m[140]), .si(1'b0), .q(wdata_2x_b[140]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1050cl_sc1_msff_4x wdata_2x_b_reg141 (.d(din_m[141]), .si(1'b0), .q(wdata_2x_b[141]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1051cl_sc1_msff_4x wdata_2x_b_reg142 (.d(din_m[142]), .si(1'b0), .q(wdata_2x_b[142]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1052cl_sc1_msff_4x wdata_2x_b_reg143 (.d(din_m[143]), .si(1'b0), .q(wdata_2x_b[143]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1053cl_sc1_msff_4x wdata_2x_b_reg144 (.d(din_m[144]), .si(1'b0), .q(wdata_2x_b[144]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1054cl_sc1_msff_4x wdata_2x_b_reg145 (.d(din_m[145]), .si(1'b0), .q(wdata_2x_b[145]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1055cl_sc1_msff_4x wdata_2x_b_reg146 (.d(din_m[146]), .si(1'b0), .q(wdata_2x_b[146]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1056cl_sc1_msff_4x wdata_2x_b_reg147 (.d(din_m[147]), .si(1'b0), .q(wdata_2x_b[147]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1057cl_sc1_msff_4x wdata_2x_b_reg148 (.d(din_m[148]), .si(1'b0), .q(wdata_2x_b[148]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1058cl_sc1_msff_4x wdata_2x_b_reg149 (.d(din_m[149]), .si(1'b0), .q(wdata_2x_b[149]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1059cl_sc1_msff_4x wdata_2x_b_reg150 (.d(din_m[150]), .si(1'b0), .q(wdata_2x_b[150]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1060cl_sc1_msff_4x wdata_2x_b_reg151 (.d(din_m[151]), .si(1'b0), .q(wdata_2x_b[151]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1061//================================================
1062 assign wdata_b = wdata_2x_b;
1063 assign addr_a = rw_addr_2x_a;
1064 assign rd_en_a = do_A_read_2x_a && !do_B_write_2x_a;
1065 assign wr_en_a = do_B_write_2x_a;
1066
1067// geo: assign wcs_a = wr_en_a & ~tcu_array_wr_inhibit & ~rd_en_a ;
1068 assign wcs_a = wr_en_a & ~tcu_array_wr_inhibit;
1069
1070 assign rd_en_column[0] = rd_en_a && !addr_a[1] && !addr_a[0];
1071 assign rd_en_column[1] = rd_en_a && !addr_a[1] && addr_a[0];
1072 assign rd_en_column[2] = rd_en_a && addr_a[1] && !addr_a[0];
1073 assign rd_en_column[3] = rd_en_a && addr_a[1] && addr_a[0];
1074
1075 assign wt_en_column[0] = wcs_a && !addr_a[1] && !addr_a[0];
1076 assign wt_en_column[1] = wcs_a && !addr_a[1] && addr_a[0];
1077 assign wt_en_column[2] = wcs_a && addr_a[1] && !addr_a[0];
1078 assign wt_en_column[3] = wcs_a && addr_a[1] && addr_a[0];
1079
1080//================================================
1081 assign din_tr = { wdata_b[74],wdata_b[72],wdata_b[70],wdata_b[68],wdata_b[66],wdata_b[64],
1082 wdata_b[62],wdata_b[60],wdata_b[58],wdata_b[56],wdata_b[54],wdata_b[52],wdata_b[50],wdata_b[48],
1083 wdata_b[46],wdata_b[44],wdata_b[42],wdata_b[40],wdata_b[38],wdata_b[36],wdata_b[34],wdata_b[32],
1084 wdata_b[30],wdata_b[28],wdata_b[26],wdata_b[24],wdata_b[22],wdata_b[20],wdata_b[18],wdata_b[16],
1085 wdata_b[14],wdata_b[12],wdata_b[10],wdata_b[8],wdata_b[6],wdata_b[4],wdata_b[2],wdata_b[0]};
1086
1087 assign din_br = { wdata_b[75],wdata_b[73],wdata_b[71],wdata_b[69],wdata_b[67],wdata_b[65],
1088 wdata_b[63],wdata_b[61],wdata_b[59],wdata_b[57],wdata_b[55],wdata_b[53],wdata_b[51],wdata_b[49],
1089 wdata_b[47],wdata_b[45],wdata_b[43],wdata_b[41],wdata_b[39],wdata_b[37],wdata_b[35],wdata_b[33],
1090 wdata_b[31],wdata_b[29],wdata_b[27],wdata_b[25],wdata_b[23],wdata_b[21],wdata_b[19],wdata_b[17],
1091 wdata_b[15],wdata_b[13],wdata_b[11],wdata_b[9],wdata_b[7],wdata_b[5],wdata_b[3],wdata_b[1]};
1092
1093 assign din_tl = { wdata_b[150],wdata_b[148],wdata_b[146],wdata_b[144],wdata_b[142],wdata_b[140],
1094 wdata_b[138],wdata_b[136],wdata_b[134],wdata_b[132],wdata_b[130],wdata_b[128],wdata_b[126],wdata_b[124],
1095 wdata_b[122],wdata_b[120],wdata_b[118],wdata_b[116],wdata_b[114],wdata_b[112],wdata_b[110],wdata_b[108],
1096 wdata_b[106],wdata_b[104],wdata_b[102],wdata_b[100],wdata_b[98],wdata_b[96],wdata_b[94],wdata_b[92],
1097 wdata_b[90],wdata_b[88],wdata_b[86],wdata_b[84],wdata_b[82],wdata_b[80],wdata_b[78],wdata_b[76]};
1098
1099 assign din_bl = { wdata_b[151],wdata_b[149],wdata_b[147],wdata_b[145],wdata_b[143],wdata_b[141],
1100 wdata_b[139],wdata_b[137],wdata_b[135],wdata_b[133],wdata_b[131],wdata_b[129],wdata_b[127],wdata_b[125],
1101 wdata_b[123],wdata_b[121],wdata_b[119],wdata_b[117],wdata_b[115],wdata_b[113],wdata_b[111],wdata_b[109],
1102 wdata_b[107],wdata_b[105],wdata_b[103],wdata_b[101],wdata_b[99],wdata_b[97],wdata_b[95],wdata_b[93],
1103 wdata_b[91],wdata_b[89],wdata_b[87],wdata_b[85],wdata_b[83],wdata_b[81],wdata_b[79],wdata_b[77]};
1104
1105 assign { rd_dout[74],rd_dout[72],rd_dout[70],rd_dout[68],rd_dout[66],rd_dout[64],
1106 rd_dout[62],rd_dout[60],rd_dout[58],rd_dout[56],rd_dout[54],rd_dout[52],rd_dout[50],rd_dout[48],
1107 rd_dout[46],rd_dout[44],rd_dout[42],rd_dout[40],rd_dout[38],rd_dout[36],rd_dout[34],rd_dout[32],
1108 rd_dout[30],rd_dout[28],rd_dout[26],rd_dout[24],rd_dout[22],rd_dout[20],rd_dout[18],rd_dout[16],
1109 rd_dout[14],rd_dout[12],rd_dout[10],rd_dout[8],rd_dout[6],rd_dout[4],rd_dout[2],rd_dout[0]}
1110 = ary_rdout_tr;
1111
1112 assign { rd_dout[75],rd_dout[73],rd_dout[71],rd_dout[69],rd_dout[67],rd_dout[65],
1113 rd_dout[63],rd_dout[61],rd_dout[59],rd_dout[57],rd_dout[55],rd_dout[53],rd_dout[51],rd_dout[49],
1114 rd_dout[47],rd_dout[45],rd_dout[43],rd_dout[41],rd_dout[39],rd_dout[37],rd_dout[35],rd_dout[33],
1115 rd_dout[31],rd_dout[29],rd_dout[27],rd_dout[25],rd_dout[23],rd_dout[21],rd_dout[19],rd_dout[17],
1116 rd_dout[15],rd_dout[13],rd_dout[11],rd_dout[9],rd_dout[7],rd_dout[5],rd_dout[3],rd_dout[1]}
1117 = ary_rdout_br;
1118
1119 assign { rd_dout[150],rd_dout[148],rd_dout[146],rd_dout[144],rd_dout[142],rd_dout[140],
1120 rd_dout[138],rd_dout[136],rd_dout[134],rd_dout[132],rd_dout[130],rd_dout[128],rd_dout[126],rd_dout[124],
1121 rd_dout[122],rd_dout[120],rd_dout[118],rd_dout[116],rd_dout[114],rd_dout[112],rd_dout[110],rd_dout[108],
1122 rd_dout[106],rd_dout[104],rd_dout[102],rd_dout[100],rd_dout[98],rd_dout[96],rd_dout[94],rd_dout[92],
1123 rd_dout[90],rd_dout[88],rd_dout[86],rd_dout[84],rd_dout[82],rd_dout[80],rd_dout[78],rd_dout[76]}
1124 = ary_rdout_tl;
1125
1126 assign { rd_dout[151],rd_dout[149],rd_dout[147],rd_dout[145],rd_dout[143],rd_dout[141],
1127 rd_dout[139],rd_dout[137],rd_dout[135],rd_dout[133],rd_dout[131],rd_dout[129],rd_dout[127],rd_dout[125],
1128 rd_dout[123],rd_dout[121],rd_dout[119],rd_dout[117],rd_dout[115],rd_dout[113],rd_dout[111],rd_dout[109],
1129 rd_dout[107],rd_dout[105],rd_dout[103],rd_dout[101],rd_dout[99],rd_dout[97],rd_dout[95],rd_dout[93],
1130 rd_dout[91],rd_dout[89],rd_dout[87],rd_dout[85],rd_dout[83],rd_dout[81],rd_dout[79],rd_dout[77]}
1131 = ary_rdout_bl;
1132
1133//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1134 n2_niu_sp_64x156s_array niu_sp_64x156s_array_br (
1135 .din (din_br[37:0]),
1136 .rw_addr_subbank (addr_a[8:2]),
1137 .rd_addr_column (rd_addr_column_b[1:0]),
1138 .rd_en_column (rd_en_column[3:0]),
1139 .wt_en_column (wt_en_column[3:0]),
1140 .red_value (red_v_br),
1141 .repair_en (red_en_br),
1142 .l1clk (l1clk_2x_free),
1143 .ary_rdout (ary_rdout_br)
1144 );
1145
1146 n2_niu_sp_64x156s_array niu_sp_64x156s_array_tr (
1147 .din (din_tr[37:0]),
1148 .rw_addr_subbank (addr_a[8:2]),
1149 .rd_addr_column (rd_addr_column_b[1:0]),
1150 .rd_en_column (rd_en_column[3:0]),
1151 .wt_en_column (wt_en_column[3:0]),
1152 .red_value (red_v_tr),
1153 .repair_en (red_en_tr),
1154 .l1clk (l1clk_2x_free),
1155 .ary_rdout (ary_rdout_tr)
1156 );
1157
1158 n2_niu_sp_64x156s_array niu_sp_64x156s_array_bl (
1159 .din (din_bl[37:0]),
1160 .rw_addr_subbank (addr_a[8:2]),
1161 .rd_addr_column (rd_addr_column_b[1:0]),
1162 .rd_en_column (rd_en_column[3:0]),
1163 .wt_en_column (wt_en_column[3:0]),
1164 .red_value (red_v_bl),
1165 .repair_en (red_en_bl),
1166 .l1clk (l1clk_2x_free),
1167 .ary_rdout (ary_rdout_bl)
1168 );
1169
1170 n2_niu_sp_64x156s_array niu_sp_64x156s_array_tl (
1171 .din (din_tl[37:0]),
1172 .rw_addr_subbank (addr_a[8:2]),
1173 .rd_addr_column (rd_addr_column_b[1:0]),
1174 .rd_en_column (rd_en_column[3:0]),
1175 .wt_en_column (wt_en_column[3:0]),
1176 .red_value (red_v_tl),
1177 .repair_en (red_en_tl),
1178 .l1clk (l1clk_2x_free),
1179 .ary_rdout (ary_rdout_tl)
1180 );
1181
1182 assign dout = rd_dout[151:0];
1183
1184// fixscan start:
1185 assign dff_wr_adr_m_scanin[0] = scan_in ;
1186 assign dff_rd_adr_m_scanin[0] = dff_wr_adr_m_scanout[0] ;
1187 assign dff_wr_adr_m_scanin[1] = dff_rd_adr_m_scanout[0] ;
1188 assign dff_rd_adr_m_scanin[1] = dff_wr_adr_m_scanout[1] ;
1189 assign dff_wr_adr_m_scanin[2] = dff_rd_adr_m_scanout[1] ;
1190 assign dff_rd_adr_m_scanin[2] = dff_wr_adr_m_scanout[2] ;
1191 assign dff_wr_adr_m_scanin[3] = dff_rd_adr_m_scanout[2] ;
1192 assign dff_rd_adr_m_scanin[3] = dff_wr_adr_m_scanout[3] ;
1193 assign dff_wr_adr_m_scanin[4] = dff_rd_adr_m_scanout[3] ;
1194 assign dff_rd_adr_m_scanin[4] = dff_wr_adr_m_scanout[4] ;
1195 assign dff_wr_adr_m_scanin[5] = dff_rd_adr_m_scanout[4] ;
1196 assign dff_rd_adr_m_scanin[5] = dff_wr_adr_m_scanout[5] ;
1197 assign dff_wr_adr_m_scanin[6] = dff_rd_adr_m_scanout[5] ;
1198 assign dff_rd_adr_m_scanin[6] = dff_wr_adr_m_scanout[6] ;
1199 assign dff_wr_adr_m_scanin[7] = dff_rd_adr_m_scanout[6] ;
1200 assign dff_rd_adr_m_scanin[7] = dff_wr_adr_m_scanout[7] ;
1201 assign dff_wr_adr_m_scanin[8] = dff_rd_adr_m_scanout[7] ;
1202 assign dff_rd_adr_m_scanin[8] = dff_wr_adr_m_scanout[8] ;
1203 assign dff_wr_en_m_scanin = dff_rd_adr_m_scanout[8] ;
1204 assign dff_rd_en_m_scanin = dff_wr_en_m_scanout ;
1205 assign dff_test_clk_scanin = dff_rd_en_m_scanout ;
1206 assign dff_test_mode_scanin = dff_test_clk_scanout ;
1207
1208 assign dff_wdata_m_scanin[151] = dff_test_mode_scanout ;
1209 assign dff_wdata_m_scanin[150] = dff_wdata_m_scanout[151] ;
1210 assign dff_wdata_m_scanin[149] = dff_wdata_m_scanout[150] ;
1211 assign dff_wdata_m_scanin[148] = dff_wdata_m_scanout[149] ;
1212 assign dff_wdata_m_scanin[147] = dff_wdata_m_scanout[148] ;
1213 assign dff_wdata_m_scanin[146] = dff_wdata_m_scanout[147] ;
1214 assign dff_wdata_m_scanin[145] = dff_wdata_m_scanout[146] ;
1215 assign dff_wdata_m_scanin[144] = dff_wdata_m_scanout[145] ;
1216 assign dff_wdata_m_scanin[143] = dff_wdata_m_scanout[144] ;
1217 assign dff_wdata_m_scanin[142] = dff_wdata_m_scanout[143] ;
1218 assign dff_wdata_m_scanin[141] = dff_wdata_m_scanout[142] ;
1219 assign dff_wdata_m_scanin[140] = dff_wdata_m_scanout[141] ;
1220 assign dff_wdata_m_scanin[139] = dff_wdata_m_scanout[140] ;
1221 assign dff_wdata_m_scanin[138] = dff_wdata_m_scanout[139] ;
1222 assign dff_wdata_m_scanin[137] = dff_wdata_m_scanout[138] ;
1223 assign dff_wdata_m_scanin[136] = dff_wdata_m_scanout[137] ;
1224 assign dff_wdata_m_scanin[135] = dff_wdata_m_scanout[136] ;
1225 assign dff_wdata_m_scanin[134] = dff_wdata_m_scanout[135] ;
1226 assign dff_wdata_m_scanin[133] = dff_wdata_m_scanout[134] ;
1227 assign dff_wdata_m_scanin[132] = dff_wdata_m_scanout[133] ;
1228 assign dff_wdata_m_scanin[131] = dff_wdata_m_scanout[132] ;
1229 assign dff_wdata_m_scanin[130] = dff_wdata_m_scanout[131] ;
1230 assign dff_wdata_m_scanin[129] = dff_wdata_m_scanout[130] ;
1231 assign dff_wdata_m_scanin[128] = dff_wdata_m_scanout[129] ;
1232 assign dff_wdata_m_scanin[127] = dff_wdata_m_scanout[128] ;
1233 assign dff_wdata_m_scanin[126] = dff_wdata_m_scanout[127] ;
1234 assign dff_wdata_m_scanin[125] = dff_wdata_m_scanout[126] ;
1235 assign dff_wdata_m_scanin[124] = dff_wdata_m_scanout[125] ;
1236 assign dff_wdata_m_scanin[123] = dff_wdata_m_scanout[124] ;
1237 assign dff_wdata_m_scanin[122] = dff_wdata_m_scanout[123] ;
1238 assign dff_wdata_m_scanin[121] = dff_wdata_m_scanout[122] ;
1239 assign dff_wdata_m_scanin[120] = dff_wdata_m_scanout[121] ;
1240 assign dff_wdata_m_scanin[119] = dff_wdata_m_scanout[120] ;
1241 assign dff_wdata_m_scanin[118] = dff_wdata_m_scanout[119] ;
1242
1243 assign dff_wdata_m_scanin[117] = dff_wdata_m_scanout[118] ;
1244 assign dff_wdata_m_scanin[116] = dff_wdata_m_scanout[117] ;
1245 assign dff_wdata_m_scanin[115] = dff_wdata_m_scanout[116] ;
1246 assign dff_wdata_m_scanin[114] = dff_wdata_m_scanout[115] ;
1247
1248 assign dff_wdata_m_scanin[113] = dff_wdata_m_scanout[114] ;
1249 assign dff_wdata_m_scanin[112] = dff_wdata_m_scanout[113] ;
1250 assign dff_wdata_m_scanin[111] = dff_wdata_m_scanout[112] ;
1251 assign dff_wdata_m_scanin[110] = dff_wdata_m_scanout[111] ;
1252 assign dff_wdata_m_scanin[109] = dff_wdata_m_scanout[110] ;
1253 assign dff_wdata_m_scanin[108] = dff_wdata_m_scanout[109] ;
1254 assign dff_wdata_m_scanin[107] = dff_wdata_m_scanout[108] ;
1255 assign dff_wdata_m_scanin[106] = dff_wdata_m_scanout[107] ;
1256 assign dff_wdata_m_scanin[105] = dff_wdata_m_scanout[106] ;
1257 assign dff_wdata_m_scanin[104] = dff_wdata_m_scanout[105] ;
1258 assign dff_wdata_m_scanin[103] = dff_wdata_m_scanout[104] ;
1259 assign dff_wdata_m_scanin[102] = dff_wdata_m_scanout[103] ;
1260 assign dff_wdata_m_scanin[101] = dff_wdata_m_scanout[102] ;
1261 assign dff_wdata_m_scanin[100] = dff_wdata_m_scanout[101] ;
1262 assign dff_wdata_m_scanin[99] = dff_wdata_m_scanout[100] ;
1263 assign dff_wdata_m_scanin[98] = dff_wdata_m_scanout[99] ;
1264 assign dff_wdata_m_scanin[97] = dff_wdata_m_scanout[98] ;
1265 assign dff_wdata_m_scanin[96] = dff_wdata_m_scanout[97] ;
1266 assign dff_wdata_m_scanin[95] = dff_wdata_m_scanout[96] ;
1267 assign dff_wdata_m_scanin[94] = dff_wdata_m_scanout[95] ;
1268 assign dff_wdata_m_scanin[93] = dff_wdata_m_scanout[94] ;
1269 assign dff_wdata_m_scanin[92] = dff_wdata_m_scanout[93] ;
1270 assign dff_wdata_m_scanin[91] = dff_wdata_m_scanout[92] ;
1271 assign dff_wdata_m_scanin[90] = dff_wdata_m_scanout[91] ;
1272 assign dff_wdata_m_scanin[89] = dff_wdata_m_scanout[90] ;
1273 assign dff_wdata_m_scanin[88] = dff_wdata_m_scanout[89] ;
1274 assign dff_wdata_m_scanin[87] = dff_wdata_m_scanout[88] ;
1275 assign dff_wdata_m_scanin[86] = dff_wdata_m_scanout[87] ;
1276 assign dff_wdata_m_scanin[85] = dff_wdata_m_scanout[86] ;
1277 assign dff_wdata_m_scanin[84] = dff_wdata_m_scanout[85] ;
1278 assign dff_wdata_m_scanin[83] = dff_wdata_m_scanout[84] ;
1279 assign dff_wdata_m_scanin[82] = dff_wdata_m_scanout[83] ;
1280 assign dff_wdata_m_scanin[81] = dff_wdata_m_scanout[82] ;
1281 assign dff_wdata_m_scanin[80] = dff_wdata_m_scanout[81] ;
1282 assign dff_wdata_m_scanin[79] = dff_wdata_m_scanout[80] ;
1283 assign dff_wdata_m_scanin[78] = dff_wdata_m_scanout[79] ;
1284 assign dff_wdata_m_scanin[77] = dff_wdata_m_scanout[78] ;
1285 assign dff_wdata_m_scanin[76] = dff_wdata_m_scanout[77] ;
1286
1287 assign dff_wdata_m_scanin[75] = dff_wdata_m_scanout[76] ;
1288 assign dff_wdata_m_scanin[74] = dff_wdata_m_scanout[75] ;
1289 assign dff_wdata_m_scanin[73] = dff_wdata_m_scanout[74] ;
1290 assign dff_wdata_m_scanin[72] = dff_wdata_m_scanout[73] ;
1291 assign dff_wdata_m_scanin[71] = dff_wdata_m_scanout[72] ;
1292 assign dff_wdata_m_scanin[70] = dff_wdata_m_scanout[71] ;
1293 assign dff_wdata_m_scanin[69] = dff_wdata_m_scanout[70] ;
1294 assign dff_wdata_m_scanin[68] = dff_wdata_m_scanout[69] ;
1295 assign dff_wdata_m_scanin[67] = dff_wdata_m_scanout[68] ;
1296 assign dff_wdata_m_scanin[66] = dff_wdata_m_scanout[67] ;
1297 assign dff_wdata_m_scanin[65] = dff_wdata_m_scanout[66] ;
1298 assign dff_wdata_m_scanin[64] = dff_wdata_m_scanout[65] ;
1299 assign dff_wdata_m_scanin[63] = dff_wdata_m_scanout[64] ;
1300 assign dff_wdata_m_scanin[62] = dff_wdata_m_scanout[63] ;
1301 assign dff_wdata_m_scanin[61] = dff_wdata_m_scanout[62] ;
1302 assign dff_wdata_m_scanin[60] = dff_wdata_m_scanout[61] ;
1303 assign dff_wdata_m_scanin[59] = dff_wdata_m_scanout[60] ;
1304 assign dff_wdata_m_scanin[58] = dff_wdata_m_scanout[59] ;
1305 assign dff_wdata_m_scanin[57] = dff_wdata_m_scanout[58] ;
1306 assign dff_wdata_m_scanin[56] = dff_wdata_m_scanout[57] ;
1307 assign dff_wdata_m_scanin[55] = dff_wdata_m_scanout[56] ;
1308 assign dff_wdata_m_scanin[54] = dff_wdata_m_scanout[55] ;
1309 assign dff_wdata_m_scanin[53] = dff_wdata_m_scanout[54] ;
1310 assign dff_wdata_m_scanin[52] = dff_wdata_m_scanout[53] ;
1311 assign dff_wdata_m_scanin[51] = dff_wdata_m_scanout[52] ;
1312 assign dff_wdata_m_scanin[50] = dff_wdata_m_scanout[51] ;
1313 assign dff_wdata_m_scanin[49] = dff_wdata_m_scanout[50] ;
1314 assign dff_wdata_m_scanin[48] = dff_wdata_m_scanout[49] ;
1315 assign dff_wdata_m_scanin[47] = dff_wdata_m_scanout[48] ;
1316 assign dff_wdata_m_scanin[46] = dff_wdata_m_scanout[47] ;
1317 assign dff_wdata_m_scanin[45] = dff_wdata_m_scanout[46] ;
1318 assign dff_wdata_m_scanin[44] = dff_wdata_m_scanout[45] ;
1319 assign dff_wdata_m_scanin[43] = dff_wdata_m_scanout[44] ;
1320 assign dff_wdata_m_scanin[42] = dff_wdata_m_scanout[43] ;
1321 assign dff_wdata_m_scanin[41] = dff_wdata_m_scanout[42] ;
1322 assign dff_wdata_m_scanin[40] = dff_wdata_m_scanout[41] ;
1323 assign dff_wdata_m_scanin[39] = dff_wdata_m_scanout[40] ;
1324 assign dff_wdata_m_scanin[38] = dff_wdata_m_scanout[39] ;
1325
1326 assign dff_wdata_m_scanin[37] = dff_wdata_m_scanout[38] ;
1327 assign dff_wdata_m_scanin[36] = dff_wdata_m_scanout[37] ;
1328 assign dff_wdata_m_scanin[35] = dff_wdata_m_scanout[36] ;
1329 assign dff_wdata_m_scanin[34] = dff_wdata_m_scanout[35] ;
1330 assign dff_wdata_m_scanin[33] = dff_wdata_m_scanout[34] ;
1331 assign dff_wdata_m_scanin[32] = dff_wdata_m_scanout[33] ;
1332 assign dff_wdata_m_scanin[31] = dff_wdata_m_scanout[32] ;
1333 assign dff_wdata_m_scanin[30] = dff_wdata_m_scanout[31] ;
1334 assign dff_wdata_m_scanin[29] = dff_wdata_m_scanout[30] ;
1335 assign dff_wdata_m_scanin[28] = dff_wdata_m_scanout[29] ;
1336 assign dff_wdata_m_scanin[27] = dff_wdata_m_scanout[28] ;
1337 assign dff_wdata_m_scanin[26] = dff_wdata_m_scanout[27] ;
1338 assign dff_wdata_m_scanin[25] = dff_wdata_m_scanout[26] ;
1339 assign dff_wdata_m_scanin[24] = dff_wdata_m_scanout[25] ;
1340 assign dff_wdata_m_scanin[23] = dff_wdata_m_scanout[24] ;
1341 assign dff_wdata_m_scanin[22] = dff_wdata_m_scanout[23] ;
1342 assign dff_wdata_m_scanin[21] = dff_wdata_m_scanout[22] ;
1343 assign dff_wdata_m_scanin[20] = dff_wdata_m_scanout[21] ;
1344 assign dff_wdata_m_scanin[19] = dff_wdata_m_scanout[20] ;
1345 assign dff_wdata_m_scanin[18] = dff_wdata_m_scanout[19] ;
1346 assign dff_wdata_m_scanin[17] = dff_wdata_m_scanout[18] ;
1347 assign dff_wdata_m_scanin[16] = dff_wdata_m_scanout[17] ;
1348 assign dff_wdata_m_scanin[15] = dff_wdata_m_scanout[16] ;
1349 assign dff_wdata_m_scanin[14] = dff_wdata_m_scanout[15] ;
1350 assign dff_wdata_m_scanin[13] = dff_wdata_m_scanout[14] ;
1351 assign dff_wdata_m_scanin[12] = dff_wdata_m_scanout[13] ;
1352 assign dff_wdata_m_scanin[11] = dff_wdata_m_scanout[12] ;
1353 assign dff_wdata_m_scanin[10] = dff_wdata_m_scanout[11] ;
1354 assign dff_wdata_m_scanin[9] = dff_wdata_m_scanout[10] ;
1355 assign dff_wdata_m_scanin[8] = dff_wdata_m_scanout[9] ;
1356 assign dff_wdata_m_scanin[7] = dff_wdata_m_scanout[8] ;
1357 assign dff_wdata_m_scanin[6] = dff_wdata_m_scanout[7] ;
1358 assign dff_wdata_m_scanin[5] = dff_wdata_m_scanout[6] ;
1359 assign dff_wdata_m_scanin[4] = dff_wdata_m_scanout[5] ;
1360 assign dff_wdata_m_scanin[3] = dff_wdata_m_scanout[4] ;
1361 assign dff_wdata_m_scanin[2] = dff_wdata_m_scanout[3] ;
1362 assign dff_wdata_m_scanin[1] = dff_wdata_m_scanout[2] ;
1363 assign dff_wdata_m_scanin[0] = dff_wdata_m_scanout[1] ;
1364 assign scan_out = dff_wdata_m_scanout[0] ;
1365
1366
1367
1368// fixscan end:
1369
1370endmodule
1371
1372
1373
1374//
1375// invert macro
1376//
1377//
1378
1379
1380
1381
1382
1383module niu256_inv_macro__width_1 (
1384 din,
1385 dout);
1386 input [0:0] din;
1387 output [0:0] dout;
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397cl_u1_inv_1x d0_0 (
1398.in(din[0]),
1399.out(dout[0])
1400);
1401
1402
1403
1404
1405
1406endmodule
1407
1408
1409
1410
1411
1412//
1413// and macro for ports = 2,3,4
1414//
1415//
1416
1417
1418
1419
1420
1421module niu256_and_macro__width_1 (
1422 din0,
1423 din1,
1424 dout);
1425wire [0:0] nandout;
1426
1427 input [0:0] din0;
1428 input [0:0] din1;
1429 output [0:0] dout;
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439cl_u1_nand2_1x d0_0 (
1440.in0(din0[0]),
1441.in1(din1[0]),
1442.out(nandout[0])
1443);
1444
1445cl_u1_inv_1x d1_0 (
1446.in(nandout[0]),
1447.out(dout[0])
1448);
1449
1450
1451
1452
1453endmodule
1454
1455
1456
1457
1458
1459//
1460// and macro for ports = 2,3,4
1461//
1462//
1463
1464
1465
1466
1467
1468module niu256_and_macro__width_9 (
1469 din0,
1470 din1,
1471 dout);
1472wire [8:0] nandout;
1473
1474 input [8:0] din0;
1475 input [8:0] din1;
1476 output [8:0] dout;
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486cl_u1_nand2_1x d0_0 (
1487.in0(din0[0]),
1488.in1(din1[0]),
1489.out(nandout[0])
1490);
1491
1492cl_u1_nand2_1x d0_1 (
1493.in0(din0[1]),
1494.in1(din1[1]),
1495.out(nandout[1])
1496);
1497
1498cl_u1_nand2_1x d0_2 (
1499.in0(din0[2]),
1500.in1(din1[2]),
1501.out(nandout[2])
1502);
1503
1504cl_u1_nand2_1x d0_3 (
1505.in0(din0[3]),
1506.in1(din1[3]),
1507.out(nandout[3])
1508);
1509
1510cl_u1_nand2_1x d0_4 (
1511.in0(din0[4]),
1512.in1(din1[4]),
1513.out(nandout[4])
1514);
1515
1516cl_u1_nand2_1x d0_5 (
1517.in0(din0[5]),
1518.in1(din1[5]),
1519.out(nandout[5])
1520);
1521
1522cl_u1_nand2_1x d0_6 (
1523.in0(din0[6]),
1524.in1(din1[6]),
1525.out(nandout[6])
1526);
1527
1528cl_u1_nand2_1x d0_7 (
1529.in0(din0[7]),
1530.in1(din1[7]),
1531.out(nandout[7])
1532);
1533
1534cl_u1_nand2_1x d0_8 (
1535.in0(din0[8]),
1536.in1(din1[8]),
1537.out(nandout[8])
1538);
1539
1540cl_u1_inv_1x d1_0 (
1541.in(nandout[0]),
1542.out(dout[0])
1543);
1544cl_u1_inv_1x d1_1 (
1545.in(nandout[1]),
1546.out(dout[1])
1547);
1548cl_u1_inv_1x d1_2 (
1549.in(nandout[2]),
1550.out(dout[2])
1551);
1552cl_u1_inv_1x d1_3 (
1553.in(nandout[3]),
1554.out(dout[3])
1555);
1556cl_u1_inv_1x d1_4 (
1557.in(nandout[4]),
1558.out(dout[4])
1559);
1560cl_u1_inv_1x d1_5 (
1561.in(nandout[5]),
1562.out(dout[5])
1563);
1564cl_u1_inv_1x d1_6 (
1565.in(nandout[6]),
1566.out(dout[6])
1567);
1568cl_u1_inv_1x d1_7 (
1569.in(nandout[7]),
1570.out(dout[7])
1571);
1572cl_u1_inv_1x d1_8 (
1573.in(nandout[8]),
1574.out(dout[8])
1575);
1576
1577
1578
1579
1580endmodule
1581
1582
1583
1584
1585
1586//
1587// or macro for ports = 2,3
1588//
1589//
1590
1591
1592
1593
1594
1595module niu256_or_macro__width_9 (
1596 din0,
1597 din1,
1598 dout);
1599wire [8:0] norout;
1600
1601 input [8:0] din0;
1602 input [8:0] din1;
1603 output [8:0] dout;
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613cl_u1_nor2_1x d0_0 (
1614.in0(din0[0]),
1615.in1(din1[0]),
1616.out(norout[0])
1617);
1618
1619cl_u1_nor2_1x d0_1 (
1620.in0(din0[1]),
1621.in1(din1[1]),
1622.out(norout[1])
1623);
1624
1625cl_u1_nor2_1x d0_2 (
1626.in0(din0[2]),
1627.in1(din1[2]),
1628.out(norout[2])
1629);
1630
1631cl_u1_nor2_1x d0_3 (
1632.in0(din0[3]),
1633.in1(din1[3]),
1634.out(norout[3])
1635);
1636
1637cl_u1_nor2_1x d0_4 (
1638.in0(din0[4]),
1639.in1(din1[4]),
1640.out(norout[4])
1641);
1642
1643cl_u1_nor2_1x d0_5 (
1644.in0(din0[5]),
1645.in1(din1[5]),
1646.out(norout[5])
1647);
1648
1649cl_u1_nor2_1x d0_6 (
1650.in0(din0[6]),
1651.in1(din1[6]),
1652.out(norout[6])
1653);
1654
1655cl_u1_nor2_1x d0_7 (
1656.in0(din0[7]),
1657.in1(din1[7]),
1658.out(norout[7])
1659);
1660
1661cl_u1_nor2_1x d0_8 (
1662.in0(din0[8]),
1663.in1(din1[8]),
1664.out(norout[8])
1665);
1666
1667cl_u1_inv_1x d1_0 (
1668.in(norout[0]),
1669.out(dout[0])
1670);
1671cl_u1_inv_1x d1_1 (
1672.in(norout[1]),
1673.out(dout[1])
1674);
1675cl_u1_inv_1x d1_2 (
1676.in(norout[2]),
1677.out(dout[2])
1678);
1679cl_u1_inv_1x d1_3 (
1680.in(norout[3]),
1681.out(dout[3])
1682);
1683cl_u1_inv_1x d1_4 (
1684.in(norout[4]),
1685.out(dout[4])
1686);
1687cl_u1_inv_1x d1_5 (
1688.in(norout[5]),
1689.out(dout[5])
1690);
1691cl_u1_inv_1x d1_6 (
1692.in(norout[6]),
1693.out(dout[6])
1694);
1695cl_u1_inv_1x d1_7 (
1696.in(norout[7]),
1697.out(dout[7])
1698);
1699cl_u1_inv_1x d1_8 (
1700.in(norout[8]),
1701.out(dout[8])
1702);
1703
1704
1705
1706
1707endmodule
1708
1709
1710
1711
1712
1713module n2_niu_sp_64x156s_array (
1714 din,
1715 rw_addr_subbank,
1716 rd_addr_column,
1717 rd_en_column,
1718 wt_en_column,
1719 red_value,
1720 repair_en,
1721 l1clk,
1722 ary_rdout);
1723
1724input [37:0] din;
1725input [6:0] rw_addr_subbank;
1726input [1:0] rd_addr_column;
1727input [3:0] rd_en_column;
1728input [3:0] wt_en_column;
1729input [5:0] red_value;
1730input repair_en;
1731input l1clk;
1732
1733output [37:0] ary_rdout;
1734
1735wire [37:0] ary_rdout;
1736
1737wire [37:0] ary_rdout_c0;
1738wire [37:0] ary_rdout_c1;
1739wire [37:0] ary_rdout_c2;
1740wire [37:0] ary_rdout_c3;
1741
1742 n2_niu_sp_64x39s_subbank niu_sp_64x39s_subbank_c0 (
1743 .din (din),
1744 .rw_addr (rw_addr_subbank),
1745 .rd_en (rd_en_column[0]),
1746 .wt_en (wt_en_column[0]),
1747 .red_value (red_value),
1748 .repair_en (repair_en),
1749 .l1clk (l1clk),
1750 .ary_rdout (ary_rdout_c0)
1751 );
1752
1753 n2_niu_sp_64x39s_subbank niu_sp_64x39s_subbank_c1 (
1754 .din (din),
1755 .rw_addr (rw_addr_subbank),
1756 .rd_en (rd_en_column[1]),
1757 .wt_en (wt_en_column[1]),
1758 .red_value (red_value),
1759 .repair_en (repair_en),
1760 .l1clk (l1clk),
1761 .ary_rdout (ary_rdout_c1)
1762 );
1763
1764 n2_niu_sp_64x39s_subbank niu_sp_64x39s_subbank_c2 (
1765 .din (din),
1766 .rw_addr (rw_addr_subbank),
1767 .rd_en (rd_en_column[2]),
1768 .wt_en (wt_en_column[2]),
1769 .red_value (red_value),
1770 .repair_en (repair_en),
1771 .l1clk (l1clk),
1772 .ary_rdout (ary_rdout_c2)
1773 );
1774
1775 n2_niu_sp_64x39s_subbank niu_sp_64x39s_subbank_c3 (
1776 .din (din),
1777 .rw_addr (rw_addr_subbank),
1778 .rd_en (rd_en_column[3]),
1779 .wt_en (wt_en_column[3]),
1780 .red_value (red_value),
1781 .repair_en (repair_en),
1782 .l1clk (l1clk),
1783 .ary_rdout (ary_rdout_c3)
1784 );
1785
1786
1787assign ary_rdout = rd_addr_column[1]? ( rd_addr_column[0]? ary_rdout_c3: ary_rdout_c2 ) :
1788 ( rd_addr_column[0]? ary_rdout_c1: ary_rdout_c0);
1789
1790
1791endmodule
1792
1793
1794
1795
1796module n2_niu_sp_64x39s_subbank (
1797 din,
1798 rw_addr,
1799 rd_en,
1800 wt_en,
1801 red_value,
1802 repair_en,
1803 l1clk,
1804 ary_rdout);
1805// din,
1806// rw_addr,
1807// rd_en,
1808// wt_en,
1809// red_value,
1810// repair_en,
1811// l1clk,
1812// ary_rdout
1813// );
1814
1815input [37:0] din;
1816input [6:0] rw_addr;
1817input rd_en;
1818input wt_en;
1819input [5:0] red_value;
1820input repair_en;
1821input l1clk;
1822
1823output [37:0] ary_rdout;
1824
1825// ----------------------------------------------------------------------------
1826// Zero In Checkers
1827// ----------------------------------------------------------------------------
1828// checker to verify on accesses's that no bits are x
1829// 0in kndr -var rw_addr
1830// 0in kndr -var rd_en
1831// 0in kndr -var wt_en
1832// 0in kndr -var red_value
1833// 0in kndr -var repair_en
1834
1835wire [37:0] ary_rdout;
1836
1837wire [38:0] wr_data;
1838
1839reg [38:0] mem_ary_dout;
1840
1841integer n;
1842
1843//`ifndef INNOLOGIC
1844//// Emulate reset
1845//integer i;
1846//initial begin
1847// for (i=0; i<64; i=i+1) begin
1848// mem[i] = {39{1'b0}};
1849// end
1850// mem_ary_dout = {39{1'b0}};
1851//end
1852//`endif
1853
1854//////////////////////////////
1855// Redundancy write shifter //
1856//////////////////////////////
1857reg [38:0] wr_data_rep;
1858
1859wire [31:0] red_value_32bit = {{(32-6){1'h0}},red_value}; // 0in < max 37 -active ( (repair_en==1'b1) && (l1clk==1'b1) ) -group mbist_mode
1860
1861
1862wire [38:0] shift_col_en = {39{~repair_en}} |
1863 ( { {37{1'b1}}, {2'b00} } << red_value[5:0] ) ;
1864
1865assign wr_data[38:0] = (~shift_col_en & {{1'b0}, din}) | (shift_col_en & {din, {din[0]}}) ;
1866
1867
1868//////////////////////////////
1869// Read/write array //
1870//////////////////////////////
1871reg rd_en_blat;
1872
1873 always @ (l1clk or rd_en)
1874 if (!l1clk)
1875 rd_en_blat = rd_en;
1876 else
1877 rd_en_blat = rd_en_blat;
1878
1879`ifdef AXIS_SMEM_BAD
1880
1881// internal variable
1882integer k, l;
1883
1884reg [38:0] write_mask;
1885
1886wire [38:0] axis_dout ;
1887wire [38:0] axis_din = wr_data ;
1888wire [5:0] axis_waddr = rw_addr[5:0];
1889wire [5:0] axis_raddr = rw_addr[5:0];
1890wire axis_wen = wt_en ;
1891wire axis_ren = rd_en ;
1892wire axis_clk = l1clk ;
1893
1894axis_smem #(6, 39, 2, 1'b0) mem // addr_width,data_width,num_ports,init_value
1895( {axis_dout , {39{1'bz}} }, // Output Port (1,2)
1896 {{39{1'bz}} , axis_din }, // Input Port (1,2)
1897 {axis_raddr , axis_waddr }, // Address Port (1,2)
1898 {1'b0 , axis_wen }, // Write Enable (1,2)
1899 {1'b1 , 1'b1 }, // Chip Enable (1,2)
1900 {axis_clk , axis_clk }, // Port Clocks (1,2)
1901 {{39{1'bz}} , {39{1'bz}}} ); // Write Mask (1,2)
1902
1903always @(posedge l1clk) begin
1904 if (rd_en_blat) begin
1905 if (axis_wen)
1906 mem_ary_dout <= 39'hx;
1907 else
1908 mem_ary_dout <= axis_dout;
1909 end
1910end
1911
1912`else
1913
1914reg [38:0] mem[0:64-1];
1915
1916 always @ (negedge l1clk) begin
1917 if (wt_en) begin
1918 if(rd_en)
1919 mem[rw_addr[5:0]] <= {39{1'hx}}; // 0in < fire -severity 1 -message "Detected rd/wr collision in NIU 512x152s RAM, dout driven as X's" -group mbist_mode
1920
1921 else
1922 mem[rw_addr[5:0]] <= wr_data;
1923 end
1924 end
1925
1926
1927 always @(posedge l1clk) begin
1928 if (rd_en_blat) begin
1929 if (wt_en)
1930 mem_ary_dout <= {39{1'hx}}; // 0in < fire -severity 1 -message "Detected rd/wr collision in NIU 512x152s RAM, dout driven as X's" -group mbist_mode
1931
1932
1933 else
1934 mem_ary_dout <= mem[rw_addr[5:0]] ;
1935 end
1936 end
1937
1938// Initialize the arrays.
1939`ifndef NOINITMEM
1940integer j;
1941initial begin
1942 for (j=0;j<64;j=j+1) begin
1943 mem[j] = 39'd0;
1944 end
1945
1946 mem_ary_dout[38:0] = 39'h0;
1947
1948end
1949`endif // NOINITMEM
1950
1951`endif // AXIS_SMEM
1952
1953//////////////////////////////
1954// Redundancy read shifter //
1955//////////////////////////////
1956reg [37:0] mem_ary_dout_rep;
1957
1958 always @(red_value_32bit or mem_ary_dout ) begin
1959 for (n = 0; n < 38; n = n + 1) begin
1960 if ( n <= (red_value_32bit))
1961 mem_ary_dout_rep[n] = mem_ary_dout[n];
1962 else
1963 mem_ary_dout_rep[n] = mem_ary_dout[n+1];
1964 end
1965 end
1966
1967 assign ary_rdout = repair_en ? mem_ary_dout_rep : mem_ary_dout[38:1];
1968
1969
1970
1971
1972supply0 vss;
1973supply1 vdd;
1974
1975endmodule
1976
1977
1978
1979
1980module n2_niu_dp_256x152s_repair (
1981 tcu_aclk,
1982 tcu_bclk,
1983 tcu_scan_en,
1984 tcu_se_scancollar_in,
1985 tcu_se_scancollar_out,
1986 pce,
1987 tcu_pce_ov,
1988 tcu_array_wr_inhibit,
1989 scan_in,
1990 hdr_sram_rvalue,
1991 hdr_sram_rid,
1992 hdr_sram_wr_en,
1993 hdr_sram_red_clr,
1994 l2clk,
1995 sram_hdr_read_data,
1996 red_value_b0,
1997 red_value_b1,
1998 red_value_b2,
1999 red_value_b3,
2000 repair_en_bk,
2001 scan_out);
2002`define RID_BITS__1 2
2003
2004
2005wire l1clk_in_en;
2006wire l1clk_out_en;
2007wire l1clk_gate_en;
2008wire [6:0] hdr_rvalue_reg_scanin;
2009wire [6:0] hdr_rvalue_reg_scanout;
2010wire [1:0] hdr_sram_rid_reg_scanin;
2011wire [1:0] hdr_sram_rid_reg_scanout;
2012wire hdr_sram_wr_en_reg_scanin;
2013wire hdr_sram_wr_en_reg_scanout;
2014wire hdr_sram_red_clr_reg_scanin;
2015wire hdr_sram_red_clr_reg_scanout;
2016wire [6:0] sram_read_data_reg_scanin;
2017wire [6:0] sram_read_data_reg_scanout;
2018
2019
2020
2021
2022input tcu_aclk;
2023input tcu_bclk;
2024input tcu_scan_en;
2025input tcu_se_scancollar_in;
2026input tcu_se_scancollar_out;
2027input pce;
2028input tcu_pce_ov;
2029input tcu_array_wr_inhibit; // direct input, not flopped
2030input scan_in;
2031input [6:0] hdr_sram_rvalue;
2032input [`RID_BITS__1-1:0] hdr_sram_rid;
2033input hdr_sram_wr_en;
2034input hdr_sram_red_clr;
2035
2036input l2clk;
2037
2038output [6:0] sram_hdr_read_data;
2039
2040output [5:0] red_value_b0; // to subbank
2041output [5:0] red_value_b1;
2042output [5:0] red_value_b2;
2043output [5:0] red_value_b3;
2044output [3:0] repair_en_bk;
2045
2046output scan_out;
2047
2048wire [6:0] sram_hdr_read_data;
2049
2050wire [5:0] red_value_b0; // to subbank
2051wire [5:0] red_value_b1;
2052wire [5:0] red_value_b2;
2053wire [5:0] red_value_b3;
2054wire [3:0] repair_en_bk; // to subbank
2055
2056wire scan_out;
2057
2058// scan renames
2059wire siclk = tcu_aclk;
2060wire soclk = tcu_bclk;
2061// end scan
2062
2063wire [3:0] red_id;
2064wire [3:0] red_reg_clk_p;
2065wire [5:0] fuse_red_data;
2066wire fuse_red_enable;
2067
2068wire [5:0] red_data_reg_b0;
2069wire [5:0] red_data_reg_b1;
2070wire [5:0] red_data_reg_b2;
2071wire [5:0] red_data_reg_b3;
2072wire [3:0] red_en_reg_bk;
2073
2074wire [3:0] scan_input_bk;
2075wire [3:0] scan_output_bk;
2076
2077//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2078//================================================
2079// l2 clock Domain: Clock headers
2080//================================================
2081wire l1clk_in;
2082wire l1clk_gate;
2083wire l1clk_out;
2084
2085//cl_sc1_l1hdr_8x l1ch_in (
2086// .l2clk (l2clk),
2087// .pce (pce),
2088// .l1clk (l1clk_in),
2089// .se (tcu_se_scancollar_in),
2090// .pce_ov (tcu_pce_ov),
2091// .stop (1'b0)
2092// );
2093
2094
2095//cl_sc1_l1hdr_8x l1ch_out (
2096// .l2clk (l2clk),
2097// .pce (pce),
2098// .l1clk (l1clk_out),
2099// .se (tcu_se_scancollar_out),
2100// .pce_ov (tcu_pce_ov),
2101// .stop (1'b0)
2102// );
2103
2104//cl_sc1_l1hdr_8x l1ch_gate (
2105// .l1clk (l1clk_gate),
2106// .l2clk (l2clk),
2107// .se (tcu_scan_en),
2108// .pce (pce),
2109// .pce_ov (tcu_pce_ov),
2110// .stop (1'b0)
2111// );
2112
2113///////////////////////////////////
2114// decomposed l1hdr for l1clk_in
2115///////////////////////////////////
2116
2117cl_mc1_l1enable_12x l1ch_in_l1en (
2118 .l2clk (l2clk),
2119 .pce (pce),
2120 .pce_ov (tcu_pce_ov),
2121 .l1en (l1clk_in_en)
2122 );
2123
2124cl_mc1_l1driver_12x l1ch_in_l1drvr (
2125 .se (tcu_se_scancollar_in),
2126 .l1en (l1clk_in_en),
2127 .l1clk (l1clk_in),
2128 .l2clk(l2clk)
2129 );
2130
2131///////////////////////////////////
2132// decomposed l1hdr for l1clk_out
2133///////////////////////////////////
2134
2135cl_mc1_l1enable_12x l1ch_out_l1en (
2136 .l2clk (l2clk),
2137 .pce (pce),
2138 .pce_ov (tcu_pce_ov),
2139 .l1en (l1clk_out_en)
2140 );
2141
2142cl_mc1_l1driver_12x l1ch_out_l1drvr (
2143 .se (tcu_se_scancollar_out),
2144 .l1en (l1clk_out_en),
2145 .l1clk (l1clk_out),
2146 .l2clk(l2clk)
2147 );
2148
2149
2150///////////////////////////////////
2151// decomposed l1hdr for l1clk_gate
2152///////////////////////////////////
2153
2154cl_mc1_l1enable_12x l1ch_gate_l1en (
2155 .l2clk (l2clk),
2156 .pce (pce),
2157 .pce_ov (tcu_pce_ov),
2158 .l1en (l1clk_gate_en)
2159 );
2160
2161cl_mc1_l1driver_12x l1ch_gate_l1drvr (
2162 .se (tcu_scan_en),
2163 .l1en (l1clk_gate_en),
2164 .l1clk (l1clk_gate),
2165 .l2clk(l2clk)
2166 );
2167
2168
2169//================================================
2170// l2 clock Domain: Input flops
2171//================================================
2172
2173/****************************************************/
2174wire [5:0] fuse_niu_repair_value;
2175wire fuse_niu_repair_en;
2176wire [`RID_BITS__1-1:0] fuse_niu_rid;
2177wire fuse_niu_wen;
2178wire fuse_red_reset;
2179
2180wire dff_rvalue_m_scanin;
2181wire dff_rvalue_m_scanout;
2182wire dff_rid_m_scanin;
2183wire dff_rid_m_scanout;
2184wire dff_wr_en_m_scanin;
2185wire dff_wr_en_m_scanout;
2186wire dff_red_clr_m_scanin;
2187wire dff_red_clr_m_scanout;
2188
2189wire sr10;
2190wire hdr_wr_en;
2191wire hdr_red_clr;
2192
2193// msff_ctl_macro srhdr_rvalue (width=7) (
2194// .scan_in (dff_rvalue_m_scanin),
2195// .scan_out (dff_rvalue_m_scanout),
2196// .l1clk (l1clk_in),
2197// .din (hdr_sram_rvalue[6:0]),
2198// .dout ({fuse_niu_repair_value[5:0],fuse_niu_repair_en}) );
2199//
2200// msff_ctl_macro srhdr_rid (width=RID_BITS) (
2201// .scan_in (dff_rid_m_scanin),
2202// .scan_out (dff_rid_m_scanout),
2203// .l1clk (l1clk_in),
2204// .din (hdr_sram_rid[RID_BITS-1:0]),
2205// .dout (fuse_niu_rid[RID_BITS-1:0]) );
2206//
2207// msff_ctl_macro srhdr_wr_en (width=1) (
2208// .scan_in (dff_wr_en_m_scanin),
2209// .scan_out (dff_wr_en_m_scanout),
2210// .l1clk (l1clk_in),
2211// .din (hdr_sram_wr_en),
2212// .dout (hdr_wr_en) );
2213//
2214// msff_ctl_macro srhdr_red_clr (width=1) (
2215// .scan_in (dff_red_clr_m_scanin),
2216// .scan_out (dff_red_clr_m_scanout),
2217// .l1clk (l1clk_in),
2218// .din (hdr_sram_red_clr),
2219// .dout (hdr_red_clr) );
2220
2221
2222cl_sc1_msff_4x srhdr_rvalue_reg_0 (.d(hdr_sram_rvalue[0]),.si(hdr_rvalue_reg_scanin[0]),.q(fuse_niu_repair_en),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[0]));
2223cl_sc1_msff_4x srhdr_rvalue_reg_1 (.d(hdr_sram_rvalue[1]),.si(hdr_rvalue_reg_scanin[1]),.q(fuse_niu_repair_value[0]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[1]));
2224cl_sc1_msff_4x srhdr_rvalue_reg_2 (.d(hdr_sram_rvalue[2]),.si(hdr_rvalue_reg_scanin[2]),.q(fuse_niu_repair_value[1]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[2]));
2225cl_sc1_msff_4x srhdr_rvalue_reg_3 (.d(hdr_sram_rvalue[3]),.si(hdr_rvalue_reg_scanin[3]),.q(fuse_niu_repair_value[2]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[3]));
2226cl_sc1_msff_4x srhdr_rvalue_reg_4 (.d(hdr_sram_rvalue[4]),.si(hdr_rvalue_reg_scanin[4]),.q(fuse_niu_repair_value[3]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[4]));
2227cl_sc1_msff_4x srhdr_rvalue_reg_5 (.d(hdr_sram_rvalue[5]),.si(hdr_rvalue_reg_scanin[5]),.q(fuse_niu_repair_value[4]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[5]));
2228cl_sc1_msff_4x srhdr_rvalue_reg_6 (.d(hdr_sram_rvalue[6]),.si(hdr_rvalue_reg_scanin[6]),.q(fuse_niu_repair_value[5]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[6]));
2229
2230cl_sc1_msff_4x hdr_sram_rid_reg_0 (.d(hdr_sram_rid[0]),.si(hdr_sram_rid_reg_scanin[0]),.q(fuse_niu_rid[0]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_rid_reg_scanout[0]));
2231cl_sc1_msff_4x hdr_sram_rid_reg_1 (.d(hdr_sram_rid[1]),.si(hdr_sram_rid_reg_scanin[1]),.q(fuse_niu_rid[1]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_rid_reg_scanout[1]));
2232
2233cl_sc1_msff_4x hdr_sram_wr_en_reg (.d(hdr_sram_wr_en),.si(hdr_sram_wr_en_reg_scanin),.q(hdr_wr_en),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_wr_en_reg_scanout));
2234
2235cl_sc1_msff_4x hdr_sram_red_clr_reg (.d(hdr_sram_red_clr),.si(hdr_sram_red_clr_reg_scanin),.q(hdr_red_clr),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_red_clr_reg_scanout));
2236
2237
2238// assign fuse_niu_wen = hdr_wr_en && !tcu_array_wr_inhibit;
2239// assign fuse_red_reset = hdr_red_clr && !tcu_array_wr_inhibit;
2240
2241 niu256_inv_macro__width_1 r1 (.dout(sr10), .din(tcu_array_wr_inhibit) );
2242 niu256_and_macro__width_1 r2 (.dout(fuse_niu_wen), .din0(hdr_wr_en), .din1(sr10) );
2243 niu256_and_macro__width_1 r3 (.dout(fuse_red_reset), .din0(hdr_red_clr), .din1(sr10) );
2244
2245//================================================
2246// l2 clock Domain: output flops
2247//================================================
2248
2249// ------------ repair_ph.a register ----------------
2250wire [5:0] niu_fuse_repair_value;
2251wire niu_fuse_repair_en;
2252
2253wire dff_read_data_m_scanin;
2254wire dff_read_data_m_scanout;
2255
2256// msff_ctl_macro sram_read_data (width=7) (
2257// .scan_in (dff_read_data_m_scanin),
2258// .scan_out (dff_read_data_m_scanout),
2259// .l1clk (l1clk_out),
2260// .din ({niu_fuse_repair_value[5:0],niu_fuse_repair_en}),
2261// .dout (sram_hdr_read_data[6:0]) );
2262
2263cl_sc1_msff_4x sram_read_data_reg_0 (.d(niu_fuse_repair_en),.si(sram_read_data_reg_scanin[0]),.q(sram_hdr_read_data[0]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[0]));
2264cl_sc1_msff_4x sram_read_data_reg_1 (.d(niu_fuse_repair_value[0]),.si(sram_read_data_reg_scanin[1]),.q(sram_hdr_read_data[1]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[1]));
2265cl_sc1_msff_4x sram_read_data_reg_2 (.d(niu_fuse_repair_value[1]),.si(sram_read_data_reg_scanin[2]),.q(sram_hdr_read_data[2]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[2]));
2266cl_sc1_msff_4x sram_read_data_reg_3 (.d(niu_fuse_repair_value[2]),.si(sram_read_data_reg_scanin[3]),.q(sram_hdr_read_data[3]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[3]));
2267cl_sc1_msff_4x sram_read_data_reg_4 (.d(niu_fuse_repair_value[3]),.si(sram_read_data_reg_scanin[4]),.q(sram_hdr_read_data[4]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[4]));
2268cl_sc1_msff_4x sram_read_data_reg_5 (.d(niu_fuse_repair_value[4]),.si(sram_read_data_reg_scanin[5]),.q(sram_hdr_read_data[5]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[5]));
2269cl_sc1_msff_4x sram_read_data_reg_6 (.d(niu_fuse_repair_value[5]),.si(sram_read_data_reg_scanin[6]),.q(sram_hdr_read_data[6]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[6]));
2270
2271
2272//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2273//////////////////////////////
2274// Redundancy Register //
2275//////////////////////////////
2276 assign red_id[0] = !fuse_niu_rid[1] && !fuse_niu_rid[0];
2277 assign red_id[1] = !fuse_niu_rid[1] && fuse_niu_rid[0];
2278 assign red_id[2] = fuse_niu_rid[1] && !fuse_niu_rid[0];
2279 assign red_id[3] = fuse_niu_rid[1] && fuse_niu_rid[0];
2280
2281 assign red_reg_clk_p[0] = (!l1clk_gate && (red_id[0] && fuse_niu_wen || fuse_red_reset));
2282 assign red_reg_clk_p[1] = (!l1clk_gate && (red_id[1] && fuse_niu_wen || fuse_red_reset));
2283 assign red_reg_clk_p[2] = (!l1clk_gate && (red_id[2] && fuse_niu_wen || fuse_red_reset));
2284 assign red_reg_clk_p[3] = (!l1clk_gate && (red_id[3] && fuse_niu_wen || fuse_red_reset));
2285
2286 assign fuse_red_data = fuse_niu_repair_value & {6{!fuse_red_reset}};
2287 assign fuse_red_enable = fuse_niu_repair_en && !fuse_red_reset;
2288
2289//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2290 n2_niu_dp_256x152s_redreg redreg_0 (
2291 .fuse_red_data (fuse_red_data),
2292 .fuse_red_enable (fuse_red_enable),
2293 .red_reg_clk_p (red_reg_clk_p[0]),
2294 .red_data_reg (red_data_reg_b0),
2295 .red_en_reg (red_en_reg_bk[0]),
2296 .red_value (red_value_b0),
2297 .repair_en (repair_en_bk[0])
2298 );
2299
2300 n2_niu_dp_256x152s_redreg redreg_1 (
2301 .fuse_red_data (fuse_red_data),
2302 .fuse_red_enable (fuse_red_enable),
2303 .red_reg_clk_p (red_reg_clk_p[1]),
2304 .red_data_reg (red_data_reg_b1),
2305 .red_en_reg (red_en_reg_bk[1]),
2306 .red_value (red_value_b1),
2307 .repair_en (repair_en_bk[1])
2308 );
2309
2310 n2_niu_dp_256x152s_redreg redreg_2 (
2311 .fuse_red_data (fuse_red_data),
2312 .fuse_red_enable (fuse_red_enable),
2313 .red_reg_clk_p (red_reg_clk_p[2]),
2314 .red_data_reg (red_data_reg_b2),
2315 .red_en_reg (red_en_reg_bk[2]),
2316 .red_value (red_value_b2),
2317 .repair_en (repair_en_bk[2])
2318 );
2319
2320 n2_niu_dp_256x152s_redreg redreg_3 (
2321 .fuse_red_data (fuse_red_data),
2322 .fuse_red_enable (fuse_red_enable),
2323 .red_reg_clk_p (red_reg_clk_p[3]),
2324 .red_data_reg (red_data_reg_b3),
2325 .red_en_reg (red_en_reg_bk[3]),
2326 .red_value (red_value_b3),
2327 .repair_en (repair_en_bk[3])
2328 );
2329
2330//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2331wire [5:0] niu_fuse_repair_value_b0;
2332wire [5:0] niu_fuse_repair_value_b1;
2333wire [5:0] niu_fuse_repair_value_b2;
2334wire [5:0] niu_fuse_repair_value_b3;
2335wire [5:0] or_val_b0;
2336wire [5:0] or_val_b1;
2337
2338 // assign niu_fuse_repair_value = (red_data_reg_b0 & {6{red_id[0]}}) |
2339 // (red_data_reg_b1 & {6{red_id[1]}}) |
2340 // (red_data_reg_b2 & {6{red_id[2]}}) |
2341 // (red_data_reg_b3 & {6{red_id[3]}});
2342
2343 niu256_and_macro__width_6 ava0 (.dout(niu_fuse_repair_value_b0), .din0(red_data_reg_b0), .din1({6{red_id[0]}}));
2344 niu256_and_macro__width_6 ava1 (.dout(niu_fuse_repair_value_b1), .din0(red_data_reg_b1), .din1({6{red_id[1]}}));
2345 niu256_and_macro__width_6 ava2 (.dout(niu_fuse_repair_value_b2), .din0(red_data_reg_b2), .din1({6{red_id[2]}}));
2346 niu256_and_macro__width_6 ava3 (.dout(niu_fuse_repair_value_b3), .din0(red_data_reg_b3), .din1({6{red_id[3]}}));
2347
2348 niu256_or_macro__width_6 ova0 (.dout(or_val_b0), .din0(niu_fuse_repair_value_b0), .din1(niu_fuse_repair_value_b1));
2349 niu256_or_macro__width_6 ova1 (.dout(or_val_b1), .din0(or_val_b0), .din1(niu_fuse_repair_value_b2));
2350 niu256_or_macro__width_6 ova2 (.dout(niu_fuse_repair_value), .din0(or_val_b1), .din1(niu_fuse_repair_value_b3));
2351
2352wire [3:0] niu_fuse_repair_en_bk;
2353wire [1:0] or_ena;
2354
2355 // assign niu_fuse_repair_en = (red_en_reg_bk[0] && red_id[0]) ||
2356 // (red_en_reg_bk[1] && red_id[1]) ||
2357 // (red_en_reg_bk[2] && red_id[2]) ||
2358 // (red_en_reg_bk[3] && red_id[3]);
2359
2360 niu256_and_macro__width_4 aen0 (.dout(niu_fuse_repair_en_bk), .din0(red_en_reg_bk[3:0]), .din1(red_id[3:0]) );
2361
2362 niu256_or_macro__width_1 oen0 (.dout(or_ena[0]), .din0(niu_fuse_repair_en_bk[0]),.din1(niu_fuse_repair_en_bk[1]));
2363 niu256_or_macro__width_1 oen1 (.dout(or_ena[1]), .din0(or_ena[0]), .din1(niu_fuse_repair_en_bk[2]));
2364 niu256_or_macro__width_1 oen2 (.dout(niu_fuse_repair_en),.din0(or_ena[1]), .din1(niu_fuse_repair_en_bk[3]));
2365
2366//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2367
2368// from Candong's 7/21/05 email
2369//
2370//(1) scan_in ==> dff_red_clr
2371//(2) dff_red_clr ==> drr_wr_en;
2372//(3) ==> rid<1>
2373//(4) ==> rid<0>
2374//(5) ==> rvalue<6> ,...rvalue<0> (from MSB to LSB)
2375//(6) ==> repair_value<0>, ... repair_value<6>, (output red values, from LSB to MSB)
2376//(7) scan_out ==> repair_vaule<6>
2377
2378
2379// fixscan start:
2380assign hdr_sram_red_clr_reg_scanin = scan_in ;
2381assign hdr_sram_wr_en_reg_scanin = hdr_sram_red_clr_reg_scanout;
2382assign hdr_sram_rid_reg_scanin[1] = hdr_sram_wr_en_reg_scanout;
2383assign hdr_sram_rid_reg_scanin[0] = hdr_sram_rid_reg_scanout[1];
2384assign hdr_rvalue_reg_scanin[6] = hdr_sram_rid_reg_scanout[0];
2385assign hdr_rvalue_reg_scanin[5] = hdr_rvalue_reg_scanout[6];
2386assign hdr_rvalue_reg_scanin[4] = hdr_rvalue_reg_scanout[5];
2387assign hdr_rvalue_reg_scanin[3] = hdr_rvalue_reg_scanout[4];
2388assign hdr_rvalue_reg_scanin[2] = hdr_rvalue_reg_scanout[3];
2389assign hdr_rvalue_reg_scanin[1] = hdr_rvalue_reg_scanout[2];
2390assign hdr_rvalue_reg_scanin[0] = hdr_rvalue_reg_scanout[1];
2391
2392assign sram_read_data_reg_scanin[6]= hdr_rvalue_reg_scanout[0];
2393assign sram_read_data_reg_scanin[5]= sram_read_data_reg_scanout[6];
2394assign sram_read_data_reg_scanin[4]= sram_read_data_reg_scanout[5];
2395assign sram_read_data_reg_scanin[3]= sram_read_data_reg_scanout[4];
2396assign sram_read_data_reg_scanin[2]= sram_read_data_reg_scanout[3];
2397assign sram_read_data_reg_scanin[1]= sram_read_data_reg_scanout[2];
2398assign sram_read_data_reg_scanin[0]= sram_read_data_reg_scanout[1];
2399assign scan_out = sram_read_data_reg_scanout[0];
2400
2401// fixscan end:
2402
2403endmodule
2404
2405
2406
2407
2408module n2_niu_dp_256x152s_redreg (
2409 fuse_red_data,
2410 fuse_red_enable,
2411 red_reg_clk_p,
2412 red_data_reg,
2413 red_en_reg,
2414 red_value,
2415 repair_en);
2416
2417input [5:0] fuse_red_data;
2418input fuse_red_enable;
2419input red_reg_clk_p;
2420
2421output [5:0] red_data_reg; // to repair output
2422output red_en_reg;
2423output [5:0] red_value; // to subbank
2424output repair_en;
2425
2426wire [5:0] red_value;
2427wire repair_en;
2428
2429wire [5:0] red_data_reg;
2430wire red_en_reg;
2431
2432wire red_en_reg1;
2433
2434
2435
2436//////////////////////////////
2437// Redundancy Register //
2438//////////////////////////////
2439
2440// `ifdef NOINITMEM
2441// `else
2442// // Initialize the arrays.
2443// initial begin
2444// red_data_reg = {6{1'h0}};
2445// red_en_reg = 1'h0;
2446// end
2447// `endif
2448
2449// always @(posedge red_reg_clk_p) begin
2450// red_data_reg <= fuse_red_data;
2451// red_en_reg <= fuse_red_enable;
2452// end
2453
2454cl_sc1_msff_4x e_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg));
2455cl_sc1_msff_4x e_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg1));
2456
2457cl_sc1_msff_4x d_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[0]),.q(red_data_reg[0]));
2458cl_sc1_msff_4x d_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[1]),.q(red_data_reg[1]));
2459cl_sc1_msff_4x d_r2 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[2]),.q(red_data_reg[2]));
2460cl_sc1_msff_4x d_r3 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[3]),.q(red_data_reg[3]));
2461cl_sc1_msff_4x d_r4 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[4]),.q(red_data_reg[4]));
2462cl_sc1_msff_4x d_r5 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[5]),.q(red_data_reg[5]));
2463
2464// assign repair_en = red_en_reg;
2465
2466 niu256_and_macro__width_1 a0 (.dout(repair_en), .din0(red_en_reg), .din1(red_en_reg1));
2467
2468 assign red_value = red_data_reg[5:0];
2469
2470endmodule
2471
2472
2473
2474//
2475// and macro for ports = 2,3,4
2476//
2477//
2478
2479
2480
2481
2482
2483module niu256_and_macro__width_6 (
2484 din0,
2485 din1,
2486 dout);
2487wire [5:0] nandout;
2488
2489 input [5:0] din0;
2490 input [5:0] din1;
2491 output [5:0] dout;
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501cl_u1_nand2_1x d0_0 (
2502.in0(din0[0]),
2503.in1(din1[0]),
2504.out(nandout[0])
2505);
2506
2507cl_u1_nand2_1x d0_1 (
2508.in0(din0[1]),
2509.in1(din1[1]),
2510.out(nandout[1])
2511);
2512
2513cl_u1_nand2_1x d0_2 (
2514.in0(din0[2]),
2515.in1(din1[2]),
2516.out(nandout[2])
2517);
2518
2519cl_u1_nand2_1x d0_3 (
2520.in0(din0[3]),
2521.in1(din1[3]),
2522.out(nandout[3])
2523);
2524
2525cl_u1_nand2_1x d0_4 (
2526.in0(din0[4]),
2527.in1(din1[4]),
2528.out(nandout[4])
2529);
2530
2531cl_u1_nand2_1x d0_5 (
2532.in0(din0[5]),
2533.in1(din1[5]),
2534.out(nandout[5])
2535);
2536
2537cl_u1_inv_1x d1_0 (
2538.in(nandout[0]),
2539.out(dout[0])
2540);
2541cl_u1_inv_1x d1_1 (
2542.in(nandout[1]),
2543.out(dout[1])
2544);
2545cl_u1_inv_1x d1_2 (
2546.in(nandout[2]),
2547.out(dout[2])
2548);
2549cl_u1_inv_1x d1_3 (
2550.in(nandout[3]),
2551.out(dout[3])
2552);
2553cl_u1_inv_1x d1_4 (
2554.in(nandout[4]),
2555.out(dout[4])
2556);
2557cl_u1_inv_1x d1_5 (
2558.in(nandout[5]),
2559.out(dout[5])
2560);
2561
2562
2563
2564
2565endmodule
2566
2567
2568
2569
2570
2571//
2572// or macro for ports = 2,3
2573//
2574//
2575
2576
2577
2578
2579
2580module niu256_or_macro__width_6 (
2581 din0,
2582 din1,
2583 dout);
2584wire [5:0] norout;
2585
2586 input [5:0] din0;
2587 input [5:0] din1;
2588 output [5:0] dout;
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598cl_u1_nor2_1x d0_0 (
2599.in0(din0[0]),
2600.in1(din1[0]),
2601.out(norout[0])
2602);
2603
2604cl_u1_nor2_1x d0_1 (
2605.in0(din0[1]),
2606.in1(din1[1]),
2607.out(norout[1])
2608);
2609
2610cl_u1_nor2_1x d0_2 (
2611.in0(din0[2]),
2612.in1(din1[2]),
2613.out(norout[2])
2614);
2615
2616cl_u1_nor2_1x d0_3 (
2617.in0(din0[3]),
2618.in1(din1[3]),
2619.out(norout[3])
2620);
2621
2622cl_u1_nor2_1x d0_4 (
2623.in0(din0[4]),
2624.in1(din1[4]),
2625.out(norout[4])
2626);
2627
2628cl_u1_nor2_1x d0_5 (
2629.in0(din0[5]),
2630.in1(din1[5]),
2631.out(norout[5])
2632);
2633
2634cl_u1_inv_1x d1_0 (
2635.in(norout[0]),
2636.out(dout[0])
2637);
2638cl_u1_inv_1x d1_1 (
2639.in(norout[1]),
2640.out(dout[1])
2641);
2642cl_u1_inv_1x d1_2 (
2643.in(norout[2]),
2644.out(dout[2])
2645);
2646cl_u1_inv_1x d1_3 (
2647.in(norout[3]),
2648.out(dout[3])
2649);
2650cl_u1_inv_1x d1_4 (
2651.in(norout[4]),
2652.out(dout[4])
2653);
2654cl_u1_inv_1x d1_5 (
2655.in(norout[5]),
2656.out(dout[5])
2657);
2658
2659
2660
2661
2662endmodule
2663
2664
2665
2666
2667
2668//
2669// and macro for ports = 2,3,4
2670//
2671//
2672
2673
2674
2675
2676
2677module niu256_and_macro__width_4 (
2678 din0,
2679 din1,
2680 dout);
2681wire [3:0] nandout;
2682
2683 input [3:0] din0;
2684 input [3:0] din1;
2685 output [3:0] dout;
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695cl_u1_nand2_1x d0_0 (
2696.in0(din0[0]),
2697.in1(din1[0]),
2698.out(nandout[0])
2699);
2700
2701cl_u1_nand2_1x d0_1 (
2702.in0(din0[1]),
2703.in1(din1[1]),
2704.out(nandout[1])
2705);
2706
2707cl_u1_nand2_1x d0_2 (
2708.in0(din0[2]),
2709.in1(din1[2]),
2710.out(nandout[2])
2711);
2712
2713cl_u1_nand2_1x d0_3 (
2714.in0(din0[3]),
2715.in1(din1[3]),
2716.out(nandout[3])
2717);
2718
2719cl_u1_inv_1x d1_0 (
2720.in(nandout[0]),
2721.out(dout[0])
2722);
2723cl_u1_inv_1x d1_1 (
2724.in(nandout[1]),
2725.out(dout[1])
2726);
2727cl_u1_inv_1x d1_2 (
2728.in(nandout[2]),
2729.out(dout[2])
2730);
2731cl_u1_inv_1x d1_3 (
2732.in(nandout[3]),
2733.out(dout[3])
2734);
2735
2736
2737
2738
2739endmodule
2740
2741
2742
2743
2744
2745//
2746// or macro for ports = 2,3
2747//
2748//
2749
2750
2751
2752
2753
2754module niu256_or_macro__width_1 (
2755 din0,
2756 din1,
2757 dout);
2758wire [0:0] norout;
2759
2760 input [0:0] din0;
2761 input [0:0] din1;
2762 output [0:0] dout;
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772cl_u1_nor2_1x d0_0 (
2773.in0(din0[0]),
2774.in1(din1[0]),
2775.out(norout[0])
2776);
2777
2778cl_u1_inv_1x d1_0 (
2779.in(norout[0]),
2780.out(dout[0])
2781);
2782
2783
2784
2785
2786endmodule
2787
2788
2789
2790
Full OpenSPARC design & verification tarball including full HDL.