Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_iom_sp_devtsb_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_iom_sp_devtsb_cust ( | |
36 | // clocks, scan | |
37 | clk, | |
38 | scan_in, | |
39 | tcu_se_scancollar_in, | |
40 | tcu_scan_en, | |
41 | tcu_pce_ov, | |
42 | pce, | |
43 | tcu_aclk, | |
44 | tcu_bclk, | |
45 | tcu_array_wr_inhibit, | |
46 | scan_out, | |
47 | ||
48 | // efu inputs | |
49 | efu_bits, | |
50 | ||
51 | // ram control | |
52 | dev_rd, | |
53 | adr_r, | |
54 | tsb_rd, | |
55 | lkup_en, | |
56 | adr_bs, | |
57 | dev_wr, | |
58 | adr_w, | |
59 | tsb_wr, | |
60 | din, | |
61 | dout, | |
62 | tsb_adr_r | |
63 | ||
64 | ); | |
65 | ||
66 | ||
67 | // clocks, scan | |
68 | input clk; // io clock | |
69 | input scan_in; // | |
70 | input tcu_se_scancollar_in; // | |
71 | input tcu_scan_en; // | |
72 | input tcu_pce_ov; // scan signals | |
73 | input pce; // | |
74 | input tcu_aclk; // | |
75 | input tcu_bclk; // | |
76 | input tcu_array_wr_inhibit; // | |
77 | output scan_out; // | |
78 | input [3:0] efu_bits; // efu inputs to adjust access time | |
79 | ||
80 | ||
81 | input dev_rd; // Read enable for DEV RAM read port | |
82 | input [4:0] adr_r; // Address for read port | |
83 | input tsb_rd; // Read enable for TSB RAM read port | |
84 | input lkup_en; // Lookup process enable | |
85 | input [2:0] adr_bs; | |
86 | input dev_wr; // Write enable for DEV RAM write port | |
87 | input [4:0] adr_w; // Address for write port | |
88 | input tsb_wr; // Write enable for TSB RAM write port | |
89 | input [63:0] din; | |
90 | output [63:0] dout; | |
91 | output [4:0] tsb_adr_r; | |
92 | ||
93 | ||
94 | //------------------------------------------------------------------------ | |
95 | // checker for read/write exclusivity | |
96 | //------------------------------------------------------------------------ | |
97 | wire [1:0] dev_rw,tsb_rw; | |
98 | assign dev_rw[1:0] = {dev_rd,dev_wr}; | |
99 | assign tsb_rw[1:0] = {tsb_rd,tsb_wr}; | |
100 | // 0in bits_on -var dev_rw -max 1 | |
101 | // 0in bits_on -var tsb_rw -max 1 | |
102 | //------------------------------------------------------------------------ | |
103 | // scan chain connections | |
104 | //------------------------------------------------------------------------ | |
105 | // scan renames | |
106 | wire [1:0] siclk,soclk; | |
107 | wire se,wr_inhibit,and_clk; | |
108 | assign wr_inhibit = tcu_array_wr_inhibit; | |
109 | // end scan | |
110 | //------------------------------------------------------------------------ | |
111 | // instantiate clock headers | |
112 | //------------------------------------------------------------------------ | |
113 | wire [1:0] collar_clk; | |
114 | wire pce_ov = tcu_pce_ov; | |
115 | wire stop = 1'b0; | |
116 | wire aclk = tcu_aclk; | |
117 | wire bclk = tcu_bclk; | |
118 | assign se = tcu_se_scancollar_in; // TEMP | |
119 | ||
120 | cl_dp1_l1hdr_8x clk_hdr_cntl ( | |
121 | .l2clk(clk), | |
122 | .pce (pce), | |
123 | .l1clk(collar_clk[0]), | |
124 | .siclk_out(siclk[0]), | |
125 | .soclk_out(soclk[0]), | |
126 | .se(se), | |
127 | .pce_ov(pce_ov), | |
128 | .stop(stop), | |
129 | .aclk(aclk), | |
130 | .bclk(bclk) | |
131 | ); | |
132 | ||
133 | cl_dp1_l1hdr_8x clk_hdr_data1 ( | |
134 | .l2clk(clk), | |
135 | .pce (pce), | |
136 | .l1clk(collar_clk[1]), | |
137 | .siclk_out(siclk[1]), | |
138 | .soclk_out(soclk[1]), | |
139 | .se(se), | |
140 | .pce_ov(pce_ov), | |
141 | .stop(stop), | |
142 | .aclk(aclk), | |
143 | .bclk(bclk) | |
144 | ); | |
145 | ||
146 | cl_dp1_l1hdr_8x scan_en_hdr ( | |
147 | .l2clk(clk), | |
148 | .pce (pce), | |
149 | .l1clk(and_clk), | |
150 | .siclk_out(), | |
151 | .soclk_out(), | |
152 | .se(tcu_scan_en), | |
153 | .pce_ov(pce_ov), | |
154 | .stop(stop), | |
155 | .aclk(aclk), | |
156 | .bclk(bclk) | |
157 | ); | |
158 | ||
159 | ||
160 | ||
161 | //------------------------------------------------------------------------ | |
162 | // input flops | |
163 | //------------------------------------------------------------------------ | |
164 | wire [4:0] r_adr_r,rd_addr_so; | |
165 | wire [4:0] r_adr_w,wr_addr_so; | |
166 | wire [2:0] adr_bs_so; | |
167 | wire [2:0] dev_dout_sel; | |
168 | wire r_lkup_en; | |
169 | wire lkup_en_so; | |
170 | wire r_dev_rd,r_dev_wr; | |
171 | wire r_tsb_rd,r_tsb_wr; | |
172 | wire dev_rd_so,dev_wr_so; | |
173 | wire tsb_rd_so,tsb_wr_so; | |
174 | wire [63:0] r_din; | |
175 | wire [63:0] din_so; | |
176 | //reg [63:0] dout; | |
177 | wire [63:0] dout; | |
178 | ||
179 | wire [4:0] rd_addr_si; | |
180 | wire [4:0] wr_addr_si; | |
181 | wire [2:0] adr_bs_si; | |
182 | wire dev_rd_si; | |
183 | wire tsb_rd_si; | |
184 | wire dev_wr_si; | |
185 | wire tsb_wr_si; | |
186 | wire lkup_en_si; | |
187 | wire [63:0] din_si; | |
188 | ||
189 | ||
190 | cl_mc1_sram_msff_mo_8x rd_addr_so_4 ( .si(rd_addr_si[4]), .so(rd_addr_so[4]), .l1clk(collar_clk[0]), | |
191 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_r[4]), .mq(r_adr_r[4]), .and_clk(and_clk) ); | |
192 | cl_mc1_sram_msff_mo_8x rd_addr_so_3 ( .si(rd_addr_si[3]), .so(rd_addr_so[3]), .l1clk(collar_clk[0]), | |
193 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_r[3]), .mq(r_adr_r[3]), .and_clk(and_clk) ); | |
194 | cl_mc1_sram_msff_mo_8x rd_addr_so_2 ( .si(rd_addr_si[2]), .so(rd_addr_so[2]), .l1clk(collar_clk[0]), | |
195 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_r[2]), .mq(r_adr_r[2]), .and_clk(and_clk) ); | |
196 | cl_mc1_sram_msff_mo_8x rd_addr_so_1 ( .si(rd_addr_si[1]), .so(rd_addr_so[1]), .l1clk(collar_clk[0]), | |
197 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_r[1]), .mq(r_adr_r[1]), .and_clk(and_clk) ); | |
198 | cl_mc1_sram_msff_mo_8x rd_addr_so_0 ( .si(rd_addr_si[0]), .so(rd_addr_so[0]), .l1clk(collar_clk[0]), | |
199 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_r[0]), .mq(r_adr_r[0]), .and_clk(and_clk) ); | |
200 | ||
201 | cl_mc1_sram_msff_mo_8x wr_addr_so_4 ( .si(wr_addr_si[4]), .so(wr_addr_so[4]), .l1clk(collar_clk[0]), | |
202 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_w[4]), .mq(r_adr_w[4]), .and_clk(and_clk) ); | |
203 | cl_mc1_sram_msff_mo_8x wr_addr_so_3 ( .si(wr_addr_si[3]), .so(wr_addr_so[3]), .l1clk(collar_clk[0]), | |
204 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_w[3]), .mq(r_adr_w[3]), .and_clk(and_clk) ); | |
205 | cl_mc1_sram_msff_mo_8x wr_addr_so_2 ( .si(wr_addr_si[2]), .so(wr_addr_so[2]), .l1clk(collar_clk[0]), | |
206 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_w[2]), .mq(r_adr_w[2]), .and_clk(and_clk) ); | |
207 | cl_mc1_sram_msff_mo_8x wr_addr_so_1 ( .si(wr_addr_si[1]), .so(wr_addr_so[1]), .l1clk(collar_clk[0]), | |
208 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_w[1]), .mq(r_adr_w[1]), .and_clk(and_clk) ); | |
209 | cl_mc1_sram_msff_mo_8x wr_addr_so_0 ( .si(wr_addr_si[0]), .so(wr_addr_so[0]), .l1clk(collar_clk[0]), | |
210 | .siclk(siclk[0]), .soclk(soclk[0]), .d(adr_w[0]), .mq(r_adr_w[0]), .and_clk(and_clk) ); | |
211 | ||
212 | cl_mc1_sram_msff_mo_8x adr_bs_so_2 ( .si(adr_bs_si[2]), .so(adr_bs_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), | |
213 | .soclk(soclk[0]), .d(adr_bs[2]), .mq(dev_dout_sel[2]), .and_clk(and_clk) ); | |
214 | cl_mc1_sram_msff_mo_8x adr_bs_so_1 ( .si(adr_bs_si[1]), .so(adr_bs_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), | |
215 | .soclk(soclk[0]), .d(adr_bs[1]), .mq(dev_dout_sel[1]), .and_clk(and_clk) ); | |
216 | cl_mc1_sram_msff_mo_8x adr_bs_so_0 ( .si(adr_bs_si[0]), .so(adr_bs_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), | |
217 | .soclk(soclk[0]), .d(adr_bs[0]), .mq(dev_dout_sel[0]), .and_clk(and_clk) ); | |
218 | ||
219 | cl_mc1_sram_msff_mo_8x dev_rd_so_ff ( .si(dev_rd_si), .so(dev_rd_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), | |
220 | .d(dev_rd), .mq(r_dev_rd), .and_clk(and_clk) ); | |
221 | ||
222 | cl_mc1_sram_msff_mo_8x tsb_rd_so_ff ( .si(tsb_rd_si), .so(tsb_rd_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), | |
223 | .d(tsb_rd), .mq(r_tsb_rd), .and_clk(and_clk) ); | |
224 | ||
225 | cl_mc1_sram_msff_mo_8x dev_wr_so_ff ( .si(dev_wr_si), .so(dev_wr_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), | |
226 | .d(dev_wr), .mq(r_dev_wr), .and_clk(and_clk) ); | |
227 | ||
228 | cl_mc1_sram_msff_mo_8x tsb_wr_so_ff ( .si(tsb_wr_si), .so(tsb_wr_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), | |
229 | .d(tsb_wr), .mq(r_tsb_wr), .and_clk(and_clk) ); | |
230 | ||
231 | cl_mc1_sram_msff_mo_8x lkup_en_ff ( .si(lkup_en_si), .so(lkup_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]), | |
232 | .d(lkup_en), .mq(r_lkup_en), .and_clk(and_clk) ); | |
233 | ||
234 | ||
235 | cl_sc1_msff_8x din_63 ( .si(din_si[63]), .so(din_so[63]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[63]), .q(r_din[63]) ); | |
236 | cl_sc1_msff_8x din_62 ( .si(din_si[62]), .so(din_so[62]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[62]), .q(r_din[62]) ); | |
237 | cl_sc1_msff_8x din_61 ( .si(din_si[61]), .so(din_so[61]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[61]), .q(r_din[61]) ); | |
238 | cl_sc1_msff_8x din_60 ( .si(din_si[60]), .so(din_so[60]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[60]), .q(r_din[60]) ); | |
239 | ||
240 | cl_sc1_msff_8x din_59 ( .si(din_si[59]), .so(din_so[59]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[59]), .q(r_din[59]) ); | |
241 | cl_sc1_msff_8x din_58 ( .si(din_si[58]), .so(din_so[58]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[58]), .q(r_din[58]) ); | |
242 | cl_sc1_msff_8x din_57 ( .si(din_si[57]), .so(din_so[57]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[57]), .q(r_din[57]) ); | |
243 | cl_sc1_msff_8x din_56 ( .si(din_si[56]), .so(din_so[56]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[56]), .q(r_din[56]) ); | |
244 | cl_sc1_msff_8x din_55 ( .si(din_si[55]), .so(din_so[55]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[55]), .q(r_din[55]) ); | |
245 | cl_sc1_msff_8x din_54 ( .si(din_si[54]), .so(din_so[54]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[54]), .q(r_din[54]) ); | |
246 | cl_sc1_msff_8x din_53 ( .si(din_si[53]), .so(din_so[53]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[53]), .q(r_din[53]) ); | |
247 | cl_sc1_msff_8x din_52 ( .si(din_si[52]), .so(din_so[52]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[52]), .q(r_din[52]) ); | |
248 | cl_sc1_msff_8x din_51 ( .si(din_si[51]), .so(din_so[51]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[51]), .q(r_din[51]) ); | |
249 | cl_sc1_msff_8x din_50 ( .si(din_si[50]), .so(din_so[50]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[50]), .q(r_din[50]) ); | |
250 | ||
251 | cl_sc1_msff_8x din_49 ( .si(din_si[49]), .so(din_so[49]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[49]), .q(r_din[49]) ); | |
252 | cl_sc1_msff_8x din_48 ( .si(din_si[48]), .so(din_so[48]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[48]), .q(r_din[48]) ); | |
253 | cl_sc1_msff_8x din_47 ( .si(din_si[47]), .so(din_so[47]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[47]), .q(r_din[47]) ); | |
254 | cl_sc1_msff_8x din_46 ( .si(din_si[46]), .so(din_so[46]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[46]), .q(r_din[46]) ); | |
255 | cl_sc1_msff_8x din_45 ( .si(din_si[45]), .so(din_so[45]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[45]), .q(r_din[45]) ); | |
256 | cl_sc1_msff_8x din_44 ( .si(din_si[44]), .so(din_so[44]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[44]), .q(r_din[44]) ); | |
257 | cl_sc1_msff_8x din_43 ( .si(din_si[43]), .so(din_so[43]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[43]), .q(r_din[43]) ); | |
258 | cl_sc1_msff_8x din_42 ( .si(din_si[42]), .so(din_so[42]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[42]), .q(r_din[42]) ); | |
259 | cl_sc1_msff_8x din_41 ( .si(din_si[41]), .so(din_so[41]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[41]), .q(r_din[41]) ); | |
260 | cl_sc1_msff_8x din_40 ( .si(din_si[40]), .so(din_so[40]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[40]), .q(r_din[40]) ); | |
261 | ||
262 | cl_sc1_msff_8x din_39 ( .si(din_si[39]), .so(din_so[39]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[39]), .q(r_din[39]) ); | |
263 | cl_sc1_msff_8x din_38 ( .si(din_si[38]), .so(din_so[38]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[38]), .q(r_din[38]) ); | |
264 | cl_sc1_msff_8x din_37 ( .si(din_si[37]), .so(din_so[37]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[37]), .q(r_din[37]) ); | |
265 | cl_sc1_msff_8x din_36 ( .si(din_si[36]), .so(din_so[36]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[36]), .q(r_din[36]) ); | |
266 | cl_sc1_msff_8x din_35 ( .si(din_si[35]), .so(din_so[35]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[35]), .q(r_din[35]) ); | |
267 | cl_sc1_msff_8x din_34 ( .si(din_si[34]), .so(din_so[34]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[34]), .q(r_din[34]) ); | |
268 | cl_sc1_msff_8x din_33 ( .si(din_si[33]), .so(din_so[33]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[33]), .q(r_din[33]) ); | |
269 | cl_sc1_msff_8x din_32 ( .si(din_si[32]), .so(din_so[32]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[32]), .q(r_din[32]) ); | |
270 | cl_sc1_msff_8x din_31 ( .si(din_si[31]), .so(din_so[31]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[31]), .q(r_din[31]) ); | |
271 | cl_sc1_msff_8x din_30 ( .si(din_si[30]), .so(din_so[30]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[30]), .q(r_din[30]) ); | |
272 | ||
273 | cl_sc1_msff_8x din_29 ( .si(din_si[29]), .so(din_so[29]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[29]), .q(r_din[29]) ); | |
274 | cl_sc1_msff_8x din_28 ( .si(din_si[28]), .so(din_so[28]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[28]), .q(r_din[28]) ); | |
275 | cl_sc1_msff_8x din_27 ( .si(din_si[27]), .so(din_so[27]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[27]), .q(r_din[27]) ); | |
276 | cl_sc1_msff_8x din_26 ( .si(din_si[26]), .so(din_so[26]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[26]), .q(r_din[26]) ); | |
277 | cl_sc1_msff_8x din_25 ( .si(din_si[25]), .so(din_so[25]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[25]), .q(r_din[25]) ); | |
278 | cl_sc1_msff_8x din_24 ( .si(din_si[24]), .so(din_so[24]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[24]), .q(r_din[24]) ); | |
279 | cl_sc1_msff_8x din_23 ( .si(din_si[23]), .so(din_so[23]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[23]), .q(r_din[23]) ); | |
280 | cl_sc1_msff_8x din_22 ( .si(din_si[22]), .so(din_so[22]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[22]), .q(r_din[22]) ); | |
281 | cl_sc1_msff_8x din_21 ( .si(din_si[21]), .so(din_so[21]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[21]), .q(r_din[21]) ); | |
282 | cl_sc1_msff_8x din_20 ( .si(din_si[20]), .so(din_so[20]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[20]), .q(r_din[20]) ); | |
283 | ||
284 | cl_sc1_msff_8x din_19 ( .si(din_si[19]), .so(din_so[19]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[19]), .q(r_din[19]) ); | |
285 | cl_sc1_msff_8x din_18 ( .si(din_si[18]), .so(din_so[18]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[18]), .q(r_din[18]) ); | |
286 | cl_sc1_msff_8x din_17 ( .si(din_si[17]), .so(din_so[17]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[17]), .q(r_din[17]) ); | |
287 | cl_sc1_msff_8x din_16 ( .si(din_si[16]), .so(din_so[16]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[16]), .q(r_din[16]) ); | |
288 | cl_sc1_msff_8x din_15 ( .si(din_si[15]), .so(din_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[15]), .q(r_din[15]) ); | |
289 | cl_sc1_msff_8x din_14 ( .si(din_si[14]), .so(din_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[14]), .q(r_din[14]) ); | |
290 | cl_sc1_msff_8x din_13 ( .si(din_si[13]), .so(din_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[13]), .q(r_din[13]) ); | |
291 | cl_sc1_msff_8x din_12 ( .si(din_si[12]), .so(din_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[12]), .q(r_din[12]) ); | |
292 | cl_sc1_msff_8x din_11 ( .si(din_si[11]), .so(din_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[11]), .q(r_din[11]) ); | |
293 | cl_sc1_msff_8x din_10 ( .si(din_si[10]), .so(din_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[10]), .q(r_din[10]) ); | |
294 | ||
295 | cl_sc1_msff_8x din_9 ( .si(din_si[9]), .so(din_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[9]), .q(r_din[9]) ); | |
296 | cl_sc1_msff_8x din_8 ( .si(din_si[8]), .so(din_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[8]), .q(r_din[8]) ); | |
297 | cl_sc1_msff_8x din_7 ( .si(din_si[7]), .so(din_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[7]), .q(r_din[7]) ); | |
298 | cl_sc1_msff_8x din_6 ( .si(din_si[6]), .so(din_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[6]), .q(r_din[6]) ); | |
299 | cl_sc1_msff_8x din_5 ( .si(din_si[5]), .so(din_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[5]), .q(r_din[5]) ); | |
300 | cl_sc1_msff_8x din_4 ( .si(din_si[4]), .so(din_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[4]), .q(r_din[4]) ); | |
301 | cl_sc1_msff_8x din_3 ( .si(din_si[3]), .so(din_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[3]), .q(r_din[3]) ); | |
302 | cl_sc1_msff_8x din_2 ( .si(din_si[2]), .so(din_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[2]), .q(r_din[2]) ); | |
303 | cl_sc1_msff_8x din_1 ( .si(din_si[1]), .so(din_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[1]), .q(r_din[1]) ); | |
304 | cl_sc1_msff_8x din_0 ( .si(din_si[0]), .so(din_so[0]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[0]), .q(r_din[0]) ); | |
305 | ||
306 | // scan chain is being stitched here with assign statement: Uttam 03/29/05 | |
307 | // scan chain is being re-stitched here with assign statement: Uttam 09/07/05 | |
308 | // Left array | |
309 | ||
310 | assign din_si[32]=scan_in; | |
311 | assign din_si[33]=din_so[32]; | |
312 | assign din_si[34]=din_so[33]; | |
313 | assign din_si[35]=din_so[34]; | |
314 | assign din_si[36]=din_so[35]; | |
315 | assign din_si[37]=din_so[36]; | |
316 | assign din_si[38]=din_so[37]; | |
317 | assign din_si[39]=din_so[38]; | |
318 | assign din_si[40]=din_so[39]; | |
319 | assign din_si[41]=din_so[40]; | |
320 | assign din_si[42]=din_so[41]; | |
321 | assign din_si[43]=din_so[42]; | |
322 | assign din_si[44]=din_so[43]; | |
323 | assign din_si[45]=din_so[44]; | |
324 | assign din_si[46]=din_so[45]; | |
325 | assign din_si[47]=din_so[46]; | |
326 | assign din_si[48]=din_so[47]; | |
327 | assign din_si[49]=din_so[48]; | |
328 | assign din_si[50]=din_so[49]; | |
329 | assign din_si[51]=din_so[50]; | |
330 | assign din_si[52]=din_so[51]; | |
331 | assign din_si[53]=din_so[52]; | |
332 | assign din_si[54]=din_so[53]; | |
333 | assign din_si[55]=din_so[54]; | |
334 | assign din_si[56]=din_so[55]; | |
335 | assign din_si[57]=din_so[56]; | |
336 | assign din_si[58]=din_so[57]; | |
337 | assign din_si[59]=din_so[58]; | |
338 | assign din_si[60]=din_so[59]; | |
339 | assign din_si[61]=din_so[60]; | |
340 | assign din_si[62]=din_so[61]; | |
341 | assign din_si[63]=din_so[62]; | |
342 | ||
343 | // Decoder | |
344 | ||
345 | assign tsb_wr_si=din_so[63]; | |
346 | assign tsb_rd_si=tsb_wr_so; | |
347 | assign lkup_en_si=tsb_rd_so; | |
348 | assign rd_addr_si[4]=lkup_en_so; | |
349 | assign rd_addr_si[3]=rd_addr_so[4]; | |
350 | assign wr_addr_si[4]=rd_addr_so[3]; | |
351 | assign wr_addr_si[3]=wr_addr_so[4]; | |
352 | assign rd_addr_si[2]=wr_addr_so[3]; | |
353 | assign rd_addr_si[1]=rd_addr_so[2]; | |
354 | assign wr_addr_si[2]=rd_addr_so[1]; | |
355 | assign wr_addr_si[1]=wr_addr_so[2]; | |
356 | assign rd_addr_si[0]=wr_addr_so[1]; | |
357 | assign dev_wr_si=rd_addr_so[0]; | |
358 | assign wr_addr_si[0]=dev_wr_so; | |
359 | assign dev_rd_si=wr_addr_so[0]; | |
360 | assign adr_bs_si[2]=dev_rd_so; | |
361 | assign adr_bs_si[1]=adr_bs_so[2]; | |
362 | assign adr_bs_si[0]=adr_bs_so[1]; | |
363 | ||
364 | ||
365 | // Right array | |
366 | ||
367 | assign din_si[0]=adr_bs_so[0]; | |
368 | assign din_si[1]=din_so[0]; | |
369 | assign din_si[2]=din_so[1]; | |
370 | assign din_si[3]=din_so[2]; | |
371 | assign din_si[4]=din_so[3]; | |
372 | assign din_si[5]=din_so[4]; | |
373 | assign din_si[6]=din_so[5]; | |
374 | assign din_si[7]=din_so[6]; | |
375 | assign din_si[8]=din_so[7]; | |
376 | assign din_si[9]=din_so[8]; | |
377 | assign din_si[10]=din_so[9]; | |
378 | assign din_si[11]=din_so[10]; | |
379 | assign din_si[12]=din_so[11]; | |
380 | assign din_si[13]=din_so[12]; | |
381 | assign din_si[14]=din_so[13]; | |
382 | assign din_si[15]=din_so[14]; | |
383 | assign din_si[16]=din_so[15]; | |
384 | assign din_si[17]=din_so[16]; | |
385 | assign din_si[18]=din_so[17]; | |
386 | assign din_si[19]=din_so[18]; | |
387 | assign din_si[20]=din_so[19]; | |
388 | assign din_si[21]=din_so[20]; | |
389 | assign din_si[22]=din_so[21]; | |
390 | assign din_si[23]=din_so[22]; | |
391 | assign din_si[24]=din_so[23]; | |
392 | assign din_si[25]=din_so[24]; | |
393 | assign din_si[26]=din_so[25]; | |
394 | assign din_si[27]=din_so[26]; | |
395 | assign din_si[28]=din_so[27]; | |
396 | assign din_si[29]=din_so[28]; | |
397 | assign din_si[30]=din_so[29]; | |
398 | assign din_si[31]=din_so[30]; | |
399 | assign scan_out=din_so[31]; | |
400 | ||
401 | // end of scan chain connection uttam 03/29/05 | |
402 | ||
403 | ||
404 | //wire r_d_rd,r_d_wr; | |
405 | //assign r_d_rd = !wr_inhibit && !r_dev_wr && r_dev_rd; | |
406 | //assign r_d_wr = !wr_inhibit && r_dev_wr; | |
407 | ||
408 | wire x1_,x2_,x3,r_d_rd, r_d_wr; | |
409 | not rd2 (x1_,wr_inhibit); | |
410 | not rd3 (x2_,r_dev_wr); | |
411 | and rd1 (x3,x2_,x1_); | |
412 | and rd4 (r_d_rd,x3,r_dev_rd); | |
413 | ||
414 | and wr1 (r_d_wr,x1_,r_dev_wr); | |
415 | ||
416 | //------------------------------------------------------------------------ | |
417 | // instantiate the clock-less ram | |
418 | //------------------------------------------------------------------------ | |
419 | wire [63:0] dev_dout; | |
420 | wire [63:0] tsb_dout; | |
421 | ||
422 | n2_iom_sp_1024b_cust iommu_dev_ram ( | |
423 | .clk (and_clk), | |
424 | .adr_r (r_adr_r[3:0]), | |
425 | .adr_w (r_adr_w[3:0]), | |
426 | .rd (r_d_rd), | |
427 | .wr (r_d_wr), | |
428 | .din (r_din), | |
429 | .dout (dev_dout) | |
430 | ); | |
431 | ||
432 | ||
433 | // assign bypass_dout[63:0] = r_din[63:0]; | |
434 | ||
435 | wire [4:0] sel_dev_dout; | |
436 | //always @(dev_dout_sel or dev_dout) | |
437 | // begin | |
438 | // case(dev_dout_sel) | |
439 | // 3'b000 : sel_dev_dout = dev_dout[4:0]; | |
440 | // 3'b001 : sel_dev_dout = dev_dout[12:8]; | |
441 | // 3'b010 : sel_dev_dout = dev_dout[20:16]; | |
442 | // 3'b011 : sel_dev_dout = dev_dout[28:24]; | |
443 | // 3'b100 : sel_dev_dout = dev_dout[36:32]; | |
444 | // 3'b101 : sel_dev_dout = dev_dout[44:40]; | |
445 | // 3'b110 : sel_dev_dout = dev_dout[52:48]; | |
446 | // 3'b111 : sel_dev_dout = dev_dout[60:56]; | |
447 | // default : sel_dev_dout = 5'bxxxx; | |
448 | // endcase | |
449 | // end | |
450 | wire [7:0] sel; | |
451 | wire dev_dout_sel_2_,dev_dout_sel_1_,dev_dout_sel_0_; | |
452 | wire f_2_f_1,f_2_t_1,t_2_f_1,t_2_t_1; | |
453 | not case_sel_0 (dev_dout_sel_2_,dev_dout_sel[2]); | |
454 | not case_sel_1 (dev_dout_sel_1_,dev_dout_sel[1]); | |
455 | not case_sel_2 (dev_dout_sel_0_,dev_dout_sel[0]); | |
456 | and case_sel_3 (f_2_f_1,dev_dout_sel_2_,dev_dout_sel_1_); | |
457 | and case_sel_4 (sel[0],f_2_f_1,dev_dout_sel_0_); | |
458 | and case_sel_5 (sel[1],f_2_f_1,dev_dout_sel[0]); | |
459 | and case_sel_6 (f_2_t_1,dev_dout_sel_2_,dev_dout_sel[1]); | |
460 | and case_sel_7 (sel[2],f_2_t_1,dev_dout_sel_0_); | |
461 | and case_sel_8 (sel[3],f_2_t_1,dev_dout_sel[0]); | |
462 | and case_sel_9 (t_2_f_1,dev_dout_sel[2],dev_dout_sel_1_); | |
463 | and case_sel_10 (sel[4],t_2_f_1,dev_dout_sel_0_); | |
464 | and case_sel_11 (sel[5],t_2_f_1,dev_dout_sel[0]); | |
465 | and case_sel_12 (t_2_t_1,dev_dout_sel[2],dev_dout_sel[1]); | |
466 | and case_sel_13 (sel[6],t_2_t_1,dev_dout_sel_0_); | |
467 | and case_sel_14 (sel[7],t_2_t_1,dev_dout_sel[0]); | |
468 | cl_a1_aomux8_4x sel_dev_dout_mux_0 ( .out(sel_dev_dout[0]) , | |
469 | .sel0(sel[0]), .sel1(sel[1]), .in0(dev_dout[0]), .in1(dev_dout[8]), | |
470 | .sel2(sel[2]), .sel3(sel[3]), .in2(dev_dout[16]), .in3(dev_dout[24]), | |
471 | .sel4(sel[4]), .sel5(sel[5]), .in4(dev_dout[32]), .in5(dev_dout[40]), | |
472 | .sel6(sel[6]), .sel7(sel[7]), .in6(dev_dout[48]), .in7(dev_dout[56]) ); | |
473 | cl_a1_aomux8_4x sel_dev_dout_mux_1 ( .out(sel_dev_dout[1]) , | |
474 | .sel0(sel[0]), .sel1(sel[1]), .in0(dev_dout[1]), .in1(dev_dout[9]), | |
475 | .sel2(sel[2]), .sel3(sel[3]), .in2(dev_dout[17]), .in3(dev_dout[25]), | |
476 | .sel4(sel[4]), .sel5(sel[5]), .in4(dev_dout[33]), .in5(dev_dout[41]), | |
477 | .sel6(sel[6]), .sel7(sel[7]), .in6(dev_dout[49]), .in7(dev_dout[57]) ); | |
478 | cl_a1_aomux8_4x sel_dev_dout_mux_2 ( .out(sel_dev_dout[2]) , | |
479 | .sel0(sel[0]), .sel1(sel[1]), .in0(dev_dout[2]), .in1(dev_dout[10]), | |
480 | .sel2(sel[2]), .sel3(sel[3]), .in2(dev_dout[18]), .in3(dev_dout[26]), | |
481 | .sel4(sel[4]), .sel5(sel[5]), .in4(dev_dout[34]), .in5(dev_dout[42]), | |
482 | .sel6(sel[6]), .sel7(sel[7]), .in6(dev_dout[50]), .in7(dev_dout[58]) ); | |
483 | cl_a1_aomux8_4x sel_dev_dout_mux_3 ( .out(sel_dev_dout[3]) , | |
484 | .sel0(sel[0]), .sel1(sel[1]), .in0(dev_dout[3]), .in1(dev_dout[11]), | |
485 | .sel2(sel[2]), .sel3(sel[3]), .in2(dev_dout[19]), .in3(dev_dout[27]), | |
486 | .sel4(sel[4]), .sel5(sel[5]), .in4(dev_dout[35]), .in5(dev_dout[43]), | |
487 | .sel6(sel[6]), .sel7(sel[7]), .in6(dev_dout[51]), .in7(dev_dout[59]) ); | |
488 | cl_a1_aomux8_4x sel_dev_dout_mux_4 ( .out(sel_dev_dout[4]) , | |
489 | .sel0(sel[0]), .sel1(sel[1]), .in0(dev_dout[4]), .in1(dev_dout[12]), | |
490 | .sel2(sel[2]), .sel3(sel[3]), .in2(dev_dout[20]), .in3(dev_dout[28]), | |
491 | .sel4(sel[4]), .sel5(sel[5]), .in4(dev_dout[36]), .in5(dev_dout[44]), | |
492 | .sel6(sel[6]), .sel7(sel[7]), .in6(dev_dout[52]), .in7(dev_dout[60]) ); | |
493 | ||
494 | // assign sel_dev_dout = ((dev_dout_sel == 3'b000) ? dev_dout[4:0] : | |
495 | // (dev_dout_sel == 3'b001) ? dev_dout[12:8] : | |
496 | // (dev_dout_sel == 3'b010) ? dev_dout[20:16] : | |
497 | // (dev_dout_sel == 3'b011) ? dev_dout[28:24] : | |
498 | // (dev_dout_sel == 3'b100) ? dev_dout[36:32] : | |
499 | // (dev_dout_sel == 3'b101) ? dev_dout[44:40] : | |
500 | // (dev_dout_sel == 3'b110) ? dev_dout[52:48] : | |
501 | // (dev_dout_sel == 3'b111) ? dev_dout[60:56] : 4'bxxxx ); | |
502 | ||
503 | wire r_t_rd,r_t_wr; | |
504 | wire [4:0] rd_and_r_adr,tsb_adr_r,tsb_ram_adr_r,rd_wr_adr; | |
505 | wire r_tsb_wr_,wr_inhibit_,y0,r_lkup_en_; | |
506 | ||
507 | //assign tsb_read_addr = r_lkup_en ? sel_dev_dout : r_adr_r ; | |
508 | //assign tsb_adr_r = r_tsb_wr ? r_adr_w : tsb_read_addr; | |
509 | //BP 9-27-06 eco 119647changes below for TO 2.0 to make rtl match schematic because of atpg mismatches | |
510 | not r_lkup_en_0 (r_lkup_en_,r_lkup_en); | |
511 | and rd_and_addr_4_g (rd_and_r_adr[4], r_adr_r[4],r_tsb_rd); | |
512 | and rd_and_addr_3_g (rd_and_r_adr[3], r_adr_r[3],r_tsb_rd); | |
513 | and rd_and_addr_2_g (rd_and_r_adr[2], r_adr_r[2],r_tsb_rd); | |
514 | and rd_and_addr_1_g (rd_and_r_adr[1], r_adr_r[1],r_tsb_rd); | |
515 | and rd_and_addr_0_g (rd_and_r_adr[0], r_adr_r[0],r_tsb_rd); | |
516 | cl_a1_aomux2_4x rd_addr_mux_4 ( .sel0(r_lkup_en), .sel1(r_lkup_en_), .in0(sel_dev_dout[4]), .in1(rd_wr_adr[4]), .out(tsb_ram_adr_r[4]) ); | |
517 | cl_a1_aomux2_4x rd_addr_mux_3 ( .sel0(r_lkup_en), .sel1(r_lkup_en_), .in0(sel_dev_dout[3]), .in1(rd_wr_adr[3]), .out(tsb_ram_adr_r[3]) ); | |
518 | cl_a1_aomux2_4x rd_addr_mux_2 ( .sel0(r_lkup_en), .sel1(r_lkup_en_), .in0(sel_dev_dout[2]), .in1(rd_wr_adr[2]), .out(tsb_ram_adr_r[2]) ); | |
519 | cl_a1_aomux2_4x rd_addr_mux_1 ( .sel0(r_lkup_en), .sel1(r_lkup_en_), .in0(sel_dev_dout[1]), .in1(rd_wr_adr[1]), .out(tsb_ram_adr_r[1]) ); | |
520 | cl_a1_aomux2_4x rd_addr_mux_0 ( .sel0(r_lkup_en), .sel1(r_lkup_en_), .in0(sel_dev_dout[0]), .in1(rd_wr_adr[0]), .out(tsb_ram_adr_r[0]) ); | |
521 | cl_a1_aomux2_4x tsb_adr_r_mux_4 ( .sel0(r_tsb_wr), .sel1(r_tsb_wr_), .in0(r_adr_w[4]), .in1(rd_and_r_adr[4]), .out(rd_wr_adr[4]) ); | |
522 | cl_a1_aomux2_4x tsb_adr_r_mux_3 ( .sel0(r_tsb_wr), .sel1(r_tsb_wr_), .in0(r_adr_w[3]), .in1(rd_and_r_adr[3]), .out(rd_wr_adr[3]) ); | |
523 | cl_a1_aomux2_4x tsb_adr_r_mux_2 ( .sel0(r_tsb_wr), .sel1(r_tsb_wr_), .in0(r_adr_w[2]), .in1(rd_and_r_adr[2]), .out(rd_wr_adr[2]) ); | |
524 | cl_a1_aomux2_4x tsb_adr_r_mux_1 ( .sel0(r_tsb_wr), .sel1(r_tsb_wr_), .in0(r_adr_w[1]), .in1(rd_and_r_adr[1]), .out(rd_wr_adr[1]) ); | |
525 | cl_a1_aomux2_4x tsb_adr_r_mux_0 ( .sel0(r_tsb_wr), .sel1(r_tsb_wr_), .in0(r_adr_w[0]), .in1(rd_and_r_adr[0]), .out(rd_wr_adr[0]) ); | |
526 | ||
527 | //BP 4-12-05 need latch to hold tsb_ram_adr_r because the new mo latch causes latched inputs to go to 0 during ~clk | |
528 | cl_mc1_tisram_blb_4x tsb_adr_r_o_4 ( .l1clk(~and_clk), .d_a(tsb_ram_adr_r[4]), .q_b(tsb_adr_r[4]) ); | |
529 | cl_mc1_tisram_blb_4x tsb_adr_r_o_3 ( .l1clk(~and_clk), .d_a(tsb_ram_adr_r[3]), .q_b(tsb_adr_r[3]) ); | |
530 | cl_mc1_tisram_blb_4x tsb_adr_r_o_2 ( .l1clk(~and_clk), .d_a(tsb_ram_adr_r[2]), .q_b(tsb_adr_r[2]) ); | |
531 | cl_mc1_tisram_blb_4x tsb_adr_r_o_1 ( .l1clk(~and_clk), .d_a(tsb_ram_adr_r[1]), .q_b(tsb_adr_r[1]) ); | |
532 | cl_mc1_tisram_blb_4x tsb_adr_r_o_0 ( .l1clk(~and_clk), .d_a(tsb_ram_adr_r[0]), .q_b(tsb_adr_r[0]) ); | |
533 | ||
534 | //assign r_t_rd = !wr_inhibit && !r_tsb_wr && r_tsb_rd; | |
535 | //assign r_t_wr = !wr_inhibit && r_tsb_wr; | |
536 | ||
537 | not tsb_0 (wr_inhibit_,wr_inhibit); | |
538 | not tsb_1 (r_tsb_wr_,r_tsb_wr); | |
539 | and tsb_2 (y0,wr_inhibit_,r_tsb_wr_); | |
540 | and tsb_3 (r_t_rd,y0,r_tsb_rd); | |
541 | and tsb_4 (r_t_wr,wr_inhibit_,r_tsb_wr); | |
542 | ||
543 | n2_iom_sp_2048b_cust iommu_tsb_ram ( | |
544 | .clk (and_clk), | |
545 | .adr_r (tsb_ram_adr_r), | |
546 | // .adr_w (r_adr_w), | |
547 | .adr_w (tsb_ram_adr_r), | |
548 | .rd (r_t_rd), | |
549 | .wr (r_t_wr), | |
550 | .din (r_din), | |
551 | .dout (tsb_dout), | |
552 | .efu_bits (efu_bits[3:0]) | |
553 | ); | |
554 | ||
555 | ||
556 | // wire [63:0] dout_array; | |
557 | //always @(clk or r_t_rd or tsb_dout or dev_dout or r_d_rd or r_tsb_rd ) begin | |
558 | // | |
559 | // if (clk) begin | |
560 | // if (r_t_rd & r_tsb_rd) begin | |
561 | // dout[63:0] = tsb_dout; | |
562 | // end | |
563 | // else if (r_d_rd & ~r_tsb_rd) begin | |
564 | // dout[63:0] = dev_dout; | |
565 | // end | |
566 | // end | |
567 | //end | |
568 | wire [63:0] mux_dout; | |
569 | wire r_tsb_rd_,tsb_sel_,tsb_sel,dev_sel_,dev_sel; | |
570 | ||
571 | cl_a1_inv_4x mux_sel_4 ( .out(r_tsb_rd_), .in(r_tsb_rd) ); | |
572 | //cl_a1_nand2_4x mux_sel_0 ( .out(tsb_sel_), .in0(r_t_rd), .in1(r_tsb_rd) ); | |
573 | cl_a1_nand2_4x mux_sel_0 ( .out(tsb_sel_), .in0(wr_inhibit_), .in1(r_tsb_rd) ); | |
574 | cl_a1_inv_4x mux_sel_1 ( .out(tsb_sel), .in(tsb_sel_) ); | |
575 | //cl_a1_nand2_4x mux_sel_2 ( .out(dev_sel_), .in0(r_d_rd), .in1(r_tsb_rd_) ); | |
576 | cl_a1_nand2_4x mux_sel_2 ( .out(dev_sel_), .in0(wr_inhibit_), .in1(r_tsb_rd_) ); | |
577 | cl_a1_inv_4x mux_sel_3 ( .out(dev_sel), .in(dev_sel_) ); | |
578 | ||
579 | cl_a1_aomux2_4x mux_dout_63 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[63]), .in1(dev_dout[63]), .out(mux_dout[63]) ); | |
580 | cl_a1_aomux2_4x mux_dout_62 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[62]), .in1(dev_dout[62]), .out(mux_dout[62]) ); | |
581 | cl_a1_aomux2_4x mux_dout_61 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[61]), .in1(dev_dout[61]), .out(mux_dout[61]) ); | |
582 | cl_a1_aomux2_4x mux_dout_60 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[60]), .in1(dev_dout[60]), .out(mux_dout[60]) ); | |
583 | ||
584 | cl_a1_aomux2_4x mux_dout_59 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[59]), .in1(dev_dout[59]), .out(mux_dout[59]) ); | |
585 | cl_a1_aomux2_4x mux_dout_58 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[58]), .in1(dev_dout[58]), .out(mux_dout[58]) ); | |
586 | cl_a1_aomux2_4x mux_dout_57 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[57]), .in1(dev_dout[57]), .out(mux_dout[57]) ); | |
587 | cl_a1_aomux2_4x mux_dout_56 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[56]), .in1(dev_dout[56]), .out(mux_dout[56]) ); | |
588 | cl_a1_aomux2_4x mux_dout_55 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[55]), .in1(dev_dout[55]), .out(mux_dout[55]) ); | |
589 | cl_a1_aomux2_4x mux_dout_54 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[54]), .in1(dev_dout[54]), .out(mux_dout[54]) ); | |
590 | cl_a1_aomux2_4x mux_dout_53 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[53]), .in1(dev_dout[53]), .out(mux_dout[53]) ); | |
591 | cl_a1_aomux2_4x mux_dout_52 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[52]), .in1(dev_dout[52]), .out(mux_dout[52]) ); | |
592 | cl_a1_aomux2_4x mux_dout_51 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[51]), .in1(dev_dout[51]), .out(mux_dout[51]) ); | |
593 | cl_a1_aomux2_4x mux_dout_50 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[50]), .in1(dev_dout[50]), .out(mux_dout[50]) ); | |
594 | ||
595 | cl_a1_aomux2_4x mux_dout_49 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[49]), .in1(dev_dout[49]), .out(mux_dout[49]) ); | |
596 | cl_a1_aomux2_4x mux_dout_48 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[48]), .in1(dev_dout[48]), .out(mux_dout[48]) ); | |
597 | cl_a1_aomux2_4x mux_dout_47 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[47]), .in1(dev_dout[47]), .out(mux_dout[47]) ); | |
598 | cl_a1_aomux2_4x mux_dout_46 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[46]), .in1(dev_dout[46]), .out(mux_dout[46]) ); | |
599 | cl_a1_aomux2_4x mux_dout_45 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[45]), .in1(dev_dout[45]), .out(mux_dout[45]) ); | |
600 | cl_a1_aomux2_4x mux_dout_44 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[44]), .in1(dev_dout[44]), .out(mux_dout[44]) ); | |
601 | cl_a1_aomux2_4x mux_dout_43 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[43]), .in1(dev_dout[43]), .out(mux_dout[43]) ); | |
602 | cl_a1_aomux2_4x mux_dout_42 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[42]), .in1(dev_dout[42]), .out(mux_dout[42]) ); | |
603 | cl_a1_aomux2_4x mux_dout_41 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[41]), .in1(dev_dout[41]), .out(mux_dout[41]) ); | |
604 | cl_a1_aomux2_4x mux_dout_40 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[40]), .in1(dev_dout[40]), .out(mux_dout[40]) ); | |
605 | ||
606 | cl_a1_aomux2_4x mux_dout_39 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[39]), .in1(dev_dout[39]), .out(mux_dout[39]) ); | |
607 | cl_a1_aomux2_4x mux_dout_38 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[38]), .in1(dev_dout[38]), .out(mux_dout[38]) ); | |
608 | cl_a1_aomux2_4x mux_dout_37 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[37]), .in1(dev_dout[37]), .out(mux_dout[37]) ); | |
609 | cl_a1_aomux2_4x mux_dout_36 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[36]), .in1(dev_dout[36]), .out(mux_dout[36]) ); | |
610 | cl_a1_aomux2_4x mux_dout_35 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[35]), .in1(dev_dout[35]), .out(mux_dout[35]) ); | |
611 | cl_a1_aomux2_4x mux_dout_34 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[34]), .in1(dev_dout[34]), .out(mux_dout[34]) ); | |
612 | cl_a1_aomux2_4x mux_dout_33 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[33]), .in1(dev_dout[33]), .out(mux_dout[33]) ); | |
613 | cl_a1_aomux2_4x mux_dout_32 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[32]), .in1(dev_dout[32]), .out(mux_dout[32]) ); | |
614 | cl_a1_aomux2_4x mux_dout_31 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[31]), .in1(dev_dout[31]), .out(mux_dout[31]) ); | |
615 | cl_a1_aomux2_4x mux_dout_30 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[30]), .in1(dev_dout[30]), .out(mux_dout[30]) ); | |
616 | ||
617 | cl_a1_aomux2_4x mux_dout_29 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[29]), .in1(dev_dout[29]), .out(mux_dout[29]) ); | |
618 | cl_a1_aomux2_4x mux_dout_28 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[28]), .in1(dev_dout[28]), .out(mux_dout[28]) ); | |
619 | cl_a1_aomux2_4x mux_dout_27 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[27]), .in1(dev_dout[27]), .out(mux_dout[27]) ); | |
620 | cl_a1_aomux2_4x mux_dout_26 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[26]), .in1(dev_dout[26]), .out(mux_dout[26]) ); | |
621 | cl_a1_aomux2_4x mux_dout_25 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[25]), .in1(dev_dout[25]), .out(mux_dout[25]) ); | |
622 | cl_a1_aomux2_4x mux_dout_24 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[24]), .in1(dev_dout[24]), .out(mux_dout[24]) ); | |
623 | cl_a1_aomux2_4x mux_dout_23 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[23]), .in1(dev_dout[23]), .out(mux_dout[23]) ); | |
624 | cl_a1_aomux2_4x mux_dout_22 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[22]), .in1(dev_dout[22]), .out(mux_dout[22]) ); | |
625 | cl_a1_aomux2_4x mux_dout_21 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[21]), .in1(dev_dout[21]), .out(mux_dout[21]) ); | |
626 | cl_a1_aomux2_4x mux_dout_20 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[20]), .in1(dev_dout[20]), .out(mux_dout[20]) ); | |
627 | ||
628 | cl_a1_aomux2_4x mux_dout_19 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[19]), .in1(dev_dout[19]), .out(mux_dout[19]) ); | |
629 | cl_a1_aomux2_4x mux_dout_18 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[18]), .in1(dev_dout[18]), .out(mux_dout[18]) ); | |
630 | cl_a1_aomux2_4x mux_dout_17 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[17]), .in1(dev_dout[17]), .out(mux_dout[17]) ); | |
631 | cl_a1_aomux2_4x mux_dout_16 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[16]), .in1(dev_dout[16]), .out(mux_dout[16]) ); | |
632 | cl_a1_aomux2_4x mux_dout_15 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[15]), .in1(dev_dout[15]), .out(mux_dout[15]) ); | |
633 | cl_a1_aomux2_4x mux_dout_14 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[14]), .in1(dev_dout[14]), .out(mux_dout[14]) ); | |
634 | cl_a1_aomux2_4x mux_dout_13 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[13]), .in1(dev_dout[13]), .out(mux_dout[13]) ); | |
635 | cl_a1_aomux2_4x mux_dout_12 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[12]), .in1(dev_dout[12]), .out(mux_dout[12]) ); | |
636 | cl_a1_aomux2_4x mux_dout_11 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[11]), .in1(dev_dout[11]), .out(mux_dout[11]) ); | |
637 | cl_a1_aomux2_4x mux_dout_10 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[10]), .in1(dev_dout[10]), .out(mux_dout[10]) ); | |
638 | ||
639 | cl_a1_aomux2_4x mux_dout_9 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[9]), .in1(dev_dout[9]), .out(mux_dout[9]) ); | |
640 | cl_a1_aomux2_4x mux_dout_8 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[8]), .in1(dev_dout[8]), .out(mux_dout[8]) ); | |
641 | cl_a1_aomux2_4x mux_dout_7 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[7]), .in1(dev_dout[7]), .out(mux_dout[7]) ); | |
642 | cl_a1_aomux2_4x mux_dout_6 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[6]), .in1(dev_dout[6]), .out(mux_dout[6]) ); | |
643 | cl_a1_aomux2_4x mux_dout_5 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[5]), .in1(dev_dout[5]), .out(mux_dout[5]) ); | |
644 | cl_a1_aomux2_4x mux_dout_4 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[4]), .in1(dev_dout[4]), .out(mux_dout[4]) ); | |
645 | cl_a1_aomux2_4x mux_dout_3 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[3]), .in1(dev_dout[3]), .out(mux_dout[3]) ); | |
646 | cl_a1_aomux2_4x mux_dout_2 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[2]), .in1(dev_dout[2]), .out(mux_dout[2]) ); | |
647 | cl_a1_aomux2_4x mux_dout_1 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[1]), .in1(dev_dout[1]), .out(mux_dout[1]) ); | |
648 | cl_a1_aomux2_4x mux_dout_0 ( .sel0(tsb_sel), .sel1(dev_sel), .in0(tsb_dout[0]), .in1(dev_dout[0]), .out(mux_dout[0]) ); | |
649 | ||
650 | wire latch_clk; | |
651 | //assign latch_clk = ~(clk & ( r_t_rd | r_d_rd)); | |
652 | wire rd_; | |
653 | cl_a1_nor2_4x latch_0 ( .out(rd_), .in0(r_tsb_rd), .in1(r_dev_rd) ); | |
654 | cl_a1_inv_4x latch_1 ( .out(rd), .in(rd_) ); | |
655 | //BP eco119647 latch_2 ( .out(latch_clk), .in0(rd), .in1(and_clk) ); | |
656 | cl_a1_nand3_4x latch_2 ( .out(latch_clk), .in0(rd), .in1(and_clk), .in2(wr_inhibit_) ); | |
657 | ||
658 | cl_mc1_tisram_blb_4x dout_63 ( .l1clk(latch_clk), .d_a(mux_dout[63]), .q_b(dout[63]) ); | |
659 | cl_mc1_tisram_blb_4x dout_62 ( .l1clk(latch_clk), .d_a(mux_dout[62]), .q_b(dout[62]) ); | |
660 | cl_mc1_tisram_blb_4x dout_61 ( .l1clk(latch_clk), .d_a(mux_dout[61]), .q_b(dout[61]) ); | |
661 | cl_mc1_tisram_blb_4x dout_60 ( .l1clk(latch_clk), .d_a(mux_dout[60]), .q_b(dout[60]) ); | |
662 | ||
663 | cl_mc1_tisram_blb_4x dout_59 ( .l1clk(latch_clk), .d_a(mux_dout[59]), .q_b(dout[59]) ); | |
664 | cl_mc1_tisram_blb_4x dout_58 ( .l1clk(latch_clk), .d_a(mux_dout[58]), .q_b(dout[58]) ); | |
665 | cl_mc1_tisram_blb_4x dout_57 ( .l1clk(latch_clk), .d_a(mux_dout[57]), .q_b(dout[57]) ); | |
666 | cl_mc1_tisram_blb_4x dout_56 ( .l1clk(latch_clk), .d_a(mux_dout[56]), .q_b(dout[56]) ); | |
667 | cl_mc1_tisram_blb_4x dout_55 ( .l1clk(latch_clk), .d_a(mux_dout[55]), .q_b(dout[55]) ); | |
668 | cl_mc1_tisram_blb_4x dout_54 ( .l1clk(latch_clk), .d_a(mux_dout[54]), .q_b(dout[54]) ); | |
669 | cl_mc1_tisram_blb_4x dout_53 ( .l1clk(latch_clk), .d_a(mux_dout[53]), .q_b(dout[53]) ); | |
670 | cl_mc1_tisram_blb_4x dout_52 ( .l1clk(latch_clk), .d_a(mux_dout[52]), .q_b(dout[52]) ); | |
671 | cl_mc1_tisram_blb_4x dout_51 ( .l1clk(latch_clk), .d_a(mux_dout[51]), .q_b(dout[51]) ); | |
672 | cl_mc1_tisram_blb_4x dout_50 ( .l1clk(latch_clk), .d_a(mux_dout[50]), .q_b(dout[50]) ); | |
673 | ||
674 | cl_mc1_tisram_blb_4x dout_49 ( .l1clk(latch_clk), .d_a(mux_dout[49]), .q_b(dout[49]) ); | |
675 | cl_mc1_tisram_blb_4x dout_48 ( .l1clk(latch_clk), .d_a(mux_dout[48]), .q_b(dout[48]) ); | |
676 | cl_mc1_tisram_blb_4x dout_47 ( .l1clk(latch_clk), .d_a(mux_dout[47]), .q_b(dout[47]) ); | |
677 | cl_mc1_tisram_blb_4x dout_46 ( .l1clk(latch_clk), .d_a(mux_dout[46]), .q_b(dout[46]) ); | |
678 | cl_mc1_tisram_blb_4x dout_45 ( .l1clk(latch_clk), .d_a(mux_dout[45]), .q_b(dout[45]) ); | |
679 | cl_mc1_tisram_blb_4x dout_44 ( .l1clk(latch_clk), .d_a(mux_dout[44]), .q_b(dout[44]) ); | |
680 | cl_mc1_tisram_blb_4x dout_43 ( .l1clk(latch_clk), .d_a(mux_dout[43]), .q_b(dout[43]) ); | |
681 | cl_mc1_tisram_blb_4x dout_42 ( .l1clk(latch_clk), .d_a(mux_dout[42]), .q_b(dout[42]) ); | |
682 | cl_mc1_tisram_blb_4x dout_41 ( .l1clk(latch_clk), .d_a(mux_dout[41]), .q_b(dout[41]) ); | |
683 | cl_mc1_tisram_blb_4x dout_40 ( .l1clk(latch_clk), .d_a(mux_dout[40]), .q_b(dout[40]) ); | |
684 | ||
685 | cl_mc1_tisram_blb_4x dout_39 ( .l1clk(latch_clk), .d_a(mux_dout[39]), .q_b(dout[39]) ); | |
686 | cl_mc1_tisram_blb_4x dout_38 ( .l1clk(latch_clk), .d_a(mux_dout[38]), .q_b(dout[38]) ); | |
687 | cl_mc1_tisram_blb_4x dout_37 ( .l1clk(latch_clk), .d_a(mux_dout[37]), .q_b(dout[37]) ); | |
688 | cl_mc1_tisram_blb_4x dout_36 ( .l1clk(latch_clk), .d_a(mux_dout[36]), .q_b(dout[36]) ); | |
689 | cl_mc1_tisram_blb_4x dout_35 ( .l1clk(latch_clk), .d_a(mux_dout[35]), .q_b(dout[35]) ); | |
690 | cl_mc1_tisram_blb_4x dout_34 ( .l1clk(latch_clk), .d_a(mux_dout[34]), .q_b(dout[34]) ); | |
691 | cl_mc1_tisram_blb_4x dout_33 ( .l1clk(latch_clk), .d_a(mux_dout[33]), .q_b(dout[33]) ); | |
692 | cl_mc1_tisram_blb_4x dout_32 ( .l1clk(latch_clk), .d_a(mux_dout[32]), .q_b(dout[32]) ); | |
693 | cl_mc1_tisram_blb_4x dout_31 ( .l1clk(latch_clk), .d_a(mux_dout[31]), .q_b(dout[31]) ); | |
694 | cl_mc1_tisram_blb_4x dout_30 ( .l1clk(latch_clk), .d_a(mux_dout[30]), .q_b(dout[30]) ); | |
695 | ||
696 | cl_mc1_tisram_blb_4x dout_29 ( .l1clk(latch_clk), .d_a(mux_dout[29]), .q_b(dout[29]) ); | |
697 | cl_mc1_tisram_blb_4x dout_28 ( .l1clk(latch_clk), .d_a(mux_dout[28]), .q_b(dout[28]) ); | |
698 | cl_mc1_tisram_blb_4x dout_27 ( .l1clk(latch_clk), .d_a(mux_dout[27]), .q_b(dout[27]) ); | |
699 | cl_mc1_tisram_blb_4x dout_26 ( .l1clk(latch_clk), .d_a(mux_dout[26]), .q_b(dout[26]) ); | |
700 | cl_mc1_tisram_blb_4x dout_25 ( .l1clk(latch_clk), .d_a(mux_dout[25]), .q_b(dout[25]) ); | |
701 | cl_mc1_tisram_blb_4x dout_24 ( .l1clk(latch_clk), .d_a(mux_dout[24]), .q_b(dout[24]) ); | |
702 | cl_mc1_tisram_blb_4x dout_23 ( .l1clk(latch_clk), .d_a(mux_dout[23]), .q_b(dout[23]) ); | |
703 | cl_mc1_tisram_blb_4x dout_22 ( .l1clk(latch_clk), .d_a(mux_dout[22]), .q_b(dout[22]) ); | |
704 | cl_mc1_tisram_blb_4x dout_21 ( .l1clk(latch_clk), .d_a(mux_dout[21]), .q_b(dout[21]) ); | |
705 | cl_mc1_tisram_blb_4x dout_20 ( .l1clk(latch_clk), .d_a(mux_dout[20]), .q_b(dout[20]) ); | |
706 | ||
707 | cl_mc1_tisram_blb_4x dout_19 ( .l1clk(latch_clk), .d_a(mux_dout[19]), .q_b(dout[19]) ); | |
708 | cl_mc1_tisram_blb_4x dout_18 ( .l1clk(latch_clk), .d_a(mux_dout[18]), .q_b(dout[18]) ); | |
709 | cl_mc1_tisram_blb_4x dout_17 ( .l1clk(latch_clk), .d_a(mux_dout[17]), .q_b(dout[17]) ); | |
710 | cl_mc1_tisram_blb_4x dout_16 ( .l1clk(latch_clk), .d_a(mux_dout[16]), .q_b(dout[16]) ); | |
711 | cl_mc1_tisram_blb_4x dout_15 ( .l1clk(latch_clk), .d_a(mux_dout[15]), .q_b(dout[15]) ); | |
712 | cl_mc1_tisram_blb_4x dout_14 ( .l1clk(latch_clk), .d_a(mux_dout[14]), .q_b(dout[14]) ); | |
713 | cl_mc1_tisram_blb_4x dout_13 ( .l1clk(latch_clk), .d_a(mux_dout[13]), .q_b(dout[13]) ); | |
714 | cl_mc1_tisram_blb_4x dout_12 ( .l1clk(latch_clk), .d_a(mux_dout[12]), .q_b(dout[12]) ); | |
715 | cl_mc1_tisram_blb_4x dout_11 ( .l1clk(latch_clk), .d_a(mux_dout[11]), .q_b(dout[11]) ); | |
716 | cl_mc1_tisram_blb_4x dout_10 ( .l1clk(latch_clk), .d_a(mux_dout[10]), .q_b(dout[10]) ); | |
717 | ||
718 | cl_mc1_tisram_blb_4x dout_9 ( .l1clk(latch_clk), .d_a(mux_dout[9]), .q_b(dout[9]) ); | |
719 | cl_mc1_tisram_blb_4x dout_8 ( .l1clk(latch_clk), .d_a(mux_dout[8]), .q_b(dout[8]) ); | |
720 | cl_mc1_tisram_blb_4x dout_7 ( .l1clk(latch_clk), .d_a(mux_dout[7]), .q_b(dout[7]) ); | |
721 | cl_mc1_tisram_blb_4x dout_6 ( .l1clk(latch_clk), .d_a(mux_dout[6]), .q_b(dout[6]) ); | |
722 | cl_mc1_tisram_blb_4x dout_5 ( .l1clk(latch_clk), .d_a(mux_dout[5]), .q_b(dout[5]) ); | |
723 | cl_mc1_tisram_blb_4x dout_4 ( .l1clk(latch_clk), .d_a(mux_dout[4]), .q_b(dout[4]) ); | |
724 | cl_mc1_tisram_blb_4x dout_3 ( .l1clk(latch_clk), .d_a(mux_dout[3]), .q_b(dout[3]) ); | |
725 | cl_mc1_tisram_blb_4x dout_2 ( .l1clk(latch_clk), .d_a(mux_dout[2]), .q_b(dout[2]) ); | |
726 | cl_mc1_tisram_blb_4x dout_1 ( .l1clk(latch_clk), .d_a(mux_dout[1]), .q_b(dout[1]) ); | |
727 | cl_mc1_tisram_blb_4x dout_0 ( .l1clk(latch_clk), .d_a(mux_dout[0]), .q_b(dout[0]) ); | |
728 | ||
729 | ||
730 | ||
731 | ||
732 | ||
733 | ||
734 | ||
735 | ||
736 | ||
737 | ||
738 | //assign dout = r_tsb_rd ? tsb_dout : dev_dout ; // behavioural before output latch added above | |
739 | ||
740 | ||
741 | ||
742 | endmodule // n2_iom_sp_devtsb_cust | |
743 | ||
744 | ||
745 | module n2_iom_sp_1024b_cust ( | |
746 | ||
747 | clk, | |
748 | adr_r, | |
749 | adr_w, | |
750 | rd, | |
751 | wr, | |
752 | din, | |
753 | dout | |
754 | ||
755 | ); | |
756 | ||
757 | ||
758 | input clk; | |
759 | input [3:0] adr_r; | |
760 | input [3:0] adr_w; | |
761 | input rd; | |
762 | input wr; | |
763 | input [63:0] din; | |
764 | output [63:0] dout; | |
765 | ||
766 | ||
767 | /* RAM Array: =16 - 1 -> 15 */ | |
768 | ||
769 | reg [63:0] array_ram [0:15]; | |
770 | reg [63:0] dout; | |
771 | ||
772 | `ifndef NOINITMEM | |
773 | integer i; | |
774 | ||
775 | initial begin | |
776 | for (i=0; i<16; i=i+1) begin | |
777 | array_ram[i] = 64'b0; | |
778 | end | |
779 | dout[63:0] = 64'b0; | |
780 | end | |
781 | `endif | |
782 | ||
783 | ||
784 | // ---------------------------------------------------------------------------- | |
785 | // Read/write the array, single port | |
786 | // ---------------------------------------------------------------------------- | |
787 | always @(clk or rd or adr_r or wr or adr_w or din ) begin | |
788 | if (clk) begin | |
789 | if (rd ) begin | |
790 | dout[63:0] <= array_ram[adr_r[3:0]]; | |
791 | end | |
792 | else begin | |
793 | dout[63:0] <= {64{1'b0}}; | |
794 | if (wr ) | |
795 | array_ram[adr_w[3:0]] <= din[63:0]; | |
796 | end | |
797 | end | |
798 | end | |
799 | ||
800 | ||
801 | endmodule // n2_iom_sp_1024b_cust | |
802 | ||
803 | ||
804 | ||
805 | module n2_iom_sp_2048b_cust ( | |
806 | ||
807 | clk, | |
808 | adr_r, | |
809 | adr_w, | |
810 | rd, | |
811 | wr, | |
812 | din, | |
813 | dout, | |
814 | efu_bits | |
815 | ||
816 | ); | |
817 | ||
818 | ||
819 | input clk; | |
820 | input [4:0] adr_r; | |
821 | input [4:0] adr_w; | |
822 | input rd; | |
823 | input wr; | |
824 | input [63:0] din; | |
825 | input [3:0] efu_bits; | |
826 | output [63:0] dout; | |
827 | ||
828 | ||
829 | /* RAM Array: =32 - 1 -> 31 */ | |
830 | ||
831 | reg [63:0] array_ram [0:31]; | |
832 | reg [63:0] dout; | |
833 | ||
834 | `ifndef NOINITMEM | |
835 | integer i; | |
836 | ||
837 | initial begin | |
838 | for (i=0; i<32; i=i+1) begin | |
839 | array_ram[i] = 64'b0; | |
840 | end | |
841 | dout[63:0] = 64'b0; | |
842 | end | |
843 | `endif | |
844 | ||
845 | // 0in one_hot -var efu_bits | |
846 | // ---------------------------------------------------------------------------- | |
847 | // Read/write the array , single port | |
848 | // ---------------------------------------------------------------------------- | |
849 | always @(clk or rd or adr_r or wr or adr_w or din or efu_bits) begin | |
850 | ||
851 | if (clk) begin | |
852 | if (rd) begin | |
853 | if (efu_bits[0]) begin | |
854 | dout[63:0] <= array_ram[adr_r[4:0]]; | |
855 | end | |
856 | else if (efu_bits[1]) begin | |
857 | dout[63:0] <= array_ram[adr_r[4:0]]; | |
858 | end | |
859 | else if (efu_bits[2]) begin | |
860 | dout[63:0] <= array_ram[adr_r[4:0]]; | |
861 | end | |
862 | else if (efu_bits[3]) begin | |
863 | dout[63:0] <= array_ram[adr_r[4:0]]; | |
864 | end | |
865 | end | |
866 | else begin | |
867 | dout[63:0] <= {64{1'b0}}; | |
868 | if(wr ) | |
869 | array_ram[adr_w[4:0]] <= din[63:0]; | |
870 | end | |
871 | end | |
872 | end | |
873 | ||
874 | ||
875 | endmodule // n2_iom_sp_2048b_cust | |
876 | ||
877 |