projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: n2_l2t_quad.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `define L2T_ARR_D_WIDTH 28 | |
| 36 | `define L2T_ARR_DEPTH 512 | |
| 37 | `define WAY_HIT_WIDTH 16 | |
| 38 | `define BADREAD BADBADD | |
| 39 | ||
| 40 | ||
| 41 | ||
| 42 | module n2_l2t_quad ( | |
| 43 | vnw_ary, | |
| 44 | scan_in, | |
| 45 | scan_out, | |
| 46 | arst_l, | |
| 47 | din, | |
| 48 | index, | |
| 49 | lkup_tag, | |
| 50 | l2clk, | |
| 51 | pce_ov, | |
| 52 | pce_out, | |
| 53 | pce_din, | |
| 54 | pce_ctl, | |
| 55 | rd_en_a, | |
| 56 | red_d_in, | |
| 57 | red_en_in, | |
| 58 | red_wen, | |
| 59 | rid_in, | |
| 60 | tcu_aclk, | |
| 61 | tcu_bclk, | |
| 62 | se_inff, | |
| 63 | se_outff, | |
| 64 | scan_en, | |
| 65 | way, | |
| 66 | wr_en_a, | |
| 67 | wr_inhibit_a, | |
| 68 | req_d_quad, | |
| 69 | req_en_quad, | |
| 70 | tag_way0, | |
| 71 | tag_way1, | |
| 72 | tag_way2, | |
| 73 | tag_way3, | |
| 74 | way_hit); | |
| 75 | wire l1clk_din0; | |
| 76 | wire l1clk_din1; | |
| 77 | wire l1clk_in; | |
| 78 | wire se_unused; | |
| 79 | wire siclk; | |
| 80 | wire soclk; | |
| 81 | wire clk_stop; | |
| 82 | wire [4:0] reg_d1; | |
| 83 | wire [4:0] reg_d0; | |
| 84 | wire [1:0] reg_en1; | |
| 85 | wire [1:0] reg_en0; | |
| 86 | wire [27:0] tag_way0_0; | |
| 87 | wire [27:0] tag_way1_0; | |
| 88 | wire [27:0] tag_way0_1; | |
| 89 | wire [27:0] tag_way1_1; | |
| 90 | wire [1:0] way_hit_a1; | |
| 91 | wire [1:0] way_hit_a0; | |
| 92 | wire [8:0] index_a; | |
| 93 | wire [1:0] way_a0; | |
| 94 | wire [1:0] way_a1; | |
| 95 | wire [4:0] reg_d_in; | |
| 96 | wire [1:0] reg_en_in; | |
| 97 | wire not_quad_active; | |
| 98 | wire quad_active_unused; | |
| 99 | wire not_arst_l; | |
| 100 | wire [1:0] not_rid_in; | |
| 101 | wire rid_rgt1; | |
| 102 | wire rid_rgt0; | |
| 103 | wire rid_lft1; | |
| 104 | wire rid_lft0; | |
| 105 | wire rid_rgt1_wen; | |
| 106 | wire reg_wen_rgt1; | |
| 107 | wire rid_rgt0_wen; | |
| 108 | wire reg_wen_rgt0; | |
| 109 | wire rid_lft1_wen; | |
| 110 | wire reg_wen_lft1; | |
| 111 | wire rid_lft0_wen; | |
| 112 | wire reg_wen_lft0; | |
| 113 | wire bank0_scanout; | |
| 114 | wire bank0_scanin; | |
| 115 | wire [27:0] din_r; | |
| 116 | wire bank1_scanout; | |
| 117 | wire bank1_scanin; | |
| 118 | wire reg_din_27_scanin; | |
| 119 | wire reg_din_27_scanout; | |
| 120 | wire reg_din_26_scanin; | |
| 121 | wire reg_din_26_scanout; | |
| 122 | wire reg_din_25_scanin; | |
| 123 | wire reg_din_25_scanout; | |
| 124 | wire reg_din_24_scanin; | |
| 125 | wire reg_din_24_scanout; | |
| 126 | wire reg_din_23_scanin; | |
| 127 | wire reg_din_23_scanout; | |
| 128 | wire reg_din_22_scanin; | |
| 129 | wire reg_din_22_scanout; | |
| 130 | wire reg_din_21_scanin; | |
| 131 | wire reg_din_21_scanout; | |
| 132 | wire reg_din_20_scanin; | |
| 133 | wire reg_din_20_scanout; | |
| 134 | wire reg_din_19_scanin; | |
| 135 | wire reg_din_19_scanout; | |
| 136 | wire reg_din_18_scanin; | |
| 137 | wire reg_din_18_scanout; | |
| 138 | wire reg_din_17_scanin; | |
| 139 | wire reg_din_17_scanout; | |
| 140 | wire reg_din_16_scanin; | |
| 141 | wire reg_din_16_scanout; | |
| 142 | wire reg_din_15_scanin; | |
| 143 | wire reg_din_15_scanout; | |
| 144 | wire reg_din_14_scanin; | |
| 145 | wire reg_din_14_scanout; | |
| 146 | wire reg_din_13_scanin; | |
| 147 | wire reg_din_13_scanout; | |
| 148 | wire reg_din_12_scanin; | |
| 149 | wire reg_din_12_scanout; | |
| 150 | wire reg_din_11_scanin; | |
| 151 | wire reg_din_11_scanout; | |
| 152 | wire reg_din_10_scanin; | |
| 153 | wire reg_din_10_scanout; | |
| 154 | wire reg_din_9_scanin; | |
| 155 | wire reg_din_9_scanout; | |
| 156 | wire reg_din_8_scanin; | |
| 157 | wire reg_din_8_scanout; | |
| 158 | wire reg_din_7_scanin; | |
| 159 | wire reg_din_7_scanout; | |
| 160 | wire reg_din_6_scanin; | |
| 161 | wire reg_din_6_scanout; | |
| 162 | wire reg_din_5_scanin; | |
| 163 | wire reg_din_5_scanout; | |
| 164 | wire reg_din_4_scanin; | |
| 165 | wire reg_din_4_scanout; | |
| 166 | wire reg_din_3_scanin; | |
| 167 | wire reg_din_3_scanout; | |
| 168 | wire reg_din_2_scanin; | |
| 169 | wire reg_din_2_scanout; | |
| 170 | wire reg_din_1_scanin; | |
| 171 | wire reg_din_1_scanout; | |
| 172 | wire reg_din_0_scanin; | |
| 173 | wire reg_din_0_scanout; | |
| 174 | ||
| 175 | ||
| 176 | input vnw_ary; | |
| 177 | input scan_in; | |
| 178 | output scan_out; | |
| 179 | ||
| 180 | input arst_l; | |
| 181 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
| 182 | input [8:0] index; | |
| 183 | input [`L2T_ARR_D_WIDTH - 1:1] lkup_tag; | |
| 184 | input l2clk; | |
| 185 | input pce_ov; | |
| 186 | input pce_out; | |
| 187 | input pce_din; | |
| 188 | input pce_ctl; | |
| 189 | input rd_en_a; | |
| 190 | input [4:0] red_d_in; | |
| 191 | input [1:0] red_en_in; | |
| 192 | input red_wen; | |
| 193 | input [3:0] rid_in; | |
| 194 | input tcu_aclk; | |
| 195 | input tcu_bclk; | |
| 196 | input se_inff; | |
| 197 | input se_outff; | |
| 198 | input scan_en; | |
| 199 | input [3:0] way; | |
| 200 | input wr_en_a; | |
| 201 | input wr_inhibit_a; | |
| 202 | ||
| 203 | output [4:0] req_d_quad; | |
| 204 | output [1:0] req_en_quad; | |
| 205 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way0; | |
| 206 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way1; | |
| 207 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way2; | |
| 208 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way3; | |
| 209 | output [3:0] way_hit; | |
| 210 | ||
| 211 | ///////////////////////////////////////// | |
| 212 | // Clock Header // | |
| 213 | ///////////////////////////////////////// | |
| 214 | ||
| 215 | // Clk. header for data input flops | |
| 216 | //cl_sc1_l1hdr_48x clk_hdr_din ( | |
| 217 | // .l2clk (l2clk), | |
| 218 | // .pce (pce_din), | |
| 219 | // .pce_ov (pce_ov), | |
| 220 | // .stop (1'b0), | |
| 221 | // .l1clk (l1clk_din), | |
| 222 | // .se (se_inff) | |
| 223 | // ); | |
| 224 | ||
| 225 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_din0 ( | |
| 226 | .l2clk (l2clk), | |
| 227 | .l1en (pce_din), | |
| 228 | .pce_ov (pce_ov), | |
| 229 | .stop (1'b0), | |
| 230 | .l1clk (l1clk_din0), | |
| 231 | .se (se_inff) | |
| 232 | ); | |
| 233 | ||
| 234 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_din1 ( | |
| 235 | .l2clk (l2clk), | |
| 236 | .l1en (pce_din), | |
| 237 | .pce_ov (pce_ov), | |
| 238 | .stop (1'b0), | |
| 239 | .l1clk (l1clk_din1), | |
| 240 | .se (se_inff) | |
| 241 | ); | |
| 242 | ||
| 243 | ||
| 244 | ||
| 245 | // Clk. header for control input flops | |
| 246 | //cl_sc1_l1hdr_32x clk_hdr_ctl ( | |
| 247 | // .l2clk (l2clk), | |
| 248 | // .pce (pce_ctl), | |
| 249 | // .pce_ov (pce_ov), | |
| 250 | // .stop (1'b0), | |
| 251 | // .l1clk (l1clk_in), | |
| 252 | // .se (se_inff) | |
| 253 | // ); | |
| 254 | ||
| 255 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_ctl ( | |
| 256 | .l2clk (l2clk), | |
| 257 | .l1en (pce_ctl), | |
| 258 | .pce_ov (pce_ov), | |
| 259 | .stop (1'b0), | |
| 260 | .l1clk (l1clk_in), | |
| 261 | .se (se_inff) | |
| 262 | ); | |
| 263 | ||
| 264 | assign se_unused = se_inff; | |
| 265 | assign siclk = tcu_aclk; | |
| 266 | assign soclk = tcu_bclk; | |
| 267 | assign clk_stop = 1'b0; | |
| 268 | ||
| 269 | ||
| 270 | //--------------------------------------- | |
| 271 | // output signals | |
| 272 | //--------------------------------------- | |
| 273 | // reg_d1/reg_en0 are from top quad. reg_d0/reg_en0 are from bottom quad. | |
| 274 | ||
| 275 | //assign req_d_quad[4:0] = (reg_d1[4:0] | reg_d0[4:0]); | |
| 276 | //assign req_en_quad[1:0] = (reg_en1[1:0] | reg_en0[1:0]); | |
| 277 | ||
| 278 | //Change to structural coding CC | |
| 279 | //assign req_d_quad[4] = (reg_d1[4] | reg_d0[4]); | |
| 280 | //assign req_d_quad[3] = (reg_d1[3] | reg_d0[3]); | |
| 281 | //assign req_d_quad[2] = (reg_d1[2] | reg_d0[2]); | |
| 282 | //assign req_d_quad[1] = (reg_d1[1] | reg_d0[1]); | |
| 283 | //assign req_d_quad[0] = (reg_d1[0] | reg_d0[0]); | |
| 284 | ||
| 285 | n2_l2t_quad_or_macro__ports_2__width_5 or_req_d_quad | |
| 286 | ( | |
| 287 | .din0 (reg_d1[4:0]), | |
| 288 | .din1 (reg_d0[4:0]), | |
| 289 | .dout (req_d_quad[4:0]) | |
| 290 | ); | |
| 291 | ||
| 292 | //assign req_en_quad[1] = (reg_en1[1] | reg_en0[1]); | |
| 293 | //assign req_en_quad[0] = (reg_en1[0] | reg_en0[0]); | |
| 294 | ||
| 295 | n2_l2t_quad_or_macro__ports_2__width_2 or_req_en_quad | |
| 296 | ( | |
| 297 | .din0 (reg_en1[1:0]), | |
| 298 | .din1 (reg_en0[1:0]), | |
| 299 | .dout (req_en_quad[1:0]) | |
| 300 | ); | |
| 301 | ||
| 302 | assign tag_way0[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_0[`L2T_ARR_D_WIDTH - 1:0]; | |
| 303 | assign tag_way2[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_0[`L2T_ARR_D_WIDTH - 1:0]; | |
| 304 | assign tag_way1[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_1[`L2T_ARR_D_WIDTH - 1:0]; | |
| 305 | assign tag_way3[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_1[`L2T_ARR_D_WIDTH - 1:0]; | |
| 306 | ||
| 307 | assign way_hit[3] = way_hit_a1[1]; | |
| 308 | assign way_hit[2] = way_hit_a0[1]; | |
| 309 | assign way_hit[1] = way_hit_a1[0]; | |
| 310 | assign way_hit[0] = way_hit_a0[0]; | |
| 311 | //--------------------------------------- | |
| 312 | // internal signals | |
| 313 | //--------------------------------------- | |
| 314 | ||
| 315 | assign index_a[8:0] = index[8:0]; | |
| 316 | ||
| 317 | assign way_a0[1:0] = {way[2], way[0]}; | |
| 318 | assign way_a1[1:0] = {way[3], way[1]}; | |
| 319 | ||
| 320 | //assign reg_d_in[4:0] = {arst_l, arst_l, arst_l, arst_l, arst_l} & red_d_in[4:0]; | |
| 321 | n2_l2t_quad_and_macro__ports_2__width_5 and_reg_d_in | |
| 322 | ( | |
| 323 | .din0 ({arst_l,arst_l, arst_l, arst_l, arst_l}), | |
| 324 | .din1 (red_d_in[4:0]), | |
| 325 | .dout (reg_d_in[4:0]) | |
| 326 | ); | |
| 327 | ||
| 328 | //assign reg_en_in[1:0] = {arst_l, arst_l} & red_en_in[1:0]; | |
| 329 | n2_l2t_quad_and_macro__ports_2__width_2 and_reg_en_in | |
| 330 | ( | |
| 331 | .din0 ({arst_l,arst_l}), | |
| 332 | .din1 (red_en_in[1:0]), | |
| 333 | .dout (reg_en_in[1:0]) | |
| 334 | ); | |
| 335 | ||
| 336 | // rid_in<3:2> selects one of four quads, and rid_in<1:0> selects one of | |
| 337 | // four arrays in a quad. | |
| 338 | ||
| 339 | //assign quad_active = ~(rid_in[3] && rid_in[2]) ; | |
| 340 | n2_l2t_quad_and_macro__ports_2__width_1 and_quad_active | |
| 341 | ( | |
| 342 | .din0 (rid_in[3]), | |
| 343 | .din1 (rid_in[2]), | |
| 344 | .dout (not_quad_active) | |
| 345 | ); | |
| 346 | ||
| 347 | n2_l2t_quad_inv_macro__width_1 inv_quad_active | |
| 348 | ( | |
| 349 | .din(not_quad_active), | |
| 350 | .dout(quad_active_unused) | |
| 351 | ); | |
| 352 | ||
| 353 | // Bank0 (bottom bank) | |
| 354 | //assign reg_wen_lft0 = quad_active && (rid_in[1:0] == 2'b00) ? red_wen : 1'b0 ; | |
| 355 | //assign reg_wen_rgt0 = quad_active && (rid_in[1:0] == 2'b01) ? red_wen : 1'b0 ; | |
| 356 | //assign rid_rgt0 = quad_active && (rid_in[1:0] == 2'b01) ? 1'b1 : 1'b0; | |
| 357 | //assign rid_lft0 = quad_active && (rid_in[1:0] == 2'b00) ? 1'b1 : 1'b0; | |
| 358 | // Bank1 (top bank) | |
| 359 | //assign reg_wen_lft1 = quad_active && (rid_in[1:0] == 2'b10) ? red_wen : 1'b0 ; | |
| 360 | //assign reg_wen_rgt1 = quad_active && (rid_in[1:0] == 2'b11) ? red_wen : 1'b0 ; | |
| 361 | //assign rid_rgt1 = quad_active && (rid_in[1:0] == 2'b11) ? 1'b1 : 1'b0; | |
| 362 | //assign rid_lft1 = quad_active && (rid_in[1:0] == 2'b10) ? 1'b1 : 1'b0; | |
| 363 | ||
| 364 | // rid_in<1:0> selects one of four arrays : | |
| 365 | // rid_in<1:0> = 11 => top, right array | |
| 366 | // rid_in<1:0> = 10 => top, left array | |
| 367 | // rid_in<1:0> = 01 => bot, right array | |
| 368 | // rid_in<1:0> = 00 => bot, left array | |
| 369 | ||
| 370 | // Change to structural CC | |
| 371 | //assign rid_rgt1 = !quad_active && ( (rid_in[1]) && ( rid_in[0])); | |
| 372 | //assign rid_lft1 = !quad_active && ( (rid_in[1]) && (!rid_in[0])); | |
| 373 | //assign rid_rgt0 = !quad_active && (!(rid_in[1]) && ( rid_in[0])); | |
| 374 | //assign rid_lft0 = !quad_active && (!(rid_in[1]) && (!rid_in[0])); | |
| 375 | ||
| 376 | ||
| 377 | n2_l2t_quad_inv_macro__width_1 inv_arst_l | |
| 378 | ( | |
| 379 | .din (arst_l), | |
| 380 | .dout (not_arst_l) | |
| 381 | ); | |
| 382 | ||
| 383 | n2_l2t_quad_inv_macro__width_2 inv_rid_in | |
| 384 | ( | |
| 385 | .din (rid_in[1:0]), | |
| 386 | .dout (not_rid_in[1:0]) | |
| 387 | ); | |
| 388 | ||
| 389 | n2_l2t_quad_and_macro__ports_3__width_1 and_rid_rgt1 | |
| 390 | ( | |
| 391 | .din0 (not_quad_active), | |
| 392 | .din1 (rid_in[0]), | |
| 393 | .din2 (rid_in[1]), | |
| 394 | .dout (rid_rgt1) | |
| 395 | ); | |
| 396 | ||
| 397 | n2_l2t_quad_and_macro__ports_3__width_1 and_rid_rgt0 | |
| 398 | ( | |
| 399 | .din0 (not_quad_active), | |
| 400 | .din1 (rid_in[0]), | |
| 401 | .din2 (not_rid_in[1]), | |
| 402 | .dout (rid_rgt0) | |
| 403 | ); | |
| 404 | ||
| 405 | n2_l2t_quad_and_macro__ports_3__width_1 and_rid_lft1 | |
| 406 | ( | |
| 407 | .din0 (not_quad_active), | |
| 408 | .din1 (not_rid_in[0]), | |
| 409 | .din2 (rid_in[1]), | |
| 410 | .dout (rid_lft1) | |
| 411 | ); | |
| 412 | ||
| 413 | n2_l2t_quad_and_macro__ports_3__width_1 and_rid_lft0 | |
| 414 | ( | |
| 415 | .din0 (not_quad_active), | |
| 416 | .din1 (not_rid_in[0]), | |
| 417 | .din2 (not_rid_in[1]), | |
| 418 | .dout (rid_lft0) | |
| 419 | ); | |
| 420 | ||
| 421 | //assign reg_wen_rgt1 = !arst_l || (rid_rgt1 && red_wen); | |
| 422 | //assign reg_wen_lft1 = !arst_l || (rid_lft1 && red_wen); | |
| 423 | //assign reg_wen_rgt0 = !arst_l || (rid_rgt0 && red_wen); | |
| 424 | //assign reg_wen_lft0 = !arst_l || (rid_lft0 && red_wen); | |
| 425 | ||
| 426 | n2_l2t_quad_or_macro__ports_2__width_1 or_reg_wen_rgt1 | |
| 427 | ( | |
| 428 | .din0 (rid_rgt1_wen), | |
| 429 | .din1 (not_arst_l), | |
| 430 | .dout (reg_wen_rgt1) | |
| 431 | ); | |
| 432 | ||
| 433 | n2_l2t_quad_or_macro__ports_2__width_1 or_reg_wen_rgt0 | |
| 434 | ( | |
| 435 | .din0 (rid_rgt0_wen), | |
| 436 | .din1 (not_arst_l), | |
| 437 | .dout (reg_wen_rgt0) | |
| 438 | ); | |
| 439 | ||
| 440 | n2_l2t_quad_or_macro__ports_2__width_1 or_reg_wen_lft1 | |
| 441 | ( | |
| 442 | .din0 (rid_lft1_wen), | |
| 443 | .din1 (not_arst_l), | |
| 444 | .dout (reg_wen_lft1) | |
| 445 | ); | |
| 446 | ||
| 447 | n2_l2t_quad_or_macro__ports_2__width_1 or_reg_wen_lft0 | |
| 448 | ( | |
| 449 | .din0 (rid_lft0_wen), | |
| 450 | .din1 (not_arst_l), | |
| 451 | .dout (reg_wen_lft0) | |
| 452 | ); | |
| 453 | ||
| 454 | n2_l2t_quad_and_macro__ports_2__width_1 and_rid_rgt1_wen | |
| 455 | ( | |
| 456 | .din0 (rid_rgt1), | |
| 457 | .din1 (red_wen), | |
| 458 | .dout (rid_rgt1_wen) | |
| 459 | ); | |
| 460 | ||
| 461 | n2_l2t_quad_and_macro__ports_2__width_1 and_rid_rgt0_wen | |
| 462 | ( | |
| 463 | .din0 (rid_rgt0), | |
| 464 | .din1 (red_wen), | |
| 465 | .dout (rid_rgt0_wen) | |
| 466 | ); | |
| 467 | ||
| 468 | n2_l2t_quad_and_macro__ports_2__width_1 and_rid_lft1_wen | |
| 469 | ( | |
| 470 | .din0 (rid_lft1), | |
| 471 | .din1 (red_wen), | |
| 472 | .dout (rid_lft1_wen) | |
| 473 | ); | |
| 474 | ||
| 475 | n2_l2t_quad_and_macro__ports_2__width_1 and_rid_lft0_wen | |
| 476 | ( | |
| 477 | .din0 (rid_lft0), | |
| 478 | .din1 (red_wen), | |
| 479 | .dout (rid_lft0_wen) | |
| 480 | ); | |
| 481 | ||
| 482 | ||
| 483 | //--------------------------------------- | |
| 484 | // L2T BANKS INSTANTIATION | |
| 485 | //--------------------------------------- | |
| 486 | ||
| 487 | n2_l2t_bank bank0( /*AUTOINST*/ | |
| 488 | // Outputs | |
| 489 | .scan_out (bank0_scanout), // Templated | |
| 490 | .reg_d (reg_d0[4:0]), // Templated | |
| 491 | .reg_en (reg_en0[1:0]), // Templated | |
| 492 | .tag_way0 (tag_way0_0[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
| 493 | .tag_way1 (tag_way1_0[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
| 494 | .way_hit_a (way_hit_a0[1:0]), // Templated | |
| 495 | // Inputs | |
| 496 | .vnw_ary (vnw_ary), | |
| 497 | .l1clk_in (l1clk_in), | |
| 498 | .scan_in (bank0_scanin), // Templated | |
| 499 | .clk_stop (clk_stop), | |
| 500 | .se_outff (se_outff), | |
| 501 | .scan_en (scan_en), | |
| 502 | .din (din_r[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
| 503 | .index_a (index_a[8:0]), | |
| 504 | .l2clk (l2clk), | |
| 505 | .lkuptag_d1 (lkup_tag[`L2T_ARR_D_WIDTH-1:1]), // Templated | |
| 506 | .pce_out (pce_out), | |
| 507 | .pce_ctl (pce_ctl), | |
| 508 | .pce_ov (pce_ov), | |
| 509 | .rd_en_a (rd_en_a), | |
| 510 | .reg_d_in (reg_d_in[4:0]), | |
| 511 | .reg_en_in (reg_en_in[1:0]), | |
| 512 | .reg_wen_lft (reg_wen_lft0), // Templated | |
| 513 | .reg_wen_rgt (reg_wen_rgt0), // Templated | |
| 514 | .rid_lft (rid_lft0), // Templated | |
| 515 | .rid_rgt (rid_rgt0), // Templated | |
| 516 | .tcu_aclk (tcu_aclk), | |
| 517 | .tcu_bclk (tcu_bclk), | |
| 518 | .way_a (way_a0[1:0]), // Templated | |
| 519 | .wr_en_a (wr_en_a), | |
| 520 | .wr_inhibit_a (wr_inhibit_a)); | |
| 521 | ||
| 522 | n2_l2t_bank bank1( /*AUTOINST*/ | |
| 523 | // Outputs | |
| 524 | .scan_out (bank1_scanout), // Templated | |
| 525 | .reg_d (reg_d1[4:0]), // Templated | |
| 526 | .reg_en (reg_en1[1:0]), // Templated | |
| 527 | .tag_way0 (tag_way0_1[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
| 528 | .tag_way1 (tag_way1_1[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
| 529 | .way_hit_a (way_hit_a1[1:0]), // Templated | |
| 530 | // Inputs | |
| 531 | .vnw_ary (vnw_ary), | |
| 532 | .l1clk_in (l1clk_in), | |
| 533 | .scan_in (bank1_scanin), // Templated | |
| 534 | .clk_stop (clk_stop), | |
| 535 | .se_outff (se_outff), | |
| 536 | .scan_en (scan_en), | |
| 537 | .din (din_r[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
| 538 | .index_a (index_a[8:0]), | |
| 539 | .l2clk (l2clk), | |
| 540 | .lkuptag_d1 (lkup_tag[`L2T_ARR_D_WIDTH-1:1]), // Templated | |
| 541 | .pce_out (pce_out), | |
| 542 | .pce_ctl (pce_ctl), | |
| 543 | .pce_ov (pce_ov), | |
| 544 | .rd_en_a (rd_en_a), | |
| 545 | .reg_d_in (reg_d_in[4:0]), | |
| 546 | .reg_en_in (reg_en_in[1:0]), | |
| 547 | .reg_wen_lft (reg_wen_lft1), // Templated | |
| 548 | .reg_wen_rgt (reg_wen_rgt1), // Templated | |
| 549 | .rid_lft (rid_lft1), // Templated | |
| 550 | .rid_rgt (rid_rgt1), // Templated | |
| 551 | .tcu_aclk (tcu_aclk), | |
| 552 | .tcu_bclk (tcu_bclk), | |
| 553 | .way_a (way_a1[1:0]), // Templated | |
| 554 | .wr_en_a (wr_en_a), | |
| 555 | .wr_inhibit_a (wr_inhibit_a)); | |
| 556 | //************************************************************************ | |
| 557 | // REGISTERS SECTION | |
| 558 | //************************************************************************ | |
| 559 | ||
| 560 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_27 (.scan_in(reg_din_27_scanin), .scan_out(reg_din_27_scanout), | |
| 561 | .dout(din_r[27]), .l1clk(l1clk_din0), .din(din[27]), | |
| 562 | .siclk(siclk), | |
| 563 | .soclk(soclk)); | |
| 564 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_26 (.scan_in(reg_din_26_scanin), .scan_out(reg_din_26_scanout), | |
| 565 | .dout(din_r[26]), .l1clk(l1clk_din0), .din(din[26]), | |
| 566 | .siclk(siclk), | |
| 567 | .soclk(soclk)); | |
| 568 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_25 (.scan_in(reg_din_25_scanin), .scan_out(reg_din_25_scanout), | |
| 569 | .dout(din_r[25]), .l1clk(l1clk_din0), .din(din[25]), | |
| 570 | .siclk(siclk), | |
| 571 | .soclk(soclk)); | |
| 572 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_24 (.scan_in(reg_din_24_scanin), .scan_out(reg_din_24_scanout), | |
| 573 | .dout(din_r[24]), .l1clk(l1clk_din0), .din(din[24]), | |
| 574 | .siclk(siclk), | |
| 575 | .soclk(soclk)); | |
| 576 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_23 (.scan_in(reg_din_23_scanin), .scan_out(reg_din_23_scanout), | |
| 577 | .dout(din_r[23]), .l1clk(l1clk_din0), .din(din[23]), | |
| 578 | .siclk(siclk), | |
| 579 | .soclk(soclk)); | |
| 580 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_22 (.scan_in(reg_din_22_scanin), .scan_out(reg_din_22_scanout), | |
| 581 | .dout(din_r[22]), .l1clk(l1clk_din0), .din(din[22]), | |
| 582 | .siclk(siclk), | |
| 583 | .soclk(soclk)); | |
| 584 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_21 (.scan_in(reg_din_21_scanin), .scan_out(reg_din_21_scanout), | |
| 585 | .dout(din_r[21]), .l1clk(l1clk_din0), .din(din[21]), | |
| 586 | .siclk(siclk), | |
| 587 | .soclk(soclk)); | |
| 588 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_20 (.scan_in(reg_din_20_scanin), .scan_out(reg_din_20_scanout), | |
| 589 | .dout(din_r[20]), .l1clk(l1clk_din0), .din(din[20]), | |
| 590 | .siclk(siclk), | |
| 591 | .soclk(soclk)); | |
| 592 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_19 (.scan_in(reg_din_19_scanin), .scan_out(reg_din_19_scanout), | |
| 593 | .dout(din_r[19]), .l1clk(l1clk_din0), .din(din[19]), | |
| 594 | .siclk(siclk), | |
| 595 | .soclk(soclk)); | |
| 596 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_18 (.scan_in(reg_din_18_scanin), .scan_out(reg_din_18_scanout), | |
| 597 | .dout(din_r[18]), .l1clk(l1clk_din0), .din(din[18]), | |
| 598 | .siclk(siclk), | |
| 599 | .soclk(soclk)); | |
| 600 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_17 (.scan_in(reg_din_17_scanin), .scan_out(reg_din_17_scanout), | |
| 601 | .dout(din_r[17]), .l1clk(l1clk_din0), .din(din[17]), | |
| 602 | .siclk(siclk), | |
| 603 | .soclk(soclk)); | |
| 604 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_16 (.scan_in(reg_din_16_scanin), .scan_out(reg_din_16_scanout), | |
| 605 | .dout(din_r[16]), .l1clk(l1clk_din0), .din(din[16]), | |
| 606 | .siclk(siclk), | |
| 607 | .soclk(soclk)); | |
| 608 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_15 (.scan_in(reg_din_15_scanin), .scan_out(reg_din_15_scanout), | |
| 609 | .dout(din_r[15]), .l1clk(l1clk_din0), .din(din[15]), | |
| 610 | .siclk(siclk), | |
| 611 | .soclk(soclk)); | |
| 612 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_14 (.scan_in(reg_din_14_scanin), .scan_out(reg_din_14_scanout), | |
| 613 | .dout(din_r[14]), .l1clk(l1clk_din0), .din(din[14]), | |
| 614 | .siclk(siclk), | |
| 615 | .soclk(soclk)); | |
| 616 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_13 (.scan_in(reg_din_13_scanin), .scan_out(reg_din_13_scanout), | |
| 617 | .dout(din_r[13]), .l1clk(l1clk_din0), .din(din[13]), | |
| 618 | .siclk(siclk), | |
| 619 | .soclk(soclk)); | |
| 620 | ||
| 621 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_12 (.scan_in(reg_din_12_scanin), .scan_out(reg_din_12_scanout), | |
| 622 | .dout(din_r[12]), .l1clk(l1clk_din1), .din(din[12]), | |
| 623 | .siclk(siclk), | |
| 624 | .soclk(soclk)); | |
| 625 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_11 (.scan_in(reg_din_11_scanin), .scan_out(reg_din_11_scanout), | |
| 626 | .dout(din_r[11]), .l1clk(l1clk_din1), .din(din[11]), | |
| 627 | .siclk(siclk), | |
| 628 | .soclk(soclk)); | |
| 629 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_10 (.scan_in(reg_din_10_scanin), .scan_out(reg_din_10_scanout), | |
| 630 | .dout(din_r[10]), .l1clk(l1clk_din1), .din(din[10]), | |
| 631 | .siclk(siclk), | |
| 632 | .soclk(soclk)); | |
| 633 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_9 (.scan_in(reg_din_9_scanin), .scan_out(reg_din_9_scanout), | |
| 634 | .dout(din_r[9]), .l1clk(l1clk_din1), .din(din[9]), | |
| 635 | .siclk(siclk), | |
| 636 | .soclk(soclk)); | |
| 637 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_8 (.scan_in(reg_din_8_scanin), .scan_out(reg_din_8_scanout), | |
| 638 | .dout(din_r[8]), .l1clk(l1clk_din1), .din(din[8]), | |
| 639 | .siclk(siclk), | |
| 640 | .soclk(soclk)); | |
| 641 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_7 (.scan_in(reg_din_7_scanin), .scan_out(reg_din_7_scanout), | |
| 642 | .dout(din_r[7]), .l1clk(l1clk_din1), .din(din[7]), | |
| 643 | .siclk(siclk), | |
| 644 | .soclk(soclk)); | |
| 645 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_6 (.scan_in(reg_din_6_scanin), .scan_out(reg_din_6_scanout), | |
| 646 | .dout(din_r[6]), .l1clk(l1clk_din1), .din(din[6]), | |
| 647 | .siclk(siclk), | |
| 648 | .soclk(soclk)); | |
| 649 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_5 (.scan_in(reg_din_5_scanin), .scan_out(reg_din_5_scanout), | |
| 650 | .dout(din_r[5]), .l1clk(l1clk_din1), .din(din[5]), | |
| 651 | .siclk(siclk), | |
| 652 | .soclk(soclk)); | |
| 653 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_4 (.scan_in(reg_din_4_scanin), .scan_out(reg_din_4_scanout), | |
| 654 | .dout(din_r[4]), .l1clk(l1clk_din1), .din(din[4]), | |
| 655 | .siclk(siclk), | |
| 656 | .soclk(soclk)); | |
| 657 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_3 (.scan_in(reg_din_3_scanin), .scan_out(reg_din_3_scanout), | |
| 658 | .dout(din_r[3]), .l1clk(l1clk_din1), .din(din[3]), | |
| 659 | .siclk(siclk), | |
| 660 | .soclk(soclk)); | |
| 661 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_2 (.scan_in(reg_din_2_scanin), .scan_out(reg_din_2_scanout), | |
| 662 | .dout(din_r[2]), .l1clk(l1clk_din1), .din(din[2]), | |
| 663 | .siclk(siclk), | |
| 664 | .soclk(soclk)); | |
| 665 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_1 (.scan_in(reg_din_1_scanin), .scan_out(reg_din_1_scanout), | |
| 666 | .dout(din_r[1]), .l1clk(l1clk_din1), .din(din[1]), | |
| 667 | .siclk(siclk), | |
| 668 | .soclk(soclk)); | |
| 669 | n2_l2t_quad_msff_ctl_macro__width_1 reg_din_0 (.scan_in(reg_din_0_scanin), .scan_out(reg_din_0_scanout), | |
| 670 | .dout(din_r[0]), .l1clk(l1clk_din1), .din(din[0]), | |
| 671 | .siclk(siclk), | |
| 672 | .soclk(soclk)); | |
| 673 | ||
| 674 | // =============== VERILOG-MODE AUTO TEMPLATES | |
| 675 | ||
| 676 | /* | |
| 677 | ||
| 678 | n2_l2t_bank AUTO_TEMPLATE ( | |
| 679 | .din(din_r[`L2T_ARR_D_WIDTH - 1 : 0]), | |
| 680 | .reg_wen_lft (reg_wen_lft@), | |
| 681 | .reg_wen_rgt (reg_wen_rgt@), | |
| 682 | .rid_lft (rid_lft@), | |
| 683 | .rid_rgt (rid_rgt@), | |
| 684 | .way_a (way_a@[1:0]), | |
| 685 | .tcu_pce_ov(pce_ov), | |
| 686 | .lkuptag_d1(lkup_tag[`L2T_ARR_D_WIDTH-1:1]), | |
| 687 | .reg_d(reg_d@[4:0]), | |
| 688 | .reg_en(reg_en@[1:0]), | |
| 689 | .tag_way0(tag_way0_@[`L2T_ARR_D_WIDTH - 1:0]), | |
| 690 | .tag_way1(tag_way1_@[`L2T_ARR_D_WIDTH - 1:0]), | |
| 691 | .way_hit_a (way_hit_a@[1:0]), | |
| 692 | .scan_out (bank@_scanout), | |
| 693 | .scan_in (bank@_scanin), | |
| 694 | ); | |
| 695 | ||
| 696 | */ | |
| 697 | ||
| 698 | // Manual scan section | |
| 699 | assign bank1_scanin = scan_in ; | |
| 700 | ||
| 701 | assign reg_din_0_scanin = bank1_scanout ; | |
| 702 | assign reg_din_1_scanin = reg_din_0_scanout ; | |
| 703 | assign reg_din_2_scanin = reg_din_1_scanout ; | |
| 704 | assign reg_din_3_scanin = reg_din_2_scanout ; | |
| 705 | assign reg_din_4_scanin = reg_din_3_scanout ; | |
| 706 | assign reg_din_5_scanin = reg_din_4_scanout ; | |
| 707 | assign reg_din_6_scanin = reg_din_5_scanout ; | |
| 708 | assign reg_din_7_scanin = reg_din_6_scanout ; | |
| 709 | assign reg_din_8_scanin = reg_din_7_scanout ; | |
| 710 | assign reg_din_9_scanin = reg_din_8_scanout ; | |
| 711 | assign reg_din_10_scanin = reg_din_9_scanout ; | |
| 712 | assign reg_din_11_scanin = reg_din_10_scanout ; | |
| 713 | assign reg_din_12_scanin = reg_din_11_scanout ; | |
| 714 | assign reg_din_13_scanin = reg_din_12_scanout ; | |
| 715 | assign reg_din_14_scanin = reg_din_13_scanout ; | |
| 716 | assign reg_din_15_scanin = reg_din_14_scanout ; | |
| 717 | assign reg_din_16_scanin = reg_din_15_scanout ; | |
| 718 | assign reg_din_17_scanin = reg_din_16_scanout ; | |
| 719 | assign reg_din_18_scanin = reg_din_17_scanout ; | |
| 720 | assign reg_din_19_scanin = reg_din_18_scanout ; | |
| 721 | assign reg_din_20_scanin = reg_din_19_scanout ; | |
| 722 | assign reg_din_21_scanin = reg_din_20_scanout ; | |
| 723 | assign reg_din_22_scanin = reg_din_21_scanout ; | |
| 724 | assign reg_din_23_scanin = reg_din_22_scanout ; | |
| 725 | assign reg_din_24_scanin = reg_din_23_scanout ; | |
| 726 | assign reg_din_25_scanin = reg_din_24_scanout ; | |
| 727 | assign reg_din_26_scanin = reg_din_25_scanout ; | |
| 728 | assign reg_din_27_scanin = reg_din_26_scanout ; | |
| 729 | assign bank0_scanin = reg_din_27_scanout ; | |
| 730 | assign scan_out = bank0_scanout ; | |
| 731 | endmodule | |
| 732 | ||
| 733 | ||
| 734 | ||
| 735 | ||
| 736 | ||
| 737 | ||
| 738 | // any PARAMS parms go into naming of macro | |
| 739 | ||
| 740 | module n2_l2t_quad_l1clkhdr_ctl_macro ( | |
| 741 | l2clk, | |
| 742 | l1en, | |
| 743 | pce_ov, | |
| 744 | stop, | |
| 745 | se, | |
| 746 | l1clk); | |
| 747 | ||
| 748 | ||
| 749 | input l2clk; | |
| 750 | input l1en; | |
| 751 | input pce_ov; | |
| 752 | input stop; | |
| 753 | input se; | |
| 754 | output l1clk; | |
| 755 | ||
| 756 | ||
| 757 | ||
| 758 | ||
| 759 | ||
| 760 | cl_sc1_l1hdr_8x c_0 ( | |
| 761 | ||
| 762 | ||
| 763 | .l2clk(l2clk), | |
| 764 | .pce(l1en), | |
| 765 | .l1clk(l1clk), | |
| 766 | .se(se), | |
| 767 | .pce_ov(pce_ov), | |
| 768 | .stop(stop) | |
| 769 | ); | |
| 770 | ||
| 771 | ||
| 772 | ||
| 773 | endmodule | |
| 774 | ||
| 775 | ||
| 776 | ||
| 777 | ||
| 778 | ||
| 779 | ||
| 780 | ||
| 781 | ||
| 782 | ||
| 783 | // | |
| 784 | // or macro for ports = 2,3 | |
| 785 | // | |
| 786 | // | |
| 787 | ||
| 788 | ||
| 789 | ||
| 790 | ||
| 791 | ||
| 792 | module n2_l2t_quad_or_macro__ports_2__width_5 ( | |
| 793 | din0, | |
| 794 | din1, | |
| 795 | dout); | |
| 796 | input [4:0] din0; | |
| 797 | input [4:0] din1; | |
| 798 | output [4:0] dout; | |
| 799 | ||
| 800 | ||
| 801 | ||
| 802 | ||
| 803 | ||
| 804 | ||
| 805 | or2 #(5) d0_0 ( | |
| 806 | .in0(din0[4:0]), | |
| 807 | .in1(din1[4:0]), | |
| 808 | .out(dout[4:0]) | |
| 809 | ); | |
| 810 | ||
| 811 | ||
| 812 | ||
| 813 | ||
| 814 | ||
| 815 | ||
| 816 | ||
| 817 | ||
| 818 | ||
| 819 | endmodule | |
| 820 | ||
| 821 | ||
| 822 | ||
| 823 | ||
| 824 | ||
| 825 | // | |
| 826 | // or macro for ports = 2,3 | |
| 827 | // | |
| 828 | // | |
| 829 | ||
| 830 | ||
| 831 | ||
| 832 | ||
| 833 | ||
| 834 | module n2_l2t_quad_or_macro__ports_2__width_2 ( | |
| 835 | din0, | |
| 836 | din1, | |
| 837 | dout); | |
| 838 | input [1:0] din0; | |
| 839 | input [1:0] din1; | |
| 840 | output [1:0] dout; | |
| 841 | ||
| 842 | ||
| 843 | ||
| 844 | ||
| 845 | ||
| 846 | ||
| 847 | or2 #(2) d0_0 ( | |
| 848 | .in0(din0[1:0]), | |
| 849 | .in1(din1[1:0]), | |
| 850 | .out(dout[1:0]) | |
| 851 | ); | |
| 852 | ||
| 853 | ||
| 854 | ||
| 855 | ||
| 856 | ||
| 857 | ||
| 858 | ||
| 859 | ||
| 860 | ||
| 861 | endmodule | |
| 862 | ||
| 863 | ||
| 864 | ||
| 865 | ||
| 866 | ||
| 867 | // | |
| 868 | // and macro for ports = 2,3,4 | |
| 869 | // | |
| 870 | // | |
| 871 | ||
| 872 | ||
| 873 | ||
| 874 | ||
| 875 | ||
| 876 | module n2_l2t_quad_and_macro__ports_2__width_5 ( | |
| 877 | din0, | |
| 878 | din1, | |
| 879 | dout); | |
| 880 | input [4:0] din0; | |
| 881 | input [4:0] din1; | |
| 882 | output [4:0] dout; | |
| 883 | ||
| 884 | ||
| 885 | ||
| 886 | ||
| 887 | ||
| 888 | ||
| 889 | and2 #(5) d0_0 ( | |
| 890 | .in0(din0[4:0]), | |
| 891 | .in1(din1[4:0]), | |
| 892 | .out(dout[4:0]) | |
| 893 | ); | |
| 894 | ||
| 895 | ||
| 896 | ||
| 897 | ||
| 898 | ||
| 899 | ||
| 900 | ||
| 901 | ||
| 902 | ||
| 903 | endmodule | |
| 904 | ||
| 905 | ||
| 906 | ||
| 907 | ||
| 908 | ||
| 909 | // | |
| 910 | // and macro for ports = 2,3,4 | |
| 911 | // | |
| 912 | // | |
| 913 | ||
| 914 | ||
| 915 | ||
| 916 | ||
| 917 | ||
| 918 | module n2_l2t_quad_and_macro__ports_2__width_2 ( | |
| 919 | din0, | |
| 920 | din1, | |
| 921 | dout); | |
| 922 | input [1:0] din0; | |
| 923 | input [1:0] din1; | |
| 924 | output [1:0] dout; | |
| 925 | ||
| 926 | ||
| 927 | ||
| 928 | ||
| 929 | ||
| 930 | ||
| 931 | and2 #(2) d0_0 ( | |
| 932 | .in0(din0[1:0]), | |
| 933 | .in1(din1[1:0]), | |
| 934 | .out(dout[1:0]) | |
| 935 | ); | |
| 936 | ||
| 937 | ||
| 938 | ||
| 939 | ||
| 940 | ||
| 941 | ||
| 942 | ||
| 943 | ||
| 944 | ||
| 945 | endmodule | |
| 946 | ||
| 947 | ||
| 948 | ||
| 949 | ||
| 950 | ||
| 951 | // | |
| 952 | // and macro for ports = 2,3,4 | |
| 953 | // | |
| 954 | // | |
| 955 | ||
| 956 | ||
| 957 | ||
| 958 | ||
| 959 | ||
| 960 | module n2_l2t_quad_and_macro__ports_2__width_1 ( | |
| 961 | din0, | |
| 962 | din1, | |
| 963 | dout); | |
| 964 | input [0:0] din0; | |
| 965 | input [0:0] din1; | |
| 966 | output [0:0] dout; | |
| 967 | ||
| 968 | ||
| 969 | ||
| 970 | ||
| 971 | ||
| 972 | ||
| 973 | and2 #(1) d0_0 ( | |
| 974 | .in0(din0[0:0]), | |
| 975 | .in1(din1[0:0]), | |
| 976 | .out(dout[0:0]) | |
| 977 | ); | |
| 978 | ||
| 979 | ||
| 980 | ||
| 981 | ||
| 982 | ||
| 983 | ||
| 984 | ||
| 985 | ||
| 986 | ||
| 987 | endmodule | |
| 988 | ||
| 989 | ||
| 990 | ||
| 991 | ||
| 992 | ||
| 993 | // | |
| 994 | // invert macro | |
| 995 | // | |
| 996 | // | |
| 997 | ||
| 998 | ||
| 999 | ||
| 1000 | ||
| 1001 | ||
| 1002 | module n2_l2t_quad_inv_macro__width_1 ( | |
| 1003 | din, | |
| 1004 | dout); | |
| 1005 | input [0:0] din; | |
| 1006 | output [0:0] dout; | |
| 1007 | ||
| 1008 | ||
| 1009 | ||
| 1010 | ||
| 1011 | ||
| 1012 | ||
| 1013 | inv #(1) d0_0 ( | |
| 1014 | .in(din[0:0]), | |
| 1015 | .out(dout[0:0]) | |
| 1016 | ); | |
| 1017 | ||
| 1018 | ||
| 1019 | ||
| 1020 | ||
| 1021 | ||
| 1022 | ||
| 1023 | ||
| 1024 | ||
| 1025 | ||
| 1026 | endmodule | |
| 1027 | ||
| 1028 | ||
| 1029 | ||
| 1030 | ||
| 1031 | ||
| 1032 | // | |
| 1033 | // invert macro | |
| 1034 | // | |
| 1035 | // | |
| 1036 | ||
| 1037 | ||
| 1038 | ||
| 1039 | ||
| 1040 | ||
| 1041 | module n2_l2t_quad_inv_macro__width_2 ( | |
| 1042 | din, | |
| 1043 | dout); | |
| 1044 | input [1:0] din; | |
| 1045 | output [1:0] dout; | |
| 1046 | ||
| 1047 | ||
| 1048 | ||
| 1049 | ||
| 1050 | ||
| 1051 | ||
| 1052 | inv #(2) d0_0 ( | |
| 1053 | .in(din[1:0]), | |
| 1054 | .out(dout[1:0]) | |
| 1055 | ); | |
| 1056 | ||
| 1057 | ||
| 1058 | ||
| 1059 | ||
| 1060 | ||
| 1061 | ||
| 1062 | ||
| 1063 | ||
| 1064 | ||
| 1065 | endmodule | |
| 1066 | ||
| 1067 | ||
| 1068 | ||
| 1069 | ||
| 1070 | ||
| 1071 | // | |
| 1072 | // and macro for ports = 2,3,4 | |
| 1073 | // | |
| 1074 | // | |
| 1075 | ||
| 1076 | ||
| 1077 | ||
| 1078 | ||
| 1079 | ||
| 1080 | module n2_l2t_quad_and_macro__ports_3__width_1 ( | |
| 1081 | din0, | |
| 1082 | din1, | |
| 1083 | din2, | |
| 1084 | dout); | |
| 1085 | input [0:0] din0; | |
| 1086 | input [0:0] din1; | |
| 1087 | input [0:0] din2; | |
| 1088 | output [0:0] dout; | |
| 1089 | ||
| 1090 | ||
| 1091 | ||
| 1092 | ||
| 1093 | ||
| 1094 | ||
| 1095 | and3 #(1) d0_0 ( | |
| 1096 | .in0(din0[0:0]), | |
| 1097 | .in1(din1[0:0]), | |
| 1098 | .in2(din2[0:0]), | |
| 1099 | .out(dout[0:0]) | |
| 1100 | ); | |
| 1101 | ||
| 1102 | ||
| 1103 | ||
| 1104 | ||
| 1105 | ||
| 1106 | ||
| 1107 | ||
| 1108 | ||
| 1109 | ||
| 1110 | endmodule | |
| 1111 | ||
| 1112 | ||
| 1113 | ||
| 1114 | ||
| 1115 | ||
| 1116 | // | |
| 1117 | // or macro for ports = 2,3 | |
| 1118 | // | |
| 1119 | // | |
| 1120 | ||
| 1121 | ||
| 1122 | ||
| 1123 | ||
| 1124 | ||
| 1125 | module n2_l2t_quad_or_macro__ports_2__width_1 ( | |
| 1126 | din0, | |
| 1127 | din1, | |
| 1128 | dout); | |
| 1129 | input [0:0] din0; | |
| 1130 | input [0:0] din1; | |
| 1131 | output [0:0] dout; | |
| 1132 | ||
| 1133 | ||
| 1134 | ||
| 1135 | ||
| 1136 | ||
| 1137 | ||
| 1138 | or2 #(1) d0_0 ( | |
| 1139 | .in0(din0[0:0]), | |
| 1140 | .in1(din1[0:0]), | |
| 1141 | .out(dout[0:0]) | |
| 1142 | ); | |
| 1143 | ||
| 1144 | ||
| 1145 | ||
| 1146 | ||
| 1147 | ||
| 1148 | ||
| 1149 | ||
| 1150 | ||
| 1151 | ||
| 1152 | endmodule | |
| 1153 | ||
| 1154 | ||
| 1155 | ||
| 1156 | ||
| 1157 | ||
| 1158 | ||
| 1159 | ||
| 1160 | `define L2T_ARR_D_WIDTH 28 | |
| 1161 | `define L2T_ARR_DEPTH 512 | |
| 1162 | `define WAY_HIT_WIDTH 16 | |
| 1163 | `define BADREAD BADBADD | |
| 1164 | ||
| 1165 | ||
| 1166 | ||
| 1167 | module n2_l2t_bank ( | |
| 1168 | l1clk_in, | |
| 1169 | scan_in, | |
| 1170 | clk_stop, | |
| 1171 | se_outff, | |
| 1172 | scan_en, | |
| 1173 | vnw_ary, | |
| 1174 | scan_out, | |
| 1175 | din, | |
| 1176 | index_a, | |
| 1177 | l2clk, | |
| 1178 | lkuptag_d1, | |
| 1179 | pce_out, | |
| 1180 | pce_ctl, | |
| 1181 | pce_ov, | |
| 1182 | rd_en_a, | |
| 1183 | reg_d_in, | |
| 1184 | reg_en_in, | |
| 1185 | reg_wen_lft, | |
| 1186 | reg_wen_rgt, | |
| 1187 | rid_lft, | |
| 1188 | rid_rgt, | |
| 1189 | tcu_aclk, | |
| 1190 | tcu_bclk, | |
| 1191 | way_a, | |
| 1192 | wr_en_a, | |
| 1193 | wr_inhibit_a, | |
| 1194 | reg_d, | |
| 1195 | reg_en, | |
| 1196 | tag_way0, | |
| 1197 | tag_way1, | |
| 1198 | way_hit_a); | |
| 1199 | wire l1clk_int_v1; | |
| 1200 | wire l1clk_int_v2; | |
| 1201 | wire l1clk_out0; | |
| 1202 | wire l1clk_out1; | |
| 1203 | wire se_unused; | |
| 1204 | wire siclk; | |
| 1205 | wire soclk; | |
| 1206 | wire w1_cmp27to19; | |
| 1207 | wire w1_cmp27to25; | |
| 1208 | wire w1_cmp24to22; | |
| 1209 | wire w1_cmp21to19; | |
| 1210 | wire w0_cmp27to19; | |
| 1211 | wire w0_cmp27to25; | |
| 1212 | wire w0_cmp24to22; | |
| 1213 | wire w0_cmp21to19; | |
| 1214 | wire w1_cmp18to10; | |
| 1215 | wire w1_cmp18to16; | |
| 1216 | wire w1_cmp15to13; | |
| 1217 | wire w1_cmp12to10; | |
| 1218 | wire w0_cmp18to10; | |
| 1219 | wire w0_cmp18to16; | |
| 1220 | wire w0_cmp15to13; | |
| 1221 | wire w0_cmp12to10; | |
| 1222 | wire w1_cmp9to1; | |
| 1223 | wire w1_cmp9to7; | |
| 1224 | wire w1_cmp6to4; | |
| 1225 | wire w1_cmp3to1; | |
| 1226 | wire w0_cmp9to1; | |
| 1227 | wire w0_cmp9to7; | |
| 1228 | wire w0_cmp6to4; | |
| 1229 | wire w0_cmp3to1; | |
| 1230 | wire w1_cmp27to1; | |
| 1231 | wire rd_en_d1_a; | |
| 1232 | wire w0_cmp27to1; | |
| 1233 | wire [4:0] reg_d_lft; | |
| 1234 | wire [4:0] reg_d_rgt; | |
| 1235 | wire rid_lft_b; | |
| 1236 | wire rid_rgt_b; | |
| 1237 | wire [1:0] reg_en_lft; | |
| 1238 | wire [1:0] reg_en_rgt; | |
| 1239 | wire ln1clk; | |
| 1240 | wire ln2clk; | |
| 1241 | wire wr_inhibit_a_l; | |
| 1242 | wire not_reg_wen_lft; | |
| 1243 | wire wen_clk_lft; | |
| 1244 | wire not_reg_wen_rgt; | |
| 1245 | wire wen_clk_rgt; | |
| 1246 | wire en_lft; | |
| 1247 | wire en_rgt; | |
| 1248 | wire [4:0] not_reg_d_lft; | |
| 1249 | wire [1:0] rpda_lft; | |
| 1250 | wire [3:0] rpdb_lft; | |
| 1251 | wire [3:0] rpdc_lft; | |
| 1252 | wire [4:0] not_reg_d_rgt; | |
| 1253 | wire [1:0] rpda_rgt; | |
| 1254 | wire [3:0] rpdb_rgt; | |
| 1255 | wire [3:0] rpdc_rgt; | |
| 1256 | wire [27:0] sao_mx0_h; | |
| 1257 | wire [27:0] sao_mx0_l; | |
| 1258 | wire [27:0] sao_mx1_h; | |
| 1259 | wire [27:0] sao_mx1_l; | |
| 1260 | wire [8:0] addr_b; | |
| 1261 | wire rd_en_b; | |
| 1262 | wire wr_en_b; | |
| 1263 | wire wr_en_d1_a; | |
| 1264 | wire [1:0] wr_way_b; | |
| 1265 | wire [1:0] wr_way_b_l; | |
| 1266 | wire [27:0] sao_mx1; | |
| 1267 | wire [27:0] sao_mx0; | |
| 1268 | wire reg_addr_b_8_scanin; | |
| 1269 | wire reg_addr_b_8_scanout; | |
| 1270 | wire reg_addr_b_8_unused; | |
| 1271 | wire reg_addr_b_7_scanin; | |
| 1272 | wire reg_addr_b_7_scanout; | |
| 1273 | wire reg_addr_b_7_unused; | |
| 1274 | wire reg_addr_b_6_scanin; | |
| 1275 | wire reg_addr_b_6_scanout; | |
| 1276 | wire reg_addr_b_6_unused; | |
| 1277 | wire reg_addr_b_5_scanin; | |
| 1278 | wire reg_addr_b_5_scanout; | |
| 1279 | wire reg_addr_b_5_unused; | |
| 1280 | wire reg_addr_b_4_scanin; | |
| 1281 | wire reg_addr_b_4_scanout; | |
| 1282 | wire reg_addr_b_4_unused; | |
| 1283 | wire reg_addr_b_3_scanin; | |
| 1284 | wire reg_addr_b_3_scanout; | |
| 1285 | wire reg_addr_b_3_unused; | |
| 1286 | wire reg_addr_b_2_scanin; | |
| 1287 | wire reg_addr_b_2_scanout; | |
| 1288 | wire reg_addr_b_2_unused; | |
| 1289 | wire reg_addr_b_1_scanin; | |
| 1290 | wire reg_addr_b_1_scanout; | |
| 1291 | wire reg_addr_b_1_unused; | |
| 1292 | wire reg_addr_b_0_scanin; | |
| 1293 | wire reg_addr_b_0_scanout; | |
| 1294 | wire reg_addr_b_0_unused; | |
| 1295 | wire reg_wr_way_b_scanin; | |
| 1296 | wire reg_wr_way_b_scanout; | |
| 1297 | wire reg_wr_en_b_scanin; | |
| 1298 | wire reg_wr_en_b_scanout; | |
| 1299 | wire reg_wr_en_b_unused; | |
| 1300 | wire reg_rd_en_b_scanin; | |
| 1301 | wire reg_rd_en_b_scanout; | |
| 1302 | wire reg_rd_en_b_unused; | |
| 1303 | wire reg_wr_en_a_scanin; | |
| 1304 | wire reg_wr_en_a_scanout; | |
| 1305 | wire reg_rd_en_a_scanin; | |
| 1306 | wire reg_rd_en_a_scanout; | |
| 1307 | wire reg_tag_way1_27_scanin; | |
| 1308 | wire reg_tag_way1_27_scanout; | |
| 1309 | wire reg_tag_way0_27_scanin; | |
| 1310 | wire reg_tag_way0_27_scanout; | |
| 1311 | wire reg_tag_way1_26_scanin; | |
| 1312 | wire reg_tag_way1_26_scanout; | |
| 1313 | wire reg_tag_way0_26_scanin; | |
| 1314 | wire reg_tag_way0_26_scanout; | |
| 1315 | wire reg_tag_way1_25_scanin; | |
| 1316 | wire reg_tag_way1_25_scanout; | |
| 1317 | wire reg_tag_way0_25_scanin; | |
| 1318 | wire reg_tag_way0_25_scanout; | |
| 1319 | wire reg_tag_way1_24_scanin; | |
| 1320 | wire reg_tag_way1_24_scanout; | |
| 1321 | wire reg_tag_way0_24_scanin; | |
| 1322 | wire reg_tag_way0_24_scanout; | |
| 1323 | wire reg_tag_way1_23_scanin; | |
| 1324 | wire reg_tag_way1_23_scanout; | |
| 1325 | wire reg_tag_way0_23_scanin; | |
| 1326 | wire reg_tag_way0_23_scanout; | |
| 1327 | wire reg_tag_way1_22_scanin; | |
| 1328 | wire reg_tag_way1_22_scanout; | |
| 1329 | wire reg_tag_way0_22_scanin; | |
| 1330 | wire reg_tag_way0_22_scanout; | |
| 1331 | wire reg_tag_way1_21_scanin; | |
| 1332 | wire reg_tag_way1_21_scanout; | |
| 1333 | wire reg_tag_way0_21_scanin; | |
| 1334 | wire reg_tag_way0_21_scanout; | |
| 1335 | wire reg_tag_way1_20_scanin; | |
| 1336 | wire reg_tag_way1_20_scanout; | |
| 1337 | wire reg_tag_way0_20_scanin; | |
| 1338 | wire reg_tag_way0_20_scanout; | |
| 1339 | wire reg_tag_way1_19_scanin; | |
| 1340 | wire reg_tag_way1_19_scanout; | |
| 1341 | wire reg_tag_way0_19_scanin; | |
| 1342 | wire reg_tag_way0_19_scanout; | |
| 1343 | wire reg_tag_way1_18_scanin; | |
| 1344 | wire reg_tag_way1_18_scanout; | |
| 1345 | wire reg_tag_way0_18_scanin; | |
| 1346 | wire reg_tag_way0_18_scanout; | |
| 1347 | wire reg_tag_way1_17_scanin; | |
| 1348 | wire reg_tag_way1_17_scanout; | |
| 1349 | wire reg_tag_way0_17_scanin; | |
| 1350 | wire reg_tag_way0_17_scanout; | |
| 1351 | wire reg_tag_way1_16_scanin; | |
| 1352 | wire reg_tag_way1_16_scanout; | |
| 1353 | wire reg_tag_way0_16_scanin; | |
| 1354 | wire reg_tag_way0_16_scanout; | |
| 1355 | wire reg_tag_way1_15_scanin; | |
| 1356 | wire reg_tag_way1_15_scanout; | |
| 1357 | wire reg_tag_way0_15_scanin; | |
| 1358 | wire reg_tag_way0_15_scanout; | |
| 1359 | wire reg_tag_way1_14_scanin; | |
| 1360 | wire reg_tag_way1_14_scanout; | |
| 1361 | wire reg_tag_way0_14_scanin; | |
| 1362 | wire reg_tag_way0_14_scanout; | |
| 1363 | wire reg_tag_way1_13_scanin; | |
| 1364 | wire reg_tag_way1_13_scanout; | |
| 1365 | wire reg_tag_way0_13_scanin; | |
| 1366 | wire reg_tag_way0_13_scanout; | |
| 1367 | wire reg_tag_way1_12_scanin; | |
| 1368 | wire reg_tag_way1_12_scanout; | |
| 1369 | wire reg_tag_way0_12_scanin; | |
| 1370 | wire reg_tag_way0_12_scanout; | |
| 1371 | wire reg_tag_way1_11_scanin; | |
| 1372 | wire reg_tag_way1_11_scanout; | |
| 1373 | wire reg_tag_way0_11_scanin; | |
| 1374 | wire reg_tag_way0_11_scanout; | |
| 1375 | wire reg_tag_way1_10_scanin; | |
| 1376 | wire reg_tag_way1_10_scanout; | |
| 1377 | wire reg_tag_way0_10_scanin; | |
| 1378 | wire reg_tag_way0_10_scanout; | |
| 1379 | wire reg_tag_way1_9_scanin; | |
| 1380 | wire reg_tag_way1_9_scanout; | |
| 1381 | wire reg_tag_way0_9_scanin; | |
| 1382 | wire reg_tag_way0_9_scanout; | |
| 1383 | wire reg_tag_way1_8_scanin; | |
| 1384 | wire reg_tag_way1_8_scanout; | |
| 1385 | wire reg_tag_way0_8_scanin; | |
| 1386 | wire reg_tag_way0_8_scanout; | |
| 1387 | wire reg_tag_way1_7_scanin; | |
| 1388 | wire reg_tag_way1_7_scanout; | |
| 1389 | wire reg_tag_way0_7_scanin; | |
| 1390 | wire reg_tag_way0_7_scanout; | |
| 1391 | wire reg_tag_way1_6_scanin; | |
| 1392 | wire reg_tag_way1_6_scanout; | |
| 1393 | wire reg_tag_way0_6_scanin; | |
| 1394 | wire reg_tag_way0_6_scanout; | |
| 1395 | wire reg_tag_way1_5_scanin; | |
| 1396 | wire reg_tag_way1_5_scanout; | |
| 1397 | wire reg_tag_way0_5_scanin; | |
| 1398 | wire reg_tag_way0_5_scanout; | |
| 1399 | wire reg_tag_way1_4_scanin; | |
| 1400 | wire reg_tag_way1_4_scanout; | |
| 1401 | wire reg_tag_way0_4_scanin; | |
| 1402 | wire reg_tag_way0_4_scanout; | |
| 1403 | wire reg_tag_way1_3_scanin; | |
| 1404 | wire reg_tag_way1_3_scanout; | |
| 1405 | wire reg_tag_way0_3_scanin; | |
| 1406 | wire reg_tag_way0_3_scanout; | |
| 1407 | wire reg_tag_way1_2_scanin; | |
| 1408 | wire reg_tag_way1_2_scanout; | |
| 1409 | wire reg_tag_way0_2_scanin; | |
| 1410 | wire reg_tag_way0_2_scanout; | |
| 1411 | wire reg_tag_way1_1_scanin; | |
| 1412 | wire reg_tag_way1_1_scanout; | |
| 1413 | wire reg_tag_way0_1_scanin; | |
| 1414 | wire reg_tag_way0_1_scanout; | |
| 1415 | wire reg_tag_way1_0_scanin; | |
| 1416 | wire reg_tag_way1_0_scanout; | |
| 1417 | wire reg_tag_way0_0_scanin; | |
| 1418 | wire reg_tag_way0_0_scanout; | |
| 1419 | wire reg_way_hit_a0_scanin; | |
| 1420 | wire reg_way_hit_a0_scanout; | |
| 1421 | wire reg_way_hit_a1_scanin; | |
| 1422 | wire reg_way_hit_a1_scanout; | |
| 1423 | ||
| 1424 | ||
| 1425 | // input l2clk; // cmp clock | |
| 1426 | input l1clk_in; // io clock | |
| 1427 | input scan_in; | |
| 1428 | input clk_stop; | |
| 1429 | input se_outff; | |
| 1430 | input scan_en; | |
| 1431 | input vnw_ary; | |
| 1432 | ||
| 1433 | // input tcu_aclk; | |
| 1434 | // input tcu_bclk; | |
| 1435 | // input tcu_scan_en; | |
| 1436 | // input tcu_muxtest; | |
| 1437 | // input tcu_dectest; | |
| 1438 | output scan_out; | |
| 1439 | ||
| 1440 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
| 1441 | input [8:0] index_a; | |
| 1442 | input l2clk; | |
| 1443 | input [`L2T_ARR_D_WIDTH - 1:1] lkuptag_d1; | |
| 1444 | input pce_out; | |
| 1445 | input pce_ctl; | |
| 1446 | input pce_ov; | |
| 1447 | input rd_en_a; | |
| 1448 | input [4:0] reg_d_in; | |
| 1449 | input [1:0] reg_en_in; | |
| 1450 | input reg_wen_lft; | |
| 1451 | input reg_wen_rgt; | |
| 1452 | input rid_lft; | |
| 1453 | input rid_rgt; | |
| 1454 | input tcu_aclk; | |
| 1455 | input tcu_bclk; | |
| 1456 | input [1:0] way_a; | |
| 1457 | input wr_en_a; | |
| 1458 | input wr_inhibit_a; | |
| 1459 | ||
| 1460 | output [4:0] reg_d; | |
| 1461 | output [1:0] reg_en; | |
| 1462 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way0; | |
| 1463 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way1; | |
| 1464 | output [1:0] way_hit_a; | |
| 1465 | ||
| 1466 | ||
| 1467 | ||
| 1468 | ///////////////////////////////////////// | |
| 1469 | // Clock Header // | |
| 1470 | ///////////////////////////////////////// | |
| 1471 | ||
| 1472 | //INTERNAL HEADER | |
| 1473 | // | |
| 1474 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_int_v1 ( | |
| 1475 | .l2clk (l2clk), | |
| 1476 | .l1en (pce_ctl), | |
| 1477 | .pce_ov (pce_ov), | |
| 1478 | .stop (clk_stop), | |
| 1479 | .se (scan_en), | |
| 1480 | .l1clk (l1clk_int_v1)); | |
| 1481 | ||
| 1482 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_int_v2 ( | |
| 1483 | .l2clk (l2clk), | |
| 1484 | .l1en (pce_ctl), | |
| 1485 | .pce_ov (pce_ov), | |
| 1486 | .stop (clk_stop), | |
| 1487 | .se (scan_en), | |
| 1488 | .l1clk (l1clk_int_v2)); | |
| 1489 | ||
| 1490 | ||
| 1491 | //OUTPUT HEADER | |
| 1492 | // | |
| 1493 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_out0 ( | |
| 1494 | .l2clk (l2clk), | |
| 1495 | .l1en (pce_out), | |
| 1496 | .pce_ov (pce_ov), | |
| 1497 | .stop (clk_stop), | |
| 1498 | .se (se_outff), | |
| 1499 | .l1clk (l1clk_out0)); | |
| 1500 | ||
| 1501 | n2_l2t_quad_l1clkhdr_ctl_macro clk_hdr_out1 ( | |
| 1502 | .l2clk (l2clk), | |
| 1503 | .l1en (pce_out), | |
| 1504 | .pce_ov (pce_ov), | |
| 1505 | .stop (clk_stop), | |
| 1506 | .se (se_outff), | |
| 1507 | .l1clk (l1clk_out1)); | |
| 1508 | ||
| 1509 | assign se_unused = se_outff; | |
| 1510 | assign siclk = tcu_aclk; | |
| 1511 | assign soclk = tcu_bclk; | |
| 1512 | ||
| 1513 | //--------------------------------------- | |
| 1514 | // output signals | |
| 1515 | //--------------------------------------- | |
| 1516 | ||
| 1517 | // Behaviourial coding for compare: | |
| 1518 | //assign way_hit_a_l[1] = (lkuptag_d1[`L2T_ARR_D_WIDTH - 1 :1] == sao_mx1_h[`L2T_ARR_D_WIDTH - 1 :1] ) ? | |
| 1519 | // 1'b0 : 1'b1; | |
| 1520 | //assign way_hit_a_l[0] = (lkuptag_d1[`L2T_ARR_D_WIDTH - 1 :1] == sao_mx0_h[`L2T_ARR_D_WIDTH - 1 :1] ) ? | |
| 1521 | // 1'b0 : 1'b1; | |
| 1522 | ||
| 1523 | // Structural coding for 27bit compare (for two ways): | |
| 1524 | n2_l2t_quad_nor_macro__ports_3__width_1 w1_nor_cmp27to19 ( | |
| 1525 | .dout (w1_cmp27to19), | |
| 1526 | .din0 (w1_cmp27to25), | |
| 1527 | .din1 (w1_cmp24to22), | |
| 1528 | .din2 (w1_cmp21to19)); | |
| 1529 | ||
| 1530 | n2_l2t_quad_nor_macro__ports_3__width_1 w0_nor_cmp27to19 | |
| 1531 | ( | |
| 1532 | .dout (w0_cmp27to19), | |
| 1533 | .din0 (w0_cmp27to25), | |
| 1534 | .din1 (w0_cmp24to22), | |
| 1535 | .din2 (w0_cmp21to19)); | |
| 1536 | ||
| 1537 | n2_l2t_quad_nor_macro__ports_3__width_1 w1_nor_cmp18to10 | |
| 1538 | ( | |
| 1539 | .dout (w1_cmp18to10), | |
| 1540 | .din0 (w1_cmp18to16), | |
| 1541 | .din1 (w1_cmp15to13), | |
| 1542 | .din2 (w1_cmp12to10)); | |
| 1543 | ||
| 1544 | n2_l2t_quad_nor_macro__ports_3__width_1 w0_nor_cmp18to10 | |
| 1545 | ( | |
| 1546 | .dout (w0_cmp18to10), | |
| 1547 | .din0 (w0_cmp18to16), | |
| 1548 | .din1 (w0_cmp15to13), | |
| 1549 | .din2 (w0_cmp12to10)); | |
| 1550 | ||
| 1551 | ||
| 1552 | n2_l2t_quad_nor_macro__ports_3__width_1 w1_nor_cmp9to1 | |
| 1553 | ( | |
| 1554 | .dout (w1_cmp9to1), | |
| 1555 | .din0 (w1_cmp9to7), | |
| 1556 | .din1 (w1_cmp6to4), | |
| 1557 | .din2 (w1_cmp3to1)); | |
| 1558 | ||
| 1559 | ||
| 1560 | n2_l2t_quad_nor_macro__ports_3__width_1 w0_nor_cmp9to1 | |
| 1561 | ( | |
| 1562 | .dout (w0_cmp9to1), | |
| 1563 | .din0 (w0_cmp9to7), | |
| 1564 | .din1 (w0_cmp6to4), | |
| 1565 | .din2 (w0_cmp3to1)); | |
| 1566 | ||
| 1567 | ||
| 1568 | // Third stage nand | |
| 1569 | //assign w1_cmp27to1 = ~(rd_en_d1_a & w1_cmp27to19 & w1_cmp18to10 & w1_cmp9to1); | |
| 1570 | //assign w0_cmp27to1 = ~(rd_en_d1_a & w0_cmp27to19 & w0_cmp18to10 & w0_cmp9to1); | |
| 1571 | ||
| 1572 | n2_l2t_quad_nand_macro__ports_4__width_1 w1_nand_cmp27to1 | |
| 1573 | ( | |
| 1574 | .dout (w1_cmp27to1), | |
| 1575 | .din0 (rd_en_d1_a), | |
| 1576 | .din1 (w1_cmp27to19), | |
| 1577 | .din2 (w1_cmp18to10), | |
| 1578 | .din3 (w1_cmp9to1)); | |
| 1579 | ||
| 1580 | n2_l2t_quad_nand_macro__ports_4__width_1 w0_nand_cmp27to1 | |
| 1581 | ( | |
| 1582 | .dout (w0_cmp27to1), | |
| 1583 | .din0 (rd_en_d1_a), | |
| 1584 | .din1 (w0_cmp27to19), | |
| 1585 | .din2 (w0_cmp18to10), | |
| 1586 | .din3 (w0_cmp9to1)); | |
| 1587 | ||
| 1588 | // The mux is not explicit (check with Connie) | |
| 1589 | //assign reg_sel[1:0] = {rid_lft_b, rid_rgt_b}; | |
| 1590 | //assign reg_d[4:0] = (reg_sel == 2'b10) ? reg_d_lft[4:0] : (reg_sel == 2'b01) ? reg_d_rgt[4:0] : 5'b00000; | |
| 1591 | //assign reg_en[1:0] = (reg_sel == 2'b10) ? reg_en_lft[1:0] : (reg_sel == 2'b01) ? reg_en_rgt[1:0] : 2'b00; | |
| 1592 | ||
| 1593 | n2_l2t_quad_mux_macro__mux_aonpe__ports_2__stack_156c__width_5 mux_reg_d_lft_reg_d_rgt | |
| 1594 | ( | |
| 1595 | .dout (reg_d[4:0]), | |
| 1596 | .din0 (reg_d_lft[4:0]), | |
| 1597 | .din1 (reg_d_rgt[4:0]), | |
| 1598 | .sel0 (rid_lft_b), | |
| 1599 | .sel1 (rid_rgt_b) | |
| 1600 | ); | |
| 1601 | ||
| 1602 | n2_l2t_quad_mux_macro__mux_aonpe__ports_2__stack_156c__width_2 mux_reg_en_lft_reg_en_rgt | |
| 1603 | ( | |
| 1604 | .dout (reg_en[1:0]), | |
| 1605 | .din0 (reg_en_lft[1:0]), | |
| 1606 | .din1 (reg_en_rgt[1:0]), | |
| 1607 | .sel0 (rid_lft_b), | |
| 1608 | .sel1 (rid_rgt_b) | |
| 1609 | ); | |
| 1610 | ||
| 1611 | ||
| 1612 | ||
| 1613 | //--------------------------------------- | |
| 1614 | // internal signals | |
| 1615 | //--------------------------------------- | |
| 1616 | assign ln1clk = l1clk_int_v2; | |
| 1617 | assign ln2clk = l1clk_int_v2; | |
| 1618 | //Change to structural CC | |
| 1619 | // assign wr_inhibit_a_l = ~wr_inhibit_a; | |
| 1620 | ||
| 1621 | n2_l2t_quad_inv_macro__width_1 inv_wr_inhibit_a | |
| 1622 | ( | |
| 1623 | .din (wr_inhibit_a), | |
| 1624 | .dout (wr_inhibit_a_l) | |
| 1625 | ); | |
| 1626 | ||
| 1627 | //--------------------------------------- | |
| 1628 | // Redundancy section | |
| 1629 | //--------------------------------------- | |
| 1630 | ||
| 1631 | //Change to structural CC | |
| 1632 | //assign wen_clk_lft = ~((~l1clk_int_v1) && reg_wen_lft); | |
| 1633 | //assign wen_clk_rgt = ~((~l1clk_int_v2) && reg_wen_rgt); | |
| 1634 | ||
| 1635 | n2_l2t_quad_inv_macro__width_1 inv_reg_wen_lft | |
| 1636 | ( | |
| 1637 | .din (reg_wen_lft), | |
| 1638 | .dout (not_reg_wen_lft) | |
| 1639 | ); | |
| 1640 | ||
| 1641 | n2_l2t_quad_or_macro__ports_2__width_1 or_wen_clk_lft | |
| 1642 | ( | |
| 1643 | .din0 (l1clk_int_v1), | |
| 1644 | .din1 (not_reg_wen_lft), | |
| 1645 | .dout (wen_clk_lft) | |
| 1646 | ); | |
| 1647 | ||
| 1648 | n2_l2t_quad_inv_macro__width_1 inv_reg_wen_rgt | |
| 1649 | ( | |
| 1650 | .din (reg_wen_rgt), | |
| 1651 | .dout (not_reg_wen_rgt) | |
| 1652 | ); | |
| 1653 | ||
| 1654 | n2_l2t_quad_or_macro__ports_2__width_1 or_wen_clk_rgt | |
| 1655 | ( | |
| 1656 | .din0 (l1clk_int_v2), | |
| 1657 | .din1 (not_reg_wen_rgt), | |
| 1658 | .dout (wen_clk_rgt) | |
| 1659 | ); | |
| 1660 | ||
| 1661 | ||
| 1662 | //assign en_lft = ®_en_lft[1:0]; | |
| 1663 | //assign en_rgt = ®_en_rgt[1:0]; | |
| 1664 | ||
| 1665 | n2_l2t_quad_and_macro__ports_2__width_1 and_en_lft | |
| 1666 | ( | |
| 1667 | .din0 (reg_en_lft[0]), | |
| 1668 | .din1 (reg_en_lft[1]), | |
| 1669 | .dout (en_lft) | |
| 1670 | ); | |
| 1671 | ||
| 1672 | n2_l2t_quad_and_macro__ports_2__width_1 and_en_rgt | |
| 1673 | ( | |
| 1674 | .din0 (reg_en_rgt[0]), | |
| 1675 | .din1 (reg_en_rgt[1]), | |
| 1676 | .dout (en_rgt) | |
| 1677 | ); | |
| 1678 | ||
| 1679 | // Redundancy decoding : | |
| 1680 | //Change to structural CC | |
| 1681 | ||
| 1682 | // LEFT SIDE | |
| 1683 | n2_l2t_quad_inv_macro__width_5 inv_reg_d_lft | |
| 1684 | ( | |
| 1685 | .din (reg_d_lft[4:0]), | |
| 1686 | .dout (not_reg_d_lft[4:0]) | |
| 1687 | ); | |
| 1688 | ||
| 1689 | //assign rpdb_lft[3] = en_lft && ( reg_d_lft[3]) && ( reg_d_lft[2]); | |
| 1690 | //assign rpda_lft[1] = en_lft && ( reg_d_lft[4]); | |
| 1691 | n2_l2t_quad_and_macro__ports_2__width_1 and_rpda_lft_1 | |
| 1692 | ( | |
| 1693 | .din0 (reg_d_lft[4]), | |
| 1694 | .din1 (en_lft), | |
| 1695 | .dout (rpda_lft[1]) | |
| 1696 | ); | |
| 1697 | ||
| 1698 | //assign rpda_lft[0] = en_lft && (~reg_d_lft[4]); | |
| 1699 | n2_l2t_quad_and_macro__ports_2__width_1 and_rpda_lft_0 | |
| 1700 | ( | |
| 1701 | .din0 (not_reg_d_lft[4]), | |
| 1702 | .din1 (en_lft), | |
| 1703 | .dout (rpda_lft[0]) | |
| 1704 | ); | |
| 1705 | ||
| 1706 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_lft_3 | |
| 1707 | ( | |
| 1708 | .din0 (reg_d_lft[3]), | |
| 1709 | .din1 (en_lft), | |
| 1710 | .din2 (reg_d_lft[2]), | |
| 1711 | .dout (rpdb_lft[3]) | |
| 1712 | ); | |
| 1713 | ||
| 1714 | //assign rpdb_lft[2] = en_lft && ( reg_d_lft[3]) && (~reg_d_lft[2]); | |
| 1715 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_lft_2 | |
| 1716 | ( | |
| 1717 | .din0 (reg_d_lft[3]), | |
| 1718 | .din1 (en_lft), | |
| 1719 | .din2 (not_reg_d_lft[2]), | |
| 1720 | .dout (rpdb_lft[2]) | |
| 1721 | ); | |
| 1722 | ||
| 1723 | //assign rpdb_lft[1] = en_lft && (~reg_d_lft[3]) && ( reg_d_lft[2]); | |
| 1724 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_lft_1 | |
| 1725 | ( | |
| 1726 | .din0 (not_reg_d_lft[3]), | |
| 1727 | .din1 (en_lft), | |
| 1728 | .din2 (reg_d_lft[2]), | |
| 1729 | .dout (rpdb_lft[1]) | |
| 1730 | ); | |
| 1731 | ||
| 1732 | //assign rpdb_lft[0] = en_lft && (~reg_d_lft[3]) && (~reg_d_lft[2]); | |
| 1733 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_lft_0 | |
| 1734 | ( | |
| 1735 | .din0 (not_reg_d_lft[3]), | |
| 1736 | .din1 (en_lft), | |
| 1737 | .din2 (not_reg_d_lft[2]), | |
| 1738 | .dout (rpdb_lft[0]) | |
| 1739 | ); | |
| 1740 | ||
| 1741 | //assign rpdc_lft[3] = en_lft && ( reg_d_lft[1]) && ( reg_d_lft[0]); | |
| 1742 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_lft_3 | |
| 1743 | ( | |
| 1744 | .din0 (reg_d_lft[1]), | |
| 1745 | .din1 (en_lft), | |
| 1746 | .din2 (reg_d_lft[0]), | |
| 1747 | .dout (rpdc_lft[3]) | |
| 1748 | ); | |
| 1749 | ||
| 1750 | //assign rpdc_lft[2] = en_lft && ( reg_d_lft[1]) && (~reg_d_lft[0]); | |
| 1751 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_lft_2 | |
| 1752 | ( | |
| 1753 | .din0 (reg_d_lft[1]), | |
| 1754 | .din1 (en_lft), | |
| 1755 | .din2 (not_reg_d_lft[0]), | |
| 1756 | .dout (rpdc_lft[2]) | |
| 1757 | ); | |
| 1758 | ||
| 1759 | //assign rpdc_lft[1] = en_lft && (~reg_d_lft[1]) && ( reg_d_lft[0]); | |
| 1760 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_lft_1 | |
| 1761 | ( | |
| 1762 | .din0 (reg_d_lft[0]), | |
| 1763 | .din1 (en_lft), | |
| 1764 | .din2 (not_reg_d_lft[1]), | |
| 1765 | .dout (rpdc_lft[1]) | |
| 1766 | ); | |
| 1767 | ||
| 1768 | //assign rpdc_lft[0] = en_lft && (~reg_d_lft[1]) && (~reg_d_lft[0]); | |
| 1769 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_lft_0 | |
| 1770 | ( | |
| 1771 | .din0 (not_reg_d_lft[0]), | |
| 1772 | .din1 (en_lft), | |
| 1773 | .din2 (not_reg_d_lft[1]), | |
| 1774 | .dout (rpdc_lft[0]) | |
| 1775 | ); | |
| 1776 | // RIGHT SIDE | |
| 1777 | n2_l2t_quad_inv_macro__width_5 inv_reg_d_rgt | |
| 1778 | ( | |
| 1779 | .din (reg_d_rgt[4:0]), | |
| 1780 | .dout (not_reg_d_rgt[4:0]) | |
| 1781 | ); | |
| 1782 | ||
| 1783 | //assign rpda_rgt[1] = en_rgt && ( reg_d_rgt[4]); | |
| 1784 | n2_l2t_quad_and_macro__ports_2__width_1 and_rpda_rgt_1 | |
| 1785 | ( | |
| 1786 | .din0 (reg_d_rgt[4]), | |
| 1787 | .din1 (en_rgt), | |
| 1788 | .dout (rpda_rgt[1]) | |
| 1789 | ); | |
| 1790 | ||
| 1791 | //assign rpda_rgt[0] = en_rgt && (~reg_d_rgt[4]); | |
| 1792 | n2_l2t_quad_and_macro__ports_2__width_1 and_rpda_rgt_0 | |
| 1793 | ( | |
| 1794 | .din0 (not_reg_d_rgt[4]), | |
| 1795 | .din1 (en_rgt), | |
| 1796 | .dout (rpda_rgt[0]) | |
| 1797 | ); | |
| 1798 | ||
| 1799 | //assign rpdb_rgt[3] = en_rgt && ( reg_d_rgt[3]) && ( reg_d_rgt[2]); | |
| 1800 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_rgt_3 | |
| 1801 | ( | |
| 1802 | .din0 (reg_d_rgt[2]), | |
| 1803 | .din1 (en_rgt), | |
| 1804 | .din2 (reg_d_rgt[3]), | |
| 1805 | .dout (rpdb_rgt[3]) | |
| 1806 | ); | |
| 1807 | ||
| 1808 | //assign rpdb_rgt[2] = en_rgt && ( reg_d_rgt[3]) && (~reg_d_rgt[2]); | |
| 1809 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_rgt_2 | |
| 1810 | ( | |
| 1811 | .din0 (not_reg_d_rgt[2]), | |
| 1812 | .din1 (en_rgt), | |
| 1813 | .din2 (reg_d_rgt[3]), | |
| 1814 | .dout (rpdb_rgt[2]) | |
| 1815 | ); | |
| 1816 | ||
| 1817 | //assign rpdb_rgt[1] = en_rgt && (~reg_d_rgt[3]) && ( reg_d_rgt[2]); | |
| 1818 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_rgt_1 | |
| 1819 | ( | |
| 1820 | .din0 (reg_d_rgt[2]), | |
| 1821 | .din1 (en_rgt), | |
| 1822 | .din2 (not_reg_d_rgt[3]), | |
| 1823 | .dout (rpdb_rgt[1]) | |
| 1824 | ); | |
| 1825 | ||
| 1826 | //assign rpdb_rgt[0] = en_rgt && (~reg_d_rgt[3]) && (~reg_d_rgt[2]); | |
| 1827 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdb_rgt_0 | |
| 1828 | ( | |
| 1829 | .din0 (not_reg_d_rgt[2]), | |
| 1830 | .din1 (en_rgt), | |
| 1831 | .din2 (not_reg_d_rgt[3]), | |
| 1832 | .dout (rpdb_rgt[0]) | |
| 1833 | ); | |
| 1834 | ||
| 1835 | //assign rpdc_rgt[3] = en_rgt && ( reg_d_rgt[1]) && ( reg_d_rgt[0]); | |
| 1836 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_rgt_3 | |
| 1837 | ( | |
| 1838 | .din0 (reg_d_rgt[1]), | |
| 1839 | .din1 (en_rgt), | |
| 1840 | .din2 (reg_d_rgt[0]), | |
| 1841 | .dout (rpdc_rgt[3]) | |
| 1842 | ); | |
| 1843 | ||
| 1844 | //assign rpdc_rgt[2] = en_rgt && ( reg_d_rgt[1]) && (~reg_d_rgt[0]); | |
| 1845 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_rgt_2 | |
| 1846 | ( | |
| 1847 | .din0 (reg_d_rgt[1]), | |
| 1848 | .din1 (en_rgt), | |
| 1849 | .din2 (not_reg_d_rgt[0]), | |
| 1850 | .dout (rpdc_rgt[2]) | |
| 1851 | ); | |
| 1852 | ||
| 1853 | //assign rpdc_rgt[1] = en_rgt && (~reg_d_rgt[1]) && ( reg_d_rgt[0]); | |
| 1854 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_rgt_1 | |
| 1855 | ( | |
| 1856 | .din0 (not_reg_d_rgt[1]), | |
| 1857 | .din1 (en_rgt), | |
| 1858 | .din2 (reg_d_rgt[0]), | |
| 1859 | .dout (rpdc_rgt[1]) | |
| 1860 | ); | |
| 1861 | ||
| 1862 | //assign rpdc_rgt[0] = en_rgt && (~reg_d_rgt[1]) && (~reg_d_rgt[0]); | |
| 1863 | n2_l2t_quad_and_macro__ports_3__width_1 and_rpdc_rgt_0 | |
| 1864 | ( | |
| 1865 | .din0 (not_reg_d_rgt[1]), | |
| 1866 | .din1 (en_rgt), | |
| 1867 | .din2 (not_reg_d_rgt[0]), | |
| 1868 | .dout (rpdc_rgt[0]) | |
| 1869 | ); | |
| 1870 | ||
| 1871 | // --- | |
| 1872 | ||
| 1873 | ||
| 1874 | //assign rpda_lft[1:0] = en_lft ? (reg_d_lft[4] ? 2'b10 : 2'b01 ): 2'b00; | |
| 1875 | //assign rpdb_lft[3:0] = en_lft ? ((reg_d_lft[3:2] == 2'b11) ? 4'b1000 : | |
| 1876 | // (reg_d_lft[3:2] == 2'b10) ? 4'b0100 : | |
| 1877 | // (reg_d_lft[3:2] == 2'b01) ? 4'b0010 : | |
| 1878 | // 4'b0001 ) : 4'b0000; | |
| 1879 | //assign rpdc_lft[3:0] = en_lft ? ((reg_d_lft[1:0] == 2'b11) ? 4'b1000 : | |
| 1880 | // (reg_d_lft[1:0] == 2'b10) ? 4'b0100 : | |
| 1881 | // (reg_d_lft[1:0] == 2'b01) ? 4'b0010 : | |
| 1882 | // 4'b0001 ) : 4'b0000; | |
| 1883 | //assign rpda_rgt[1:0] = en_rgt ? (reg_d_rgt[4] ? 2'b10 : 2'b01 ): 2'b00; | |
| 1884 | //assign rpdb_rgt[3:0] = en_rgt ? ((reg_d_rgt[3:2] == 2'b11) ? 4'b1000 : | |
| 1885 | // (reg_d_rgt[3:2] == 2'b10) ? 4'b0100 : | |
| 1886 | // (reg_d_rgt[3:2] == 2'b01) ? 4'b0010 : | |
| 1887 | // 4'b0001 ) : 4'b0000; | |
| 1888 | //assign rpdc_rgt[3:0] = en_rgt ? ((reg_d_rgt[1:0] == 2'b11) ? 4'b1000 : | |
| 1889 | // (reg_d_rgt[1:0] == 2'b10) ? 4'b0100 : | |
| 1890 | // (reg_d_rgt[1:0] == 2'b01) ? 4'b0010 : | |
| 1891 | // 4'b0001 ) : 4'b0000; | |
| 1892 | ||
| 1893 | ||
| 1894 | //--------------------------------------- | |
| 1895 | // L2T ARRAY INSTANTIATION | |
| 1896 | //--------------------------------------- | |
| 1897 | n2_l2t_array l2t_array (/*AUTOINST*/ | |
| 1898 | // Outputs | |
| 1899 | .sao_mx0_h (sao_mx0_h[`L2T_ARR_D_WIDTH-1:0]), | |
| 1900 | .sao_mx0_l (sao_mx0_l[`L2T_ARR_D_WIDTH-1:0]), | |
| 1901 | .sao_mx1_h (sao_mx1_h[`L2T_ARR_D_WIDTH-1:0]), | |
| 1902 | .sao_mx1_l (sao_mx1_l[`L2T_ARR_D_WIDTH-1:0]), | |
| 1903 | // Inputs | |
| 1904 | .vnw_ary (vnw_ary), | |
| 1905 | .din (din[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
| 1906 | .addr_b (addr_b[8:0]), | |
| 1907 | .l1clk_internal_v1(l1clk_int_v1), // Templated | |
| 1908 | .l1clk_internal_v2(l1clk_int_v2), // Templated | |
| 1909 | .ln1clk (ln1clk), | |
| 1910 | .ln2clk (ln2clk), | |
| 1911 | .rd_en_b (rd_en_b), | |
| 1912 | .rd_en_d1_a (rd_en_d1_a), | |
| 1913 | .rpda_lft (rpda_lft[1:0]), | |
| 1914 | .rpda_rgt (rpda_rgt[1:0]), | |
| 1915 | .rpdb_lft (rpdb_lft[3:0]), | |
| 1916 | .rpdb_rgt (rpdb_rgt[3:0]), | |
| 1917 | .rpdc_lft (rpdc_lft[3:0]), | |
| 1918 | .rpdc_rgt (rpdc_rgt[3:0]), | |
| 1919 | .w_inhibit_l (wr_inhibit_a_l), | |
| 1920 | .wr_en_b (wr_en_b), | |
| 1921 | .wr_en_d1_a (wr_en_d1_a), | |
| 1922 | .wr_way_b (wr_way_b[1:0]), | |
| 1923 | .wr_way_b_l (wr_way_b_l[1:0])); | |
| 1924 | ||
| 1925 | //--------------------------------------- | |
| 1926 | // SET RESET LATCH FOR SENSE AMP OUT | |
| 1927 | //--------------------------------------- | |
| 1928 | ||
| 1929 | n2_l2t_sr_latch srlatch_sao_mx1_27 (.set (sao_mx1_h[27]), .reset (sao_mx1_l[27]), .out (sao_mx1[27])); | |
| 1930 | n2_l2t_sr_latch srlatch_sao_mx1_26 (.set (sao_mx1_h[26]), .reset (sao_mx1_l[26]), .out (sao_mx1[26])); | |
| 1931 | n2_l2t_sr_latch srlatch_sao_mx1_25 (.set (sao_mx1_h[25]), .reset (sao_mx1_l[25]), .out (sao_mx1[25])); | |
| 1932 | n2_l2t_sr_latch srlatch_sao_mx1_24 (.set (sao_mx1_h[24]), .reset (sao_mx1_l[24]), .out (sao_mx1[24])); | |
| 1933 | n2_l2t_sr_latch srlatch_sao_mx1_23 (.set (sao_mx1_h[23]), .reset (sao_mx1_l[23]), .out (sao_mx1[23])); | |
| 1934 | n2_l2t_sr_latch srlatch_sao_mx1_22 (.set (sao_mx1_h[22]), .reset (sao_mx1_l[22]), .out (sao_mx1[22])); | |
| 1935 | n2_l2t_sr_latch srlatch_sao_mx1_21 (.set (sao_mx1_h[21]), .reset (sao_mx1_l[21]), .out (sao_mx1[21])); | |
| 1936 | n2_l2t_sr_latch srlatch_sao_mx1_20 (.set (sao_mx1_h[20]), .reset (sao_mx1_l[20]), .out (sao_mx1[20])); | |
| 1937 | n2_l2t_sr_latch srlatch_sao_mx1_19 (.set (sao_mx1_h[19]), .reset (sao_mx1_l[19]), .out (sao_mx1[19])); | |
| 1938 | n2_l2t_sr_latch srlatch_sao_mx1_18 (.set (sao_mx1_h[18]), .reset (sao_mx1_l[18]), .out (sao_mx1[18])); | |
| 1939 | n2_l2t_sr_latch srlatch_sao_mx1_17 (.set (sao_mx1_h[17]), .reset (sao_mx1_l[17]), .out (sao_mx1[17])); | |
| 1940 | n2_l2t_sr_latch srlatch_sao_mx1_16 (.set (sao_mx1_h[16]), .reset (sao_mx1_l[16]), .out (sao_mx1[16])); | |
| 1941 | n2_l2t_sr_latch srlatch_sao_mx1_15 (.set (sao_mx1_h[15]), .reset (sao_mx1_l[15]), .out (sao_mx1[15])); | |
| 1942 | n2_l2t_sr_latch srlatch_sao_mx1_14 (.set (sao_mx1_h[14]), .reset (sao_mx1_l[14]), .out (sao_mx1[14])); | |
| 1943 | n2_l2t_sr_latch srlatch_sao_mx1_13 (.set (sao_mx1_h[13]), .reset (sao_mx1_l[13]), .out (sao_mx1[13])); | |
| 1944 | n2_l2t_sr_latch srlatch_sao_mx1_12 (.set (sao_mx1_h[12]), .reset (sao_mx1_l[12]), .out (sao_mx1[12])); | |
| 1945 | n2_l2t_sr_latch srlatch_sao_mx1_11 (.set (sao_mx1_h[11]), .reset (sao_mx1_l[11]), .out (sao_mx1[11])); | |
| 1946 | n2_l2t_sr_latch srlatch_sao_mx1_10 (.set (sao_mx1_h[10]), .reset (sao_mx1_l[10]), .out (sao_mx1[10])); | |
| 1947 | n2_l2t_sr_latch srlatch_sao_mx1_9 (.set (sao_mx1_h[9]), .reset (sao_mx1_l[9]), .out (sao_mx1[9])); | |
| 1948 | n2_l2t_sr_latch srlatch_sao_mx1_8 (.set (sao_mx1_h[8]), .reset (sao_mx1_l[8]), .out (sao_mx1[8])); | |
| 1949 | n2_l2t_sr_latch srlatch_sao_mx1_7 (.set (sao_mx1_h[7]), .reset (sao_mx1_l[7]), .out (sao_mx1[7])); | |
| 1950 | n2_l2t_sr_latch srlatch_sao_mx1_6 (.set (sao_mx1_h[6]), .reset (sao_mx1_l[6]), .out (sao_mx1[6])); | |
| 1951 | n2_l2t_sr_latch srlatch_sao_mx1_5 (.set (sao_mx1_h[5]), .reset (sao_mx1_l[5]), .out (sao_mx1[5])); | |
| 1952 | n2_l2t_sr_latch srlatch_sao_mx1_4 (.set (sao_mx1_h[4]), .reset (sao_mx1_l[4]), .out (sao_mx1[4])); | |
| 1953 | n2_l2t_sr_latch srlatch_sao_mx1_3 (.set (sao_mx1_h[3]), .reset (sao_mx1_l[3]), .out (sao_mx1[3])); | |
| 1954 | n2_l2t_sr_latch srlatch_sao_mx1_2 (.set (sao_mx1_h[2]), .reset (sao_mx1_l[2]), .out (sao_mx1[2])); | |
| 1955 | n2_l2t_sr_latch srlatch_sao_mx1_1 (.set (sao_mx1_h[1]), .reset (sao_mx1_l[1]), .out (sao_mx1[1])); | |
| 1956 | n2_l2t_sr_latch srlatch_sao_mx1_0 (.set (sao_mx1_h[0]), .reset (sao_mx1_l[0 ]), .out (sao_mx1[0])); | |
| 1957 | ||
| 1958 | n2_l2t_sr_latch srlatch_sao_mx0_27 (.set (sao_mx0_h[27]), .reset (sao_mx0_l[27]), .out (sao_mx0[27])); | |
| 1959 | n2_l2t_sr_latch srlatch_sao_mx0_26 (.set (sao_mx0_h[26]), .reset (sao_mx0_l[26]), .out (sao_mx0[26])); | |
| 1960 | n2_l2t_sr_latch srlatch_sao_mx0_25 (.set (sao_mx0_h[25]), .reset (sao_mx0_l[25]), .out (sao_mx0[25])); | |
| 1961 | n2_l2t_sr_latch srlatch_sao_mx0_24 (.set (sao_mx0_h[24]), .reset (sao_mx0_l[24]), .out (sao_mx0[24])); | |
| 1962 | n2_l2t_sr_latch srlatch_sao_mx0_23 (.set (sao_mx0_h[23]), .reset (sao_mx0_l[23]), .out (sao_mx0[23])); | |
| 1963 | n2_l2t_sr_latch srlatch_sao_mx0_22 (.set (sao_mx0_h[22]), .reset (sao_mx0_l[22]), .out (sao_mx0[22])); | |
| 1964 | n2_l2t_sr_latch srlatch_sao_mx0_21 (.set (sao_mx0_h[21]), .reset (sao_mx0_l[21]), .out (sao_mx0[21])); | |
| 1965 | n2_l2t_sr_latch srlatch_sao_mx0_20 (.set (sao_mx0_h[20]), .reset (sao_mx0_l[20]), .out (sao_mx0[20])); | |
| 1966 | n2_l2t_sr_latch srlatch_sao_mx0_19 (.set (sao_mx0_h[19]), .reset (sao_mx0_l[19]), .out (sao_mx0[19])); | |
| 1967 | n2_l2t_sr_latch srlatch_sao_mx0_18 (.set (sao_mx0_h[18]), .reset (sao_mx0_l[18]), .out (sao_mx0[18])); | |
| 1968 | n2_l2t_sr_latch srlatch_sao_mx0_17 (.set (sao_mx0_h[17]), .reset (sao_mx0_l[17]), .out (sao_mx0[17])); | |
| 1969 | n2_l2t_sr_latch srlatch_sao_mx0_16 (.set (sao_mx0_h[16]), .reset (sao_mx0_l[16]), .out (sao_mx0[16])); | |
| 1970 | n2_l2t_sr_latch srlatch_sao_mx0_15 (.set (sao_mx0_h[15]), .reset (sao_mx0_l[15]), .out (sao_mx0[15])); | |
| 1971 | n2_l2t_sr_latch srlatch_sao_mx0_14 (.set (sao_mx0_h[14]), .reset (sao_mx0_l[14]), .out (sao_mx0[14])); | |
| 1972 | n2_l2t_sr_latch srlatch_sao_mx0_13 (.set (sao_mx0_h[13]), .reset (sao_mx0_l[13]), .out (sao_mx0[13])); | |
| 1973 | n2_l2t_sr_latch srlatch_sao_mx0_12 (.set (sao_mx0_h[12]), .reset (sao_mx0_l[12]), .out (sao_mx0[12])); | |
| 1974 | n2_l2t_sr_latch srlatch_sao_mx0_11 (.set (sao_mx0_h[11]), .reset (sao_mx0_l[11]), .out (sao_mx0[11])); | |
| 1975 | n2_l2t_sr_latch srlatch_sao_mx0_10 (.set (sao_mx0_h[10]), .reset (sao_mx0_l[10]), .out (sao_mx0[10])); | |
| 1976 | n2_l2t_sr_latch srlatch_sao_mx0_9 (.set (sao_mx0_h[9]), .reset (sao_mx0_l[9]), .out (sao_mx0[9])); | |
| 1977 | n2_l2t_sr_latch srlatch_sao_mx0_8 (.set (sao_mx0_h[8]), .reset (sao_mx0_l[8]), .out (sao_mx0[8])); | |
| 1978 | n2_l2t_sr_latch srlatch_sao_mx0_7 (.set (sao_mx0_h[7]), .reset (sao_mx0_l[7]), .out (sao_mx0[7])); | |
| 1979 | n2_l2t_sr_latch srlatch_sao_mx0_6 (.set (sao_mx0_h[6]), .reset (sao_mx0_l[6]), .out (sao_mx0[6])); | |
| 1980 | n2_l2t_sr_latch srlatch_sao_mx0_5 (.set (sao_mx0_h[5]), .reset (sao_mx0_l[5]), .out (sao_mx0[5])); | |
| 1981 | n2_l2t_sr_latch srlatch_sao_mx0_4 (.set (sao_mx0_h[4]), .reset (sao_mx0_l[4]), .out (sao_mx0[4])); | |
| 1982 | n2_l2t_sr_latch srlatch_sao_mx0_3 (.set (sao_mx0_h[3]), .reset (sao_mx0_l[3]), .out (sao_mx0[3])); | |
| 1983 | n2_l2t_sr_latch srlatch_sao_mx0_2 (.set (sao_mx0_h[2]), .reset (sao_mx0_l[2]), .out (sao_mx0[2])); | |
| 1984 | n2_l2t_sr_latch srlatch_sao_mx0_1 (.set (sao_mx0_h[1]), .reset (sao_mx0_l[1]), .out (sao_mx0[1])); | |
| 1985 | n2_l2t_sr_latch srlatch_sao_mx0_0 (.set (sao_mx0_h[0]), .reset (sao_mx0_l[0]), .out (sao_mx0[0])); | |
| 1986 | ||
| 1987 | ||
| 1988 | ||
| 1989 | //--------------------------------------- | |
| 1990 | // L2T 3BIT COMPARE (FIRST STAGE) | |
| 1991 | //--------------------------------------- | |
| 1992 | n2_l2t_cmp_3bx2 cmp27to25 ( | |
| 1993 | .sao_mx1_h (sao_mx1_h[27:25]), | |
| 1994 | .sao_mx1_l (sao_mx1_l[27:25]), | |
| 1995 | .sao_mx0_h (sao_mx0_h[27:25]), | |
| 1996 | .sao_mx0_l (sao_mx0_l[27:25]), | |
| 1997 | .lkuptag_d1 (lkuptag_d1[27:25]), | |
| 1998 | .l1clk_d (l1clk_int_v2), | |
| 1999 | .w1_cmp3b (w1_cmp27to25), | |
| 2000 | .w0_cmp3b (w0_cmp27to25)); | |
| 2001 | ||
| 2002 | n2_l2t_cmp_3bx2 cmp24to22 ( | |
| 2003 | .sao_mx1_h (sao_mx1_h[24:22]), | |
| 2004 | .sao_mx1_l (sao_mx1_l[24:22]), | |
| 2005 | .sao_mx0_h (sao_mx0_h[24:22]), | |
| 2006 | .sao_mx0_l (sao_mx0_l[24:22]), | |
| 2007 | .lkuptag_d1 (lkuptag_d1[24:22]), | |
| 2008 | .l1clk_d (l1clk_int_v2), | |
| 2009 | .w1_cmp3b (w1_cmp24to22), | |
| 2010 | .w0_cmp3b (w0_cmp24to22)); | |
| 2011 | ||
| 2012 | n2_l2t_cmp_3bx2 cmp21to19 ( | |
| 2013 | .sao_mx1_h (sao_mx1_h[21:19]), | |
| 2014 | .sao_mx1_l (sao_mx1_l[21:19]), | |
| 2015 | .sao_mx0_h (sao_mx0_h[21:19]), | |
| 2016 | .sao_mx0_l (sao_mx0_l[21:19]), | |
| 2017 | .lkuptag_d1 (lkuptag_d1[21:19]), | |
| 2018 | .l1clk_d (l1clk_int_v2), | |
| 2019 | .w1_cmp3b (w1_cmp21to19), | |
| 2020 | .w0_cmp3b (w0_cmp21to19)); | |
| 2021 | ||
| 2022 | n2_l2t_cmp_3bx2 cmp18to16 ( | |
| 2023 | .sao_mx1_h (sao_mx1_h[18:16]), | |
| 2024 | .sao_mx1_l (sao_mx1_l[18:16]), | |
| 2025 | .sao_mx0_h (sao_mx0_h[18:16]), | |
| 2026 | .sao_mx0_l (sao_mx0_l[18:16]), | |
| 2027 | .lkuptag_d1 (lkuptag_d1[18:16]), | |
| 2028 | .l1clk_d (l1clk_int_v2), | |
| 2029 | .w1_cmp3b (w1_cmp18to16), | |
| 2030 | .w0_cmp3b (w0_cmp18to16)); | |
| 2031 | ||
| 2032 | n2_l2t_cmp_3bx2 cmp15to13 ( | |
| 2033 | .sao_mx1_h (sao_mx1_h[15:13]), | |
| 2034 | .sao_mx1_l (sao_mx1_l[15:13]), | |
| 2035 | .sao_mx0_h (sao_mx0_h[15:13]), | |
| 2036 | .sao_mx0_l (sao_mx0_l[15:13]), | |
| 2037 | .lkuptag_d1 (lkuptag_d1[15:13]), | |
| 2038 | .l1clk_d (l1clk_int_v2), | |
| 2039 | .w1_cmp3b (w1_cmp15to13), | |
| 2040 | .w0_cmp3b (w0_cmp15to13)); | |
| 2041 | ||
| 2042 | n2_l2t_cmp_3bx2 cmp12to10 ( | |
| 2043 | .sao_mx1_h (sao_mx1_h[12:10]), | |
| 2044 | .sao_mx1_l (sao_mx1_l[12:10]), | |
| 2045 | .sao_mx0_h (sao_mx0_h[12:10]), | |
| 2046 | .sao_mx0_l (sao_mx0_l[12:10]), | |
| 2047 | .lkuptag_d1 (lkuptag_d1[12:10]), | |
| 2048 | .l1clk_d (l1clk_int_v2), | |
| 2049 | .w1_cmp3b (w1_cmp12to10), | |
| 2050 | .w0_cmp3b (w0_cmp12to10)); | |
| 2051 | ||
| 2052 | n2_l2t_cmp_3bx2 cmp9to7 ( | |
| 2053 | .sao_mx1_h (sao_mx1_h[9:7]), | |
| 2054 | .sao_mx1_l (sao_mx1_l[9:7]), | |
| 2055 | .sao_mx0_h (sao_mx0_h[9:7]), | |
| 2056 | .sao_mx0_l (sao_mx0_l[9:7]), | |
| 2057 | .lkuptag_d1 (lkuptag_d1[9:7]), | |
| 2058 | .l1clk_d (l1clk_int_v2), | |
| 2059 | .w1_cmp3b (w1_cmp9to7), | |
| 2060 | .w0_cmp3b (w0_cmp9to7)); | |
| 2061 | ||
| 2062 | ||
| 2063 | n2_l2t_cmp_3bx2 cmp6to4 ( | |
| 2064 | .sao_mx1_h (sao_mx1_h[6:4]), | |
| 2065 | .sao_mx1_l (sao_mx1_l[6:4]), | |
| 2066 | .sao_mx0_h (sao_mx0_h[6:4]), | |
| 2067 | .sao_mx0_l (sao_mx0_l[6:4]), | |
| 2068 | .lkuptag_d1 (lkuptag_d1[6:4]), | |
| 2069 | .l1clk_d (l1clk_int_v2), | |
| 2070 | .w1_cmp3b (w1_cmp6to4), | |
| 2071 | .w0_cmp3b (w0_cmp6to4)); | |
| 2072 | ||
| 2073 | ||
| 2074 | n2_l2t_cmp_3bx2 cmp3to1 ( | |
| 2075 | .sao_mx1_h (sao_mx1_h[3:1]), | |
| 2076 | .sao_mx1_l (sao_mx1_l[3:1]), | |
| 2077 | .sao_mx0_h (sao_mx0_h[3:1]), | |
| 2078 | .sao_mx0_l (sao_mx0_l[3:1]), | |
| 2079 | .lkuptag_d1 (lkuptag_d1[3:1]), | |
| 2080 | .l1clk_d (l1clk_int_v2), | |
| 2081 | .w1_cmp3b (w1_cmp3to1), | |
| 2082 | .w0_cmp3b (w0_cmp3to1)); | |
| 2083 | ||
| 2084 | ||
| 2085 | ||
| 2086 | //************************************************************************ | |
| 2087 | // REGISTERS SECTION | |
| 2088 | //************************************************************************ | |
| 2089 | ||
| 2090 | // INPUT FLOPS | |
| 2091 | n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_2 lat_reg_en_lft | |
| 2092 | ( | |
| 2093 | .d_a(reg_en_in[1:0]), | |
| 2094 | .q_b(reg_en_lft[1:0]), | |
| 2095 | .l1clk(wen_clk_lft) | |
| 2096 | ); | |
| 2097 | ||
| 2098 | n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_5 lat_reg_d_lft | |
| 2099 | ( | |
| 2100 | .d_a(reg_d_in[4:0]), | |
| 2101 | .q_b(reg_d_lft[4:0]), | |
| 2102 | .l1clk(wen_clk_lft) | |
| 2103 | ); | |
| 2104 | ||
| 2105 | n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_2 lat_reg_en_rgt | |
| 2106 | ( | |
| 2107 | .d_a(reg_en_in[1:0]), | |
| 2108 | .q_b(reg_en_rgt[1:0]), | |
| 2109 | .l1clk(wen_clk_rgt) | |
| 2110 | ); | |
| 2111 | ||
| 2112 | n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_5 lat_reg_d_rgt | |
| 2113 | ( | |
| 2114 | .d_a(reg_d_in[4:0]), | |
| 2115 | .q_b(reg_d_rgt[4:0]), | |
| 2116 | .l1clk(wen_clk_rgt) | |
| 2117 | ); | |
| 2118 | ||
| 2119 | // BLB for rid_lft and rid_rgt: | |
| 2120 | ||
| 2121 | n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_1 lat_rid_lft | |
| 2122 | ( | |
| 2123 | .d_a(rid_lft), | |
| 2124 | .q_b(rid_lft_b), | |
| 2125 | .l1clk(l1clk_int_v1) | |
| 2126 | ); | |
| 2127 | ||
| 2128 | n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_1 lat_rid_rgt | |
| 2129 | ( | |
| 2130 | .d_a(rid_rgt), | |
| 2131 | .q_b(rid_rgt_b), | |
| 2132 | .l1clk(l1clk_int_v1) | |
| 2133 | ); | |
| 2134 | ||
| 2135 | ||
| 2136 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_8 (.scan_in (reg_addr_b_8_scanin), .scan_out(reg_addr_b_8_scanout), | |
| 2137 | .latout(addr_b[8]), .latout_l(reg_addr_b_8_unused), .l1clk(l1clk_in), .d(index_a[8]), | |
| 2138 | .siclk(siclk), | |
| 2139 | .soclk(soclk)); | |
| 2140 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_7 (.scan_in (reg_addr_b_7_scanin), .scan_out(reg_addr_b_7_scanout), | |
| 2141 | .latout(addr_b[7]), .latout_l(reg_addr_b_7_unused), .l1clk(l1clk_in), .d(index_a[7]), | |
| 2142 | .siclk(siclk), | |
| 2143 | .soclk(soclk)); | |
| 2144 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_6 (.scan_in (reg_addr_b_6_scanin), .scan_out(reg_addr_b_6_scanout), | |
| 2145 | .latout(addr_b[6]), .latout_l(reg_addr_b_6_unused), .l1clk(l1clk_in), .d(index_a[6]), | |
| 2146 | .siclk(siclk), | |
| 2147 | .soclk(soclk)); | |
| 2148 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_5 (.scan_in (reg_addr_b_5_scanin), .scan_out(reg_addr_b_5_scanout), | |
| 2149 | .latout(addr_b[5]), .latout_l(reg_addr_b_5_unused), .l1clk(l1clk_in), .d(index_a[5]), | |
| 2150 | .siclk(siclk), | |
| 2151 | .soclk(soclk)); | |
| 2152 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_4 (.scan_in (reg_addr_b_4_scanin), .scan_out(reg_addr_b_4_scanout), | |
| 2153 | .latout(addr_b[4]), .latout_l(reg_addr_b_4_unused), .l1clk(l1clk_in), .d(index_a[4]), | |
| 2154 | .siclk(siclk), | |
| 2155 | .soclk(soclk)); | |
| 2156 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_3 (.scan_in (reg_addr_b_3_scanin), .scan_out(reg_addr_b_3_scanout), | |
| 2157 | .latout(addr_b[3]), .latout_l(reg_addr_b_3_unused), .l1clk(l1clk_in), .d(index_a[3]), | |
| 2158 | .siclk(siclk), | |
| 2159 | .soclk(soclk)); | |
| 2160 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_2 (.scan_in (reg_addr_b_2_scanin), .scan_out(reg_addr_b_2_scanout), | |
| 2161 | .latout(addr_b[2]), .latout_l(reg_addr_b_2_unused), .l1clk(l1clk_in), .d(index_a[2]), | |
| 2162 | .siclk(siclk), | |
| 2163 | .soclk(soclk)); | |
| 2164 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_1 (.scan_in (reg_addr_b_1_scanin), .scan_out(reg_addr_b_1_scanout), | |
| 2165 | .latout(addr_b[1]), .latout_l(reg_addr_b_1_unused), .l1clk(l1clk_in), .d(index_a[1]), | |
| 2166 | .siclk(siclk), | |
| 2167 | .soclk(soclk)); | |
| 2168 | ||
| 2169 | n2_l2t_quad_tisram_msff_macro__width_1 reg_addr_b_0 (.scan_in (reg_addr_b_0_scanin), .scan_out(reg_addr_b_0_scanout), | |
| 2170 | .latout(addr_b[0]), .latout_l(reg_addr_b_0_unused), .l1clk(l1clk_in), .d(index_a[0]), | |
| 2171 | .siclk(siclk), | |
| 2172 | .soclk(soclk)); | |
| 2173 | ||
| 2174 | n2_l2t_quad_tisram_msff_macro__width_2 reg_wr_way_b ( | |
| 2175 | .scan_in (reg_wr_way_b_scanin), | |
| 2176 | .scan_out(reg_wr_way_b_scanout), | |
| 2177 | .latout (wr_way_b[1:0]), | |
| 2178 | .latout_l(wr_way_b_l[1:0]), | |
| 2179 | .l1clk(l1clk_in), | |
| 2180 | .d(way_a[1:0]), | |
| 2181 | .siclk(siclk), | |
| 2182 | .soclk(soclk)); | |
| 2183 | ||
| 2184 | n2_l2t_quad_tisram_msff_macro__width_1 reg_wr_en_b ( | |
| 2185 | .scan_in (reg_wr_en_b_scanin), | |
| 2186 | .scan_out(reg_wr_en_b_scanout), | |
| 2187 | .latout(wr_en_b), | |
| 2188 | .latout_l(reg_wr_en_b_unused), | |
| 2189 | .l1clk(l1clk_in), | |
| 2190 | .d(wr_en_a), | |
| 2191 | .siclk(siclk), | |
| 2192 | .soclk(soclk)); | |
| 2193 | ||
| 2194 | n2_l2t_quad_tisram_msff_macro__width_1 reg_rd_en_b ( | |
| 2195 | .scan_in (reg_rd_en_b_scanin), | |
| 2196 | .scan_out(reg_rd_en_b_scanout), | |
| 2197 | .latout(rd_en_b), | |
| 2198 | .latout_l(reg_rd_en_b_unused), | |
| 2199 | .l1clk(l1clk_in), | |
| 2200 | .d(rd_en_a), | |
| 2201 | .siclk(siclk), | |
| 2202 | .soclk(soclk)); | |
| 2203 | ||
| 2204 | n2_l2t_quad_msff_ctl_macro__width_1 reg_wr_en_a ( | |
| 2205 | .scan_in(reg_wr_en_a_scanin), | |
| 2206 | .scan_out(reg_wr_en_a_scanout), | |
| 2207 | .dout(wr_en_d1_a), | |
| 2208 | .l1clk(l1clk_in), | |
| 2209 | .din(wr_en_a), | |
| 2210 | .siclk(siclk), | |
| 2211 | .soclk(soclk)); | |
| 2212 | ||
| 2213 | n2_l2t_quad_msff_ctl_macro__width_1 reg_rd_en_a ( | |
| 2214 | .scan_in(reg_rd_en_a_scanin), | |
| 2215 | .scan_out(reg_rd_en_a_scanout), | |
| 2216 | .dout(rd_en_d1_a), | |
| 2217 | .l1clk(l1clk_in), | |
| 2218 | .din(rd_en_a), | |
| 2219 | .siclk(siclk), | |
| 2220 | .soclk(soclk)); | |
| 2221 | ||
| 2222 | //----------------------------------------------------------- | |
| 2223 | // output | |
| 2224 | //----------------------------------------------------------- | |
| 2225 | ||
| 2226 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_27 (.scan_in(reg_tag_way1_27_scanin), .scan_out(reg_tag_way1_27_scanout), | |
| 2227 | .din(sao_mx1[27]), .dout(tag_way1[27]), .l1clk(l1clk_out0), | |
| 2228 | .siclk(siclk), | |
| 2229 | .soclk(soclk)); | |
| 2230 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_27 (.scan_in(reg_tag_way0_27_scanin), .scan_out(reg_tag_way0_27_scanout), | |
| 2231 | .din(sao_mx0[27]), .dout(tag_way0[27]), .l1clk(l1clk_out0), | |
| 2232 | .siclk(siclk), | |
| 2233 | .soclk(soclk)); | |
| 2234 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_26 (.scan_in(reg_tag_way1_26_scanin), .scan_out(reg_tag_way1_26_scanout), | |
| 2235 | .din(sao_mx1[26]), .dout(tag_way1[26]), .l1clk(l1clk_out0), | |
| 2236 | .siclk(siclk), | |
| 2237 | .soclk(soclk)); | |
| 2238 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_26 (.scan_in(reg_tag_way0_26_scanin), .scan_out(reg_tag_way0_26_scanout), | |
| 2239 | .din(sao_mx0[26]), .dout(tag_way0[26]), .l1clk(l1clk_out0), | |
| 2240 | .siclk(siclk), | |
| 2241 | .soclk(soclk)); | |
| 2242 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_25 (.scan_in(reg_tag_way1_25_scanin), .scan_out(reg_tag_way1_25_scanout), | |
| 2243 | .din(sao_mx1[25]), .dout(tag_way1[25]), .l1clk(l1clk_out0), | |
| 2244 | .siclk(siclk), | |
| 2245 | .soclk(soclk)); | |
| 2246 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_25 (.scan_in(reg_tag_way0_25_scanin), .scan_out(reg_tag_way0_25_scanout), | |
| 2247 | .din(sao_mx0[25]), .dout(tag_way0[25]), .l1clk(l1clk_out0), | |
| 2248 | .siclk(siclk), | |
| 2249 | .soclk(soclk)); | |
| 2250 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_24 (.scan_in(reg_tag_way1_24_scanin), .scan_out(reg_tag_way1_24_scanout), | |
| 2251 | .din(sao_mx1[24]), .dout(tag_way1[24]), .l1clk(l1clk_out0), | |
| 2252 | .siclk(siclk), | |
| 2253 | .soclk(soclk)); | |
| 2254 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_24 (.scan_in(reg_tag_way0_24_scanin), .scan_out(reg_tag_way0_24_scanout), | |
| 2255 | .din(sao_mx0[24]), .dout(tag_way0[24]), .l1clk(l1clk_out0), | |
| 2256 | .siclk(siclk), | |
| 2257 | .soclk(soclk)); | |
| 2258 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_23 (.scan_in(reg_tag_way1_23_scanin), .scan_out(reg_tag_way1_23_scanout), | |
| 2259 | .din(sao_mx1[23]), .dout(tag_way1[23]), .l1clk(l1clk_out0), | |
| 2260 | .siclk(siclk), | |
| 2261 | .soclk(soclk)); | |
| 2262 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_23 (.scan_in(reg_tag_way0_23_scanin), .scan_out(reg_tag_way0_23_scanout), | |
| 2263 | .din(sao_mx0[23]), .dout(tag_way0[23]), .l1clk(l1clk_out0), | |
| 2264 | .siclk(siclk), | |
| 2265 | .soclk(soclk)); | |
| 2266 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_22 (.scan_in(reg_tag_way1_22_scanin), .scan_out(reg_tag_way1_22_scanout), | |
| 2267 | .din(sao_mx1[22]), .dout(tag_way1[22]), .l1clk(l1clk_out0), | |
| 2268 | .siclk(siclk), | |
| 2269 | .soclk(soclk)); | |
| 2270 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_22 (.scan_in(reg_tag_way0_22_scanin), .scan_out(reg_tag_way0_22_scanout), | |
| 2271 | .din(sao_mx0[22]), .dout(tag_way0[22]), .l1clk(l1clk_out0), | |
| 2272 | .siclk(siclk), | |
| 2273 | .soclk(soclk)); | |
| 2274 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_21 (.scan_in(reg_tag_way1_21_scanin), .scan_out(reg_tag_way1_21_scanout), | |
| 2275 | .din(sao_mx1[21]), .dout(tag_way1[21]), .l1clk(l1clk_out0), | |
| 2276 | .siclk(siclk), | |
| 2277 | .soclk(soclk)); | |
| 2278 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_21 (.scan_in(reg_tag_way0_21_scanin), .scan_out(reg_tag_way0_21_scanout), | |
| 2279 | .din(sao_mx0[21]), .dout(tag_way0[21]), .l1clk(l1clk_out0), | |
| 2280 | .siclk(siclk), | |
| 2281 | .soclk(soclk)); | |
| 2282 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_20 (.scan_in(reg_tag_way1_20_scanin), .scan_out(reg_tag_way1_20_scanout), | |
| 2283 | .din(sao_mx1[20]), .dout(tag_way1[20]), .l1clk(l1clk_out0), | |
| 2284 | .siclk(siclk), | |
| 2285 | .soclk(soclk)); | |
| 2286 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_20 (.scan_in(reg_tag_way0_20_scanin), .scan_out(reg_tag_way0_20_scanout), | |
| 2287 | .din(sao_mx0[20]), .dout(tag_way0[20]), .l1clk(l1clk_out0), | |
| 2288 | .siclk(siclk), | |
| 2289 | .soclk(soclk)); | |
| 2290 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_19 (.scan_in(reg_tag_way1_19_scanin), .scan_out(reg_tag_way1_19_scanout), | |
| 2291 | .din(sao_mx1[19]), .dout(tag_way1[19]), .l1clk(l1clk_out0), | |
| 2292 | .siclk(siclk), | |
| 2293 | .soclk(soclk)); | |
| 2294 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_19 (.scan_in(reg_tag_way0_19_scanin), .scan_out(reg_tag_way0_19_scanout), | |
| 2295 | .din(sao_mx0[19]), .dout(tag_way0[19]), .l1clk(l1clk_out0), | |
| 2296 | .siclk(siclk), | |
| 2297 | .soclk(soclk)); | |
| 2298 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_18 (.scan_in(reg_tag_way1_18_scanin), .scan_out(reg_tag_way1_18_scanout), | |
| 2299 | .din(sao_mx1[18]), .dout(tag_way1[18]), .l1clk(l1clk_out0), | |
| 2300 | .siclk(siclk), | |
| 2301 | .soclk(soclk)); | |
| 2302 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_18 (.scan_in(reg_tag_way0_18_scanin), .scan_out(reg_tag_way0_18_scanout), | |
| 2303 | .din(sao_mx0[18]), .dout(tag_way0[18]), .l1clk(l1clk_out0), | |
| 2304 | .siclk(siclk), | |
| 2305 | .soclk(soclk)); | |
| 2306 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_17 (.scan_in(reg_tag_way1_17_scanin), .scan_out(reg_tag_way1_17_scanout), | |
| 2307 | .din(sao_mx1[17]), .dout(tag_way1[17]), .l1clk(l1clk_out0), | |
| 2308 | .siclk(siclk), | |
| 2309 | .soclk(soclk)); | |
| 2310 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_17 (.scan_in(reg_tag_way0_17_scanin), .scan_out(reg_tag_way0_17_scanout), | |
| 2311 | .din(sao_mx0[17]), .dout(tag_way0[17]), .l1clk(l1clk_out0), | |
| 2312 | .siclk(siclk), | |
| 2313 | .soclk(soclk)); | |
| 2314 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_16 (.scan_in(reg_tag_way1_16_scanin), .scan_out(reg_tag_way1_16_scanout), | |
| 2315 | .din(sao_mx1[16]), .dout(tag_way1[16]), .l1clk(l1clk_out0), | |
| 2316 | .siclk(siclk), | |
| 2317 | .soclk(soclk)); | |
| 2318 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_16 (.scan_in(reg_tag_way0_16_scanin), .scan_out(reg_tag_way0_16_scanout), | |
| 2319 | .din(sao_mx0[16]), .dout(tag_way0[16]), .l1clk(l1clk_out0), | |
| 2320 | .siclk(siclk), | |
| 2321 | .soclk(soclk)); | |
| 2322 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_15 (.scan_in(reg_tag_way1_15_scanin), .scan_out(reg_tag_way1_15_scanout), | |
| 2323 | .din(sao_mx1[15]), .dout(tag_way1[15]), .l1clk(l1clk_out0), | |
| 2324 | .siclk(siclk), | |
| 2325 | .soclk(soclk)); | |
| 2326 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_15 (.scan_in(reg_tag_way0_15_scanin), .scan_out(reg_tag_way0_15_scanout), | |
| 2327 | .din(sao_mx0[15]), .dout(tag_way0[15]), .l1clk(l1clk_out0), | |
| 2328 | .siclk(siclk), | |
| 2329 | .soclk(soclk)); | |
| 2330 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_14 (.scan_in(reg_tag_way1_14_scanin), .scan_out(reg_tag_way1_14_scanout), | |
| 2331 | .din(sao_mx1[14]), .dout(tag_way1[14]), .l1clk(l1clk_out0), | |
| 2332 | .siclk(siclk), | |
| 2333 | .soclk(soclk)); | |
| 2334 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_14 (.scan_in(reg_tag_way0_14_scanin), .scan_out(reg_tag_way0_14_scanout), | |
| 2335 | .din(sao_mx0[14]), .dout(tag_way0[14]), .l1clk(l1clk_out0), | |
| 2336 | .siclk(siclk), | |
| 2337 | .soclk(soclk)); | |
| 2338 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_13 (.scan_in(reg_tag_way1_13_scanin), .scan_out(reg_tag_way1_13_scanout), | |
| 2339 | .din(sao_mx1[13]), .dout(tag_way1[13]), .l1clk(l1clk_out0), | |
| 2340 | .siclk(siclk), | |
| 2341 | .soclk(soclk)); | |
| 2342 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_13 (.scan_in(reg_tag_way0_13_scanin), .scan_out(reg_tag_way0_13_scanout), | |
| 2343 | .din(sao_mx0[13]), .dout(tag_way0[13]), .l1clk(l1clk_out0), | |
| 2344 | .siclk(siclk), | |
| 2345 | .soclk(soclk)); | |
| 2346 | ||
| 2347 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_12 (.scan_in(reg_tag_way1_12_scanin), .scan_out(reg_tag_way1_12_scanout), | |
| 2348 | .din(sao_mx1[12]), .dout(tag_way1[12]), .l1clk(l1clk_out1), | |
| 2349 | .siclk(siclk), | |
| 2350 | .soclk(soclk)); | |
| 2351 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_12 (.scan_in(reg_tag_way0_12_scanin), .scan_out(reg_tag_way0_12_scanout), | |
| 2352 | .din(sao_mx0[12]), .dout(tag_way0[12]), .l1clk(l1clk_out1), | |
| 2353 | .siclk(siclk), | |
| 2354 | .soclk(soclk)); | |
| 2355 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_11 (.scan_in(reg_tag_way1_11_scanin), .scan_out(reg_tag_way1_11_scanout), | |
| 2356 | .din(sao_mx1[11]), .dout(tag_way1[11]), .l1clk(l1clk_out1), | |
| 2357 | .siclk(siclk), | |
| 2358 | .soclk(soclk)); | |
| 2359 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_11 (.scan_in(reg_tag_way0_11_scanin), .scan_out(reg_tag_way0_11_scanout), | |
| 2360 | .din(sao_mx0[11]), .dout(tag_way0[11]), .l1clk(l1clk_out1), | |
| 2361 | .siclk(siclk), | |
| 2362 | .soclk(soclk)); | |
| 2363 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_10 (.scan_in(reg_tag_way1_10_scanin), .scan_out(reg_tag_way1_10_scanout), | |
| 2364 | .din(sao_mx1[10]), .dout(tag_way1[10]), .l1clk(l1clk_out1), | |
| 2365 | .siclk(siclk), | |
| 2366 | .soclk(soclk)); | |
| 2367 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_10 (.scan_in(reg_tag_way0_10_scanin), .scan_out(reg_tag_way0_10_scanout), | |
| 2368 | .din(sao_mx0[10]), .dout(tag_way0[10]), .l1clk(l1clk_out1), | |
| 2369 | .siclk(siclk), | |
| 2370 | .soclk(soclk)); | |
| 2371 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_9 (.scan_in(reg_tag_way1_9_scanin), .scan_out(reg_tag_way1_9_scanout), | |
| 2372 | .din(sao_mx1[9]), .dout(tag_way1[9]), .l1clk(l1clk_out1), | |
| 2373 | .siclk(siclk), | |
| 2374 | .soclk(soclk)); | |
| 2375 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_9 (.scan_in(reg_tag_way0_9_scanin), .scan_out(reg_tag_way0_9_scanout), | |
| 2376 | .din(sao_mx0[9]), .dout(tag_way0[9]), .l1clk(l1clk_out1), | |
| 2377 | .siclk(siclk), | |
| 2378 | .soclk(soclk)); | |
| 2379 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_8 (.scan_in(reg_tag_way1_8_scanin), .scan_out(reg_tag_way1_8_scanout), | |
| 2380 | .din(sao_mx1[8]), .dout(tag_way1[8]), .l1clk(l1clk_out1), | |
| 2381 | .siclk(siclk), | |
| 2382 | .soclk(soclk)); | |
| 2383 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_8 (.scan_in(reg_tag_way0_8_scanin), .scan_out(reg_tag_way0_8_scanout), | |
| 2384 | .din(sao_mx0[8]), .dout(tag_way0[8]), .l1clk(l1clk_out1), | |
| 2385 | .siclk(siclk), | |
| 2386 | .soclk(soclk)); | |
| 2387 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_7 (.scan_in(reg_tag_way1_7_scanin), .scan_out(reg_tag_way1_7_scanout), | |
| 2388 | .din(sao_mx1[7]), .dout(tag_way1[7]), .l1clk(l1clk_out1), | |
| 2389 | .siclk(siclk), | |
| 2390 | .soclk(soclk)); | |
| 2391 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_7 (.scan_in(reg_tag_way0_7_scanin), .scan_out(reg_tag_way0_7_scanout), | |
| 2392 | .din(sao_mx0[7]), .dout(tag_way0[7]), .l1clk(l1clk_out1), | |
| 2393 | .siclk(siclk), | |
| 2394 | .soclk(soclk)); | |
| 2395 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_6 (.scan_in(reg_tag_way1_6_scanin), .scan_out(reg_tag_way1_6_scanout), | |
| 2396 | .din(sao_mx1[6]), .dout(tag_way1[6]), .l1clk(l1clk_out1), | |
| 2397 | .siclk(siclk), | |
| 2398 | .soclk(soclk)); | |
| 2399 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_6 (.scan_in(reg_tag_way0_6_scanin), .scan_out(reg_tag_way0_6_scanout), | |
| 2400 | .din(sao_mx0[6]), .dout(tag_way0[6]), .l1clk(l1clk_out1), | |
| 2401 | .siclk(siclk), | |
| 2402 | .soclk(soclk)); | |
| 2403 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_5 (.scan_in(reg_tag_way1_5_scanin), .scan_out(reg_tag_way1_5_scanout), | |
| 2404 | .din(sao_mx1[5]), .dout(tag_way1[5]), .l1clk(l1clk_out1), | |
| 2405 | .siclk(siclk), | |
| 2406 | .soclk(soclk)); | |
| 2407 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_5 (.scan_in(reg_tag_way0_5_scanin), .scan_out(reg_tag_way0_5_scanout), | |
| 2408 | .din(sao_mx0[5]), .dout(tag_way0[5]), .l1clk(l1clk_out1), | |
| 2409 | .siclk(siclk), | |
| 2410 | .soclk(soclk)); | |
| 2411 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_4 (.scan_in(reg_tag_way1_4_scanin), .scan_out(reg_tag_way1_4_scanout), | |
| 2412 | .din(sao_mx1[4]), .dout(tag_way1[4]), .l1clk(l1clk_out1), | |
| 2413 | .siclk(siclk), | |
| 2414 | .soclk(soclk)); | |
| 2415 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_4 (.scan_in(reg_tag_way0_4_scanin), .scan_out(reg_tag_way0_4_scanout), | |
| 2416 | .din(sao_mx0[4]), .dout(tag_way0[4]), .l1clk(l1clk_out1), | |
| 2417 | .siclk(siclk), | |
| 2418 | .soclk(soclk)); | |
| 2419 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_3 (.scan_in(reg_tag_way1_3_scanin), .scan_out(reg_tag_way1_3_scanout), | |
| 2420 | .din(sao_mx1[3]), .dout(tag_way1[3]), .l1clk(l1clk_out1), | |
| 2421 | .siclk(siclk), | |
| 2422 | .soclk(soclk)); | |
| 2423 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_3 (.scan_in(reg_tag_way0_3_scanin), .scan_out(reg_tag_way0_3_scanout), | |
| 2424 | .din(sao_mx0[3]), .dout(tag_way0[3]), .l1clk(l1clk_out1), | |
| 2425 | .siclk(siclk), | |
| 2426 | .soclk(soclk)); | |
| 2427 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_2 (.scan_in(reg_tag_way1_2_scanin), .scan_out(reg_tag_way1_2_scanout), | |
| 2428 | .din(sao_mx1[2]), .dout(tag_way1[2]), .l1clk(l1clk_out1), | |
| 2429 | .siclk(siclk), | |
| 2430 | .soclk(soclk)); | |
| 2431 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_2 (.scan_in(reg_tag_way0_2_scanin), .scan_out(reg_tag_way0_2_scanout), | |
| 2432 | .din(sao_mx0[2]), .dout(tag_way0[2]), .l1clk(l1clk_out1), | |
| 2433 | .siclk(siclk), | |
| 2434 | .soclk(soclk)); | |
| 2435 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_1 (.scan_in(reg_tag_way1_1_scanin), .scan_out(reg_tag_way1_1_scanout), | |
| 2436 | .din(sao_mx1[1]), .dout(tag_way1[1]), .l1clk(l1clk_out1), | |
| 2437 | .siclk(siclk), | |
| 2438 | .soclk(soclk)); | |
| 2439 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_1 (.scan_in(reg_tag_way0_1_scanin), .scan_out(reg_tag_way0_1_scanout), | |
| 2440 | .din(sao_mx0[1]), .dout(tag_way0[1]), .l1clk(l1clk_out1), | |
| 2441 | .siclk(siclk), | |
| 2442 | .soclk(soclk)); | |
| 2443 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way1_0 (.scan_in(reg_tag_way1_0_scanin), .scan_out(reg_tag_way1_0_scanout), | |
| 2444 | .din(sao_mx1[0]), .dout(tag_way1[0]), .l1clk(l1clk_out1), | |
| 2445 | .siclk(siclk), | |
| 2446 | .soclk(soclk)); | |
| 2447 | n2_l2t_quad_msff_ctl_macro__width_1 reg_tag_way0_0 (.scan_in(reg_tag_way0_0_scanin), .scan_out(reg_tag_way0_0_scanout), | |
| 2448 | .din(sao_mx0[0]), .dout(tag_way0[0]), .l1clk(l1clk_out1), | |
| 2449 | .siclk(siclk), | |
| 2450 | .soclk(soclk)); | |
| 2451 | ||
| 2452 | n2_l2t_quad_msffi_ctl_macro__clockwidth_0__width_1 reg_way_hit_a0 (.scan_in(reg_way_hit_a0_scanin), .scan_out(reg_way_hit_a0_scanout), | |
| 2453 | .din(w0_cmp27to1), .q_l(way_hit_a[0]), .l1clk(l1clk_out1), | |
| 2454 | .siclk(siclk), | |
| 2455 | .soclk(soclk)); | |
| 2456 | n2_l2t_quad_msffi_ctl_macro__clockwidth_0__width_1 reg_way_hit_a1 (.scan_in(reg_way_hit_a1_scanin), .scan_out(reg_way_hit_a1_scanout), | |
| 2457 | .din(w1_cmp27to1), .q_l(way_hit_a[1]), .l1clk(l1clk_out1), | |
| 2458 | .siclk(siclk), | |
| 2459 | .soclk(soclk)); | |
| 2460 | ||
| 2461 | ||
| 2462 | // =============== VERILOG-MODE AUTO TEMPLATES | |
| 2463 | ||
| 2464 | /* | |
| 2465 | ||
| 2466 | n2_l2t_array AUTO_TEMPLATE ( | |
| 2467 | .din(din[`L2T_ARR_D_WIDTH - 1 : 0]), | |
| 2468 | .l1clk_internal_v1 (l1clk_int), | |
| 2469 | .l1clk_internal_v2 (l1clk_int), | |
| 2470 | ||
| 2471 | ); | |
| 2472 | ||
| 2473 | */ | |
| 2474 | // Manual scan hookup : | |
| 2475 | ||
| 2476 | assign reg_tag_way1_27_scanin = scan_in ; | |
| 2477 | assign reg_tag_way0_27_scanin = reg_tag_way1_27_scanout ; | |
| 2478 | assign reg_tag_way1_26_scanin = reg_tag_way0_27_scanout ; | |
| 2479 | assign reg_tag_way0_26_scanin = reg_tag_way1_26_scanout ; | |
| 2480 | assign reg_tag_way1_25_scanin = reg_tag_way0_26_scanout ; | |
| 2481 | assign reg_tag_way0_25_scanin = reg_tag_way1_25_scanout ; | |
| 2482 | assign reg_tag_way1_24_scanin = reg_tag_way0_25_scanout ; | |
| 2483 | assign reg_tag_way0_24_scanin = reg_tag_way1_24_scanout ; | |
| 2484 | assign reg_tag_way1_23_scanin = reg_tag_way0_24_scanout ; | |
| 2485 | assign reg_tag_way0_23_scanin = reg_tag_way1_23_scanout ; | |
| 2486 | assign reg_tag_way1_22_scanin = reg_tag_way0_23_scanout ; | |
| 2487 | assign reg_tag_way0_22_scanin = reg_tag_way1_22_scanout ; | |
| 2488 | assign reg_tag_way1_21_scanin = reg_tag_way0_22_scanout ; | |
| 2489 | assign reg_tag_way0_21_scanin = reg_tag_way1_21_scanout ; | |
| 2490 | assign reg_tag_way1_20_scanin = reg_tag_way0_21_scanout ; | |
| 2491 | assign reg_tag_way0_20_scanin = reg_tag_way1_20_scanout ; | |
| 2492 | assign reg_tag_way1_19_scanin = reg_tag_way0_20_scanout ; | |
| 2493 | assign reg_tag_way0_19_scanin = reg_tag_way1_19_scanout ; | |
| 2494 | assign reg_tag_way1_18_scanin = reg_tag_way0_19_scanout ; | |
| 2495 | assign reg_tag_way0_18_scanin = reg_tag_way1_18_scanout ; | |
| 2496 | assign reg_tag_way1_17_scanin = reg_tag_way0_18_scanout ; | |
| 2497 | assign reg_tag_way0_17_scanin = reg_tag_way1_17_scanout ; | |
| 2498 | assign reg_tag_way1_16_scanin = reg_tag_way0_17_scanout ; | |
| 2499 | assign reg_tag_way0_16_scanin = reg_tag_way1_16_scanout ; | |
| 2500 | assign reg_tag_way1_15_scanin = reg_tag_way0_16_scanout ; | |
| 2501 | assign reg_tag_way0_15_scanin = reg_tag_way1_15_scanout ; | |
| 2502 | assign reg_tag_way1_14_scanin = reg_tag_way0_15_scanout ; | |
| 2503 | assign reg_tag_way0_14_scanin = reg_tag_way1_14_scanout ; | |
| 2504 | assign reg_tag_way1_13_scanin = reg_tag_way0_14_scanout ; | |
| 2505 | assign reg_tag_way0_13_scanin = reg_tag_way1_13_scanout ; | |
| 2506 | ||
| 2507 | ||
| 2508 | assign reg_way_hit_a0_scanin = reg_tag_way0_13_scanout ; | |
| 2509 | assign reg_way_hit_a1_scanin = reg_way_hit_a0_scanout ; | |
| 2510 | ||
| 2511 | assign reg_addr_b_8_scanin = reg_way_hit_a1_scanout ; | |
| 2512 | assign reg_addr_b_7_scanin = reg_addr_b_8_scanout ; | |
| 2513 | assign reg_addr_b_6_scanin = reg_addr_b_7_scanout ; | |
| 2514 | assign reg_addr_b_5_scanin = reg_addr_b_6_scanout ; | |
| 2515 | assign reg_addr_b_4_scanin = reg_addr_b_5_scanout ; | |
| 2516 | assign reg_addr_b_3_scanin = reg_addr_b_4_scanout ; | |
| 2517 | assign reg_addr_b_2_scanin = reg_addr_b_3_scanout ; | |
| 2518 | assign reg_addr_b_1_scanin = reg_addr_b_2_scanout ; | |
| 2519 | ||
| 2520 | assign reg_wr_way_b_scanin = reg_addr_b_1_scanout ; | |
| 2521 | assign reg_addr_b_0_scanin = reg_wr_way_b_scanout ; | |
| 2522 | assign reg_wr_en_b_scanin = reg_addr_b_0_scanout ; | |
| 2523 | assign reg_rd_en_b_scanin = reg_wr_en_b_scanout ; | |
| 2524 | assign reg_wr_en_a_scanin = reg_rd_en_b_scanout ; | |
| 2525 | assign reg_rd_en_a_scanin = reg_wr_en_a_scanout ; | |
| 2526 | ||
| 2527 | assign reg_tag_way1_12_scanin = reg_rd_en_a_scanout ; | |
| 2528 | assign reg_tag_way0_12_scanin = reg_tag_way1_12_scanout ; | |
| 2529 | assign reg_tag_way1_11_scanin = reg_tag_way0_12_scanout ; | |
| 2530 | assign reg_tag_way0_11_scanin = reg_tag_way1_11_scanout ; | |
| 2531 | assign reg_tag_way1_10_scanin = reg_tag_way0_11_scanout ; | |
| 2532 | assign reg_tag_way0_10_scanin = reg_tag_way1_10_scanout ; | |
| 2533 | assign reg_tag_way1_9_scanin = reg_tag_way0_10_scanout ; | |
| 2534 | assign reg_tag_way0_9_scanin = reg_tag_way1_9_scanout ; | |
| 2535 | assign reg_tag_way1_8_scanin = reg_tag_way0_9_scanout ; | |
| 2536 | assign reg_tag_way0_8_scanin = reg_tag_way1_8_scanout ; | |
| 2537 | assign reg_tag_way1_7_scanin = reg_tag_way0_8_scanout ; | |
| 2538 | assign reg_tag_way0_7_scanin = reg_tag_way1_7_scanout ; | |
| 2539 | assign reg_tag_way1_6_scanin = reg_tag_way0_7_scanout ; | |
| 2540 | assign reg_tag_way0_6_scanin = reg_tag_way1_6_scanout ; | |
| 2541 | assign reg_tag_way1_5_scanin = reg_tag_way0_6_scanout ; | |
| 2542 | assign reg_tag_way0_5_scanin = reg_tag_way1_5_scanout ; | |
| 2543 | assign reg_tag_way1_4_scanin = reg_tag_way0_5_scanout ; | |
| 2544 | assign reg_tag_way0_4_scanin = reg_tag_way1_4_scanout ; | |
| 2545 | assign reg_tag_way1_3_scanin = reg_tag_way0_4_scanout ; | |
| 2546 | assign reg_tag_way0_3_scanin = reg_tag_way1_3_scanout ; | |
| 2547 | assign reg_tag_way1_2_scanin = reg_tag_way0_3_scanout ; | |
| 2548 | assign reg_tag_way0_2_scanin = reg_tag_way1_2_scanout ; | |
| 2549 | assign reg_tag_way1_1_scanin = reg_tag_way0_2_scanout ; | |
| 2550 | assign reg_tag_way0_1_scanin = reg_tag_way1_1_scanout ; | |
| 2551 | assign reg_tag_way1_0_scanin = reg_tag_way0_1_scanout ; | |
| 2552 | assign reg_tag_way0_0_scanin = reg_tag_way1_0_scanout ; | |
| 2553 | ||
| 2554 | assign scan_out = reg_tag_way0_0_scanout ; | |
| 2555 | endmodule | |
| 2556 | ||
| 2557 | ||
| 2558 | ||
| 2559 | ||
| 2560 | // | |
| 2561 | // nor macro for ports = 2,3 | |
| 2562 | // | |
| 2563 | // | |
| 2564 | ||
| 2565 | ||
| 2566 | ||
| 2567 | ||
| 2568 | ||
| 2569 | module n2_l2t_quad_nor_macro__ports_3__width_1 ( | |
| 2570 | din0, | |
| 2571 | din1, | |
| 2572 | din2, | |
| 2573 | dout); | |
| 2574 | input [0:0] din0; | |
| 2575 | input [0:0] din1; | |
| 2576 | input [0:0] din2; | |
| 2577 | output [0:0] dout; | |
| 2578 | ||
| 2579 | ||
| 2580 | ||
| 2581 | ||
| 2582 | ||
| 2583 | ||
| 2584 | nor3 #(1) d0_0 ( | |
| 2585 | .in0(din0[0:0]), | |
| 2586 | .in1(din1[0:0]), | |
| 2587 | .in2(din2[0:0]), | |
| 2588 | .out(dout[0:0]) | |
| 2589 | ); | |
| 2590 | ||
| 2591 | ||
| 2592 | ||
| 2593 | ||
| 2594 | ||
| 2595 | ||
| 2596 | ||
| 2597 | endmodule | |
| 2598 | ||
| 2599 | ||
| 2600 | ||
| 2601 | ||
| 2602 | ||
| 2603 | // | |
| 2604 | // nand macro for ports = 2,3,4 | |
| 2605 | // | |
| 2606 | // | |
| 2607 | ||
| 2608 | ||
| 2609 | ||
| 2610 | ||
| 2611 | ||
| 2612 | module n2_l2t_quad_nand_macro__ports_4__width_1 ( | |
| 2613 | din0, | |
| 2614 | din1, | |
| 2615 | din2, | |
| 2616 | din3, | |
| 2617 | dout); | |
| 2618 | input [0:0] din0; | |
| 2619 | input [0:0] din1; | |
| 2620 | input [0:0] din2; | |
| 2621 | input [0:0] din3; | |
| 2622 | output [0:0] dout; | |
| 2623 | ||
| 2624 | ||
| 2625 | ||
| 2626 | ||
| 2627 | ||
| 2628 | ||
| 2629 | nand4 #(1) d0_0 ( | |
| 2630 | .in0(din0[0:0]), | |
| 2631 | .in1(din1[0:0]), | |
| 2632 | .in2(din2[0:0]), | |
| 2633 | .in3(din3[0:0]), | |
| 2634 | .out(dout[0:0]) | |
| 2635 | ); | |
| 2636 | ||
| 2637 | ||
| 2638 | ||
| 2639 | ||
| 2640 | ||
| 2641 | ||
| 2642 | ||
| 2643 | ||
| 2644 | ||
| 2645 | endmodule | |
| 2646 | ||
| 2647 | ||
| 2648 | ||
| 2649 | ||
| 2650 | ||
| 2651 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 2652 | // also for pass-gate with decoder | |
| 2653 | ||
| 2654 | ||
| 2655 | ||
| 2656 | ||
| 2657 | ||
| 2658 | // any PARAMS parms go into naming of macro | |
| 2659 | ||
| 2660 | module n2_l2t_quad_mux_macro__mux_aonpe__ports_2__stack_156c__width_5 ( | |
| 2661 | din0, | |
| 2662 | sel0, | |
| 2663 | din1, | |
| 2664 | sel1, | |
| 2665 | dout); | |
| 2666 | wire buffout0; | |
| 2667 | wire buffout1; | |
| 2668 | ||
| 2669 | input [4:0] din0; | |
| 2670 | input sel0; | |
| 2671 | input [4:0] din1; | |
| 2672 | input sel1; | |
| 2673 | output [4:0] dout; | |
| 2674 | ||
| 2675 | ||
| 2676 | ||
| 2677 | ||
| 2678 | ||
| 2679 | cl_dp1_muxbuff2_8x c0_0 ( | |
| 2680 | .in0(sel0), | |
| 2681 | .in1(sel1), | |
| 2682 | .out0(buffout0), | |
| 2683 | .out1(buffout1) | |
| 2684 | ); | |
| 2685 | mux2s #(5) d0_0 ( | |
| 2686 | .sel0(buffout0), | |
| 2687 | .sel1(buffout1), | |
| 2688 | .in0(din0[4:0]), | |
| 2689 | .in1(din1[4:0]), | |
| 2690 | .dout(dout[4:0]) | |
| 2691 | ); | |
| 2692 | ||
| 2693 | ||
| 2694 | ||
| 2695 | ||
| 2696 | ||
| 2697 | ||
| 2698 | ||
| 2699 | ||
| 2700 | ||
| 2701 | ||
| 2702 | ||
| 2703 | ||
| 2704 | ||
| 2705 | endmodule | |
| 2706 | ||
| 2707 | ||
| 2708 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 2709 | // also for pass-gate with decoder | |
| 2710 | ||
| 2711 | ||
| 2712 | ||
| 2713 | ||
| 2714 | ||
| 2715 | // any PARAMS parms go into naming of macro | |
| 2716 | ||
| 2717 | module n2_l2t_quad_mux_macro__mux_aonpe__ports_2__stack_156c__width_2 ( | |
| 2718 | din0, | |
| 2719 | sel0, | |
| 2720 | din1, | |
| 2721 | sel1, | |
| 2722 | dout); | |
| 2723 | wire buffout0; | |
| 2724 | wire buffout1; | |
| 2725 | ||
| 2726 | input [1:0] din0; | |
| 2727 | input sel0; | |
| 2728 | input [1:0] din1; | |
| 2729 | input sel1; | |
| 2730 | output [1:0] dout; | |
| 2731 | ||
| 2732 | ||
| 2733 | ||
| 2734 | ||
| 2735 | ||
| 2736 | cl_dp1_muxbuff2_8x c0_0 ( | |
| 2737 | .in0(sel0), | |
| 2738 | .in1(sel1), | |
| 2739 | .out0(buffout0), | |
| 2740 | .out1(buffout1) | |
| 2741 | ); | |
| 2742 | mux2s #(2) d0_0 ( | |
| 2743 | .sel0(buffout0), | |
| 2744 | .sel1(buffout1), | |
| 2745 | .in0(din0[1:0]), | |
| 2746 | .in1(din1[1:0]), | |
| 2747 | .dout(dout[1:0]) | |
| 2748 | ); | |
| 2749 | ||
| 2750 | ||
| 2751 | ||
| 2752 | ||
| 2753 | ||
| 2754 | ||
| 2755 | ||
| 2756 | ||
| 2757 | ||
| 2758 | ||
| 2759 | ||
| 2760 | ||
| 2761 | ||
| 2762 | endmodule | |
| 2763 | ||
| 2764 | ||
| 2765 | // | |
| 2766 | // invert macro | |
| 2767 | // | |
| 2768 | // | |
| 2769 | ||
| 2770 | ||
| 2771 | ||
| 2772 | ||
| 2773 | ||
| 2774 | module n2_l2t_quad_inv_macro__width_5 ( | |
| 2775 | din, | |
| 2776 | dout); | |
| 2777 | input [4:0] din; | |
| 2778 | output [4:0] dout; | |
| 2779 | ||
| 2780 | ||
| 2781 | ||
| 2782 | ||
| 2783 | ||
| 2784 | ||
| 2785 | inv #(5) d0_0 ( | |
| 2786 | .in(din[4:0]), | |
| 2787 | .out(dout[4:0]) | |
| 2788 | ); | |
| 2789 | ||
| 2790 | ||
| 2791 | ||
| 2792 | ||
| 2793 | ||
| 2794 | ||
| 2795 | ||
| 2796 | ||
| 2797 | ||
| 2798 | endmodule | |
| 2799 | ||
| 2800 | ||
| 2801 | ||
| 2802 | ||
| 2803 | ||
| 2804 | ||
| 2805 | ||
| 2806 | ||
| 2807 | `define L2T_ARR_D_WIDTH 28 | |
| 2808 | `define L2T_ARR_DEPTH 512 | |
| 2809 | `define WAY_HIT_WIDTH 16 | |
| 2810 | `define BADREAD BADBADD | |
| 2811 | ||
| 2812 | ||
| 2813 | `define sh_index_lft 5'b00000 | |
| 2814 | `define sh_index_rgt 5'b00000 | |
| 2815 | ||
| 2816 | module n2_l2t_array ( | |
| 2817 | din, | |
| 2818 | addr_b, | |
| 2819 | l1clk_internal_v1, | |
| 2820 | l1clk_internal_v2, | |
| 2821 | ln1clk, | |
| 2822 | ln2clk, | |
| 2823 | rd_en_b, | |
| 2824 | rd_en_d1_a, | |
| 2825 | rpda_lft, | |
| 2826 | rpda_rgt, | |
| 2827 | rpdb_lft, | |
| 2828 | rpdb_rgt, | |
| 2829 | rpdc_lft, | |
| 2830 | rpdc_rgt, | |
| 2831 | w_inhibit_l, | |
| 2832 | wr_en_b, | |
| 2833 | wr_en_d1_a, | |
| 2834 | wr_way_b, | |
| 2835 | wr_way_b_l, | |
| 2836 | vnw_ary, | |
| 2837 | sao_mx0_h, | |
| 2838 | sao_mx0_l, | |
| 2839 | sao_mx1_h, | |
| 2840 | sao_mx1_l); | |
| 2841 | wire ln1clk_unused; | |
| 2842 | wire ln2clk_unused; | |
| 2843 | wire l1clk_int_v2_unused; | |
| 2844 | wire rd_en_b_unused; | |
| 2845 | wire wr_en_b_unused; | |
| 2846 | wire [1:0] wr_way_b_unused; | |
| 2847 | wire l1clk_int; | |
| 2848 | wire rd_en; | |
| 2849 | wire [4:0] sf_l; | |
| 2850 | wire [4:0] sf_r; | |
| 2851 | wire shift_en_lft; | |
| 2852 | wire shift_en_rgt; | |
| 2853 | wire redundancy_en; | |
| 2854 | wire [4:0] sh_index_lft; | |
| 2855 | wire [4:0] sh_index_rgt; | |
| 2856 | wire mem_wr_en0; | |
| 2857 | wire mem_wr_en1; | |
| 2858 | ||
| 2859 | ||
| 2860 | // input l2clk; // cmp clock | |
| 2861 | // input iol2clk; // io clock | |
| 2862 | // input scan_in; | |
| 2863 | // input tcu_pce_ov; // scan signals | |
| 2864 | // input tcu_clk_stop; | |
| 2865 | // input tcu_aclk; | |
| 2866 | // input tcu_bclk; | |
| 2867 | // input tcu_scan_en; | |
| 2868 | // input tcu_muxtest; | |
| 2869 | // input tcu_dectest; | |
| 2870 | // output scan_out; | |
| 2871 | ||
| 2872 | ||
| 2873 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
| 2874 | input [8:0] addr_b; | |
| 2875 | input l1clk_internal_v1; | |
| 2876 | input l1clk_internal_v2; | |
| 2877 | input ln1clk; | |
| 2878 | input ln2clk; | |
| 2879 | input rd_en_b; | |
| 2880 | input rd_en_d1_a; | |
| 2881 | input [1:0] rpda_lft; | |
| 2882 | input [1:0] rpda_rgt; | |
| 2883 | input [3:0] rpdb_lft; | |
| 2884 | input [3:0] rpdb_rgt; | |
| 2885 | input [3:0] rpdc_lft; | |
| 2886 | input [3:0] rpdc_rgt; | |
| 2887 | input w_inhibit_l; | |
| 2888 | input wr_en_b; | |
| 2889 | input wr_en_d1_a; | |
| 2890 | input [1:0] wr_way_b; | |
| 2891 | input [1:0] wr_way_b_l; | |
| 2892 | ||
| 2893 | // Added vnw_ary pin for n2 for 2.0 | |
| 2894 | ||
| 2895 | input vnw_ary; | |
| 2896 | ||
| 2897 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_h; | |
| 2898 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_l; | |
| 2899 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_h; | |
| 2900 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_l; | |
| 2901 | ||
| 2902 | ||
| 2903 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_lft[`L2T_ARR_DEPTH - 1 :0]; //one extra bit for redundancy | |
| 2904 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_rgt[`L2T_ARR_DEPTH - 1 :0]; | |
| 2905 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_lft_reg ; | |
| 2906 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_rgt_reg ; // one entry of the memonry | |
| 2907 | ||
| 2908 | ||
| 2909 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_data_lft; | |
| 2910 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_data_rgt; | |
| 2911 | ||
| 2912 | reg [14:0] rdata0_lft; | |
| 2913 | reg [14:0] rdata1_lft; | |
| 2914 | reg [0:12] rdata0_rgt; | |
| 2915 | reg [0:12] rdata1_rgt; | |
| 2916 | reg [30:0] wdata_lft; | |
| 2917 | reg [30:0] wdata_rgt; | |
| 2918 | reg [29:0] tmp_lft; | |
| 2919 | reg [25:0] tmp_rgt; | |
| 2920 | ||
| 2921 | wire [14:0] mem0_lft; | |
| 2922 | wire [14:0] mem1_lft; | |
| 2923 | wire [12:0] mem0_rgt; | |
| 2924 | wire [12:0] mem1_rgt; | |
| 2925 | wire [30:0] mem_all_lft; | |
| 2926 | wire [26:0] mem_all_rgt; | |
| 2927 | wire [30:0] rdata_out_lft; | |
| 2928 | wire [26:0] rdata_out_rgt; | |
| 2929 | integer i; | |
| 2930 | integer j; | |
| 2931 | integer l; | |
| 2932 | integer k; | |
| 2933 | ||
| 2934 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_h ; | |
| 2935 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_l ; | |
| 2936 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_h ; | |
| 2937 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_l ; | |
| 2938 | ||
| 2939 | wire [`L2T_ARR_D_WIDTH - 1:0] rdata0_out ; | |
| 2940 | wire [`L2T_ARR_D_WIDTH - 1:0] rdata1_out ; | |
| 2941 | //----------------------------------------------------------------- | |
| 2942 | // INITIALIZE MEMORY | |
| 2943 | //----------------------------------------------------------------- | |
| 2944 | `ifndef NOINITMEM | |
| 2945 | initial begin | |
| 2946 | for (i = 0; i < `L2T_ARR_DEPTH - 1; i = i + 1) | |
| 2947 | begin | |
| 2948 | mem_rgt[i]=27'h0; | |
| 2949 | mem_lft[i]=31'h0; | |
| 2950 | end | |
| 2951 | end | |
| 2952 | `endif | |
| 2953 | ||
| 2954 | ||
| 2955 | //----------------------------------------------------------------- | |
| 2956 | // UNUSED SIGNALS | |
| 2957 | //----------------------------------------------------------------- | |
| 2958 | assign ln1clk_unused = ln1clk; | |
| 2959 | assign ln2clk_unused = ln2clk; | |
| 2960 | assign l1clk_int_v2_unused = l1clk_internal_v2; | |
| 2961 | assign rd_en_b_unused = rd_en_b; | |
| 2962 | assign wr_en_b_unused = wr_en_b; | |
| 2963 | assign wr_way_b_unused[1:0] = wr_way_b_l[1:0]; | |
| 2964 | ||
| 2965 | ||
| 2966 | assign l1clk_int = l1clk_internal_v1; | |
| 2967 | ||
| 2968 | //----------------------------------------------------------------- | |
| 2969 | // OUTPUTS | |
| 2970 | //----------------------------------------------------------------- | |
| 2971 | // | |
| 2972 | //always @ (l1clk_int or rd_en) | |
| 2973 | // if (l1clk_int || ~rd_en) | |
| 2974 | // begin | |
| 2975 | // sao_mx0_h [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2976 | // sao_mx0_l [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2977 | // sao_mx1_h [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2978 | // sao_mx1_l [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2979 | // end | |
| 2980 | // | |
| 2981 | //----------------------------------------------------------------- | |
| 2982 | // INTERNAL LOGIC | |
| 2983 | //----------------------------------------------------------------- | |
| 2984 | // Add vnw_ary high check for read operation for n2_to_2.0 | |
| 2985 | // assign rd_en = rd_en_d1_a && ~wr_en_d1_a && w_inhibit_l; | |
| 2986 | assign rd_en = rd_en_d1_a && ~wr_en_d1_a && w_inhibit_l && vnw_ary; | |
| 2987 | ||
| 2988 | //----------------------------------------------------------------- | |
| 2989 | // REDUNDANCY | |
| 2990 | //----------------------------------------------------------------- | |
| 2991 | // Use [511:0] way0[29] as the redundancy bit, there are total 512 redundancy | |
| 2992 | // bits. | |
| 2993 | // Left side : way0_tmp[29:15] = mem0_lft[14:0] | |
| 2994 | // way1_tmp[27:13] = mem1_lft[14:0] | |
| 2995 | // way0_tmp[14] = red_bit_lft (redundancy bit) | |
| 2996 | // Shift mem1_lft[n] -> mem0_lft[n] , shift mem0_lft[n]->men1_rgt[n-1] | |
| 2997 | // mem0_lft[0]->redundancy bit = red_bit_lft. | |
| 2998 | // | |
| 2999 | // Right side : way0_tmp[12:0] = mem0_rgt[12:0] | |
| 3000 | // way1_tmp[12:0] = mem1_rgt[12:0] | |
| 3001 | // way0_tmp[13] = red_bit_rgt (redundancy bit) | |
| 3002 | // Shift mem1_rgt[n] -> mem0_rgt[n] , shift mem0_rgt[n]->men1_rgt[n+1] | |
| 3003 | // mem0_rgt[0]->redundancy bit = red_bit_rgt. | |
| 3004 | // | |
| 3005 | //----------------------------------------------------------------- | |
| 3006 | ||
| 3007 | //----------------------------------------------------------------- | |
| 3008 | // recover the shift index from rpda, rpdb, rpdc | |
| 3009 | //----------------------------------------------------------------- | |
| 3010 | assign sf_l[4] = rpda_lft[1] ; | |
| 3011 | assign sf_l[3:2] = rpdb_lft[3] ? 2'b11 : | |
| 3012 | rpdb_lft[2] ? 2'b10 : | |
| 3013 | rpdb_lft[1] ? 2'b01 : | |
| 3014 | 2'b00; | |
| 3015 | assign sf_l[1:0] = rpdc_lft[3] ? 2'b11 : | |
| 3016 | rpdc_lft[2] ? 2'b10 : | |
| 3017 | rpdc_lft[1] ? 2'b01 : | |
| 3018 | 2'b00; | |
| 3019 | ||
| 3020 | assign sf_r[4] = rpda_rgt[1] ; | |
| 3021 | assign sf_r[3:2] = rpdb_rgt[3] ? 2'b11 : | |
| 3022 | rpdb_rgt[2] ? 2'b10 : | |
| 3023 | rpdb_rgt[1] ? 2'b01 : | |
| 3024 | 2'b00; | |
| 3025 | assign sf_r[1:0] = rpdc_rgt[3] ? 2'b11 : | |
| 3026 | rpdc_rgt[2] ? 2'b10 : | |
| 3027 | rpdc_rgt[1] ? 2'b01 : | |
| 3028 | 2'b00; | |
| 3029 | ||
| 3030 | assign shift_en_lft = (sf_l[4:0] < 5'd30) ? (|rpda_lft[1:0]) && (|rpdb_lft[3:0]) && (|rpdc_lft[3:0]) : 1'b0; | |
| 3031 | assign shift_en_rgt = (sf_r[4:0] < 5'd26) ? (|rpda_rgt[1:0]) && (|rpdb_rgt[3:0]) && (|rpdc_rgt[3:0]) : 1'b0; | |
| 3032 | ||
| 3033 | assign redundancy_en = shift_en_lft || shift_en_rgt; | |
| 3034 | ||
| 3035 | assign sh_index_lft[4:0] = shift_en_lft && (sf_l[4:0] < 5'd30) ? sf_l[4:0] : 5'b00000; | |
| 3036 | assign sh_index_rgt[4:0] = shift_en_rgt && (sf_r[4:0] < 5'd26) ? sf_r[4:0] : 5'b00000; | |
| 3037 | ||
| 3038 | ||
| 3039 | ||
| 3040 | //----------------------------------------------------------------- | |
| 3041 | // Write Arrays | |
| 3042 | //----------------------------------------------------------------- | |
| 3043 | ||
| 3044 | ||
| 3045 | //-------------------------------------- | |
| 3046 | // Write Redundancy Mapping | |
| 3047 | //-------------------------------------- | |
| 3048 | // Shifting of redundancy base on the sh_index_lft and sh_index_rgt | |
| 3049 | ||
| 3050 | wire [14:0] din_lft ; | |
| 3051 | wire [0:12] din_rgt ; | |
| 3052 | assign din_lft[14:0] = din[27:13]; | |
| 3053 | assign din_rgt[0:12] = din[12:0]; | |
| 3054 | ||
| 3055 | // Add vnw_high check for write operation (implemented for n2_to_2.0) | |
| 3056 | ||
| 3057 | assign mem_wr_en0 = wr_way_b[0] && wr_en_b && ~rd_en_b && w_inhibit_l && wr_en_d1_a && vnw_ary; | |
| 3058 | assign mem_wr_en1 = wr_way_b[1] && wr_en_b && ~rd_en_b && w_inhibit_l && wr_en_d1_a && vnw_ary; | |
| 3059 | ||
| 3060 | ||
| 3061 | ||
| 3062 | ||
| 3063 | //-------left------- | |
| 3064 | always @ (sh_index_lft or din_lft[14:0] or shift_en_lft or mem_wr_en0 or mem_wr_en1 | |
| 3065 | or l1clk_int or addr_b[8:0] ) | |
| 3066 | ||
| 3067 | ||
| 3068 | #0 | |
| 3069 | ||
| 3070 | begin | |
| 3071 | ||
| 3072 | ||
| 3073 | mem_lft_reg[`L2T_ARR_D_WIDTH + 2:0] = mem_lft[addr_b] ; | |
| 3074 | ||
| 3075 | ||
| 3076 | ||
| 3077 | // Write to redundant bit in write cycle for way0 with no redundancy | |
| 3078 | if (l1clk_int && (~shift_en_lft) && mem_wr_en0) | |
| 3079 | begin | |
| 3080 | mem_lft_reg[0] = din_lft[0]; | |
| 3081 | end | |
| 3082 | ||
| 3083 | for (i=14; i >= 0; i=i-1) | |
| 3084 | begin | |
| 3085 | if (mem_wr_en0 && l1clk_int) //way0 | |
| 3086 | begin | |
| 3087 | if (( sh_index_lft < (2*i)) || ~shift_en_lft) | |
| 3088 | mem_lft_reg[2*i+1] = din_lft[i]; //no shift | |
| 3089 | else | |
| 3090 | begin | |
| 3091 | mem_lft_reg[2*i] = din_lft[i]; // shift | |
| 3092 | end | |
| 3093 | end | |
| 3094 | if(shift_en_lft) | |
| 3095 | mem_lft_reg[sh_index_lft+1] = 1'bx; // write "x" to bad bit | |
| 3096 | end //for | |
| 3097 | ||
| 3098 | for (i=14; i >= 0; i=i-1) | |
| 3099 | begin | |
| 3100 | if (mem_wr_en1 && l1clk_int ) //way1 | |
| 3101 | begin | |
| 3102 | if (( sh_index_lft < (2*i + 1)) || ~shift_en_lft) | |
| 3103 | mem_lft_reg[2*i+2] = din_lft[i]; //no shift | |
| 3104 | else | |
| 3105 | begin | |
| 3106 | mem_lft_reg[2*i+1] = din_lft[i]; //shift | |
| 3107 | end | |
| 3108 | end | |
| 3109 | if(shift_en_lft) | |
| 3110 | mem_lft_reg[sh_index_lft+1] = 1'bx; //write "x" to bad bit | |
| 3111 | end | |
| 3112 | ||
| 3113 | if (l1clk_int) mem_lft[addr_b] = mem_lft_reg[`L2T_ARR_D_WIDTH + 2:0] ; | |
| 3114 | ||
| 3115 | ||
| 3116 | end | |
| 3117 | ||
| 3118 | //-------right------- | |
| 3119 | ||
| 3120 | always @ (sh_index_rgt or din_rgt[0:12] or shift_en_rgt or mem_wr_en0 or mem_wr_en1 | |
| 3121 | or l1clk_int or addr_b[8:0] ) | |
| 3122 | ||
| 3123 | ||
| 3124 | #0 | |
| 3125 | ||
| 3126 | begin | |
| 3127 | ||
| 3128 | mem_rgt_reg[0 : `L2T_ARR_D_WIDTH - 2] = mem_rgt[addr_b]; | |
| 3129 | ||
| 3130 | ||
| 3131 | ||
| 3132 | // Write to redundant bit in write cycle for way0 with no redundancy | |
| 3133 | if (l1clk_int && (~shift_en_rgt) && mem_wr_en0) | |
| 3134 | begin | |
| 3135 | mem_rgt_reg[0] = din_rgt[0]; | |
| 3136 | end | |
| 3137 | ||
| 3138 | for (k=12; k >= 0; k=k-1) | |
| 3139 | begin | |
| 3140 | if (mem_wr_en0 && l1clk_int) //WAY0 | |
| 3141 | begin | |
| 3142 | if (( sh_index_rgt < (2*k )) || ~shift_en_rgt) | |
| 3143 | mem_rgt_reg[2*k+1] = din_rgt[k]; //no shift | |
| 3144 | else | |
| 3145 | begin | |
| 3146 | mem_rgt_reg[2*k] = din_rgt[k]; // shift | |
| 3147 | end | |
| 3148 | end | |
| 3149 | if(shift_en_rgt) | |
| 3150 | mem_rgt_reg[sh_index_rgt+1] = 1'bx; // Write "X" to the bad bit | |
| 3151 | end //for | |
| 3152 | ||
| 3153 | for (k=12; k >= 0; k=k-1) | |
| 3154 | begin | |
| 3155 | if (mem_wr_en1 && l1clk_int ) //WAY1 | |
| 3156 | begin | |
| 3157 | if (( sh_index_rgt < (2*k + 1)) || ~shift_en_rgt) | |
| 3158 | mem_rgt_reg[2*k+2] = din_rgt[k]; //no shift | |
| 3159 | else | |
| 3160 | begin | |
| 3161 | mem_rgt_reg[2*k+1] = din_rgt[k]; // shift | |
| 3162 | end | |
| 3163 | end | |
| 3164 | if(shift_en_rgt) | |
| 3165 | mem_rgt_reg[sh_index_rgt+1] = 1'bx; // Write "X" to the bad bit | |
| 3166 | end //for | |
| 3167 | ||
| 3168 | if (l1clk_int) mem_rgt[addr_b] = mem_rgt_reg[0 : `L2T_ARR_D_WIDTH - 2] ; | |
| 3169 | ||
| 3170 | ||
| 3171 | ||
| 3172 | end | |
| 3173 | ||
| 3174 | //----------------------------------------------------------------- | |
| 3175 | // Read Arrays | |
| 3176 | //----------------------------------------------------------------- | |
| 3177 | ||
| 3178 | //-------------------------------------- | |
| 3179 | // Read Redundancy Mapping | |
| 3180 | //-------------------------------------- | |
| 3181 | ||
| 3182 | ||
| 3183 | //---------Left-------------- | |
| 3184 | always @ (sh_index_lft or shift_en_lft or rd_en or l1clk_int or addr_b[8:0] ) | |
| 3185 | begin | |
| 3186 | if (l1clk_int) | |
| 3187 | begin | |
| 3188 | ||
| 3189 | mem_data_lft[`L2T_ARR_D_WIDTH + 2:0] = ~rd_en ? 31'hx : mem_lft[addr_b] ; | |
| 3190 | ||
| 3191 | end | |
| 3192 | ||
| 3193 | ||
| 3194 | if (rd_en && ~l1clk_int) | |
| 3195 | ||
| 3196 | ||
| 3197 | begin | |
| 3198 | ||
| 3199 | for (j=14; j >= 0; j=j-1) //WAY0 | |
| 3200 | begin | |
| 3201 | if (( sh_index_lft < (2*j )) || ~shift_en_lft) | |
| 3202 | rdata0_lft[j] = mem_data_lft[2*j+1]; // no shift | |
| 3203 | else | |
| 3204 | rdata0_lft[j] = mem_data_lft[2*j]; // shift | |
| 3205 | end //for | |
| 3206 | ||
| 3207 | for (j=14; j >= 0; j=j-1) //WAY1 | |
| 3208 | begin | |
| 3209 | if (( sh_index_lft < (2*j + 1)) || ~shift_en_lft) | |
| 3210 | rdata1_lft[j] = mem_data_lft[2*j+2]; //no shift | |
| 3211 | else | |
| 3212 | rdata1_lft[j] = mem_data_lft[2*j+1]; // shift | |
| 3213 | end | |
| 3214 | sao_mx0_h[27:13] = rdata0_lft[14:0] & {15{rd_en}}; | |
| 3215 | sao_mx0_l[27:13] = ~rdata0_lft[14:0] & {15{rd_en}}; | |
| 3216 | sao_mx1_h[27:13] = rdata1_lft[14:0] & {15{rd_en}}; | |
| 3217 | sao_mx1_l[27:13] = ~rdata1_lft[14:0] & {15{rd_en}}; | |
| 3218 | end | |
| 3219 | else if(l1clk_int || ~rd_en) | |
| 3220 | begin | |
| 3221 | sao_mx0_h[27:13] = 15'h0; | |
| 3222 | sao_mx0_l[27:13] = 15'h0; | |
| 3223 | sao_mx1_h[27:13] = 15'h0; | |
| 3224 | sao_mx1_l[27:13] = 15'h0; | |
| 3225 | end | |
| 3226 | end | |
| 3227 | ||
| 3228 | //---------Right-------------- | |
| 3229 | ||
| 3230 | always @ (sh_index_rgt or shift_en_rgt or rd_en or l1clk_int or addr_b[8:0] ) | |
| 3231 | ||
| 3232 | begin | |
| 3233 | if (l1clk_int) | |
| 3234 | begin | |
| 3235 | ||
| 3236 | mem_data_rgt[0: `L2T_ARR_D_WIDTH - 2] = ~rd_en ? 27'hx : mem_rgt[addr_b] ; | |
| 3237 | ||
| 3238 | end | |
| 3239 | ||
| 3240 | ||
| 3241 | if (rd_en && ~l1clk_int) | |
| 3242 | ||
| 3243 | ||
| 3244 | begin | |
| 3245 | ||
| 3246 | for (l=12; l >= 0; l=l-1) //WAY0 | |
| 3247 | begin | |
| 3248 | if (( sh_index_rgt < (2*l)) || ~shift_en_rgt) | |
| 3249 | rdata0_rgt[l] = mem_data_rgt[2*l+1]; // no shift | |
| 3250 | else | |
| 3251 | rdata0_rgt[l] = mem_data_rgt[2*l]; // shift | |
| 3252 | end //for | |
| 3253 | ||
| 3254 | for (l=12; l >= 0; l=l-1) //WAY1 | |
| 3255 | begin | |
| 3256 | if (( sh_index_rgt < (2*l + 1)) || ~shift_en_rgt) | |
| 3257 | rdata1_rgt[l] = mem_data_rgt[2*l+2]; //no shift | |
| 3258 | else | |
| 3259 | rdata1_rgt[l] = mem_data_rgt[2*l+1]; // shift | |
| 3260 | end | |
| 3261 | sao_mx0_h[12:0] = rdata0_rgt[0:12] & {13{rd_en}}; | |
| 3262 | sao_mx0_l[12:0] = ~rdata0_rgt[0:12] & {13{rd_en}}; | |
| 3263 | sao_mx1_h[12:0] = rdata1_rgt[0:12] & {13{rd_en}}; | |
| 3264 | sao_mx1_l[12:0] = ~rdata1_rgt[0:12] & {13{rd_en}}; | |
| 3265 | end | |
| 3266 | else if (l1clk_int || ~rd_en) | |
| 3267 | begin | |
| 3268 | sao_mx0_h[12:0] = 13'h0; | |
| 3269 | sao_mx0_l[12:0] = 13'h0; | |
| 3270 | sao_mx1_h[12:0] = 13'h0; | |
| 3271 | sao_mx1_l[12:0] = 13'h0; | |
| 3272 | end | |
| 3273 | end | |
| 3274 | ||
| 3275 | ||
| 3276 | endmodule | |
| 3277 | ||
| 3278 | ||
| 3279 | ||
| 3280 | module n2_l2t_sr_latch ( | |
| 3281 | set, | |
| 3282 | reset, | |
| 3283 | out) ; | |
| 3284 | ||
| 3285 | ||
| 3286 | input set; | |
| 3287 | input reset; | |
| 3288 | output out; | |
| 3289 | ||
| 3290 | reg out; | |
| 3291 | ||
| 3292 | always @(set or reset) | |
| 3293 | begin | |
| 3294 | if (reset) out=1'b0; | |
| 3295 | else if (set) out=1'b1; | |
| 3296 | end | |
| 3297 | endmodule // n2_l2t_sr_latch | |
| 3298 | ||
| 3299 | ||
| 3300 | ||
| 3301 | // Compare sao_mx_h with lkuptag_d1, and sao_mx_l with ~lkuptag_d1. | |
| 3302 | // Output is "0" for hit and "1" for miss | |
| 3303 | ||
| 3304 | module n2_l2t_cmp_3bx2 ( | |
| 3305 | sao_mx1_h, | |
| 3306 | sao_mx1_l, | |
| 3307 | sao_mx0_h, | |
| 3308 | sao_mx0_l, | |
| 3309 | lkuptag_d1, | |
| 3310 | l1clk_d, | |
| 3311 | w1_cmp3b, | |
| 3312 | w0_cmp3b) ; | |
| 3313 | ||
| 3314 | ||
| 3315 | input [2:0] sao_mx1_h; | |
| 3316 | input [2:0] sao_mx1_l; | |
| 3317 | input [2:0] sao_mx0_h; | |
| 3318 | input [2:0] sao_mx0_l; | |
| 3319 | input [2:0] lkuptag_d1; | |
| 3320 | input l1clk_d; | |
| 3321 | output w1_cmp3b; | |
| 3322 | output w0_cmp3b; | |
| 3323 | ||
| 3324 | reg w1_cmp3b; | |
| 3325 | reg w0_cmp3b; | |
| 3326 | ||
| 3327 | //Compare ouput is 0 for match and 1 for mismatch | |
| 3328 | ||
| 3329 | always @(l1clk_d or sao_mx1_h or sao_mx1_l or sao_mx0_h or sao_mx0_l or lkuptag_d1) | |
| 3330 | ||
| 3331 | if (l1clk_d) // Precharge mode | |
| 3332 | begin | |
| 3333 | w1_cmp3b = 1'b0; | |
| 3334 | w0_cmp3b = 1'b0; | |
| 3335 | end | |
| 3336 | else | |
| 3337 | if (~l1clk_d ) // Evaluation mode | |
| 3338 | begin | |
| 3339 | w1_cmp3b = (lkuptag_d1[2] && sao_mx1_l[2]) || (~lkuptag_d1[2] && sao_mx1_h[2]) || | |
| 3340 | (lkuptag_d1[1] && sao_mx1_l[1]) || (~lkuptag_d1[1] && sao_mx1_h[1]) || | |
| 3341 | (lkuptag_d1[0] && sao_mx1_l[0]) || (~lkuptag_d1[0] && sao_mx1_h[0]); | |
| 3342 | ||
| 3343 | w0_cmp3b = (lkuptag_d1[2] && sao_mx0_l[2]) || (~lkuptag_d1[2] && sao_mx0_h[2]) || | |
| 3344 | (lkuptag_d1[1] && sao_mx0_l[1]) || (~lkuptag_d1[1] && sao_mx0_h[1]) || | |
| 3345 | (lkuptag_d1[0] && sao_mx0_l[0]) || (~lkuptag_d1[0] && sao_mx0_h[0]); | |
| 3346 | end | |
| 3347 | ||
| 3348 | endmodule // n2_l2t_cmp_3bx2 | |
| 3349 | ||
| 3350 | ||
| 3351 | // | |
| 3352 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
| 3353 | // | |
| 3354 | // | |
| 3355 | ||
| 3356 | ||
| 3357 | ||
| 3358 | ||
| 3359 | ||
| 3360 | module n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_2 ( | |
| 3361 | d_a, | |
| 3362 | l1clk, | |
| 3363 | q_b); | |
| 3364 | input [1:0] d_a; | |
| 3365 | input l1clk; | |
| 3366 | output [1:0] q_b; | |
| 3367 | ||
| 3368 | ||
| 3369 | ||
| 3370 | ||
| 3371 | ||
| 3372 | ||
| 3373 | tisram_blb #(2) d0_0 ( | |
| 3374 | .d(d_a[1:0]), | |
| 3375 | .l1clk(l1clk), | |
| 3376 | .latout_l(q_b[1:0]) | |
| 3377 | ); | |
| 3378 | ||
| 3379 | ||
| 3380 | ||
| 3381 | ||
| 3382 | ||
| 3383 | ||
| 3384 | ||
| 3385 | ||
| 3386 | ||
| 3387 | ||
| 3388 | //place::generic_place($width,$stack,$left); | |
| 3389 | ||
| 3390 | endmodule | |
| 3391 | ||
| 3392 | ||
| 3393 | ||
| 3394 | ||
| 3395 | ||
| 3396 | // | |
| 3397 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
| 3398 | // | |
| 3399 | // | |
| 3400 | ||
| 3401 | ||
| 3402 | ||
| 3403 | ||
| 3404 | ||
| 3405 | module n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_5 ( | |
| 3406 | d_a, | |
| 3407 | l1clk, | |
| 3408 | q_b); | |
| 3409 | input [4:0] d_a; | |
| 3410 | input l1clk; | |
| 3411 | output [4:0] q_b; | |
| 3412 | ||
| 3413 | ||
| 3414 | ||
| 3415 | ||
| 3416 | ||
| 3417 | ||
| 3418 | tisram_blb #(5) d0_0 ( | |
| 3419 | .d(d_a[4:0]), | |
| 3420 | .l1clk(l1clk), | |
| 3421 | .latout_l(q_b[4:0]) | |
| 3422 | ); | |
| 3423 | ||
| 3424 | ||
| 3425 | ||
| 3426 | ||
| 3427 | ||
| 3428 | ||
| 3429 | ||
| 3430 | ||
| 3431 | ||
| 3432 | ||
| 3433 | //place::generic_place($width,$stack,$left); | |
| 3434 | ||
| 3435 | endmodule | |
| 3436 | ||
| 3437 | ||
| 3438 | ||
| 3439 | ||
| 3440 | ||
| 3441 | // | |
| 3442 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
| 3443 | // | |
| 3444 | // | |
| 3445 | ||
| 3446 | ||
| 3447 | ||
| 3448 | ||
| 3449 | ||
| 3450 | module n2_l2t_quad_tisram_blb_macro__dmsff_4x__width_1 ( | |
| 3451 | d_a, | |
| 3452 | l1clk, | |
| 3453 | q_b); | |
| 3454 | input [0:0] d_a; | |
| 3455 | input l1clk; | |
| 3456 | output [0:0] q_b; | |
| 3457 | ||
| 3458 | ||
| 3459 | ||
| 3460 | ||
| 3461 | ||
| 3462 | ||
| 3463 | tisram_blb #(1) d0_0 ( | |
| 3464 | .d(d_a[0:0]), | |
| 3465 | .l1clk(l1clk), | |
| 3466 | .latout_l(q_b[0:0]) | |
| 3467 | ); | |
| 3468 | ||
| 3469 | ||
| 3470 | ||
| 3471 | ||
| 3472 | ||
| 3473 | ||
| 3474 | ||
| 3475 | ||
| 3476 | ||
| 3477 | ||
| 3478 | //place::generic_place($width,$stack,$left); | |
| 3479 | ||
| 3480 | endmodule | |
| 3481 | ||
| 3482 | ||
| 3483 | ||
| 3484 | ||
| 3485 | ||
| 3486 | // | |
| 3487 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 3488 | // | |
| 3489 | // | |
| 3490 | ||
| 3491 | ||
| 3492 | ||
| 3493 | ||
| 3494 | ||
| 3495 | module n2_l2t_quad_tisram_msff_macro__width_1 ( | |
| 3496 | d, | |
| 3497 | scan_in, | |
| 3498 | l1clk, | |
| 3499 | siclk, | |
| 3500 | soclk, | |
| 3501 | scan_out, | |
| 3502 | latout, | |
| 3503 | latout_l); | |
| 3504 | input [0:0] d; | |
| 3505 | input scan_in; | |
| 3506 | input l1clk; | |
| 3507 | input siclk; | |
| 3508 | input soclk; | |
| 3509 | output scan_out; | |
| 3510 | output [0:0] latout; | |
| 3511 | output [0:0] latout_l; | |
| 3512 | ||
| 3513 | ||
| 3514 | ||
| 3515 | ||
| 3516 | ||
| 3517 | ||
| 3518 | tisram_msff #(1) d0_0 ( | |
| 3519 | .d(d[0:0]), | |
| 3520 | .si(scan_in), | |
| 3521 | .so(scan_out), | |
| 3522 | .l1clk(l1clk), | |
| 3523 | .siclk(siclk), | |
| 3524 | .soclk(soclk), | |
| 3525 | .latout(latout[0:0]), | |
| 3526 | .latout_l(latout_l[0:0]) | |
| 3527 | ); | |
| 3528 | ||
| 3529 | ||
| 3530 | ||
| 3531 | ||
| 3532 | ||
| 3533 | ||
| 3534 | ||
| 3535 | ||
| 3536 | ||
| 3537 | ||
| 3538 | ||
| 3539 | ||
| 3540 | //place::generic_place($width,$stack,$left); | |
| 3541 | ||
| 3542 | endmodule | |
| 3543 | ||
| 3544 | ||
| 3545 | ||
| 3546 | ||
| 3547 | ||
| 3548 | // | |
| 3549 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 3550 | // | |
| 3551 | // | |
| 3552 | ||
| 3553 | ||
| 3554 | ||
| 3555 | ||
| 3556 | ||
| 3557 | module n2_l2t_quad_tisram_msff_macro__width_2 ( | |
| 3558 | d, | |
| 3559 | scan_in, | |
| 3560 | l1clk, | |
| 3561 | siclk, | |
| 3562 | soclk, | |
| 3563 | scan_out, | |
| 3564 | latout, | |
| 3565 | latout_l); | |
| 3566 | wire [0:0] so; | |
| 3567 | ||
| 3568 | input [1:0] d; | |
| 3569 | input scan_in; | |
| 3570 | input l1clk; | |
| 3571 | input siclk; | |
| 3572 | input soclk; | |
| 3573 | output scan_out; | |
| 3574 | output [1:0] latout; | |
| 3575 | output [1:0] latout_l; | |
| 3576 | ||
| 3577 | ||
| 3578 | ||
| 3579 | ||
| 3580 | ||
| 3581 | ||
| 3582 | tisram_msff #(2) d0_0 ( | |
| 3583 | .d(d[1:0]), | |
| 3584 | .si({scan_in,so[0:0]}), | |
| 3585 | .so({so[0:0],scan_out}), | |
| 3586 | .l1clk(l1clk), | |
| 3587 | .siclk(siclk), | |
| 3588 | .soclk(soclk), | |
| 3589 | .latout(latout[1:0]), | |
| 3590 | .latout_l(latout_l[1:0]) | |
| 3591 | ); | |
| 3592 | ||
| 3593 | ||
| 3594 | ||
| 3595 | ||
| 3596 | ||
| 3597 | ||
| 3598 | ||
| 3599 | ||
| 3600 | ||
| 3601 | ||
| 3602 | ||
| 3603 | ||
| 3604 | //place::generic_place($width,$stack,$left); | |
| 3605 | ||
| 3606 | endmodule | |
| 3607 | ||
| 3608 | ||
| 3609 | ||
| 3610 | ||
| 3611 | ||
| 3612 | ||
| 3613 | ||
| 3614 | ||
| 3615 | ||
| 3616 | // any PARAMS parms go into naming of macro | |
| 3617 | ||
| 3618 | module n2_l2t_quad_msff_ctl_macro__width_1 ( | |
| 3619 | din, | |
| 3620 | l1clk, | |
| 3621 | scan_in, | |
| 3622 | siclk, | |
| 3623 | soclk, | |
| 3624 | dout, | |
| 3625 | scan_out); | |
| 3626 | wire [0:0] fdin; | |
| 3627 | ||
| 3628 | input [0:0] din; | |
| 3629 | input l1clk; | |
| 3630 | input scan_in; | |
| 3631 | ||
| 3632 | ||
| 3633 | input siclk; | |
| 3634 | input soclk; | |
| 3635 | ||
| 3636 | output [0:0] dout; | |
| 3637 | output scan_out; | |
| 3638 | assign fdin[0:0] = din[0:0]; | |
| 3639 | ||
| 3640 | ||
| 3641 | ||
| 3642 | ||
| 3643 | ||
| 3644 | ||
| 3645 | dff #(1) d0_0 ( | |
| 3646 | .l1clk(l1clk), | |
| 3647 | .siclk(siclk), | |
| 3648 | .soclk(soclk), | |
| 3649 | .d(fdin[0:0]), | |
| 3650 | .si(scan_in), | |
| 3651 | .so(scan_out), | |
| 3652 | .q(dout[0:0]) | |
| 3653 | ); | |
| 3654 | ||
| 3655 | ||
| 3656 | ||
| 3657 | ||
| 3658 | ||
| 3659 | ||
| 3660 | ||
| 3661 | ||
| 3662 | ||
| 3663 | ||
| 3664 | ||
| 3665 | ||
| 3666 | endmodule | |
| 3667 | ||
| 3668 | ||
| 3669 | ||
| 3670 | ||
| 3671 | ||
| 3672 | ||
| 3673 | ||
| 3674 | ||
| 3675 | ||
| 3676 | ||
| 3677 | ||
| 3678 | ||
| 3679 | ||
| 3680 | // any PARAMS parms go into naming of macro | |
| 3681 | ||
| 3682 | module n2_l2t_quad_msffi_ctl_macro__clockwidth_0__width_1 ( | |
| 3683 | din, | |
| 3684 | l1clk, | |
| 3685 | scan_in, | |
| 3686 | siclk, | |
| 3687 | soclk, | |
| 3688 | q_l, | |
| 3689 | scan_out); | |
| 3690 | input [0:0] din; | |
| 3691 | input l1clk; | |
| 3692 | input scan_in; | |
| 3693 | ||
| 3694 | ||
| 3695 | input siclk; | |
| 3696 | input soclk; | |
| 3697 | ||
| 3698 | output [0:0] q_l; | |
| 3699 | output scan_out; | |
| 3700 | ||
| 3701 | ||
| 3702 | ||
| 3703 | ||
| 3704 | ||
| 3705 | ||
| 3706 | msffi #(1) d0_0 ( | |
| 3707 | .l1clk(l1clk), | |
| 3708 | .siclk(siclk), | |
| 3709 | .soclk(soclk), | |
| 3710 | .d(din[0:0]), | |
| 3711 | .si(scan_in), | |
| 3712 | .so(scan_out), | |
| 3713 | .q_l(q_l[0:0]) | |
| 3714 | ); | |
| 3715 | ||
| 3716 | ||
| 3717 | ||
| 3718 | ||
| 3719 | ||
| 3720 | ||
| 3721 | ||
| 3722 | ||
| 3723 | ||
| 3724 | ||
| 3725 | ||
| 3726 | ||
| 3727 | endmodule | |
| 3728 | ||
| 3729 | ||
| 3730 | ||
| 3731 | ||
| 3732 | ||
| 3733 | ||
| 3734 | ||
| 3735 |