Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / tools / perl-5.8.0 / man / man1 / scantest.1
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129.\" ========================================================================
130.\"
131.IX Title "SCANTEST 1"
132.TH SCANTEST 1 "2003-07-24" "perl v5.8.0" "User Contributed Perl Documentation"
133.SH "NAME"
134scantest \- Perl script for scan pattern generation.
135.SH "SYNOPSIS"
136.IX Header "SYNOPSIS"
137scantest [options] gate_level_netlist
138.SH "ABSTRACT"
139.IX Header "ABSTRACT"
140\&\*(L"scantest\*(R" is a front-end interface for use of the ScanTest
141package for automatic test pattern generation using FastScan.
142\&\*(L"scantest\*(R" controls the creation of the test procedure file,
143FastScan command file and execution script, as well as the
144generation and simulation of test patterns.
145.SH "DESCRIPTION"
146.IX Header "DESCRIPTION"
147The intention behind \*(L"scantest\*(R" is to simplify the \s-1ATPG\s0 flow.
148If a design file conforms to the built-in defaults the entire
149flow can be run by specifying only the design file:
150.Sp
151.RS 4
152scantest design_file
153.RE
154.PP
155The default design settings are as follows:
156.IP "\(bu one scan chain" 4
157.IX Item "one scan chain"
158.PD 0
159.ie n .IP "\(bu clock port is named ""clk""" 4
160.el .IP "\(bu clock port is named ``clk''" 4
161.IX Item "clock port is named clk"
162.ie n .IP "\(bu scanin port is named ""si""" 4
163.el .IP "\(bu scanin port is named ``si''" 4
164.IX Item "scanin port is named si"
165.ie n .IP "\(bu scanout port is named ""so""" 4
166.el .IP "\(bu scanout port is named ``so''" 4
167.IX Item "scanout port is named so"
168.ie n .IP "\(bu scanenable port is named ""se""" 4
169.el .IP "\(bu scanenable port is named ``se''" 4
170.IX Item "scanenable port is named se"
171.PD
172.PP
173If the design does not conform to these defaults, switches
174are available to modify the operation of \*(L"scantest\*(R".
175.Sh "\s-1OPTIONS\s0"
176.IX Subsection "OPTIONS"
177.IP "\-[no]atpg" 4
178.IX Item "-[no]atpg"
179Run atpg only. If the option is negated, only simulation
180is performed. This is the same as specifying \*(L"\-sim\*(R"
181.IP "\-bb or \-blackbox" 4
182.IX Item "-bb or -blackbox"
183Enable automatic black box recognition. Typically this option
184should not be required. The switch can be used to force
185continuation of the flow in the presence of missing cells.
186Coverage is likely to be poor.
187.Sp
188Before setting this switch the user is advised to check that
189correct version of the library is being referenced and that
190all verilog files have been specified.
191.Sp
192In the event that a view is known to be missing (such as a
193memory block) this switch will need to be specified.
194.IP "\-clk" 4
195.IX Item "-clk"
196Introduces a comma separated list of rising edge active clocks.
197Default settings are overridden. Default names must be given
198explicitly if needed.
199.IP "\-comb" 4
200.IX Item "-comb"
201Specifies that the block has no sequential cells. Normally
202\&\*(L"scantest\*(R" searches for the presence of default or user
203specified clock ports. Specifying \*(L"\-comb\*(R" suppresses this
204behavior.
205.IP "\-design" 4
206.IX Item "-design"
207Optional switch that introduces a single design file.
208.IP "\-dftlib" 4
209.IX Item "-dftlib"
210Allows a non-default FastScan library to be specified.
211.Sp
212The \s-1DFT\s0 library is normally \*(L"$LIBDIR/u1/atpg/u1.mdl\*(R".
213This switch is provided for library debug purposes. Do not
214use it in the normal flow!
215.IP "\-[no]dofile" 4
216.IX Item "-[no]dofile"
217If set, this switch causes only the FastScan command file
218(dofile) to be generated.
219.Sp
220If negated, the switch allows the flow to proceed without
221generating a new default command file. The command file
222should be already present. This switch allows the user
223to develop a custom command file.
224.IP "\-dumpdir" 4
225.IX Item "-dumpdir"
226Allows a non-default dump directory to be specified.
227.Sp
228By default, \*(L"scantest\*(R" creates a dump area for simulation
229files in either \*(L"/export/home/bw\*(R" (scratch area available
230when running under dream) or \*(L"/tmp\*(R". The user is free to
231choose somewhere else.
232.Sp
233A subdirectory composed of the user's name and process
234id is created into which the simulation files are dumped.
235.RS 4
236.Sp
237.RS 4
238\&\s-1NOTE:\s0 The dump directory is never cleaned out. The user
239is responsible for ensuring that unnecessary files are
240removed.
241.RE
242.RE
243.RS 4
244.RE
245.IP "\-flist" 4
246.IX Item "-flist"
247Specifies verilog include files. This switch is necessary
248if the design is spread over multiple files.
249.Sp
250By default no include files are assumed.
251.IP "\-fslog" 4
252.IX Item "-fslog"
253Specifies an alternate name for the fastscan log file.
254.IP "\-help" 4
255.IX Item "-help"
256Prints the list of switches with brief descriptions and
257default settings.
258.IP "\-hi" 4
259.IX Item "-hi"
260Introduces a comma separated list of input ports which
261need to be contrained high.
262.Sp
263By default none are assumed.
264.IP "\-lo" 4
265.IX Item "-lo"
266Introduces a comma separated list of input ports which
267need to be contrained low.
268.Sp
269By default none are assumed.
270.IP "\-ph1" 4
271.IX Item "-ph1"
272Introduces a comma separated list of rising edge active clocks.
273This switch is an alias for \*(L"clk\*(R".
274.IP "\-ph2" 4
275.IX Item "-ph2"
276Introduces a comma separated list of falling edge active clocks.
277.Sp
278By default none are assumed.
279.IP "\-[no]runfile" 4
280.IX Item "-[no]runfile"
281If set, this switch causes only the FastScan run file to be
282generated.
283.Sp
284If negated, the switch allows the flow to proceed without
285generating a new default run file. The run file needs to
286be already present. This switch allows the user to invoke
287FastScan with customized settings.
288.IP "\-se" 4
289.IX Item "-se"
290Introduces a comma separated list of scanenable ports.
291Typically, only one scan enable port is expected. This
292switch is provided to specify a non-default port name.
293.Sp
294In the event that the default name, \*(L"se\*(R", is also required
295it needs to be explicitly specified.
296.IP "\-si" 4
297.IX Item "-si"
298Introduces a comma separated list of scanin ports. The
299default setting is overwritten. If the default name, \*(L"si\*(R",
300is also required it needs to be explicitly specified.
301.Sp
302The order of the scanin ports must match that of the
303corresponding scanout ports.
304.IP "\-[no]simulation" 4
305.IX Item "-[no]simulation"
306If set, this switch causes only simulation to be performed.
307If negated, the switch halts the flow after pattern
308generation.
309.IP "\-smalljob" 4
310.IX Item "-smalljob"
311Selects a 20 minute FastScan license. This works for small
312jobs when no licence is available on the default large queue.
313.IP "\-so" 4
314.IX Item "-so"
315Introduces a comma separated list of scanout ports. The
316default setting is overwritten. If the default name, \*(L"so\*(R",
317is also required it needs to be explicitly specified.
318.Sp
319The order of the scanout ports must match that of the
320corresponding scanin ports.
321.IP "\-[no]tpfile" 4
322.IX Item "-[no]tpfile"
323If set, this switch causes only the FastScan test procedure
324file to be generated.
325.Sp
326If negated, the switch allows the flow to proceed without
327generating a new default test procedure file. The test
328procedure file should be already present. This switch allows
329the user to develop a custom protocol.
330.IP "\-top" 4
331.IX Item "-top"
332This switch specifies the name of the top module. By default
333the top module name is taken from the root of the design
334file. The switch is necessary if the top module name does
335not match the design file name or if there are multiple top
336modules present.
337.IP "\-verbose" 4
338.IX Item "-verbose"
339If set, this switch will cause untestable fault information
340to be added to the \s-1ATPG\s0 log file. If coverage is low, this
341additional information could be large.
342.IP "\-vverbose" 4
343.IX Item "-vverbose"
344The \*(L"vverbose\*(R" flag adds instance coverage information to
345the \s-1ATPG\s0 log file. If the design file contains a large number
346of instances, printing the additional statistics slows down
347the flow and increases the size of the log file.
348.IP "\-vlist" 4
349.IX Item "-vlist"
350Allows multiple design files and/or libraries to be listed
351in a separate file. Internally this switch is used to reference
352the m1 library (\*(L"$LIBDIR/m1/compiled/m1.vL\*(R"). If this switch
353is used and the m1 library also needs to be referenced the
354library must be explicitly specified.
355.SH "ENVIRONMENT"
356.IX Header "ENVIRONMENT"
357\&\*(L"scantest\*(R" uses two environment variables:
358.IP "\s-1LIBDIR\s0" 4
359.IX Item "LIBDIR"
360Specifies the location of the design libraries.
361.IP "\s-1USER\s0" 4
362.IX Item "USER"
363Identifies where the default dump directory will be created.
364.SH "SEE ALSO"
365.IX Header "SEE ALSO"
366\&\fIScanTest\fR\|(3), http://www.mentor.com/dft
367.SH "AUTHOR"
368.IX Header "AUTHOR"
369Roger Mistely, <roger.mistely@sun.com>