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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / tools / src / nas,5.n2.os.2 / home / common / common.conf
CommitLineData
86530b38
AT		 1//
2// pli-socket options
3//
4//#if defined(RTL) || defined(PLI_REPLAY)
5OBJECT socket0 TYPE pli-socket {
6#if defined(FORCE_PC)
7 force_pc: 1
8#else
9 force_pc: 0
10#endif
11#if !defined(NOINT_SYNC) && (defined(RTL) || defined(PLI_REPLAY))
12 // int_sync is enabled
13 int_model: 1
14#else
15 int_model: 0
16#endif
17#if !defined(NOLDST_SYNC) && (defined(RTL) || defined(PLI_REPLAY))
18 // msync is enabled
19 mem_model: 1
20#else
21 mem_model: 0
22#endif
23#ifdef VERA_SOCKET
24 cmd_intf: 0
25#else
26 cmd_intf: 1
27#endif
28#ifdef PLI_REPLAY
29 replay_log: PLI_REPLAY
30 socket: 0
31 open: 0
32#elif defined(CSOCKET)
33 replay_log: 0
34 socket: CSOCKET
35 open: 1
36#else
37 replay_log: 0
38 socket: 0
39 open: 0
40#endif
41 close: 0
42 test: 0
43#ifdef PLI_LOG
44 pli_log: PLI_LOG
45#else
46 pli_log: 0
47#endif
48#if defined(NO_REG_CMP)
49 reg_cmp: 0
50#elif defined(REG_CMP)
51 reg_cmp: REG_CMP
52#else
53 reg_cmp: 1
54#endif
55#if defined(PLI_RTL_DEBUG)
56 debug_level: 9
57#elif defined(PLI_DEBUG)
58 debug_level: PLI_DEBUG
59#else
60 // default shows trap & instructions
61 debug_level: 2
62#endif
63#if !defined(NOTLB_SYNC)
64 tlb_sync: 1
65#else
66 tlb_sync: 0
67#endif
68#if defined(TLB_SYNC_DEBUG)
69 tlb_debug: TLB_SYNC_DEBUG
70#else
71 tlb_debug: 0
72#endif
73#if defined(CMP_REG_CMP)
74 cmp_cmp: CMP_REG_CMP
75#endif
76#if defined(MMU_REG_CMP)
77 mmu_cmp: MMU_REG_CMP
78#endif
79#if defined(SHOW_TRAP)
80 show_trap: SHOW_TRAP
81#else
82 show_trap: 0
83#endif
84#if defined(ENABLE_RAS)
85 enable_ras: ENABLE_RAS
86#else
87 enable_ras: 0
88#endif
89}
90
91//#endif // defined(RTL) || defined(PLI_REPLAY)
92
93//
94// swvmem0: msync, tsoChecker, and pmask related options
95//
96#if defined(MOM)
97
98OBJECT mom0 TYPE mom {
99 queue: th00
100 enable_sim: 1
101 wait-mode: 0
102#if defined(MOM_DEBUG)
103 DEBUG: 1
104#endif
105#if defined(MOM_SO_PATH)
106 so_path: MOM_SO_PATH
107#endif
108}
109
110#else // if defined(MOM)
111
112OBJECT swvmem0 TYPE swerver-memory {
113#if defined(RTL) || defined(PLI_REPLAY)
114 irq: irq0
115#endif
116#if defined(MEM_DISABLE) && !defined(PLI_REPLAY)
117 snoop: 0
118#else
119 snoop: 1
120#endif
121#if defined(TSO_CHECKER) && !defined(NO_TSO_CHECKER)
122 tso_checker: 1
123#else
124 tso_checker: 0
125#endif
126#if defined(DIS_DEBUG)
127 debug_level: 0
128#elif defined(TSO_DEBUG)
129 debug_level: 2
130#elif defined(MEM_DEBUG)
131 debug_level: MEM_DEBUG
132#else
133 debug_level: 0
134#endif
135#if defined(MEM_IFETCH) && !defined(NO_MEM_IFETCH)
136 ifetch: 1
137#else
138 ifetch: 0
139#endif
140 queue: th00
141// CMP masking
142#define XSTR(M) STR(M)
143#define STR(M) #M
144#if defined(THREAD_MASK0)
145 thread_mask0: XSTR(THREAD_MASK0)
146#else
147 thread_mask0: "01"
148#endif
149#if defined(THREAD_MASK1)
150 thread_mask1: XSTR(THREAD_MASK1)
151#endif
152#if defined(THREAD_MASK2)
153 thread_mask2: XSTR(THREAD_MASK2)
154#endif
155#if defined(THREAD_MASK3)
156 thread_mask3: XSTR(THREAD_MASK3)
157#endif
158}
159
160#endif // if defined(MOM)
161
162//=================== the following OBJECTs are not used ====================//
163
164OBJECT sim TYPE sim {
165 cpu_switch_time: 1
166 time_model: "on"
167 continue_disabled: 0
168#if !defined(NOLDST_SYNC)
169 instruction_profile_mode: instruction-cache-access-trace
170 instruction_profile_line_size: 4
171#endif
172}
173
174#ifdef CIOP0
175############################################# chip 0 IO devices
176OBJECT irq0 TYPE swerver-interrupt {
177 thread_base: 0
178 queue: th00
179}
180
181OBJECT ciop0 TYPE swerver-io-device {
182 physical_memory: phys_mem0
183 irq: irq0
184 queue: th00
185}
186OBJECT bsc0 TYPE bsc-device {
187 queue: th00
188}
189OBJECT egress0 TYPE egress-device {
190 queue: th00
191}
192OBJECT ingress0 TYPE ingress-device {
193 queue: th00
194}
195OBJECT rdma0 TYPE rdma-device {
196 queue: th00
197}
198OBJECT echo0 TYPE echo-device {
199 queue: th00
200}
201#else
202OBJECT memory_ciop TYPE ram {
203 image: memory_ciop_image
204}
205OBJECT memory_ciop_image TYPE image {
206 size: 0x7f00000000
207 queue: th00
208}
209#endif
210
211#undef sparc
212
213OBJECT irqbus0 TYPE sparc-irq-bus {
214}
215
216#if defined(RTL) || defined(PLI_REPLAY)
217OBJECT irq0 TYPE swerver-interrupt {
218 thread_base: 0
219 need_ssi: 1
220 queue: th00
221}
222#endif
223
224#ifdef SP0
225OBJECT swvp0 TYPE swerver-processor {
226 thread0: th00
227 thread1: th01
228 thread2: th02
229 thread3: th03
230 thread4: th04
231 thread5: th05
232 thread6: th06
233 thread7: th07
234 mmu:swmmu0
235}
236OBJECT swmmu0 TYPE swerver-proc-mmu {
237}
238
239OBJECT th00 TYPE niagara2 {
240 freq_mhz: 800
241 mmu: stmmu00
242 max-trap-levels: 6
243 va_bits: 48
244 physical_memory: phys_mem0
245 control_registers: (("mid", 0))
246 irq_bus: irqbus0
247 thread_id: 0
248 other_threads: (th01, th02, th03, th04, th05, th06, th07)
249 queue: th00
250#if defined(RTL) || defined(PLI_REPLAY)
251 extra_irq_enable: 0
252#endif
253}
254
255OBJECT stmmu00 TYPE swerver-thread-mmu {
256 thread-status: 1
257 full-swerver-decode: 1
258 niagara-mmu: 1
259 disable-sun4u-interrupts: 1
260 intr_trap_type: 0x60
261 stream_cmpl_trap_type: 0x70
262 ma_cmpl_trap_type: 0x74
263 model-real-sfar: 1
264#if defined(N1_ASI)
265 n2-legacy-asi: 1
266#endif
267#if defined(RTL) || defined(PLI_REPLAY)
268 ignore_asi_0x73: 1
269 match_rtl: 1
270#endif
271#if defined(MOM)
272 mom_intf: 1
273#endif
274}
275
276OBJECT spu00 TYPE swerver-spu {
277 queue: th00
278 thread: th00
279}
280
281OBJECT th01 TYPE niagara2 {
282 freq_mhz: 800
283 mmu: stmmu01
284 max-trap-levels: 6
285 va_bits: 48
286 physical_memory: phys_mem0
287 control_registers: (("mid", 1))
288 irq_bus: irqbus0
289 queue: th01
290 thread_id: 1
291 other_threads: (
292 th00,
293 th02,
294 th03,
295 th04,
296 th05,
297 th06,
298 th07
299 )
300#if defined(RTL) || defined(PLI_REPLAY)
301 extra_irq_enable: 0
302#endif
303}
304
305OBJECT stmmu01 TYPE swerver-thread-mmu {
306 full-swerver-decode: 1
307 niagara-mmu: 1
308 disable-sun4u-interrupts: 1
309 model-real-sfar: 1
310}
311
312OBJECT spu01 TYPE swerver-spu {
313 queue: th01
314 thread: th01
315}
316
317OBJECT th02 TYPE niagara2 {
318 freq_mhz: 800
319 mmu: stmmu02
320 max-trap-levels: 6
321 va_bits: 48
322 physical_memory: phys_mem0
323 control_registers: (("mid", 2))
324 irq_bus: irqbus0
325 queue: th02
326 thread_id: 2
327 other_threads: (
328 th00,
329 th01,
330 th03,
331 th04,
332 th05,
333 th06,
334 th07
335 )
336#if defined(RTL) || defined(PLI_REPLAY)
337 extra_irq_enable: 0
338#endif
339}
340
341OBJECT stmmu02 TYPE swerver-thread-mmu {
342 full-swerver-decode: 1
343 niagara-mmu: 1
344 disable-sun4u-interrupts: 1
345 model-real-sfar: 1
346}
347
348OBJECT spu02 TYPE swerver-spu {
349 queue: th02
350 thread: th02
351}
352
353OBJECT th03 TYPE niagara2 {
354 freq_mhz: 800
355 mmu: stmmu03
356 max-trap-levels: 6
357 va_bits: 48
358 physical_memory: phys_mem0
359 control_registers: (("mid", 3))
360 irq_bus: irqbus0
361 queue: th03
362 thread_id: 3
363 other_threads: (
364 th00,
365 th01,
366 th02,
367 th04,
368 th05,
369 th06,
370 th07
371 )
372#if defined(RTL) || defined(PLI_REPLAY)
373 extra_irq_enable: 0
374#endif
375}
376
377OBJECT stmmu03 TYPE swerver-thread-mmu {
378 full-swerver-decode: 1
379 niagara-mmu: 1
380 disable-sun4u-interrupts: 1
381 model-real-sfar: 1
382}
383
384OBJECT spu03 TYPE swerver-spu {
385 queue: th03
386 thread: th03
387}
388
389OBJECT th04 TYPE niagara2 {
390 freq_mhz: 800
391 mmu: stmmu04
392 max-trap-levels: 6
393 va_bits: 48
394 physical_memory: phys_mem0
395 control_registers: (("mid", 4))
396 irq_bus: irqbus0
397 queue: th04
398 thread_id: 4
399 other_threads: (
400 th00,
401 th01,
402 th02,
403 th03,
404 th05,
405 th06,
406 th07
407 )
408#if defined(RTL) || defined(PLI_REPLAY)
409 extra_irq_enable: 0
410#endif
411}
412
413OBJECT stmmu04 TYPE swerver-thread-mmu {
414 full-swerver-decode: 1
415 niagara-mmu: 1
416 disable-sun4u-interrupts: 1
417 model-real-sfar: 1
418}
419
420OBJECT spu04 TYPE swerver-spu {
421 queue: th04
422 thread: th04
423}
424
425OBJECT th05 TYPE niagara2 {
426 freq_mhz: 800
427 mmu: stmmu05
428 max-trap-levels: 6
429 va_bits: 48
430 physical_memory: phys_mem0
431 control_registers: (("mid", 5))
432 irq_bus: irqbus0
433 queue: th05
434 thread_id: 5
435 other_threads: (
436 th00,
437 th01,
438 th02,
439 th03,
440 th04,
441 th06,
442 th07
443 )
444#if defined(RTL) || defined(PLI_REPLAY)
445 extra_irq_enable: 0
446#endif
447}
448
449OBJECT stmmu05 TYPE swerver-thread-mmu {
450 full-swerver-decode: 1
451 niagara-mmu: 1
452 disable-sun4u-interrupts: 1
453 model-real-sfar: 1
454}
455
456OBJECT spu05 TYPE swerver-spu {
457 queue: th05
458 thread: th05
459}
460
461OBJECT th06 TYPE niagara2 {
462 freq_mhz: 800
463 mmu: stmmu06
464 max-trap-levels: 6
465 va_bits: 48
466 physical_memory: phys_mem0
467 control_registers: (("mid", 6))
468 irq_bus: irqbus0
469 queue: th06
470 thread_id: 6
471 other_threads: (
472 th00,
473 th01,
474 th02,
475 th03,
476 th04,
477 th05,
478 th07
479 )
480#if defined(RTL) || defined(PLI_REPLAY)
481 extra_irq_enable: 0
482#endif
483}
484
485OBJECT stmmu06 TYPE swerver-thread-mmu {
486 full-swerver-decode: 1
487 niagara-mmu: 1
488 disable-sun4u-interrupts: 1
489 model-real-sfar: 1
490}
491
492OBJECT spu06 TYPE swerver-spu {
493 queue: th06
494 thread: th06
495}
496
497OBJECT th07 TYPE niagara2 {
498 freq_mhz: 800
499 mmu: stmmu07
500 max-trap-levels: 6
501 va_bits: 48
502 physical_memory: phys_mem0
503 control_registers: (("mid", 7))
504 irq_bus: irqbus0
505 queue: th07
506 thread_id: 7
507 other_threads: (
508 th00,
509 th01,
510 th02,
511 th03,
512 th04,
513 th05,
514 th06
515 )
516#if defined(RTL) || defined(PLI_REPLAY)
517 extra_irq_enable: 0
518#endif
519}
520
521OBJECT stmmu07 TYPE swerver-thread-mmu {
522 full-swerver-decode: 1
523 niagara-mmu: 1
524 disable-sun4u-interrupts: 1
525 model-real-sfar: 1
526}
527
528OBJECT spu07 TYPE swerver-spu {
529 queue: th07
530 thread: th07
531}
532
533#endif // SP0
534
535
536#ifdef SP1
537
538OBJECT swvp1 TYPE swerver-processor {
539 thread0: th08
540 thread1: th09
541 thread2: th10
542 thread3: th11
543 thread4: th12
544 thread5: th13
545 thread6: th14
546 thread7: th15
547 mmu:swmmu1
548}
549
550OBJECT swmmu1 TYPE swerver-proc-mmu {
551}
552
553OBJECT th08 TYPE niagara2 {
554 mmu: stmmu08
555 queue: th08
556 freq_mhz: 800
557 max-trap-levels: 6
558 va_bits: 48
559 physical_memory: phys_mem0
560 control_registers: (("mid", 8))
561 irq_bus: irqbus0
562 thread_id: 0
563 other_threads: (
564 th09,
565 th10,
566 th11,
567 th12,
568 th13,
569 th14,
570 th15
571 )
572#if defined(RTL) || defined(PLI_REPLAY)
573 extra_irq_enable: 0
574#endif
575}
576
577OBJECT stmmu08 TYPE swerver-thread-mmu {
578 full-swerver-decode: 1
579 niagara-mmu: 1
580 disable-sun4u-interrupts: 1
581 model-real-sfar: 1
582}
583
584OBJECT spu08 TYPE swerver-spu {
585 queue: th08
586 thread: th08
587}
588OBJECT th09 TYPE niagara2 {
589 mmu: stmmu09
590 queue: th09
591 freq_mhz: 800
592 max-trap-levels: 6
593 va_bits: 48
594 physical_memory: phys_mem0
595 control_registers: (("mid", 9))
596 irq_bus: irqbus0
597 thread_id: 1
598 other_threads: (
599 th08,
600 th10,
601 th11,
602 th12,
603 th13,
604 th14,
605 th15
606 )
607#if defined(RTL) || defined(PLI_REPLAY)
608 extra_irq_enable: 0
609#endif
610}
611
612OBJECT stmmu09 TYPE swerver-thread-mmu {
613 full-swerver-decode: 1
614 niagara-mmu: 1
615 disable-sun4u-interrupts: 1
616 model-real-sfar: 1
617}
618
619OBJECT spu09 TYPE swerver-spu {
620 queue: th09
621 thread: th09
622}
623OBJECT th10 TYPE niagara2 {
624 mmu: stmmu10
625 queue: th10
626 freq_mhz: 800
627 max-trap-levels: 6
628 va_bits: 48
629 physical_memory: phys_mem0
630 control_registers: (("mid", 10))
631 irq_bus: irqbus0
632 thread_id: 2
633 other_threads: (
634 th08,
635 th09,
636 th11,
637 th12,
638 th13,
639 th14,
640 th15
641 )
642#if defined(RTL) || defined(PLI_REPLAY)
643 extra_irq_enable: 0
644#endif
645}
646
647OBJECT stmmu10 TYPE swerver-thread-mmu {
648 full-swerver-decode: 1
649 niagara-mmu: 1
650 disable-sun4u-interrupts: 1
651 model-real-sfar: 1
652}
653
654OBJECT spu10 TYPE swerver-spu {
655 queue: th10
656 thread: th10
657}
658
659OBJECT th11 TYPE niagara2 {
660 mmu: stmmu11
661 queue: th11
662 freq_mhz: 800
663 max-trap-levels: 6
664 va_bits: 48
665 physical_memory: phys_mem0
666 control_registers: (("mid", 11))
667 irq_bus: irqbus0
668 thread_id: 3
669 other_threads: (
670 th08,
671 th09,
672 th10,
673 th12,
674 th13,
675 th14,
676 th15
677 )
678#if defined(RTL) || defined(PLI_REPLAY)
679 extra_irq_enable: 0
680#endif
681}
682
683OBJECT stmmu11 TYPE swerver-thread-mmu {
684 full-swerver-decode: 1
685 niagara-mmu: 1
686 disable-sun4u-interrupts: 1
687 model-real-sfar: 1
688}
689
690OBJECT spu11 TYPE swerver-spu {
691 queue: th11
692 thread: th11
693}
694
695OBJECT th12 TYPE niagara2 {
696 mmu: stmmu12
697 queue: th12
698 freq_mhz: 800
699 max-trap-levels: 6
700 va_bits: 48
701 physical_memory: phys_mem0
702 control_registers: (("mid", 12))
703 irq_bus: irqbus0
704 thread_id: 4
705 other_threads: (
706 th08,
707 th09,
708 th10,
709 th11,
710 th13,
711 th14,
712 th15
713 )
714#if defined(RTL) || defined(PLI_REPLAY)
715 extra_irq_enable: 0
716#endif
717}
718
719OBJECT stmmu12 TYPE swerver-thread-mmu {
720 full-swerver-decode: 1
721 niagara-mmu: 1
722 disable-sun4u-interrupts: 1
723 model-real-sfar: 1
724}
725
726OBJECT spu12 TYPE swerver-spu {
727 queue: th12
728 thread: th12
729}
730
731OBJECT th13 TYPE niagara2 {
732 mmu: stmmu13
733 queue: th13
734 freq_mhz: 800
735 max-trap-levels: 6
736 va_bits: 48
737 physical_memory: phys_mem0
738 control_registers: (("mid", 13))
739 irq_bus: irqbus0
740 thread_id: 5
741 other_threads: (
742 th08,
743 th09,
744 th10,
745 th11,
746 th12,
747 th14,
748 th15
749 )
750#if defined(RTL) || defined(PLI_REPLAY)
751 extra_irq_enable: 0
752#endif
753}
754
755OBJECT stmmu13 TYPE swerver-thread-mmu {
756 full-swerver-decode: 1
757 niagara-mmu: 1
758 disable-sun4u-interrupts: 1
759 model-real-sfar: 1
760}
761
762OBJECT spu13 TYPE swerver-spu {
763 queue: th13
764 thread: th13
765}
766
767OBJECT th14 TYPE niagara2 {
768 mmu: stmmu14
769 queue: th14
770 freq_mhz: 800
771 max-trap-levels: 6
772 va_bits: 48
773 physical_memory: phys_mem0
774 control_registers: (("mid", 14))
775 irq_bus: irqbus0
776 thread_id: 6
777 other_threads: (
778 th08,
779 th09,
780 th10,
781 th11,
782 th12,
783 th13,
784 th15
785 )
786#if defined(RTL) || defined(PLI_REPLAY)
787 extra_irq_enable: 0
788#endif
789}
790
791OBJECT stmmu14 TYPE swerver-thread-mmu {
792 full-swerver-decode: 1
793 niagara-mmu: 1
794 disable-sun4u-interrupts: 1
795 model-real-sfar: 1
796}
797
798OBJECT spu14 TYPE swerver-spu {
799 queue: th14
800 thread: th14
801}
802
803OBJECT th15 TYPE niagara2 {
804 mmu: stmmu15
805 queue: th15
806 freq_mhz: 800
807 max-trap-levels: 6
808 va_bits: 48
809 physical_memory: phys_mem0
810 control_registers: (("mid", 15))
811 irq_bus: irqbus0
812 thread_id: 7
813 other_threads: (
814 th08,
815 th09,
816 th10,
817 th11,
818 th12,
819 th13,
820 th14
821 )
822#if defined(RTL) || defined(PLI_REPLAY)
823 extra_irq_enable: 0
824#endif
825}
826
827OBJECT stmmu15 TYPE swerver-thread-mmu {
828 full-swerver-decode: 1
829 niagara-mmu: 1
830 disable-sun4u-interrupts: 1
831 model-real-sfar: 1
832}
833
834OBJECT spu15 TYPE swerver-spu {
835 queue: th15
836 thread: th15
837}
838
839
840#endif
841
842#ifdef SP2
843
844OBJECT swvp2 TYPE swerver-processor {
845 thread0: th16
846 thread1: th17
847 thread2: th18
848 thread3: th19
849 thread4: th20
850 thread5: th21
851 thread6: th22
852 thread7: th23
853 mmu:swmmu2
854}
855
856OBJECT swmmu2 TYPE swerver-proc-mmu {
857}
858
859OBJECT th16 TYPE niagara2 {
860 mmu: stmmu16
861 queue: th16
862 freq_mhz: 800
863 max-trap-levels: 6
864 va_bits: 48
865 physical_memory: phys_mem0
866 control_registers: (("mid", 16))
867 irq_bus: irqbus0
868 thread_id: 0
869 other_threads: (
870 th17,
871 th18,
872 th19,
873 th20,
874 th21,
875 th22,
876 th23
877 )
878#if defined(RTL) || defined(PLI_REPLAY)
879 extra_irq_enable: 0
880#endif
881}
882
883OBJECT stmmu16 TYPE swerver-thread-mmu {
884 full-swerver-decode: 1
885 niagara-mmu: 1
886 disable-sun4u-interrupts: 1
887 model-real-sfar: 1
888}
889
890OBJECT spu16 TYPE swerver-spu {
891 queue: th16
892 thread: th16
893}
894
895OBJECT th17 TYPE niagara2 {
896 mmu: stmmu17
897 queue: th17
898 freq_mhz: 800
899 max-trap-levels: 6
900 va_bits: 48
901 physical_memory: phys_mem0
902 control_registers: (("mid", 17))
903 irq_bus: irqbus0
904 thread_id: 1
905 other_threads: (
906 th16,
907 th18,
908 th19,
909 th20,
910 th21,
911 th22,
912 th23
913 )
914#if defined(RTL) || defined(PLI_REPLAY)
915 extra_irq_enable: 0
916#endif
917}
918
919OBJECT stmmu17 TYPE swerver-thread-mmu {
920 full-swerver-decode: 1
921 niagara-mmu: 1
922 disable-sun4u-interrupts: 1
923 model-real-sfar: 1
924}
925
926OBJECT spu17 TYPE swerver-spu {
927 queue: th17
928 thread: th17
929}
930
931OBJECT th18 TYPE niagara2 {
932 mmu: stmmu18
933 queue: th18
934 freq_mhz: 800
935 max-trap-levels: 6
936 va_bits: 48
937 physical_memory: phys_mem0
938 control_registers: (("mid", 18))
939 irq_bus: irqbus0
940 thread_id: 2
941 other_threads: (
942 th16,
943 th17,
944 th19,
945 th20,
946 th21,
947 th22,
948 th23
949 )
950#if defined(RTL) || defined(PLI_REPLAY)
951 extra_irq_enable: 0
952#endif
953}
954
955OBJECT stmmu18 TYPE swerver-thread-mmu {
956 full-swerver-decode: 1
957 niagara-mmu: 1
958 disable-sun4u-interrupts: 1
959 model-real-sfar: 1
960}
961
962OBJECT spu18 TYPE swerver-spu {
963 queue: th18
964 thread: th18
965}
966
967OBJECT th19 TYPE niagara2 {
968 mmu: stmmu19
969 queue: th19
970 freq_mhz: 800
971 max-trap-levels: 6
972 va_bits: 48
973 physical_memory: phys_mem0
974 control_registers: (("mid", 19))
975 irq_bus: irqbus0
976 thread_id: 3
977 other_threads: (
978 th16,
979 th17,
980 th18,
981 th20,
982 th21,
983 th22,
984 th23
985 )
986#if defined(RTL) || defined(PLI_REPLAY)
987 extra_irq_enable: 0
988#endif
989}
990
991OBJECT stmmu19 TYPE swerver-thread-mmu {
992 full-swerver-decode: 1
993 niagara-mmu: 1
994 disable-sun4u-interrupts: 1
995 model-real-sfar: 1
996}
997
998OBJECT spu19 TYPE swerver-spu {
999 queue: th19
1000 thread: th19
1001}
1002
1003OBJECT th20 TYPE niagara2 {
1004 mmu: stmmu20
1005 queue: th20
1006 freq_mhz: 800
1007 max-trap-levels: 6
1008 va_bits: 48
1009 physical_memory: phys_mem0
1010 control_registers: (("mid", 20))
1011 irq_bus: irqbus0
1012 thread_id: 4
1013 other_threads: (
1014 th16,
1015 th17,
1016 th18,
1017 th19,
1018 th21,
1019 th22,
1020 th23
1021 )
1022#if defined(RTL) || defined(PLI_REPLAY)
1023 extra_irq_enable: 0
1024#endif
1025}
1026
1027OBJECT stmmu20 TYPE swerver-thread-mmu {
1028 full-swerver-decode: 1
1029 niagara-mmu: 1
1030 disable-sun4u-interrupts: 1
1031 model-real-sfar: 1
1032}
1033
1034OBJECT spu20 TYPE swerver-spu {
1035 queue: th20
1036 thread: th20
1037}
1038
1039OBJECT th21 TYPE niagara2 {
1040 mmu: stmmu21
1041 queue: th21
1042 freq_mhz: 800
1043 max-trap-levels: 6
1044 va_bits: 48
1045 physical_memory: phys_mem0
1046 control_registers: (("mid", 21))
1047 irq_bus: irqbus0
1048 thread_id: 5
1049 other_threads: (
1050 th16,
1051 th17,
1052 th18,
1053 th19,
1054 th20,
1055 th22,
1056 th23
1057 )
1058#if defined(RTL) || defined(PLI_REPLAY)
1059 extra_irq_enable: 0
1060#endif
1061}
1062
1063OBJECT stmmu21 TYPE swerver-thread-mmu {
1064 full-swerver-decode: 1
1065 niagara-mmu: 1
1066 disable-sun4u-interrupts: 1
1067 model-real-sfar: 1
1068}
1069
1070OBJECT spu21 TYPE swerver-spu {
1071 queue: th21
1072 thread: th21
1073}
1074
1075OBJECT th22 TYPE niagara2 {
1076 mmu: stmmu22
1077 queue: th22
1078 freq_mhz: 800
1079 max-trap-levels: 6
1080 va_bits: 48
1081 physical_memory: phys_mem0
1082 control_registers: (("mid", 22))
1083 irq_bus: irqbus0
1084 thread_id: 6
1085 other_threads: (
1086 th16,
1087 th17,
1088 th18,
1089 th19,
1090 th20,
1091 th21,
1092 th23
1093 )
1094#if defined(RTL) || defined(PLI_REPLAY)
1095 extra_irq_enable: 0
1096#endif
1097}
1098
1099OBJECT stmmu22 TYPE swerver-thread-mmu {
1100 full-swerver-decode: 1
1101 niagara-mmu: 1
1102 disable-sun4u-interrupts: 1
1103 model-real-sfar: 1
1104}
1105
1106OBJECT spu22 TYPE swerver-spu {
1107 queue: th22
1108 thread: th22
1109}
1110
1111OBJECT th23 TYPE niagara2 {
1112 mmu: stmmu23
1113 queue: th23
1114 freq_mhz: 800
1115 max-trap-levels: 6
1116 va_bits: 48
1117 physical_memory: phys_mem0
1118 control_registers: (("mid", 23))
1119 irq_bus: irqbus0
1120 thread_id: 7
1121 other_threads: (
1122 th16,
1123 th17,
1124 th18,
1125 th19,
1126 th20,
1127 th21,
1128 th22
1129 )
1130#if defined(RTL) || defined(PLI_REPLAY)
1131 extra_irq_enable: 0
1132#endif
1133}
1134
1135OBJECT stmmu23 TYPE swerver-thread-mmu {
1136 full-swerver-decode: 1
1137 niagara-mmu: 1
1138 disable-sun4u-interrupts: 1
1139 model-real-sfar: 1
1140}
1141
1142OBJECT spu23 TYPE swerver-spu {
1143 queue: th23
1144 thread: th23
1145}
1146
1147
1148#endif
1149
1150#ifdef SP3
1151
1152OBJECT swvp3 TYPE swerver-processor {
1153 thread0: th24
1154 thread1: th25
1155 thread2: th26
1156 thread3: th27
1157 thread4: th28
1158 thread5: th29
1159 thread6: th30
1160 thread7: th31
1161 mmu:swmmu3
1162}
1163
1164OBJECT swmmu3 TYPE swerver-proc-mmu {
1165}
1166
1167OBJECT th24 TYPE niagara2 {
1168 mmu: stmmu24
1169 queue: th24
1170 freq_mhz: 800
1171 max-trap-levels: 6
1172 va_bits: 48
1173 physical_memory: phys_mem0
1174 control_registers: (("mid", 24))
1175 irq_bus: irqbus0
1176 thread_id: 0
1177 other_threads: (
1178 th25,
1179 th26,
1180 th27,
1181 th28,
1182 th29,
1183 th30,
1184 th31
1185 )
1186#if defined(RTL) || defined(PLI_REPLAY)
1187 extra_irq_enable: 0
1188#endif
1189}
1190
1191OBJECT stmmu24 TYPE swerver-thread-mmu {
1192 full-swerver-decode: 1
1193 niagara-mmu: 1
1194 disable-sun4u-interrupts: 1
1195 model-real-sfar: 1
1196}
1197
1198OBJECT spu24 TYPE swerver-spu {
1199 queue: th24
1200 thread: th24
1201}
1202
1203OBJECT th25 TYPE niagara2 {
1204 mmu: stmmu25
1205 queue: th25
1206 freq_mhz: 800
1207 max-trap-levels: 6
1208 va_bits: 48
1209 physical_memory: phys_mem0
1210 control_registers: (("mid", 25))
1211 irq_bus: irqbus0
1212 thread_id: 1
1213 other_threads: (
1214 th24,
1215 th26,
1216 th27,
1217 th28,
1218 th29,
1219 th30,
1220 th31
1221 )
1222#if defined(RTL) || defined(PLI_REPLAY)
1223 extra_irq_enable: 0
1224#endif
1225}
1226
1227OBJECT stmmu25 TYPE swerver-thread-mmu {
1228 full-swerver-decode: 1
1229 niagara-mmu: 1
1230 disable-sun4u-interrupts: 1
1231 model-real-sfar: 1
1232}
1233
1234OBJECT spu25 TYPE swerver-spu {
1235 queue: th25
1236 thread: th25
1237}
1238
1239OBJECT th26 TYPE niagara2 {
1240 mmu: stmmu26
1241 queue: th26
1242 freq_mhz: 800
1243 max-trap-levels: 6
1244 va_bits: 48
1245 physical_memory: phys_mem0
1246 control_registers: (("mid", 26))
1247 irq_bus: irqbus0
1248 thread_id: 2
1249 other_threads: (
1250 th24,
1251 th25,
1252 th27,
1253 th28,
1254 th29,
1255 th30,
1256 th31
1257 )
1258#if defined(RTL) || defined(PLI_REPLAY)
1259 extra_irq_enable: 0
1260#endif
1261}
1262
1263OBJECT stmmu26 TYPE swerver-thread-mmu {
1264 full-swerver-decode: 1
1265 niagara-mmu: 1
1266 disable-sun4u-interrupts: 1
1267 model-real-sfar: 1
1268}
1269
1270OBJECT spu26 TYPE swerver-spu {
1271 queue: th26
1272 thread: th26
1273}
1274
1275OBJECT th27 TYPE niagara2 {
1276 mmu: stmmu27
1277 queue: th27
1278 freq_mhz: 800
1279 max-trap-levels: 6
1280 va_bits: 48
1281 physical_memory: phys_mem0
1282 control_registers: (("mid", 27))
1283 irq_bus: irqbus0
1284 thread_id: 3
1285 other_threads: (
1286 th24,
1287 th25,
1288 th26,
1289 th28,
1290 th29,
1291 th30,
1292 th31
1293 )
1294#if defined(RTL) || defined(PLI_REPLAY)
1295 extra_irq_enable: 0
1296#endif
1297}
1298
1299OBJECT stmmu27 TYPE swerver-thread-mmu {
1300 full-swerver-decode: 1
1301 niagara-mmu: 1
1302 disable-sun4u-interrupts: 1
1303 model-real-sfar: 1
1304}
1305
1306OBJECT spu27 TYPE swerver-spu {
1307 queue: th27
1308 thread: th27
1309}
1310
1311OBJECT th28 TYPE niagara2 {
1312 mmu: stmmu28
1313 queue: th28
1314 freq_mhz: 800
1315 max-trap-levels: 6
1316 va_bits: 48
1317 physical_memory: phys_mem0
1318 control_registers: (("mid", 28))
1319 irq_bus: irqbus0
1320 thread_id: 4
1321 other_threads: (
1322 th24,
1323 th25,
1324 th26,
1325 th27,
1326 th29,
1327 th30,
1328 th31
1329 )
1330#if defined(RTL) || defined(PLI_REPLAY)
1331 extra_irq_enable: 0
1332#endif
1333}
1334
1335OBJECT stmmu28 TYPE swerver-thread-mmu {
1336 full-swerver-decode: 1
1337 niagara-mmu: 1
1338 disable-sun4u-interrupts: 1
1339 model-real-sfar: 1
1340}
1341
1342OBJECT spu28 TYPE swerver-spu {
1343 queue: th28
1344 thread: th28
1345}
1346
1347OBJECT th29 TYPE niagara2 {
1348 mmu: stmmu29
1349 queue: th29
1350 freq_mhz: 800
1351 max-trap-levels: 6
1352 va_bits: 48
1353 physical_memory: phys_mem0
1354 control_registers: (("mid", 29))
1355 irq_bus: irqbus0
1356 thread_id: 5
1357 other_threads: (
1358 th24,
1359 th25,
1360 th26,
1361 th27,
1362 th28,
1363 th30,
1364 th31
1365 )
1366#if defined(RTL) || defined(PLI_REPLAY)
1367 extra_irq_enable: 0
1368#endif
1369}
1370
1371OBJECT stmmu29 TYPE swerver-thread-mmu {
1372 full-swerver-decode: 1
1373 niagara-mmu: 1
1374 disable-sun4u-interrupts: 1
1375 model-real-sfar: 1
1376}
1377
1378OBJECT spu29 TYPE swerver-spu {
1379 queue: th29
1380 thread: th29
1381}
1382
1383OBJECT th30 TYPE niagara2 {
1384 mmu: stmmu30
1385 queue: th30
1386 freq_mhz: 800
1387 max-trap-levels: 6
1388 va_bits: 48
1389 physical_memory: phys_mem0
1390 control_registers: (("mid", 30))
1391 irq_bus: irqbus0
1392 thread_id: 6
1393 other_threads: (
1394 th24,
1395 th25,
1396 th26,
1397 th27,
1398 th28,
1399 th29,
1400 th31
1401 )
1402#if defined(RTL) || defined(PLI_REPLAY)
1403 extra_irq_enable: 0
1404#endif
1405}
1406
1407OBJECT stmmu30 TYPE swerver-thread-mmu {
1408 full-swerver-decode: 1
1409 niagara-mmu: 1
1410 disable-sun4u-interrupts: 1
1411 model-real-sfar: 1
1412}
1413
1414OBJECT spu30 TYPE swerver-spu {
1415 queue: th30
1416 thread: th30
1417}
1418
1419OBJECT th31 TYPE niagara2 {
1420 mmu: stmmu31
1421 queue: th31
1422 freq_mhz: 800
1423 max-trap-levels: 6
1424 va_bits: 48
1425 physical_memory: phys_mem0
1426 control_registers: (("mid", 31))
1427 irq_bus: irqbus0
1428 thread_id: 7
1429 other_threads: (
1430 th24,
1431 th25,
1432 th26,
1433 th27,
1434 th28,
1435 th29,
1436 th30
1437 )
1438#if defined(RTL) || defined(PLI_REPLAY)
1439 extra_irq_enable: 0
1440#endif
1441}
1442
1443OBJECT stmmu31 TYPE swerver-thread-mmu {
1444 full-swerver-decode: 1
1445 niagara-mmu: 1
1446 disable-sun4u-interrupts: 1
1447 model-real-sfar: 1
1448}
1449
1450OBJECT spu31 TYPE swerver-spu {
1451 queue: th31
1452 thread: th31
1453}
1454
1455
1456#endif
1457
1458#ifdef SP4
1459
1460OBJECT swvp4 TYPE swerver-processor {
1461 thread0: th32
1462 thread1: th33
1463 thread2: th34
1464 thread3: th35
1465 thread4: th36
1466 thread5: th37
1467 thread6: th38
1468 thread7: th39
1469 mmu:swmmu4
1470}
1471
1472OBJECT swmmu4 TYPE swerver-proc-mmu {
1473}
1474
1475OBJECT th32 TYPE niagara2 {
1476 mmu: stmmu32
1477 queue: th32
1478 freq_mhz: 800
1479 max-trap-levels: 6
1480 va_bits: 48
1481 physical_memory: phys_mem0
1482 control_registers: (("mid", 32))
1483 irq_bus: irqbus0
1484 thread_id: 0
1485 other_threads: (
1486 th33,
1487 th34,
1488 th35,
1489 th36,
1490 th37,
1491 th38,
1492 th39
1493 )
1494#if defined(RTL) || defined(PLI_REPLAY)
1495 extra_irq_enable: 0
1496#endif
1497}
1498
1499OBJECT stmmu32 TYPE swerver-thread-mmu {
1500 full-swerver-decode: 1
1501 niagara-mmu: 1
1502 disable-sun4u-interrupts: 1
1503 model-real-sfar: 1
1504}
1505
1506OBJECT spu32 TYPE swerver-spu {
1507 queue: th32
1508 thread: th32
1509}
1510
1511OBJECT th33 TYPE niagara2 {
1512 mmu: stmmu33
1513 queue: th33
1514 freq_mhz: 800
1515 max-trap-levels: 6
1516 va_bits: 48
1517 physical_memory: phys_mem0
1518 control_registers: (("mid", 33))
1519 irq_bus: irqbus0
1520 thread_id: 1
1521 other_threads: (
1522 th32,
1523 th34,
1524 th35,
1525 th36,
1526 th37,
1527 th38,
1528 th39
1529 )
1530#if defined(RTL) || defined(PLI_REPLAY)
1531 extra_irq_enable: 0
1532#endif
1533}
1534
1535OBJECT stmmu33 TYPE swerver-thread-mmu {
1536 full-swerver-decode: 1
1537 niagara-mmu: 1
1538 disable-sun4u-interrupts: 1
1539 model-real-sfar: 1
1540}
1541
1542OBJECT spu33 TYPE swerver-spu {
1543 queue: th33
1544 thread: th33
1545}
1546
1547OBJECT th34 TYPE niagara2 {
1548 mmu: stmmu34
1549 queue: th34
1550 freq_mhz: 800
1551 max-trap-levels: 6
1552 va_bits: 48
1553 physical_memory: phys_mem0
1554 control_registers: (("mid", 34))
1555 irq_bus: irqbus0
1556 thread_id: 2
1557 other_threads: (
1558 th32,
1559 th33,
1560 th35,
1561 th36,
1562 th37,
1563 th38,
1564 th39
1565 )
1566#if defined(RTL) || defined(PLI_REPLAY)
1567 extra_irq_enable: 0
1568#endif
1569}
1570
1571OBJECT stmmu34 TYPE swerver-thread-mmu {
1572 full-swerver-decode: 1
1573 niagara-mmu: 1
1574 disable-sun4u-interrupts: 1
1575 model-real-sfar: 1
1576}
1577
1578OBJECT spu34 TYPE swerver-spu {
1579 queue: th34
1580 thread: th34
1581}
1582
1583OBJECT th35 TYPE niagara2 {
1584 mmu: stmmu35
1585 queue: th35
1586 freq_mhz: 800
1587 max-trap-levels: 6
1588 va_bits: 48
1589 physical_memory: phys_mem0
1590 control_registers: (("mid", 35))
1591 irq_bus: irqbus0
1592 thread_id: 3
1593 other_threads: (
1594 th32,
1595 th33,
1596 th34,
1597 th36,
1598 th37,
1599 th38,
1600 th39
1601 )
1602#if defined(RTL) || defined(PLI_REPLAY)
1603 extra_irq_enable: 0
1604#endif
1605}
1606
1607OBJECT stmmu35 TYPE swerver-thread-mmu {
1608 full-swerver-decode: 1
1609 niagara-mmu: 1
1610 disable-sun4u-interrupts: 1
1611 model-real-sfar: 1
1612}
1613
1614OBJECT spu35 TYPE swerver-spu {
1615 queue: th35
1616 thread: th35
1617}
1618
1619OBJECT th36 TYPE niagara2 {
1620 mmu: stmmu36
1621 queue: th36
1622 freq_mhz: 800
1623 max-trap-levels: 6
1624 va_bits: 48
1625 physical_memory: phys_mem0
1626 control_registers: (("mid", 36))
1627 irq_bus: irqbus0
1628 thread_id: 4
1629 other_threads: (
1630 th32,
1631 th33,
1632 th34,
1633 th35,
1634 th37,
1635 th38,
1636 th39
1637 )
1638#if defined(RTL) || defined(PLI_REPLAY)
1639 extra_irq_enable: 0
1640#endif
1641}
1642
1643OBJECT stmmu36 TYPE swerver-thread-mmu {
1644 full-swerver-decode: 1
1645 niagara-mmu: 1
1646 disable-sun4u-interrupts: 1
1647 model-real-sfar: 1
1648}
1649
1650OBJECT spu36 TYPE swerver-spu {
1651 queue: th36
1652 thread: th36
1653}
1654
1655OBJECT th37 TYPE niagara2 {
1656 mmu: stmmu37
1657 queue: th37
1658 freq_mhz: 800
1659 max-trap-levels: 6
1660 va_bits: 48
1661 physical_memory: phys_mem0
1662 control_registers: (("mid", 37))
1663 irq_bus: irqbus0
1664 thread_id: 5
1665 other_threads: (
1666 th32,
1667 th33,
1668 th34,
1669 th35,
1670 th36,
1671 th38,
1672 th39
1673 )
1674#if defined(RTL) || defined(PLI_REPLAY)
1675 extra_irq_enable: 0
1676#endif
1677}
1678
1679OBJECT stmmu37 TYPE swerver-thread-mmu {
1680 full-swerver-decode: 1
1681 niagara-mmu: 1
1682 disable-sun4u-interrupts: 1
1683 model-real-sfar: 1
1684}
1685
1686OBJECT spu37 TYPE swerver-spu {
1687 queue: th37
1688 thread: th37
1689}
1690
1691OBJECT th38 TYPE niagara2 {
1692 mmu: stmmu38
1693 queue: th38
1694 freq_mhz: 800
1695 max-trap-levels: 6
1696 va_bits: 48
1697 physical_memory: phys_mem0
1698 control_registers: (("mid", 38))
1699 irq_bus: irqbus0
1700 thread_id: 6
1701 other_threads: (
1702 th32,
1703 th33,
1704 th34,
1705 th35,
1706 th36,
1707 th37,
1708 th39
1709 )
1710#if defined(RTL) || defined(PLI_REPLAY)
1711 extra_irq_enable: 0
1712#endif
1713}
1714
1715OBJECT stmmu38 TYPE swerver-thread-mmu {
1716 full-swerver-decode: 1
1717 niagara-mmu: 1
1718 disable-sun4u-interrupts: 1
1719 model-real-sfar: 1
1720}
1721
1722OBJECT spu38 TYPE swerver-spu {
1723 queue: th38
1724 thread: th38
1725}
1726
1727OBJECT th39 TYPE niagara2 {
1728 mmu: stmmu39
1729 queue: th39
1730 freq_mhz: 800
1731 max-trap-levels: 6
1732 va_bits: 48
1733 physical_memory: phys_mem0
1734 control_registers: (("mid", 39))
1735 irq_bus: irqbus0
1736 thread_id: 7
1737 other_threads: (
1738 th32,
1739 th33,
1740 th34,
1741 th35,
1742 th36,
1743 th37,
1744 th38
1745 )
1746#if defined(RTL) || defined(PLI_REPLAY)
1747 extra_irq_enable: 0
1748#endif
1749}
1750
1751OBJECT stmmu39 TYPE swerver-thread-mmu {
1752 full-swerver-decode: 1
1753 niagara-mmu: 1
1754 disable-sun4u-interrupts: 1
1755 model-real-sfar: 1
1756}
1757
1758OBJECT spu39 TYPE swerver-spu {
1759 queue: th39
1760 thread: th39
1761}
1762
1763
1764#endif
1765
1766#ifdef SP5
1767
1768OBJECT swvp5 TYPE swerver-processor {
1769 thread0: th40
1770 thread1: th41
1771 thread2: th42
1772 thread3: th43
1773 thread4: th44
1774 thread5: th45
1775 thread6: th46
1776 thread7: th47
1777 mmu:swmmu5
1778}
1779
1780OBJECT swmmu5 TYPE swerver-proc-mmu {
1781}
1782
1783OBJECT th40 TYPE niagara2 {
1784 mmu: stmmu40
1785 queue: th40
1786 freq_mhz: 800
1787 max-trap-levels: 6
1788 va_bits: 48
1789 physical_memory: phys_mem0
1790 control_registers: (("mid", 40))
1791 irq_bus: irqbus0
1792 thread_id: 0
1793 other_threads: (
1794 th41,
1795 th42,
1796 th43,
1797 th44,
1798 th45,
1799 th46,
1800 th47
1801 )
1802#if defined(RTL) || defined(PLI_REPLAY)
1803 extra_irq_enable: 0
1804#endif
1805}
1806
1807OBJECT stmmu40 TYPE swerver-thread-mmu {
1808 full-swerver-decode: 1
1809 niagara-mmu: 1
1810 disable-sun4u-interrupts: 1
1811 model-real-sfar: 1
1812}
1813
1814OBJECT spu40 TYPE swerver-spu {
1815 queue: th40
1816 thread: th40
1817}
1818
1819OBJECT th41 TYPE niagara2 {
1820 mmu: stmmu41
1821 queue: th41
1822 freq_mhz: 800
1823 max-trap-levels: 6
1824 va_bits: 48
1825 physical_memory: phys_mem0
1826 control_registers: (("mid", 41))
1827 irq_bus: irqbus0
1828 thread_id: 1
1829 other_threads: (
1830 th40,
1831 th42,
1832 th43,
1833 th44,
1834 th45,
1835 th46,
1836 th47
1837 )
1838#if defined(RTL) || defined(PLI_REPLAY)
1839 extra_irq_enable: 0
1840#endif
1841}
1842
1843OBJECT stmmu41 TYPE swerver-thread-mmu {
1844 full-swerver-decode: 1
1845 niagara-mmu: 1
1846 disable-sun4u-interrupts: 1
1847 model-real-sfar: 1
1848}
1849
1850OBJECT spu41 TYPE swerver-spu {
1851 queue: th41
1852 thread: th41
1853}
1854
1855OBJECT th42 TYPE niagara2 {
1856 mmu: stmmu42
1857 queue: th42
1858 freq_mhz: 800
1859 max-trap-levels: 6
1860 va_bits: 48
1861 physical_memory: phys_mem0
1862 control_registers: (("mid", 42))
1863 irq_bus: irqbus0
1864 thread_id: 2
1865 other_threads: (
1866 th40,
1867 th41,
1868 th43,
1869 th44,
1870 th45,
1871 th46,
1872 th47
1873 )
1874#if defined(RTL) || defined(PLI_REPLAY)
1875 extra_irq_enable: 0
1876#endif
1877}
1878
1879OBJECT stmmu42 TYPE swerver-thread-mmu {
1880 full-swerver-decode: 1
1881 niagara-mmu: 1
1882 disable-sun4u-interrupts: 1
1883 model-real-sfar: 1
1884}
1885
1886OBJECT spu42 TYPE swerver-spu {
1887 queue: th42
1888 thread: th42
1889}
1890
1891OBJECT th43 TYPE niagara2 {
1892 mmu: stmmu43
1893 queue: th43
1894 freq_mhz: 800
1895 max-trap-levels: 6
1896 va_bits: 48
1897 physical_memory: phys_mem0
1898 control_registers: (("mid", 43))
1899 irq_bus: irqbus0
1900 thread_id: 3
1901 other_threads: (
1902 th40,
1903 th41,
1904 th42,
1905 th44,
1906 th45,
1907 th46,
1908 th47
1909 )
1910#if defined(RTL) || defined(PLI_REPLAY)
1911 extra_irq_enable: 0
1912#endif
1913}
1914
1915OBJECT stmmu43 TYPE swerver-thread-mmu {
1916 full-swerver-decode: 1
1917 niagara-mmu: 1
1918 disable-sun4u-interrupts: 1
1919 model-real-sfar: 1
1920}
1921
1922OBJECT spu43 TYPE swerver-spu {
1923 queue: th43
1924 thread: th43
1925}
1926
1927OBJECT th44 TYPE niagara2 {
1928 mmu: stmmu44
1929 queue: th44
1930 freq_mhz: 800
1931 max-trap-levels: 6
1932 va_bits: 48
1933 physical_memory: phys_mem0
1934 control_registers: (("mid", 44))
1935 irq_bus: irqbus0
1936 thread_id: 4
1937 other_threads: (
1938 th40,
1939 th41,
1940 th42,
1941 th43,
1942 th45,
1943 th46,
1944 th47
1945 )
1946#if defined(RTL) || defined(PLI_REPLAY)
1947 extra_irq_enable: 0
1948#endif
1949}
1950
1951OBJECT stmmu44 TYPE swerver-thread-mmu {
1952 full-swerver-decode: 1
1953 niagara-mmu: 1
1954 disable-sun4u-interrupts: 1
1955 model-real-sfar: 1
1956}
1957
1958OBJECT spu44 TYPE swerver-spu {
1959 queue: th44
1960 thread: th44
1961}
1962
1963OBJECT th45 TYPE niagara2 {
1964 mmu: stmmu45
1965 queue: th45
1966 freq_mhz: 800
1967 max-trap-levels: 6
1968 va_bits: 48
1969 physical_memory: phys_mem0
1970 control_registers: (("mid", 45))
1971 irq_bus: irqbus0
1972 thread_id: 5
1973 other_threads: (
1974 th40,
1975 th41,
1976 th42,
1977 th43,
1978 th44,
1979 th46,
1980 th47
1981 )
1982#if defined(RTL) || defined(PLI_REPLAY)
1983 extra_irq_enable: 0
1984#endif
1985}
1986
1987OBJECT stmmu45 TYPE swerver-thread-mmu {
1988 full-swerver-decode: 1
1989 niagara-mmu: 1
1990 disable-sun4u-interrupts: 1
1991 model-real-sfar: 1
1992}
1993
1994OBJECT spu45 TYPE swerver-spu {
1995 queue: th45
1996 thread: th45
1997}
1998
1999OBJECT th46 TYPE niagara2 {
2000 mmu: stmmu46
2001 queue: th46
2002 freq_mhz: 800
2003 max-trap-levels: 6
2004 va_bits: 48
2005 physical_memory: phys_mem0
2006 control_registers: (("mid", 46))
2007 irq_bus: irqbus0
2008 thread_id: 6
2009 other_threads: (
2010 th40,
2011 th41,
2012 th42,
2013 th43,
2014 th44,
2015 th45,
2016 th47
2017 )
2018#if defined(RTL) || defined(PLI_REPLAY)
2019 extra_irq_enable: 0
2020#endif
2021}
2022
2023OBJECT stmmu46 TYPE swerver-thread-mmu {
2024 full-swerver-decode: 1
2025 niagara-mmu: 1
2026 disable-sun4u-interrupts: 1
2027 model-real-sfar: 1
2028}
2029
2030OBJECT spu46 TYPE swerver-spu {
2031 queue: th46
2032 thread: th46
2033}
2034
2035OBJECT th47 TYPE niagara2 {
2036 mmu: stmmu47
2037 queue: th47
2038 freq_mhz: 800
2039 max-trap-levels: 6
2040 va_bits: 48
2041 physical_memory: phys_mem0
2042 control_registers: (("mid", 47))
2043 irq_bus: irqbus0
2044 thread_id: 7
2045 other_threads: (
2046 th40,
2047 th41,
2048 th42,
2049 th43,
2050 th44,
2051 th45,
2052 th46
2053 )
2054#if defined(RTL) || defined(PLI_REPLAY)
2055 extra_irq_enable: 0
2056#endif
2057}
2058
2059OBJECT stmmu47 TYPE swerver-thread-mmu {
2060 full-swerver-decode: 1
2061 niagara-mmu: 1
2062 disable-sun4u-interrupts: 1
2063 model-real-sfar: 1
2064}
2065
2066OBJECT spu47 TYPE swerver-spu {
2067 queue: th47
2068 thread: th47
2069}
2070
2071
2072#endif
2073
2074#ifdef SP6
2075
2076OBJECT swvp6 TYPE swerver-processor {
2077 thread0: th48
2078 thread1: th49
2079 thread2: th50
2080 thread3: th51
2081 thread4: th52
2082 thread5: th53
2083 thread6: th54
2084 thread7: th55
2085 mmu:swmmu6
2086}
2087
2088OBJECT swmmu6 TYPE swerver-proc-mmu {
2089}
2090
2091OBJECT th48 TYPE niagara2 {
2092 mmu: stmmu48
2093 queue: th48
2094 freq_mhz: 800
2095 max-trap-levels: 6
2096 va_bits: 48
2097 physical_memory: phys_mem0
2098 control_registers: (("mid", 48))
2099 irq_bus: irqbus0
2100 thread_id: 0
2101 other_threads: (
2102 th49,
2103 th50,
2104 th51,
2105 th52,
2106 th53,
2107 th54,
2108 th55
2109 )
2110#if defined(RTL) || defined(PLI_REPLAY)
2111 extra_irq_enable: 0
2112#endif
2113}
2114
2115OBJECT stmmu48 TYPE swerver-thread-mmu {
2116 full-swerver-decode: 1
2117 niagara-mmu: 1
2118 disable-sun4u-interrupts: 1
2119 model-real-sfar: 1
2120}
2121
2122OBJECT spu48 TYPE swerver-spu {
2123 queue: th48
2124 thread: th48
2125}
2126
2127OBJECT th49 TYPE niagara2 {
2128 mmu: stmmu49
2129 queue: th49
2130 freq_mhz: 800
2131 max-trap-levels: 6
2132 va_bits: 48
2133 physical_memory: phys_mem0
2134 control_registers: (("mid", 49))
2135 irq_bus: irqbus0
2136 thread_id: 1
2137 other_threads: (
2138 th48,
2139 th50,
2140 th51,
2141 th52,
2142 th53,
2143 th54,
2144 th55
2145 )
2146#if defined(RTL) || defined(PLI_REPLAY)
2147 extra_irq_enable: 0
2148#endif
2149}
2150
2151OBJECT stmmu49 TYPE swerver-thread-mmu {
2152 full-swerver-decode: 1
2153 niagara-mmu: 1
2154 disable-sun4u-interrupts: 1
2155 model-real-sfar: 1
2156}
2157
2158OBJECT spu49 TYPE swerver-spu {
2159 queue: th49
2160 thread: th49
2161}
2162
2163OBJECT th50 TYPE niagara2 {
2164 mmu: stmmu50
2165 queue: th50
2166 freq_mhz: 800
2167 max-trap-levels: 6
2168 va_bits: 48
2169 physical_memory: phys_mem0
2170 control_registers: (("mid", 50))
2171 irq_bus: irqbus0
2172 thread_id: 2
2173 other_threads: (
2174 th48,
2175 th49,
2176 th51,
2177 th52,
2178 th53,
2179 th54,
2180 th55
2181 )
2182#if defined(RTL) || defined(PLI_REPLAY)
2183 extra_irq_enable: 0
2184#endif
2185}
2186
2187OBJECT stmmu50 TYPE swerver-thread-mmu {
2188 full-swerver-decode: 1
2189 niagara-mmu: 1
2190 disable-sun4u-interrupts: 1
2191 model-real-sfar: 1
2192}
2193
2194OBJECT spu50 TYPE swerver-spu {
2195 queue: th50
2196 thread: th50
2197}
2198
2199OBJECT th51 TYPE niagara2 {
2200 mmu: stmmu51
2201 queue: th51
2202 freq_mhz: 800
2203 max-trap-levels: 6
2204 va_bits: 48
2205 physical_memory: phys_mem0
2206 control_registers: (("mid", 51))
2207 irq_bus: irqbus0
2208 thread_id: 3
2209 other_threads: (
2210 th48,
2211 th49,
2212 th50,
2213 th52,
2214 th53,
2215 th54,
2216 th55
2217 )
2218#if defined(RTL) || defined(PLI_REPLAY)
2219 extra_irq_enable: 0
2220#endif
2221}
2222
2223OBJECT stmmu51 TYPE swerver-thread-mmu {
2224 full-swerver-decode: 1
2225 niagara-mmu: 1
2226 disable-sun4u-interrupts: 1
2227 model-real-sfar: 1
2228}
2229
2230OBJECT spu51 TYPE swerver-spu {
2231 queue: th51
2232 thread: th51
2233}
2234
2235OBJECT th52 TYPE niagara2 {
2236 mmu: stmmu52
2237 queue: th52
2238 freq_mhz: 800
2239 max-trap-levels: 6
2240 va_bits: 48
2241 physical_memory: phys_mem0
2242 control_registers: (("mid", 52))
2243 irq_bus: irqbus0
2244 thread_id: 4
2245 other_threads: (
2246 th48,
2247 th49,
2248 th50,
2249 th51,
2250 th53,
2251 th54,
2252 th55
2253 )
2254#if defined(RTL) || defined(PLI_REPLAY)
2255 extra_irq_enable: 0
2256#endif
2257}
2258
2259OBJECT stmmu52 TYPE swerver-thread-mmu {
2260 full-swerver-decode: 1
2261 niagara-mmu: 1
2262 disable-sun4u-interrupts: 1
2263 model-real-sfar: 1
2264}
2265
2266OBJECT spu52 TYPE swerver-spu {
2267 queue: th52
2268 thread: th52
2269}
2270
2271OBJECT th53 TYPE niagara2 {
2272 mmu: stmmu53
2273 queue: th53
2274 freq_mhz: 800
2275 max-trap-levels: 6
2276 va_bits: 48
2277 physical_memory: phys_mem0
2278 control_registers: (("mid", 53))
2279 irq_bus: irqbus0
2280 thread_id: 5
2281 other_threads: (
2282 th48,
2283 th49,
2284 th50,
2285 th51,
2286 th52,
2287 th54,
2288 th55
2289 )
2290#if defined(RTL) || defined(PLI_REPLAY)
2291 extra_irq_enable: 0
2292#endif
2293}
2294
2295OBJECT stmmu53 TYPE swerver-thread-mmu {
2296 full-swerver-decode: 1
2297 niagara-mmu: 1
2298 disable-sun4u-interrupts: 1
2299 model-real-sfar: 1
2300}
2301
2302OBJECT spu53 TYPE swerver-spu {
2303 queue: th53
2304 thread: th53
2305}
2306
2307OBJECT th54 TYPE niagara2 {
2308 mmu: stmmu54
2309 queue: th54
2310 freq_mhz: 800
2311 max-trap-levels: 6
2312 va_bits: 48
2313 physical_memory: phys_mem0
2314 control_registers: (("mid", 54))
2315 irq_bus: irqbus0
2316 thread_id: 6
2317 other_threads: (
2318 th48,
2319 th49,
2320 th50,
2321 th51,
2322 th52,
2323 th53,
2324 th55
2325 )
2326#if defined(RTL) || defined(PLI_REPLAY)
2327 extra_irq_enable: 0
2328#endif
2329}
2330
2331OBJECT stmmu54 TYPE swerver-thread-mmu {
2332 full-swerver-decode: 1
2333 niagara-mmu: 1
2334 disable-sun4u-interrupts: 1
2335 model-real-sfar: 1
2336}
2337
2338OBJECT spu54 TYPE swerver-spu {
2339 queue: th54
2340 thread: th54
2341}
2342
2343OBJECT th55 TYPE niagara2 {
2344 mmu: stmmu55
2345 queue: th55
2346 freq_mhz: 800
2347 max-trap-levels: 6
2348 va_bits: 48
2349 physical_memory: phys_mem0
2350 control_registers: (("mid", 55))
2351 irq_bus: irqbus0
2352 thread_id: 7
2353 other_threads: (
2354 th48,
2355 th49,
2356 th50,
2357 th51,
2358 th52,
2359 th53,
2360 th54
2361 )
2362#if defined(RTL) || defined(PLI_REPLAY)
2363 extra_irq_enable: 0
2364#endif
2365}
2366
2367OBJECT stmmu55 TYPE swerver-thread-mmu {
2368 full-swerver-decode: 1
2369 niagara-mmu: 1
2370 disable-sun4u-interrupts: 1
2371 model-real-sfar: 1
2372}
2373
2374OBJECT spu55 TYPE swerver-spu {
2375 queue: th55
2376 thread: th55
2377}
2378
2379
2380#endif
2381
2382#ifdef SP7
2383
2384OBJECT swvp7 TYPE swerver-processor {
2385 thread0: th56
2386 thread1: th57
2387 thread2: th58
2388 thread3: th59
2389 thread4: th60
2390 thread5: th61
2391 thread6: th62
2392 thread7: th63
2393 mmu:swmmu7
2394}
2395
2396OBJECT swmmu7 TYPE swerver-proc-mmu {
2397}
2398
2399OBJECT th56 TYPE niagara2 {
2400 mmu: stmmu56
2401 queue: th56
2402 freq_mhz: 800
2403 max-trap-levels: 6
2404 va_bits: 48
2405 physical_memory: phys_mem0
2406 control_registers: (("mid", 56))
2407 irq_bus: irqbus0
2408 thread_id: 0
2409 other_threads: (
2410 th57,
2411 th58,
2412 th59,
2413 th60,
2414 th61,
2415 th62,
2416 th63
2417 )
2418#if defined(RTL) || defined(PLI_REPLAY)
2419 extra_irq_enable: 0
2420#endif
2421}
2422
2423OBJECT stmmu56 TYPE swerver-thread-mmu {
2424 full-swerver-decode: 1
2425 niagara-mmu: 1
2426 disable-sun4u-interrupts: 1
2427 model-real-sfar: 1
2428}
2429
2430OBJECT spu56 TYPE swerver-spu {
2431 queue: th56
2432 thread: th56
2433}
2434
2435OBJECT th57 TYPE niagara2 {
2436 mmu: stmmu57
2437 queue: th57
2438 freq_mhz: 800
2439 max-trap-levels: 6
2440 va_bits: 48
2441 physical_memory: phys_mem0
2442 control_registers: (("mid", 57))
2443 irq_bus: irqbus0
2444 thread_id: 1
2445 other_threads: (
2446 th56,
2447 th58,
2448 th59,
2449 th60,
2450 th61,
2451 th62,
2452 th63
2453 )
2454#if defined(RTL) || defined(PLI_REPLAY)
2455 extra_irq_enable: 0
2456#endif
2457}
2458
2459OBJECT stmmu57 TYPE swerver-thread-mmu {
2460 full-swerver-decode: 1
2461 niagara-mmu: 1
2462 disable-sun4u-interrupts: 1
2463 model-real-sfar: 1
2464}
2465
2466OBJECT spu57 TYPE swerver-spu {
2467 queue: th57
2468 thread: th57
2469}
2470
2471OBJECT th58 TYPE niagara2 {
2472 mmu: stmmu58
2473 queue: th58
2474 freq_mhz: 800
2475 max-trap-levels: 6
2476 va_bits: 48
2477 physical_memory: phys_mem0
2478 control_registers: (("mid", 58))
2479 irq_bus: irqbus0
2480 thread_id: 2
2481 other_threads: (
2482 th56,
2483 th57,
2484 th59,
2485 th60,
2486 th61,
2487 th62,
2488 th63
2489 )
2490#if defined(RTL) || defined(PLI_REPLAY)
2491 extra_irq_enable: 0
2492#endif
2493}
2494
2495OBJECT stmmu58 TYPE swerver-thread-mmu {
2496 full-swerver-decode: 1
2497 niagara-mmu: 1
2498 disable-sun4u-interrupts: 1
2499 model-real-sfar: 1
2500}
2501
2502OBJECT spu58 TYPE swerver-spu {
2503 queue: th58
2504 thread: th58
2505}
2506
2507OBJECT th59 TYPE niagara2 {
2508 mmu: stmmu59
2509 queue: th59
2510 freq_mhz: 800
2511 max-trap-levels: 6
2512 va_bits: 48
2513 physical_memory: phys_mem0
2514 control_registers: (("mid", 59))
2515 irq_bus: irqbus0
2516 thread_id: 3
2517 other_threads: (
2518 th56,
2519 th57,
2520 th58,
2521 th60,
2522 th61,
2523 th62,
2524 th63
2525 )
2526#if defined(RTL) || defined(PLI_REPLAY)
2527 extra_irq_enable: 0
2528#endif
2529}
2530
2531OBJECT stmmu59 TYPE swerver-thread-mmu {
2532 full-swerver-decode: 1
2533 niagara-mmu: 1
2534 disable-sun4u-interrupts: 1
2535 model-real-sfar: 1
2536}
2537
2538OBJECT spu59 TYPE swerver-spu {
2539 queue: th59
2540 thread: th59
2541}
2542
2543OBJECT th60 TYPE niagara2 {
2544 mmu: stmmu60
2545 queue: th60
2546 freq_mhz: 800
2547 max-trap-levels: 6
2548 va_bits: 48
2549 physical_memory: phys_mem0
2550 control_registers: (("mid", 60))
2551 irq_bus: irqbus0
2552 thread_id: 4
2553 other_threads: (
2554 th56,
2555 th57,
2556 th58,
2557 th59,
2558 th61,
2559 th62,
2560 th63
2561 )
2562#if defined(RTL) || defined(PLI_REPLAY)
2563 extra_irq_enable: 0
2564#endif
2565}
2566
2567OBJECT stmmu60 TYPE swerver-thread-mmu {
2568 full-swerver-decode: 1
2569 niagara-mmu: 1
2570 disable-sun4u-interrupts: 1
2571 model-real-sfar: 1
2572}
2573
2574OBJECT spu60 TYPE swerver-spu {
2575 queue: th60
2576 thread: th60
2577}
2578
2579OBJECT th61 TYPE niagara2 {
2580 mmu: stmmu61
2581 queue: th61
2582 freq_mhz: 800
2583 max-trap-levels: 6
2584 va_bits: 48
2585 physical_memory: phys_mem0
2586 control_registers: (("mid", 61))
2587 irq_bus: irqbus0
2588 thread_id: 5
2589 other_threads: (
2590 th56,
2591 th57,
2592 th58,
2593 th59,
2594 th60,
2595 th62,
2596 th63
2597 )
2598#if defined(RTL) || defined(PLI_REPLAY)
2599 extra_irq_enable: 0
2600#endif
2601}
2602
2603OBJECT stmmu61 TYPE swerver-thread-mmu {
2604 full-swerver-decode: 1
2605 niagara-mmu: 1
2606 disable-sun4u-interrupts: 1
2607 model-real-sfar: 1
2608}
2609
2610OBJECT spu61 TYPE swerver-spu {
2611 queue: th61
2612 thread: th61
2613}
2614
2615OBJECT th62 TYPE niagara2 {
2616 mmu: stmmu62
2617 queue: th62
2618 freq_mhz: 800
2619 max-trap-levels: 6
2620 va_bits: 48
2621 physical_memory: phys_mem0
2622 control_registers: (("mid", 62))
2623 irq_bus: irqbus0
2624 thread_id: 6
2625 other_threads: (
2626 th56,
2627 th57,
2628 th58,
2629 th59,
2630 th60,
2631 th61,
2632 th63
2633 )
2634#if defined(RTL) || defined(PLI_REPLAY)
2635 extra_irq_enable: 0
2636#endif
2637}
2638
2639OBJECT stmmu62 TYPE swerver-thread-mmu {
2640 full-swerver-decode: 1
2641 niagara-mmu: 1
2642 disable-sun4u-interrupts: 1
2643 model-real-sfar: 1
2644}
2645
2646OBJECT spu62 TYPE swerver-spu {
2647 queue: th62
2648 thread: th62
2649}
2650
2651OBJECT th63 TYPE niagara2 {
2652 mmu: stmmu63
2653 queue: th63
2654 freq_mhz: 800
2655 max-trap-levels: 6
2656 va_bits: 48
2657 physical_memory: phys_mem0
2658 control_registers: (("mid", 63))
2659 irq_bus: irqbus0
2660 thread_id: 7
2661 other_threads: (
2662 th56,
2663 th57,
2664 th58,
2665 th59,
2666 th60,
2667 th61,
2668 th62
2669 )
2670#if defined(RTL) || defined(PLI_REPLAY)
2671 extra_irq_enable: 0
2672#endif
2673}
2674
2675OBJECT stmmu63 TYPE swerver-thread-mmu {
2676 full-swerver-decode: 1
2677 niagara-mmu: 1
2678 disable-sun4u-interrupts: 1
2679 model-real-sfar: 1
2680}
2681
2682OBJECT spu63 TYPE swerver-spu {
2683 queue: th63
2684 thread: th63
2685}
2686
2687
2688#endif
2689
2690OBJECT phys_mem0 TYPE memory-space {
2691 map: (
2692 (0x00000000000, memory_cache, 0x0, 0, 0x2000000000),
2693#ifdef CIOP0
2694 (0x0d500000000, ciop0, 0, 0, 0xb00000000),
2695 (0x0d300000000, bsc0, 0, 0, 0x200000000),
2696 (0x0c500000000, egress0, 0, 0, 0x200000000),
2697 (0x0c300000000, ingress0, 0, 0, 0x200000000),
2698 (0x0d000000000, rdma0, 0, 0, 0x300000000),
2699 (0x0ef00000000, echo0, 0, 0, 0x100000000),
2700#else
2701 (0x08000000000, memory_ciop, 0x0, 0, 0x7f00000000),
2702#endif
2703 (0x0ff00000000, memory0, 0x0, 0, 0x100000000))
2704#if defined(MOM)
2705 timing_model: mom0
2706 snoop_device: mom0
2707#elif !defined(NOLDST_SYNC) || defined(INDRA_MEM)
2708 timing_model: swvmem0
2709 snoop_device: swvmem0
2710#endif
2711}
2712
2713OBJECT memory0 TYPE ram {
2714 image: memory0_image
2715}
2716
2717OBJECT memory0_image TYPE image {
2718 size: 0x100000000
2719 queue: th00
2720}
2721
2722OBJECT memory_cache TYPE ram {
2723 image: memory_cache_image
2724}
2725
2726OBJECT memory_cache_image TYPE image {
2727 size: 0x2000000000
2728 queue: th00
2729}
2730
Full OpenSPARC design & verification tarball including full HDL.