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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / 8core.diaglist
CommitLineData
86530b38
AT		 1///////////////////////////////////////////////////////////////////////////////
2//
3// Description: DIAGS for Tester -
4// DTM diags that run on all 8 cores.
5//
6//
7///////////////////////////////////////////////////////////////////////////////
8
9<8core_diags name=8core_diags>
10<sys(8core_diags)>
11
12<runargs -vcs_run_args=+EIGHT_CORE_DTM2_TESTER>
13
14// Description: DIAGS for Tester -
15// Diags which are eight cores and
16// uses default memory config
17//
18//
19
20// Always run with TSO_CHECKER enabled
21<runargs -sas_run_args=-DTSO_CHECKER>
22
23//---MPGen diags {{{
24<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>
25
26<8core_mpgen_dynamic_caches>
27mpgen_dynamic_caches_2 mpgen_dynamic_caches_2.s
28mpgen_dynamic_caches_4 mpgen_dynamic_caches_4.s
29mpgen_dynamic_caches_5 mpgen_dynamic_caches_5.s
30</8core_mpgen_dynamic_caches>
31
32<8core_mpgen_dynamic_pwr_mgmt>
33mpgen_dynamic_pwr_mgmt mpgen_dynamic_pwr_mgmt.s
34mpgen_dynamic_pwr_mgmt_2 mpgen_dynamic_pwr_mgmt_2.s
35mpgen_dynamic_pwr_mgmt_3 mpgen_dynamic_pwr_mgmt_3.s
36mpgen_dynamic_pwr_mgmt_4 mpgen_dynamic_pwr_mgmt_4.s
37</8core_mpgen_dynamic_pwr_mgmt>
38
39<8core_mpgen_tso_all_banks>
40mpgen_tso_all_banks_2 mpgen_tso_all_banks_2.s
41mpgen_tso_all_banks_3 mpgen_tso_all_banks_3.s
42mpgen_tso_all_banks_4 mpgen_tso_all_banks_4.s
43mpgen_tso_all_banks_5 mpgen_tso_all_banks_5.s
44</8core_mpgen_tso_all_banks>
45
46<8core_mpgen_tso_atomic_all_banks>
47mpgen_tso_atomic_all_banks_2 mpgen_tso_atomic_all_banks_2.s
48mpgen_tso_atomic_all_banks_3 mpgen_tso_atomic_all_banks_3.s
49mpgen_tso_atomic_all_banks_4 mpgen_tso_atomic_all_banks_4.s
50mpgen_tso_atomic_all_banks_5 mpgen_tso_atomic_all_banks_5.s
51</8core_mpgen_tso_atomic_all_banks>
52
53<8core_mpgen_tso_atomic_asi_one_bank>
54mpgen_tso_atomic_asi_one_bank_3 mpgen_tso_atomic_asi_one_bank_3.s
55mpgen_tso_atomic_asi_one_bank_4 mpgen_tso_atomic_asi_one_bank_4.s
56mpgen_tso_atomic_asi_one_bank_5 mpgen_tso_atomic_asi_one_bank_5.s
57</8core_mpgen_tso_atomic_asi_one_bank>
58
59<8core_mpgen_tso_atomic_one_bank>
60mpgen_tso_atomic_one_bank mpgen_tso_atomic_one_bank.s
61mpgen_tso_atomic_one_bank_2 mpgen_tso_atomic_one_bank_2.s
62mpgen_tso_atomic_one_bank_3 mpgen_tso_atomic_one_bank_3.s
63mpgen_tso_atomic_one_bank_4 mpgen_tso_atomic_one_bank_4.s
64mpgen_tso_atomic_one_bank_5 mpgen_tso_atomic_one_bank_5.s
65</8core_mpgen_tso_atomic_one_bank>
66
67<8core_mpgen_tso_ba_all_banks>
68mpgen_tso_ba_all_banks mpgen_tso_ba_all_banks.s
69mpgen_tso_ba_all_banks_2 mpgen_tso_ba_all_banks_2.s
70mpgen_tso_ba_all_banks_3 mpgen_tso_ba_all_banks_3.s
71mpgen_tso_ba_all_banks_4 mpgen_tso_ba_all_banks_4.s
72mpgen_tso_ba_all_banks_5 mpgen_tso_ba_all_banks_5.s
73</8core_mpgen_tso_ba_all_banks>
74
75<8core_mpgen_tso_ba_one_bank>
76mpgen_tso_ba_one_bank_3 mpgen_tso_ba_one_bank_3.s
77mpgen_tso_ba_one_bank_4 mpgen_tso_ba_one_bank_4.s
78mpgen_tso_ba_one_bank_5 mpgen_tso_ba_one_bank_5.s
79</8core_mpgen_tso_ba_one_bank>
80
81<8core_mpgen_tso_one_bank>
82mpgen_tso_one_bank mpgen_tso_one_bank.s
83mpgen_tso_one_bank_3 mpgen_tso_one_bank_3.s
84mpgen_tso_one_bank_4 mpgen_tso_one_bank_4.s
85mpgen_tso_one_bank_5 mpgen_tso_one_bank_5.s
86</8core_mpgen_tso_one_bank>
87
88
89</runargs>
90//---MPGen diags }}}
91
92</runargs>
93
94<8core_ncu>
95
96<runargs -midas_args=-DCMP_THREAD_START=0x1 -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
97interrupt_int_vec_dis interrupt_INT_VEC_DIS.s
98interrupt_pci_spurious_err interrupt_pci_spurious_err.s
99interrupt_queue_cpu_mondo_mode interrupt_QUEUE_CPU_MONDO_mode.s
100interrupt_queue_cpu_mondo_trap interrupt_QUEUE_CPU_MONDO_trap.s
101interrupt_queue_dev_mondo_mode interrupt_QUEUE_DEV_MONDO_mode.s
102interrupt_queue_dev_mondo_trap interrupt_QUEUE_DEV_MONDO_trap.s
103interrupt_swvr_intr_r interrupt_SWVR_INTR_R.s
104</runargs>
105
106<runargs -midas_args=-DCMP_THREAD_START=0x3 -finish_mask=3 -midas_args=-DSYNC_THREADS=0x3 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
107<8core_ncu_subset>
108interrupt_swvr_intr_r_mode interrupt_SWVR_INTR_R_mode.s
109interrupt_swvr_intr_rec_mode interrupt_SWVR_INTR_REC_mode.s
110interrupt_swvr_intr_w_mode interrupt_SWVR_INTR_W_mode.s
111</8core_ncu_subset>
112</runargs>
113
114<runargs -midas_args=-DCMP_THREAD_START=0x1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
115n2_cmp_upk_pk_upk n2_cmp_upk_pk_upk.s -finish_mask=3
116</runargs>
117
118<runargs -midas_args=-DCMP_THREAD_START=0x1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
119ncu_1core_wakup ncu_1core_wakup.s -finish_mask=0x2b
120</runargs>
121
122</8core_ncu>
123
124</runargs> // EIGHT_CORE_DTM2_TESTER
125
126</sys(8core_diags)>
127</8core_diags>
128
Full OpenSPARC design & verification tarball including full HDL.