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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_DMUSII_CCE.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_DMUSII_CCE.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_ERR_STAT_REG 0x8400002280
46#define L2_ERR_STAT_REG 0xAB00000100
47
48#include "err_defines.h"
49#include "hboot.s"
50#include "peu_defines.h"
51
52#define DMA_DATA_ADDR 0x0000000123456700
53
54#define DMA_DATA_BYP_ADDR1 0xfffc000123456000
55#define DMA_DATA_BYP_ADDR2 0xfffc000123456040
56#define DMA_DATA_BYP_ADDR3 0xfffc000123456080
57#define DMA_DATA_BYP_ADDR4 0xfffc000123456100
58#define DMA_DATA_BYP_ADDR5 0xfffc000123456140
59#define DMA_DATA_BYP_ADDR6 0xfffc000123456180
60#define DMA_DATA_BYP_ADDR7 0xfffc0001234561c0
61
62
63#define ERR_BITS 0x4000000
64#define ERR_BITS_EXPECT 0x8000000004000000
65
66
67#define SOC_NCU_SYN_REG 0x8000003038
68#define SOC_SII_SYN_REG 0x8000003030
69
70/************************************************************************
71 Test case code start
72 ************************************************************************/
73.text
74.global main
75.global My_Corrected_ECC_error_trap
76.global My_Recoverable_Sw_error_trap
77
78main:
79 ta T_CHANGE_HPRIV
80 nop
81
82 clr %i7
83 clr %o6
84 clr %o7
85
86L2_err_enable:
87 set 0x3, %l1
88 mov 0xaa, %g2
89 sllx %g2, 32, %g2
90 stx %l1, [%g2]
91 stx %l1, [%g2 + 0x40]
92 stx %l1, [%g2 + 0x80]
93 stx %l1, [%g2 + 0xc0]
94 stx %l1, [%g2 + 0x100]
95 stx %l1, [%g2 + 0x140]
96 stx %l1, [%g2 + 0x180]
97 stx %l1, [%g2 + 0x1c0]
98
99dma_uev:
100 ! enable bypass in IOMMU
101 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
102 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
103 stx %g3, [%g2]
104 ldx [%g2], %g3
105
106
107inj_err1:
108 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(DMUSII_CCE, 0, 123456000)
109
110Wr_Evnt1: nop;
111 ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt1) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
112
113 ldx [%g2], %g3
114esr1:
115 setx 0x8000000000000008, %g7, %g5 ! SiiDmuCTagCe
116 setx SOC_ESR_REG, %g7, %g2
117 setx 0x20, %g7, %g6
118esr_loop1:
119 dec %g6
120 cmp %g6, %g0
121 be %xcc, test_failed
122 nop
123
124 ldx [%g2], %g3
125
126 cmp %g3, %g5
127 be %xcc, eie_1
128 nop
129
130 ba esr_loop1
131 nop
132
133eie_1:
134 setx SOC_EIE_REG, %g3, %g2
135 set 0x8, %g1
136 stx %g1, [%g2]
137 membar 0x40
138
139 set 0x1, %g1 ! 1 Trap;
140 setx 0x20, %g7, %g6
141err_trap_loop1:
142 cmp %g6, %g0
143 be %xcc, test_failed
144 nop
145
146 cmp %g1, %i7
147 be %xcc, test_passed
148 nop
149
150 ba err_trap_loop1
151 nop
152
153
154test_passed:
155 EXIT_GOOD
156
157test_failed:
158 EXIT_BAD
159
160
161/************************************************************************
162 RAS
163 Trap Handlers
164 ************************************************************************/
165My_Recoverable_Sw_error_trap:
166 ba test_failed
167 nop
168
169
170My_Corrected_ECC_error_trap:
171 inc %i7
172
173check_Syndromes:
174 setx SOC_SII_SYN_REG, %g7, %g1
175 ldx [%g1], %g2
176 cmp %g2, %g0
177 bne test_failed
178 nop
179
180check_desr_tt63:
181 ldxa [%g0]0x4c, %g2
182 nop
183 setx 0x8b00000000000000, %l0, %g3
184 subcc %g2, %g3, %g4
185 brnz %g4, test_failed
186 nop
187
188checks_tt63:
189 mov 0x1, %g1
190 cmp %g1, %i7
191 be check_1_tt63
192 nop
193
194 mov 0x4, %g1
195 cmp %g1, %i7
196 be check_4_tt63
197 nop
198
199
200 mov 0x8, %g1
201 cmp %g1, %i7
202 be check_8_tt63
203 nop
204
205 ba test_failed
206 nop
207
208check_1_tt63:
209 setx 0x8000000000000008, %g7, %g5
210 setx SOC_PER_REG, %l7, %g1
211 ldx [%g1], %g2
212 sub %g2, %g5, %g3
213 brnz %g3, test_failed
214 nop
215
216 ba clear_per_tt63
217 nop
218
219check_4_tt63:
220 setx 0x8000000000000400, %g7, %g5
221 setx SOC_PER_REG, %l7, %g1
222 ldx [%g1], %g2
223 sub %g2, %g5, %g3
224 brnz %g3, test_failed
225 nop
226
227 ba clear_per_tt63
228 nop
229
230check_8_tt63:
231 setx 0x8000000004000000, %g7, %g5
232 setx SOC_PER_REG, %l7, %g1
233 ldx [%g1], %g2
234 sub %g2, %g5, %g3
235 brnz %g3, test_failed
236 nop
237
238 ba clear_per_tt63
239 nop
240
241clear_per_tt63:
242 setx SOC_PER_REG, %l7, %i0
243 stx %g0, [%i0]
244 nop
245
246clear_esr_tt63:
247 setx SOC_ESR_REG, %l7, %i0
248 stx %g0, [%i0]
249 nop
250
251
252 retry
253 nop
254
255/************************************************************************
256 Test case data start
257************************************************************************/
258
259SECTION .DATA DATA_VA=DMA_DATA_ADDR
260attr_data {
261 Name = .DATA,
262 hypervisor,
263 compressimage
264}
265
266.data
267.global PCIAddr9
268 .xword 0x0001020304050607
269 .xword 0x08090a0b0c0d0e0f
270 .xword 0x1011121314151617
271 .xword 0x18191a1b1c1d1e1f
272 .xword 0x2021222324252627
273 .xword 0x28292a2b2c2d2e2f
274 .xword 0x3031323334353637
275 .xword 0x38393a3b3c3d3e3f
276
277 .xword 0x4041424344454647
278 .xword 0x48494a4b4c4d4e4f
279 .xword 0x5051525354555657
280 .xword 0x58595a5b5c5d5e5f
281 .xword 0x6061626364656667
282 .xword 0x68696a6b6c6d6e6f
283 .xword 0x7071727374757677
284 .xword 0x78797a7b7c7d7e7f
285
286 .xword 0x8081828384858687
287 .xword 0x88898a8b8c8d8e8f
288 .xword 0x9091929394959697
289 .xword 0x98999a9b9c9d9e9f
290 .xword 0xa0a1a2a3a4a5a6a7
291 .xword 0xa8a9aaabacadaeaf
292 .xword 0xb0b1b2b3b4b5b6b7
293 .xword 0xb8b9babbbcbdbebf
294
295 .xword 0xc0c1c2c3c4c5c6c7
296 .xword 0xc8c9cacbcccdcecf
297 .xword 0xd0d1d2d3d4d5d6d7
298 .xword 0xd8d9dadbdcdddedf
299 .xword 0xe0e1e2e3e4e5e6e7
300 .xword 0xe8e9eaebecedeeef
301 .xword 0xf0f1f2f3f4f5f6f7
302 .xword 0xf8f9fafbfcfdfeff
303
304 .xword 0x0001020304050607
305 .xword 0x08090a0b0c0d0e0f
306 .xword 0x1011121314151617
307 .xword 0x18191a1b1c1d1e1f
308 .xword 0x2021222324252627
309 .xword 0x28292a2b2c2d2e2f
310 .xword 0x3031323334353637
311 .xword 0x38393a3b3c3d3e3f
312
313 .xword 0x4041424344454647
314 .xword 0x48494a4b4c4d4e4f
315 .xword 0x5051525354555657
316 .xword 0x58595a5b5c5d5e5f
317 .xword 0x6061626364656667
318 .xword 0x68696a6b6c6d6e6f
319 .xword 0x7071727374757677
320 .xword 0x78797a7b7c7d7e7f
321
322 .xword 0x8081828384858687
323 .xword 0x88898a8b8c8d8e8f
324 .xword 0x9091929394959697
325 .xword 0x98999a9b9c9d9e9f
326 .xword 0xa0a1a2a3a4a5a6a7
327 .xword 0xa8a9aaabacadaeaf
328 .xword 0xb0b1b2b3b4b5b6b7
329 .xword 0xb8b9babbbcbdbebf
330
331 .xword 0xc0c1c2c3c4c5c6c7
332 .xword 0xc8c9cacbcccdcecf
333 .xword 0xd0d1d2d3d4d5d6d7
334 .xword 0xd8d9dadbdcdddedf
335 .xword 0xe0e1e2e3e4e5e6e7
336 .xword 0xe8e9eaebecedeeef
337 .xword 0xf0f1f2f3f4f5f6f7
338 .xword 0xf8f9fafbfcfdfeff
339
340/************************************************************************/
341
Full OpenSPARC design & verification tarball including full HDL.