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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_adv_NcuDmuUe_st.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
39 | ||
40 | #define ENABLE_PCIE_LINK_TRAINING | |
41 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
42 | #define MAIN_PAGE_HV_ALSO | |
43 | ||
44 | #include "err_defines.h" | |
45 | #include "hboot.s" | |
46 | #include "peu_defines.h" | |
47 | ||
48 | !#define IO_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) | |
49 | #define IO_WR_ADDR mpeval((N2_PCIE_BASE_ADDR + IOCFG_OFFSET_BASE_REG_DATA) | IO_ACCESS_PA) | |
50 | ||
51 | /************************************************************************ | |
52 | Test case code start | |
53 | ************************************************************************/ | |
54 | .text | |
55 | .global main | |
56 | .global My_Recoverable_Sw_error_trap | |
57 | ||
58 | main: | |
59 | ta T_CHANGE_HPRIV | |
60 | nop | |
61 | ||
62 | clear_esr_first: | |
63 | setx SOC_ESR_REG, %l7, %i0 | |
64 | stx %g0, [%i0] | |
65 | ||
66 | st_peu_first: | |
67 | setx IO_WR_ADDR, %g1, %g2 | |
68 | setx 0x55555555, %g1, %l0 | |
69 | stw %l0, [%g2] | |
70 | ||
71 | set_ejr: | |
72 | set 0x1, %i1 | |
73 | sllx %i1, ERR_FIELD, %i2 | |
74 | setx SOC_EJR_REG, %l7, %i3 | |
75 | stx %i2, [%i3] | |
76 | membar 0x40 | |
77 | ||
78 | ! This store does not complete; Informing Bench Code not to expect this store. | |
79 | Bench_noExp: nop; | |
80 | ! $EV trig_pc_d(1, @VA(.MAIN.Bench_noExp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1) | |
81 | ||
82 | PIO2: nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;nop; nop; nop; nop; nop; nop; | |
83 | ||
84 | st_peu_err: | |
85 | ! select a CFG address in PCI address range and transmit the command to NCU | |
86 | setx IO_WR_ADDR, %g1, %g2 | |
87 | setx 0x77777777, %g1, %l0 | |
88 | stw %l0, [%g2] | |
89 | ||
90 | setx 0x40, %l1, %g4 | |
91 | delay_loop: | |
92 | nop | |
93 | nop | |
94 | nop | |
95 | nop | |
96 | dec %g4 | |
97 | brnz %g4, delay_loop | |
98 | nop | |
99 | nop | |
100 | ||
101 | check_esr: | |
102 | setx SOC_ESR_REG, %l7, %i0 | |
103 | ldx [%i0], %i1 | |
104 | nop | |
105 | ||
106 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
107 | set 0x1, %i2 | |
108 | sllx %i2, ERR_FIELD, %i3 | |
109 | or %i3, %o3, %i4 | |
110 | sub %i1, %i4, %i5 | |
111 | brnz %i5, test_failed | |
112 | nop | |
113 | ||
114 | eie_reg_ones: | |
115 | setx SOC_EIE_REG, %g3, %g2 | |
116 | ||
117 | set 0x1, %i1 | |
118 | sllx %i1, ERR_FIELD, %g1 | |
119 | ||
120 | stx %g1, [%g2] | |
121 | membar 0x40 | |
122 | ||
123 | setx 0x40, %g7, %g6 | |
124 | set 0x1, %g1 ! 1 Trap | |
125 | err_trap_loop: | |
126 | cmp %g6, %g0 | |
127 | be %xcc, test_failed | |
128 | nop | |
129 | ||
130 | cmp %g1, %i7 | |
131 | be %xcc, check_tt | |
132 | nop | |
133 | ||
134 | ba err_trap_loop | |
135 | nop | |
136 | ||
137 | check_tt: | |
138 | mov 0x40, %l0 | |
139 | cmp %o7, %l0 | |
140 | bne %xcc, test_failed | |
141 | nop | |
142 | ||
143 | read_err_addr: | |
144 | ! 2nd st which is with error, should not have committed; so ld should get the old value | |
145 | setx IO_WR_ADDR, %g1, %g2 | |
146 | ld [%g2], %g1 | |
147 | set 0x55555555, %g2 | |
148 | cmp %g1, %g2 | |
149 | bne %xcc, test_failed | |
150 | nop | |
151 | nop | |
152 | ||
153 | ||
154 | test_passed: | |
155 | EXIT_GOOD | |
156 | ||
157 | test_failed: | |
158 | EXIT_BAD | |
159 | ||
160 | /************************************************************************ | |
161 | RAS | |
162 | Trap Handlers | |
163 | ************************************************************************/ | |
164 | My_Recoverable_Sw_error_trap: | |
165 | ! Signal trap taken | |
166 | setx EXECUTED, %l0, %o6 | |
167 | ! save trap type value | |
168 | rdpr %tt, %o7 | |
169 | ||
170 | inc %i7 | |
171 | ||
172 | check_desr_NcuTrap_tt40: | |
173 | ldxa [%g0]0x4c, %g2 | |
174 | nop | |
175 | ||
176 | setx 0xb300000000000000, %l0, %g3 | |
177 | subcc %g2, %g3, %g4 | |
178 | brnz %g4, test_failed | |
179 | nop | |
180 | ||
181 | ||
182 | check_per_tt40: | |
183 | setx SOC_PER_REG, %l7, %g1 | |
184 | ldx [%g1], %g2 | |
185 | setx 0x8000000000000000, %g7, %g1 | |
186 | set 0x1, %g3 | |
187 | sllx %g3, ERR_FIELD, %g4 | |
188 | or %g1, %g4, %g3 | |
189 | sub %g2, %g3, %g5 | |
190 | brnz %g5, test_failed | |
191 | nop | |
192 | ||
193 | clear_per_tt40: | |
194 | setx SOC_PER_REG, %l7, %g1 | |
195 | stx %g0, [%g1] | |
196 | nop | |
197 | ||
198 | clear_ejr_tt40: | |
199 | setx SOC_EJR_REG, %l7, %g1 | |
200 | stx %g0, [%g1] | |
201 | nop | |
202 | ||
203 | clear_eie_tt40: | |
204 | setx SOC_EIE_REG, %l7, %g1 | |
205 | stx %g0, [%g1] | |
206 | nop | |
207 | ||
208 | trap_done_tt40: | |
209 | retry | |
210 | nop | |
211 | ||
212 | /************************************************************************ | |
213 | Test case data start | |
214 | ************************************************************************/ | |
215 | ||
216 | SECTION .DATA DATA_VA=IO_WR_ADDR | |
217 | attr_data { | |
218 | Name = .DATA, | |
219 | hypervisor, | |
220 | compressimage | |
221 | } | |
222 | ||
223 | .data | |
224 | .global PCIAddr9 | |
225 | ||
226 | data0: .word 0xccccdddd | |
227 | data1: .word 0xeeeeffff | |
228 | /************************************************************************/ |