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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_tx_memerr.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_tx_memerr.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45
46#define DRAM_ERR_STAT_REG 0x8400000280
47#define L2_ERR_STAT_REG 0xAB00000000
48#define DRAM_ERR_INJ_REG 0x8400000290
49
50#include "err_defines.h"
51#include "hboot.s"
52#include "niu_defines.h"
53
54
55/************************************************************************
56 Test case code start
57 ************************************************************************/
58.text
59.global main
60.global My_Corrected_ECC_error_trap
61.global My_Recoverable_Sw_error_trap
62
63main:
64 ta T_CHANGE_HPRIV
65 nop
66
67! #include "niu_init.h"
68!
69! Thread 0 Start
70!
71!
72! thread_0:
73
74Init_flow:
75 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
76
77P_TxDMAActivate:
78 setx MAC_ID, %g1, %o0 ! 1st Parameter
79 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
80 call SetTxDMAActive
81 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
82
83P_AddTxChannels :
84 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
85
86 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
87 nop
88
89P_SetTxMaxBurst :
90 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
91 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
92 call SetTxMaxBurst
93 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
94
95 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
96 nop
97
98P_InitTxDma:
99 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
100 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
101 call InitTxDma
102 nop
103
104 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
105 nop
106
107
108
109Gen_Packet:
110 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT, 0, 0)
111 nop
112
113 setx 0x5, %g1, %g4
114delay_loop_tmp:
115 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
116 nop
117 nop
118 nop
119 nop
120 dec %g4
121 brnz %g4, delay_loop_tmp
122 nop
123
124
125 /************************************
126 RAS
127 *************************************/
128clear_esr_first:
129 setx SOC_ESR_REG, %l7, %i0
130 stx %g0, [%i0]
131
132disable_l1:
133 ldxa [%g0] ASI_LSU_CONTROL, %l0
134 ! Remove the lower 2 bits (I-Cache and D-Cache enables)
135 andn %l0, 0x3, %l0
136 stxa %l0, [%g0] ASI_LSU_CONTROL
137
138set_DRAM_error_inject_ch0:
139 mov 0x606, %l1 ! ECC Mask (2-bit error)
140 mov 0x1, %l2
141 sllx %l2, DRAM_EI_SSHOT, %l3
142 Or %l1, %l3, %l1 ! Set single shot ;
143 mov 0x1, %l2
144 sllx %l2, DRAM_EI_ENB, %l3
145 or %l1, %l3, %l1 ! Enable error injection for the next write
146 setx DRAM_ERR_INJ_REG, %l3, %g6
147 stx %l1, [%g6]
148 membar 0x40
149
150
151set_L2_Directly_Mapped_Mode:
152 setx L2CS_PA0, %l6, %g1
153 mov 0x2, %l0
154 stx %l0, [%g1]
155
156store_to_L2_way0:
157 setx 0xaaaaaaaaaaaaaaaa, %l0, %g5
158 setx 0x3456000, %l0, %g2 ! bits [21:18] select way
159 stx %g5, [%g2]
160 membar #Sync
161
162
163 ! Storing to same L2 way but different tag,this will write to mcu
164write_mcu_channel_0:
165 setx 0x1456000, %l0, %g3 ! bits [21:18] select way
166 stx %g5, [%g3]
167 membar #Sync
168
169
170L2_err_enable:
171 set 0x3, %l1
172 mov 0xaa, %g2
173 sllx %g2, 32, %g2
174 stx %l1, [%g2]
175 stx %l1, [%g2 + 0x40]
176 stx %l1, [%g2 + 0x80]
177 stx %l1, [%g2 + 0xc0]
178 stx %l1, [%g2 + 0x100]
179 stx %l1, [%g2 + 0x140]
180 stx %l1, [%g2 + 0x180]
181 stx %l1, [%g2 + 0x1c0]
182
183eie_reg_ones_rdd:
184 setx SOC_EIE_REG, %g3, %g2
185 setx 0xffffffffffffffff, %g3, %g1
186 stx %g1, [%g2]
187 membar 0x40
188
189 /*************************************/
190
191SetTxRingKick:
192 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
193 setx NIU_TxDmaNo, %g1, %o0
194 ldx [%g2], %g3
195 nop
196 mulx %o0, 0x200, %g5
197 setx TX_RING_KICK_Addr, %g1, %g2
198 add %g2, %g5, %g2
199 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
200 nop
201
202SetTxCs :
203 setx NIU_TxDmaNo, %g1, %o0
204 setx TX_CS_Data, %g1, %g3
205 mulx %o0, 0x200, %g5
206 setx TX_CS_Addr, %g1, %g2
207 add %g2, %g5, %g2
208 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
209 nop
210
211
212#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
213 setx loop_count, %g1, %g4
214delay_loop:
215 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
216 nop
217 nop
218 nop
219 nop
220 dec %g4
221 brnz %g4, delay_loop
222 nop
223#endif
224
225/*
226
227NIUTx_Pkt_Cnt_Chk:
228 setx MAC_ID, %g1, %o0
229 setx 0x9, %g1, %o1 ! one less
230 call NiuTx_check_pkt_cnt
231 nop
232*/
233
234 setx loop_count, %g1, %g4
235delay_loop_end:
236 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
237 nop
238 nop
239 nop
240 nop
241 dec %g4
242 brnz %g4, delay_loop_end
243 nop
244
245 /************************************
246 RAS
247 *************************************/
248
249read_mcu_l2_esr:
250 setx DRAM_ERR_STAT_REG, %g7, %g6
251 ldx [%g6], %g3
252
253 setx L2_ERR_STAT_REG, %g7, %g1
254 ldx [%g1], %g6
255
256cause_trap:
257 setx 0x2000ab00, %g3, %g1
258 stx %g0, [%g1]
259 setx 0x800bb00, %g3, %g1
260 ldx [%g1], %g2
261
262 setx 0x8300bb00, %g3, %g1
263 setx 0x2222222222222222, %g3, %g2
264 stx %g2, [%g1]
265 setx 0x6300bb00, %g3, %g1
266 ldx [%g1], %g2
267
268 set 0x1, %g1
269 setx 0x50, %g7, %g6
270err_trap_loop:
271 cmp %g6, %g0
272 be %xcc, test_failed
273 nop
274
275 cmp %g1, %i7
276 be %xcc, test_passed
277 nop
278
279 ba err_trap_loop
280 nop
281
282 /*************************************/
283test_passed:
284
285#ifdef CE
286 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
287#endif
288
289
290 EXIT_GOOD
291
292!.global test_failed
293!test_failed:
294! EXIT_BAD
295
296test_failed:
297 EXIT_BAD
298 nop
299/************************************************************************
300 RAS
301 Trap Handlers
302 ************************************************************************/
303My_Recoverable_Sw_error_trap:
304 inc %i7
305
306check_desr_NcuTrap_tt40:
307 ldxa [%g0]0x4c, %g2
308 nop
309
310 setx 0xb300000000000000, %l0, %g3
311 subcc %g2, %g3, %g4
312 brnz %g4, l2_trap
313 nop
314
315check_ncutrap_tt40:
316 ba esr_check
317 nop
318
319
320l2_trap:
321 nop
322
323check_desr_L2Trap_tt40:
324 setx 0xb000000000000000, %l0, %g3
325 subcc %g2, %g3, %g4
326 brnz %g4, both_l2_soc
327 nop
328
329both_l2_soc:
330 setx 0xf300000000000000, %l0, %g3
331 subcc %g2, %g3, %g4
332 brnz %g4, test_failed
333 nop
334
335check_mcu0_esr_L2Trap_tt40:
336 mov 0x1, %g1
337 sllx %g1, DRAM_ES_DAU, %g2
338
339 setx DRAM_ERR_STAT_REG, %g7, %g6
340 ldx [%g6], %g3
341
342 setx 0xffffffffffff0000, %g7, %g1
343 andcc %g1, %g3, %g4 ! Donot check SYND bits
344
345 sub %g2, %g4, %g1
346 brnz %g1, test_failed
347 nop
348
349clear_mcu_esr_L2Trap_tt40:
350 stx %g0, [%g6]
351
352
353check_L2_4_ESR_L2Trap_tt40:
354 setx L2_ERR_STAT_REG, %g7, %g1
355 ldx [%g1], %g6
356
357 setx 0xfffffffff0000000, %g7, %g1
358 andcc %g6, %g1, %g2 ! Donot check L2ESR SYND bits
359
360 mov 0x1, %g1
361 sllx %g1, L2ES_DRU, %g3
362
363 mov 0x1, %g1
364 sllx %g1, L2ES_VEU, %g4
365
366 or %g3, %g4, %g5
367
368 mov 0x1, %g1
369 sllx %g1, L2ES_MEU, %g3
370
371 or %g5, %g3, %g4
372
373 cmp %g2, %g4
374 bne %xcc, test_failed
375 nop
376
377 /* With SIU design change, now SIO will flag parity error to NIU*/
378esr_check:
379 setx SOC_PER_REG, %g7, %g5
380 ldx [%g5], %g4
381
382 mov 0x1, %g1
383 sllx %g1, NiuDataParity, %g2
384 setx 0x8000000000000000, %g7, %g1
385 or %g1, %g2, %g3
386
387 cmp %g3, %g4
388 bne %xcc, test_failed
389 nop
390
391
392clear_l2_esr_L2Trap_tt40:
393 setx L2_ERR_STAT_REG, %g7, %g1
394 stx %g0, [%g1]
395
396trap_done_tt40:
397 done
398 nop
399
400
401
402My_Corrected_ECC_error_trap:
403 ba test_failed
404 nop
405
406/************************************************************************
407 Test case data start
408 ************************************************************************/
409/* These initialization is temporary, as there looks some bug in mempli */
410
411SECTION SetRngConfig_init data_va=0x100000000
412attr_data {
413 Name = SetRngConfig_init,
414 hypervisor,
415 compressimage
416 }
417.data
418SetRngConfig_init:
419 .xword 0x0060452301000484
420/************************************************************************/
421
422SECTION SetTxRingKick_init data_va=0x100000100
423attr_data {
424 Name = SetTxRingKick_init,
425 hypervisor,
426 compressimage
427 }
428.data
429SetTxRingKick_init:
430 .xword 0x0060452301000484
431/************************************************************************/
432
433SECTION SetTxLPMask1_init data_va=0x100000200
434attr_data {
435 Name = SetTxLPMask1_init,
436 hypervisor,
437 compressimage
438 }
439.data
440SetTxLPMask1_init:
441 .xword 0x0060452301000484
442/************************************************************************/
443
444SECTION SetTxLPValue1_init data_va=0x100000300
445attr_data {
446 Name = SetTxLPValue1_init,
447 hypervisor,
448 compressimage
449 }
450.data
451SetTxLPValue1_init:
452 .xword 0x0060452301000484
453/************************************************************************/
454
455SECTION SetTxLPRELOC1_init data_va=0x100000400
456attr_data {
457 Name = SetTxLPRELOC1_init,
458 hypervisor,
459 compressimage
460 }
461.data
462SetTxLPRELOC1_init:
463 .xword 0x0060452301000484
464/************************************************************************/
465SECTION SetTxLPMask2_init data_va=0x100000500
466attr_data {
467 Name = SetTxLPMask2_init,
468 hypervisor,
469 compressimage
470 }
471.data
472SetTxLPMask2_init:
473 .xword 0x0060452301000484
474/************************************************************************/
475SECTION SetTxLPValue2_init data_va=0x100000600
476attr_data {
477 Name = SetTxLPValue2_init,
478 hypervisor,
479 compressimage
480 }
481.data
482SetTxLPValue2_init:
483 .xword 0x0060452301000484
484
485/************************************************************************/
486SECTION SetTxLPRELOC2_init data_va=0x100000700
487attr_data {
488 Name = SetTxLPRELOC2_init,
489 hypervisor,
490 compressimage
491 }
492.data
493SetTxLPRELOC2_init:
494 .xword 0x0060452301000484
495
496/************************************************************************/
497SECTION SetTxLPValid_init data_va=0x100000800
498attr_data {
499 Name = SetTxLPValid_init,
500 hypervisor,
501 compressimage
502 }
503.data
504SetTxLPValid_init:
505 .xword 0x0060452301000484
506
507/************************************************************************/
508
Full OpenSPARC design & verification tarball including full HDL.