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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_LDWC_errstr_thid1.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | #define MAIN_PAGE_NUCLEUS_ALSO | |
41 | ||
42 | #define MAIN_PAGE_HV_ALSO | |
43 | ||
44 | #define L2_ENTRY_PA 0x517590000 | |
45 | #define TEST_DATA 0x555555555555555 | |
46 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
47 | ||
48 | ||
49 | #include "hboot.s" | |
50 | #include "asi_s.h" | |
51 | #include "err_defines.h" | |
52 | ||
53 | .text | |
54 | .global main | |
55 | .global My_Corrected_ECC_error_trap | |
56 | ||
57 | ||
58 | main: | |
59 | ||
60 | ||
61 | ! Boot code does not provide TLB translation for IO address space | |
62 | ta T_CHANGE_HPRIV | |
63 | ||
64 | ||
65 | get_th_id_o0: | |
66 | ta T_RD_THID | |
67 | ||
68 | cmp %o1, 0x0 | |
69 | be main_t0 | |
70 | nop | |
71 | ||
72 | cmp %o1, 0x1 | |
73 | be main_t1 | |
74 | nop | |
75 | ||
76 | main_t0: | |
77 | ba L20_Init | |
78 | nop | |
79 | ||
80 | ||
81 | main_t1: | |
82 | nop | |
83 | nop | |
84 | nop | |
85 | ba L21_Init | |
86 | nop | |
87 | ||
88 | ||
89 | /******************* | |
90 | DIMM 0,1 | |
91 | *******************/ | |
92 | chk_core_running_status_reg: | |
93 | wr %g0, ASI_CMP_CORE, %asi | |
94 | ldxa [ASI_CMP_CORE_RUNNING_STATUS]%asi, %l0 | |
95 | ||
96 | L20_Init: | |
97 | ||
98 | setx L2_ES_W1C_VALUE, %l0, %g4 | |
99 | setx 0x2020040000, %l0, %g3 | |
100 | ||
101 | ! Now access L2 control and status registers | |
102 | disable_l1: | |
103 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
104 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
105 | andn %l0, 0x3, %l0 | |
106 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
107 | ||
108 | ||
109 | enable_err_reporting: | |
110 | setx L2EE_PA0, %l0, %l1 | |
111 | ldx [%l1], %l2 | |
112 | mov 0x1, %l0 | |
113 | or %l2, %l0, %l2 | |
114 | stx %l2, [%l1] | |
115 | ||
116 | ||
117 | ! Write 1 to clear L2 Error status registers | |
118 | ||
119 | clear_l2_ESR: | |
120 | setx L2ES_PA0, %l3, %l4 | |
121 | stx %g4, [%l4] | |
122 | nop | |
123 | ||
124 | check_th1_out_of_boot_code: | |
125 | ldx [%g3],%l2 | |
126 | set 0x11,%l1 | |
127 | membar #Sync | |
128 | cmp %l1,%l2 | |
129 | bne check_th1_out_of_boot_code | |
130 | nop | |
131 | ||
132 | ||
133 | set_L2_Directly_Mapped_Mode: | |
134 | setx L2CS_PA0, %l6, %g1 | |
135 | set 0x8002, %l0 | |
136 | stx %l0, [%g1] | |
137 | ||
138 | ||
139 | store_to_L2_way0: | |
140 | setx TEST_DATA, %l0, %g5 | |
141 | setx 0x202000aa00, %l0, %g1 | |
142 | stx %g5, [%g1] | |
143 | stx %g5, [%g1+8] | |
144 | membar #Sync | |
145 | ||
146 | ||
147 | way_found: | |
148 | ! Addressing: [39:32] See PRM, [22] odd/even word, [21:18] way, [17:8] set, [7:6] bank, [5:3] D-word, [2:0] = 0 | |
149 | setx 0x3fff8, %l0, %l2 ! Mask for extracting [17:3] | |
150 | and %g1, %l2, %g5 | |
151 | mov 0xa3, %l0 | |
152 | sllx %l0, 32, %l0 ! Bits [39:32] | |
153 | or %g5, %l0, %g5 ! %g5 has L2 Data Diag addressing | |
154 | ||
155 | ||
156 | read_l2_data_diag: | |
157 | ldx [%g5], %g6 | |
158 | ||
159 | ! Flip one bit from the data field | |
160 | xor %g6, 0x80, %g6 ! save on %g6 for future reference | |
161 | write_back_with_error: | |
162 | stx %g6, [%g5] | |
163 | ||
164 | ||
165 | ! Now do another store with the same index but different tag - to force a Write-Back | |
166 | error_address: | |
167 | mov 0x1, %l0 | |
168 | sllx %l0, 28, %l0 | |
169 | xor %g1, %l0, %l1 ! Flip bit 28 of previous L2 entry PA | |
170 | ||
171 | ! This should cause L2 LDWC (bit 51) | |
172 | store_to_L2_with_error: | |
173 | st %g5, [%l1] | |
174 | membar #Sync | |
175 | ||
176 | indicate_th1_cpx_sent: | |
177 | set 0x22,%l1 | |
178 | stx %l1,[%g3] | |
179 | membar #Sync | |
180 | ||
181 | ||
182 | enable_l1: | |
183 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
184 | or %l0, 0x3, %l0 | |
185 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
186 | ||
187 | ||
188 | ! Compute expected value of L2 error status register | |
189 | compute_expected_L2_ESR: | |
190 | mov 0x1, %l1 | |
191 | sllx %l1, L2ES_LDWC, %l0 | |
192 | sllx %l1, L2ES_VEC, %l3 ! VEC bit | |
193 | or %l0, %l3, %l0 | |
194 | ! No RW bit or Syndrome field for LDWC - %l0 has expected value | |
195 | ||
196 | setx L2ES_PA0, %l2, %l3 | |
197 | ||
198 | ||
199 | check_l2_ESR: | |
200 | ldx [%l3], %l4 | |
201 | ||
202 | cmp %l4, %l0 | |
203 | bne test_fail | |
204 | nop | |
205 | ||
206 | setx L2EA_PA0, %l2, %l3 | |
207 | check_l2_EAR: | |
208 | ldx [%l3], %l4 | |
209 | ||
210 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
211 | andn %g1, 0x3f, %l1 | |
212 | cmp %l4, %l1 | |
213 | bne test_fail | |
214 | nop | |
215 | ||
216 | ||
217 | ba test_pass | |
218 | nop | |
219 | ||
220 | ||
221 | L21_Init: | |
222 | ||
223 | indicate_out_of_boot: | |
224 | setx 0x2020040000, %l0, %g3 | |
225 | set 0x11,%l2 | |
226 | stx %l2,[%g3] | |
227 | ||
228 | check_cpx_packet_sent: | |
229 | ldx [%g3],%l2 | |
230 | set 0x22,%l3 | |
231 | cmp %l2,%l3 | |
232 | bne check_cpx_packet_sent | |
233 | nop | |
234 | ||
235 | ||
236 | ! Check if a Corrected ECC Trap happened | |
237 | check_error_trap: | |
238 | setx EXECUTED, %l1, %l0 | |
239 | cmp %o0, %l0 | |
240 | bne check_error_trap | |
241 | nop | |
242 | ||
243 | check_error_trap1: | |
244 | mov TT_Corrected_ECC, %l0 | |
245 | cmp %o1, %l0 | |
246 | bne test_fail | |
247 | nop | |
248 | ||
249 | ||
250 | ba test_pass | |
251 | nop | |
252 | ||
253 | My_Corrected_ECC_error_trap: | |
254 | ! Signal trap taken | |
255 | setx EXECUTED, %l0, %o0 | |
256 | ! save trap type value | |
257 | rdpr %tt, %o1 | |
258 | retry | |
259 | nop | |
260 | /******************************************************* | |
261 | * Exit code | |
262 | *******************************************************/ | |
263 | ||
264 | test_pass: | |
265 | ta T_GOOD_TRAP | |
266 | ||
267 | test_fail: | |
268 | ta T_BAD_TRAP | |
269 |