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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_DAU_st_trap_L2_Off.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define L2_ERR_STAT_REG 0xAB00000000 | |
42 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
43 | #define TT_SW_Error 0x40 | |
44 | ||
45 | #define TEST_DATA0 0x1000100081c3e008 | |
46 | #define TEST_DATA1 0x2000200081c3e008 | |
47 | #define TEST_DATA2 0x3000300081c3e008 | |
48 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
49 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
50 | ||
51 | #ifdef MCU0 | |
52 | #define L2_BANK_ADDR 0x0 | |
53 | #define MCU_BANK_ADDR 0x0 | |
54 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
55 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
56 | #define ERROR_ADDR 0x20200000 | |
57 | #endif | |
58 | ||
59 | #ifdef MCU1 | |
60 | #define L2_BANK_ADDR 0x80 | |
61 | #define MCU_BANK_ADDR 0x80 | |
62 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
63 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
64 | ||
65 | ||
66 | #endif | |
67 | ||
68 | #ifdef MCU2 | |
69 | #define L2_BANK_ADDR 0x100 | |
70 | #define MCU_BANK_ADDR 0x100 | |
71 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
72 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
73 | #define ERROR_ADDR 0x20200100 | |
74 | ||
75 | #endif | |
76 | ||
77 | #ifdef MCU3 | |
78 | #define L2_BANK_ADDR 0x180 | |
79 | #define MCU_BANK_ADDR 0x180 | |
80 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
81 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
82 | ||
83 | ||
84 | #endif | |
85 | ||
86 | ||
87 | #include "hboot.s" | |
88 | #include "asi_s.h" | |
89 | #include "err_defines.h" | |
90 | ||
91 | ||
92 | .text | |
93 | .global main | |
94 | .global My_Corrected_ECC_error_trap | |
95 | ||
96 | ||
97 | ||
98 | main: | |
99 | ta T_CHANGE_HPRIV | |
100 | disable_l1: | |
101 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
102 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
103 | andn %l0, 0x3, %l0 | |
104 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
105 | ||
106 | ||
107 | clear_dram_esr_0: | |
108 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
109 | setx DRAM_ES_W1C_VALUE, %l0, %l5 | |
110 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
111 | ! add %g5, MCU_BANK_ADDR, %g5 | |
112 | stx %l5, [%g5] | |
113 | ||
114 | set_DRAM_error_inject_ch0: | |
115 | mov 0x606, %l1 ! ECC Mask (Multi-bit error) | |
116 | mov 0x1, %l2 | |
117 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
118 | Or %l1, %l3, %l1 ! Set single shot ; | |
119 | mov 0x1, %l2 | |
120 | sllx %l2, DRAM_EI_ENB, %l3 | |
121 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
122 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
123 | ! add %g6, MCU_BANK_ADDR, %g6 | |
124 | stx %l1, [%g6] | |
125 | membar 0x40 | |
126 | ||
127 | enable_err_reporting: | |
128 | setx L2EE_PA0, %l0, %l1 | |
129 | add %l1, L2_BANK_ADDR, %l1 | |
130 | ldx [%l1], %l2 | |
131 | mov 0x3, %l0 | |
132 | or %l2, %l0, %l2 | |
133 | stx %l2, [%l1] | |
134 | ||
135 | ||
136 | ! Write 1 to clear L2 Error status registers | |
137 | clear_l2_ESR: | |
138 | setx L2ES_PA0, %l3, %l4 | |
139 | add %l4, L2_BANK_ADDR, %l4 | |
140 | stx %l5, [%l4] | |
141 | nop | |
142 | ||
143 | store_to_L2: | |
144 | setx TEST_DATA1, %l0, %g5 | |
145 | ||
146 | ||
147 | set_L2_Off_Mode: | |
148 | setx L2CS_PA0, %l6, %g1 | |
149 | add %g1, L2_BANK_ADDR, %g1 | |
150 | mov 0x1, %l0 | |
151 | stx %l0, [%g1] | |
152 | ||
153 | ||
154 | store_to_L2_way0: | |
155 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
156 | add %g2, L2_BANK_ADDR, %g2 | |
157 | stx %g5, [%g2] | |
158 | !stx %g5, [%g2+8] | |
159 | membar #Sync | |
160 | ||
161 | ||
162 | read_error_address_ch0: | |
163 | stb %g5, [%g2] | |
164 | membar #Sync | |
165 | ||
166 | mov 0x3f,%g1 | |
167 | clr %g3 | |
168 | loop: | |
169 | inc %g3 | |
170 | cmp %g3,%g1 | |
171 | bne loop | |
172 | nop | |
173 | ||
174 | check_DRAM_ESR_0: | |
175 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
176 | ! add %g5, MCU_BANK_ADDR, %g5 | |
177 | ldx [%g5], %l6 | |
178 | setx 0xffc0000000000000, %l0,%o2 | |
179 | and %l6,%o2,%l6 | |
180 | ||
181 | ||
182 | compute_dram_ESR: | |
183 | mov 0x1, %l1 | |
184 | sllx %l1, DRAM_ES_DAU, %l0 | |
185 | !set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed | |
186 | !or %l0, %l3, %l0 ! %l0 has expected value | |
187 | ||
188 | verify_dram_ESR: | |
189 | cmp %l0, %l6 | |
190 | bne %xcc, test_fail | |
191 | nop | |
192 | ||
193 | check_L2_ESR_0: | |
194 | setx L2_ERR_STAT_REG, %l3, %g5 | |
195 | add %g5, L2_BANK_ADDR, %g5 | |
196 | ldx [%g5], %l6 | |
197 | ||
198 | compute_L2_ESR: | |
199 | setx 0xfffffffff0000000, %l3, %l0 | |
200 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits | |
201 | mov 0x1, %l1 | |
202 | sllx %l1, L2ES_DAU, %l0 | |
203 | mov 0x1, %l1 | |
204 | sllx %l1, L2ES_VEU, %l2 | |
205 | or %l0, %l2, %l4 | |
206 | sllx %l1, L2ES_RW, %l0 | |
207 | or %l0, %l4, %l3 | |
208 | ||
209 | ||
210 | ||
211 | verify_L2_ESR: | |
212 | cmp %l6, %l3 | |
213 | bne %xcc, test_fail | |
214 | nop | |
215 | ||
216 | ||
217 | setx L2EA_PA0, %l2, %l3 | |
218 | add %l3, L2_BANK_ADDR, %l3 | |
219 | check_l2_EAR: | |
220 | ldx [%l3], %l4 | |
221 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
222 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
223 | add %g2, L2_BANK_ADDR, %g2 | |
224 | ||
225 | setx 0xffffffffc0, %l0,%o2 | |
226 | and %l4, %o2, %l4 | |
227 | cmp %l4, %g2 | |
228 | bne %xcc, test_fail | |
229 | nop | |
230 | ||
231 | check_Corr_err_trap: | |
232 | ! Check if a Corrected ECC Error Trap happened | |
233 | set EXECUTED, %l0 | |
234 | cmp %o0, %l0 | |
235 | bne test_fail | |
236 | nop | |
237 | mov TT_SW_Error, %l0 | |
238 | cmp %o1, %l0 | |
239 | bne test_fail | |
240 | nop | |
241 | ||
242 | ||
243 | ba test_pass | |
244 | nop | |
245 | ||
246 | My_Corrected_ECC_error_trap: | |
247 | ||
248 | !My_Recoverable_Sw_error_trap: | |
249 | ! Signal trap taken | |
250 | setx EXECUTED, %l0, %o0 | |
251 | ! save trap type value | |
252 | rdpr %tt, %o1 | |
253 | retry | |
254 | nop | |
255 | ||
256 | ||
257 | /******************************************************* | |
258 | * Exit code | |
259 | *******************************************************/ | |
260 | ||
261 | test_pass: | |
262 | ta T_GOOD_TRAP | |
263 | ||
264 | ||
265 | test_fail: | |
266 | ta T_BAD_TRAP | |
267 | ||
268 | ||
269 |