Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_l2_LDAC_cecc.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_l2_LDAC_cecc.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
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29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40
41#define L2_ENTRY_PA 0xa000000000
42#define TEST_DATA1 0x5555555555555555
43#define L2_ENTRY_PA0 0x30000008
44#define L2_ES_W1C_VALUE 0xc03ffff800000000
45#define SPARC_ES_W1C_VALUE 0xefffffff
46#define TT_SW_Error 0x40
47
48#include "hboot.s"
49#include "asi_s.h"
50#include "err_defines.h"
51
52.text
53.global main
54
55main:
56
57
58 ! Boot code does not provide TLB translation for IO address space
59 ta T_CHANGE_HPRIV
60
61
62disable_l1_DCache:
63 ldxa [%g0] ASI_LSU_CONTROL, %l0
64 ! Remove bit 2
65 andn %l0, 0x2, %l0
66 stxa %l0, [%g0] ASI_LSU_CONTROL
67
68
69clear_l2_ESR:
70 setx L2_ES_W1C_VALUE, %l0, %l1
71 setx L2ES_PA0, %l6, %g1
72 stx %l1, [%g1]
73
74
75set_L2_Directly_Mapped_Mode:
76 setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
77 mov 0x2, %l0
78 stx %l0, [%g1]
79
80store_to_L2:
81 setx TEST_DATA1, %l0, %g5
82
83store_to_L2_way0:
84 setx 0x303000aa00, %l0, %g2 ! bits [21:18] select way
85 stx %g5, [%g2]
86 stx %g5, [%g2+8]
87 membar #Sync
88
89nops:
90 nop; nop; nop; nop; nop
91 nop; nop; nop; nop; nop
92 nop; nop; nop; nop; nop
93 nop; nop; nop; nop; nop
94 nop; nop; nop; nop; nop
95 nop; nop; nop; nop; nop
96 nop; nop; nop; nop; nop
97
98L2_diag_load:
99 setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
100 setx L2_ENTRY_PA, %l0, %g4
101 and %g2, %l2, %g5 !g2 has L2 PA,
102 or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
103 ldx [%g5], %g6
104 membar #Sync
105
106! Flip one bits to inject error
107 xor %g6, 0x200, %g6
108 stx %g6, [%g5]
109 membar #Sync
110
111reading_back_0: !Load to L2 again to get the error
112 setx 0x303000aa00, %l0, %g2
113 ldx [%g2], %l6
114 membar #Sync
115
116
117enable_l1_DCache:
118 ldxa [%g0] ASI_LSU_CONTROL, %l0
119 or %l0, 0x2, %l0
120 stxa %l0, [%g0] ASI_LSU_CONTROL
121
122
123compute_error:
124 mov 0x1, %l1
125 sllx %l1, L2ES_LDAC, %l7
126 sllx %l1, L2ES_VEC, %l3
127 or %l7, %l3, %l7
128 mov 0x46, %l1 ! 7-bit Syndrome
129 sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21]
130 or %l7, %l3, %l7
131 sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
132 or %l7, %l3, %l7 ! %l7 has expected value
133 membar #Sync
134
135
136check_l2_ESR:
137 setx L2ES_PA0, %l6, %g1
138 ldx [%g1], %l4
139 membar #Sync
140
141verify_ESR:
142 cmp %l7, %l4 ! l7 has expected value l4 has actula value
143 bne test_fail
144
145
146check_l2_EAR:
147 setx L2EA_PA0, %l6, %l3
148 ldx [%l3], %l4
149 membar #Sync
150
151 ba test_pass
152 nop
153
154
155
156/*******************************************************
157 * Exit code
158 *******************************************************/
159
160test_pass:
161ta T_GOOD_TRAP
162
163test_fail:
164ta T_BAD_TRAP