Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_l2_LTC_cecc.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_l2_LTC_cecc.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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*/
#define MAIN_PAGE_HV_ALSO


#define  L2_ENTRY_PA        0xa400000000
#define  TEST_DATA1         0x5555555555555555
#define	 L2_ENTRY_PA0       0x2020000008
#define L2_ES_W1C_VALUE     0xc03ffff800000000

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main

main:

  ! Boot code does not provide TLB translation for IO address space
  ta    T_CHANGE_HPRIV

disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

clear_l2_ESR:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]


set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2:
  setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
  setx	0x202000aa00, %l0, %g2  ! bits [21:18] select way
  stx %g5, [%g2] 
  stx %g5, [%g2+8]
  membar #Sync

clr %l6
set 0x9, %l5
loop:
   inc %l6
   cmp %l6,%l5
   bne loop
   nop



L2_diag_load:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx	L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA, 
  or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
  ldx	[%g5], %g6
  membar #Sync

! Flip one bits to inject error
  xor	 %g6, 0x200, %g6
  stx	%g6, [%g5]
  membar #Sync

reading_back_0:                 !Load to L2 again to get the error
  setx  0x202000aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync  

compute_error:
  mov   0x1, %l1
  sllx  %l1, L2ES_LTC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7


check_l2_ESR:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

  cmp   %l7,  %l4
  bne   %xcc, test_fail


check_l2_EAR:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync

  setx  0x202000aa00, %l0, %g2  ! bits [21:18] select way
  cmp   %g2, %l4
  bne   %xcc, test_fail
  nop

  setx  TEST_DATA1, %l0, %g5

store_to_L2_mec:
  setx  0x303000aa00, %l0, %g2  ! bits [21:18] select way
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

clr %l6
set 0x9, %l5
loop_mec:
   inc %l6
   cmp %l6,%l5
   bne loop_mec
   nop



L2_diag_load_mec:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx  L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA,
  or    %g5, %g4, %g5           !g5 now has Diagnostic Data Array address
  ldx   [%g5], %g6
  membar #Sync

! Flip one bits to inject error
  xor    %g6, 0x200, %g6
  stx   %g6, [%g5]
  membar #Sync

reading_back_For_mec:                 !Load to L2 again to get the error
  setx  0x303000aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync

enable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  or    %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

compute_error_mec:
  mov   0x1, %l1
  sllx  %l1, L2ES_LTC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  sllx  %l1, L2ES_MEC, %l3
  or    %l7, %l3, %l7


!Since L2 ESR is not cleared, the err will log MEC.
check_l2_ESR_mec:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

  cmp   %l7,  %l4
  bne   %xcc, test_fail

! Since the EAR is not cleared it should have old err addr.
check_l2_EAR_mec:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync
 
  setx	0x202000aa00, %l0, %g2  ! bits [21:18] select way
  cmp   %g2, %l4
  bne   %xcc, test_fail
  nop

  ba    %xcc, test_pass
  nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta T_GOOD_TRAP 

test_fail:
ta T_BAD_TRAP