[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_l2_trap_ErrInj.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_l2_trap_ErrInj.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO


#include "hboot.s"
#include "asi_s.h"

#define L2_ES_W1C_VALUE     0xc03ffff800000000
#define  TT_SW_Error        0x40
#define  TT_HW_Error        0x63
#define  TT_DA_Error        0x32

#define L2_ADDR 0x0020134000

#ifdef L2_0
#define		L2_ADDR		0x22000000
#define         L2_ADDR_2       0x44000000
#endif

#ifdef L2_1
L2_ADDR         22000040
#endif

#ifdef L2_2
L2_ADDR         22000080
#endif

#ifdef L2_3
L2_ADDR         220000c0
#endif

#ifdef L2_4
L2_ADDR         22000100
#endif

#ifdef L2_5
L2_ADDR         22000140
#endif

#ifdef L2_6
L2_ADDR         22000180
#endif

#ifdef L2_7
L2_ADDR         220001c0
#endif


#ifdef L2_OFF
#define L2_ON_OFF_DM	0x1
#else
#define L2_ON_OFF_DM    0x0
#endif
 
.text
.global	 main


main:
	ta	  T_CHANGE_HPRIV

disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  ldx  [%l1], %l2
  mov  0x3, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]

clear_l2_ESR:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]

L2_Init:
	set     0x55555555,%g2
	set	L2_ADDR, %g1
L2_ld:
	stx     %g2,  [%g1]
	stx     %g2,  [%g1+8]
	membar #Sync
        ldx     [%g1], %g5
        ldx     [%g1+8], %g5
	membar #Sync
L2_ld_1:
	add	%g1, 0x200, %g1
        stx     %g2,  [%g1]
        stx     %g2,  [%g1+8]
        membar #Sync
        ldx     [%g1], %g5
        ldx     [%g1+8], %g5
	membar #Sync

nop
nop
nop
nop

check_sw_err_trap:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
#ifdef LDAC
  mov   TT_SW_Error, %l0
#endif
#ifdef LDAU
  mov   TT_DA_Error, %l0
#endif
#ifdef LVC
  mov   TT_HW_Error, %l0
#endif

  cmp   %o1, %l0
  bne   test_fail
  nop

compute_error:
  mov   0x1, %l1
#ifdef LDAC
  sllx  %l1, L2ES_LDAC, %l7
#endif
#ifdef LDAU
  sllx  %l1, L2ES_LDAU, %l7
#endif
#ifdef LVC
  sllx  %l1, L2ES_LVC, %l7
#endif

  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
!  sllx  %l1, L2ES_MEC, %l3
!  or    %l7, %l3, %l7
  membar #Sync


check_l2_ESR:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync
  setx  0xfffffffc00000000,%l0,%l2
  and   %l2,%l4,%l4

verify_ESR:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actual value
  bne test_fail
  nop

ba test_pass
nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_l2_trap_ErrInj.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41
	42	#include "hboot.s"
	43	#include "asi_s.h"
	44
	45	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	46	#define TT_SW_Error 0x40
	47	#define TT_HW_Error 0x63
	48	#define TT_DA_Error 0x32
	49
	50	#define L2_ADDR 0x0020134000
	51
	52	#ifdef L2_0
	53	#define L2_ADDR 0x22000000
	54	#define L2_ADDR_2 0x44000000
	55	#endif
	56
	57	#ifdef L2_1
	58	L2_ADDR 22000040
	59	#endif
	60
	61	#ifdef L2_2
	62	L2_ADDR 22000080
	63	#endif
	64
65	#ifdef L2_3
66	L2_ADDR 220000c0
67	#endif
68
69	#ifdef L2_4
70	L2_ADDR 22000100
71	#endif
72
73	#ifdef L2_5
74	L2_ADDR 22000140
75	#endif
76
77	#ifdef L2_6
78	L2_ADDR 22000180
79	#endif
80
81	#ifdef L2_7
82	L2_ADDR 220001c0
83	#endif
84
85
86	#ifdef L2_OFF
87	#define L2_ON_OFF_DM 0x1
88	#else
89	#define L2_ON_OFF_DM 0x0
90	#endif
91
92	.text
93	.global main
94
95
96	main:
97	ta T_CHANGE_HPRIV
98
99	disable_l1_DCache:
100	ldxa [%g0] ASI_LSU_CONTROL, %l0
101	! Remove bit 2
102	andn %l0, 0x2, %l0
103	stxa %l0, [%g0] ASI_LSU_CONTROL
104
105	enable_err_reporting:
106	setx L2EE_PA0, %l0, %l1
107	ldx [%l1], %l2
108	mov 0x3, %l0
109	or %l2, %l0, %l2
110	stx %l2, [%l1]
111
112	clear_l2_ESR:
113	setx L2_ES_W1C_VALUE, %l0, %l1
114	setx L2ES_PA0, %l6, %g1
115	stx %l1, [%g1]
116
117	L2_Init:
118	set 0x55555555,%g2
119	set L2_ADDR, %g1
120	L2_ld:
121	stx %g2, [%g1]
122	stx %g2, [%g1+8]
123	membar #Sync
124	ldx [%g1], %g5
125	ldx [%g1+8], %g5
126	membar #Sync
127	L2_ld_1:
128	add %g1, 0x200, %g1
129	stx %g2, [%g1]
130	stx %g2, [%g1+8]
131	membar #Sync
132	ldx [%g1], %g5
133	ldx [%g1+8], %g5
134	membar #Sync
135
136	nop
137	nop
138	nop
139	nop
140
141	check_sw_err_trap:
142	! Check if a Software Recoverable Error Trap happened
143	set EXECUTED, %l0
144	cmp %o0, %l0
145	bne test_fail
146	nop
147	#ifdef LDAC
148	mov TT_SW_Error, %l0
149	#endif
150	#ifdef LDAU
151	mov TT_DA_Error, %l0
152	#endif
153	#ifdef LVC
154	mov TT_HW_Error, %l0
155	#endif
156
157	cmp %o1, %l0
158	bne test_fail
159	nop
160
161	compute_error:
162	mov 0x1, %l1
163	#ifdef LDAC
164	sllx %l1, L2ES_LDAC, %l7
165	#endif
166	#ifdef LDAU
167	sllx %l1, L2ES_LDAU, %l7
168	#endif
169	#ifdef LVC
170	sllx %l1, L2ES_LVC, %l7
171	#endif
172
173	sllx %l1, L2ES_VEC, %l3
174	or %l7, %l3, %l7
175	! sllx %l1, L2ES_MEC, %l3
176	! or %l7, %l3, %l7
177	membar #Sync
178
179
180	check_l2_ESR:
181	setx L2ES_PA0, %l6, %g1
182	ldx [%g1], %l4
183	membar #Sync
184	setx 0xfffffffc00000000,%l0,%l2
185	and %l2,%l4,%l4
186
187	verify_ESR:
188	cmp %l7, %l4 ! l7 has expected value l4 has actual value
189	bne test_fail
190	nop
191
192	ba test_pass
193	nop
194
195	/*******************************************************
196	* Exit code
197	*******************************************************/
198
199	test_pass:
200	ta T_GOOD_TRAP
201
202	test_fail:
203	ta T_BAD_TRAP
204