[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_McuFbr_McuEcc_LDWC.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_McuFbr_McuEcc_LDWC.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"


#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc00003000aa00
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800
#define  DRAM_ERR_INJ_REG_0               0x8400000290
#define  DRAM_ERR_INJ_REG_1               0x8400001290
#define  DRAM_ERR_INJ_REG_2               0x8400002290
#define  DRAM_ERR_INJ_REG_3               0x8400003290
#define  L2_ENTRY_PA        0xa000000000


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

set_Soc_Err_Inj_reg:
        set     0x1, %i1
	setx    0x800001248c80040c,%i1,%i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

set_L2_Directly_Mapped_Mode:
  set   0x80, %l1
  set   0x100,%l2
  set   0x180, %l3
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  add   %g1,%l1,%g2
  add   %g1,%l2,%g3
  add   %g1,%l3,%g4
  mov   0x2, %l0
  stx   %l0, [%g1]
  stx   %l0, [%g2]
  stx   %l0, [%g3]
  stx   %l0, [%g4]


store_to_L2_way0_ldac:
  set   0x5555555, %g5
  setx  0x3000aa00, %l0, %g2  ! bits [21:18] select way
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

mov 0x20,%i4
clr %i3
loop:
  inc %i3
  cmp %i3,%i4
  bne loop
  nop


L2_diag_load_ldac:
  set  0x3ffff8, %l2      ! Mask for extracting [21:3]
  setx  L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA,
  or    %g5, %g4, %g5           !g5 now has Diagnostic Data Array address
  ldx   [%g5], %g6
  membar #Sync

! Flip one bits to inject error
  xor    %g6, 0x200, %g6
  stx   %g6, [%g5]
  membar #Sync

mov 0x7,%i4
clr %i3
loop_next:
  inc %i3
  cmp %i3,%i4
  bne loop_next
  nop


store_for_wb:                 !Load to L2 again to get the error
  set  0x55555555,%l6
  set  0x2000aa00, %g2
  stx   %l6, [%g2]


set_DRAM_err_cnt_reg:
  mov  0x1,%l2
  setx  DRAM_ERR_CNT_REG_PA_0,%l1,%g6
  setx  DRAM_ERR_CNT_REG_PA_1,%l1,%g3
  setx  DRAM_ERR_CNT_REG_PA_2,%l1,%g4
  setx  DRAM_ERR_CNT_REG_PA_3,%l1,%g5
  stx   %l2, [%g3]
  stx   %l2, [%g4]
  stx   %l2, [%g5]
  stx   %l2, [%g6]
  membar 0x40

set_DRAM_fbr_count_reg:
        set     0x10000, %g6            !<16>=countone=1
        setx    DRAM_FBR_CNT_REG_PA_0, %l7, %o2
        setx    DRAM_FBR_CNT_REG_PA_1, %l7, %o3
        setx    DRAM_FBR_CNT_REG_PA_2, %l7, %o4
        setx    DRAM_FBR_CNT_REG_PA_3, %l7, %o5
        stx     %g6, [%o2]
        stx     %g6, [%o3]
        stx     %g6, [%o4]
        stx     %g6, [%o5]
        ldx     [%o2], %i1
        ldx     [%o3], %i2
        ldx     [%o4], %i3
        ldx     [%o5], %i4


set_DRAM_error_inject_ch0_dac:
  mov   0x2, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG_0, %l3, %g3
  setx  DRAM_ERR_INJ_REG_1, %l3, %g4
  setx  DRAM_ERR_INJ_REG_2, %l3, %g5
  setx  DRAM_ERR_INJ_REG_3, %l3, %g6
  stx   %l1, [%g3]
  stx   %l1, [%g4]
  stx   %l1, [%g5]
  stx   %l1, [%g6]
  membar 0x40


store_to_L2_way0_dac:
  set  0x55555555,  %l0
  set  0x22000000,  %g7  ! bits [21:18] select way
  set   0x80, %l1
  set   0x100,%l2
  set   0x180, %l3
  add   %g7,%l1,%g2
  add   %g7,%l2,%g3
  add   %g7,%l3,%g4
  stx   %l0, [%g2]
  membar #Sync
  stx   %l0, [%g3]
  membar #Sync
  stx   %l0, [%g4]
  membar #Sync
  stx   %l0, [%g7]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0_dac:
  set  0x80,%l1
  set  0x31000000, %i3 ! bits [21:18] select way
  add   %i3,%l1,%i2
  add   %i2,%l1,%i7
  add   %i7,%l1,%i4
  stx %g5, [%i2]
  stx %g5, [%i3]
  stx %g5, [%i4]
  stx %g5, [%i7]
  membar #Sync

read_error_address0_dac:
 ldx   [%g2], %l0
 ldx   [%g3], %l1
 ldx   [%g4], %l2
 ldx   [%g7], %l3
  membar #Sync

read_error_address1_dac:
 ldx   [%g2], %l0
 ldx   [%g3], %l1
 ldx   [%g4], %l2
 ldx   [%g7], %l3
  membar #Sync


read_error_address2_dac:
 ldx   [%g2], %l0
 ldx   [%g3], %l1
 ldx   [%g4], %l2
 ldx   [%g7], %l3
  membar #Sync

Check_L2_esr:
        setx  L2ES_PA0, %l6, %g1
        ldx   [%g1], %g2

Verify_L2_esr:
        mov     0x1, %l1
        sllx    %l1, L2ES_MEC, %l0
        sllx    %l1, L2ES_LDWC, %l2
        or      %l0, %l2, %l2
        sllx    %l1, L2ES_DSC, %l3
        sllx    %l1, L2ES_VEC, %l4
        or      %l3, %l4, %l4
        or      %l2, %l4, %l4
        cmp     %l4, %g2
        bne     test_fail
        nop

Check_Soc_esr:
        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
        nop


Verify_Soc_esr:
        setx    0x8000036d80000000, %l7, %o3    !valid bit
        cmp     %o3, %i1
        bne     test_fail
        nop


ba test_pass
nop

test_pass:
EXIT_GOOD

test_fail:
EXIT_BAD
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_McuFbr_McuEcc_LDWC.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#include "err_defines.h"
	43	#include "hboot.s"
	44
	45
	46	#define DMA_DATA_ADDR 0x0000000123456700
	47	#define DMA_DATA_BYP_SADDR 0xfffc00003000aa00
	48	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	49	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	50	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	51	#define DRAM_ERR_INJ_REG_0 0x8400000290
	52	#define DRAM_ERR_INJ_REG_1 0x8400001290
	53	#define DRAM_ERR_INJ_REG_2 0x8400002290
	54	#define DRAM_ERR_INJ_REG_3 0x8400003290
	55	#define L2_ENTRY_PA 0xa000000000
	56
	57
	58
	59
	60	/************************************************************************
	61	Test case code start
	62	************************************************************************/
	63	.text
	64	.global main
65
66	main:
67	ta T_CHANGE_HPRIV
68	nop
69
70	set_Soc_Err_Inj_reg:
71	set 0x1, %i1
72	setx 0x800001248c80040c,%i1,%i2
73	setx SOC_EJR_REG, %l7, %i3
74	stx %i2, [%i3]
75	membar 0x40
76
77	disable_l1_DCache:
78	ldxa [%g0] ASI_LSU_CONTROL, %l0
79	! Remove bit 2
80	andn %l0, 0x2, %l0
81	stxa %l0, [%g0] ASI_LSU_CONTROL
82
83	set_L2_Directly_Mapped_Mode:
84	set 0x80, %l1
85	set 0x100,%l2
86	set 0x180, %l3
87	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
88	add %g1,%l1,%g2
89	add %g1,%l2,%g3
90	add %g1,%l3,%g4
91	mov 0x2, %l0
92	stx %l0, [%g1]
93	stx %l0, [%g2]
94	stx %l0, [%g3]
95	stx %l0, [%g4]
96
97
98	store_to_L2_way0_ldac:
99	set 0x5555555, %g5
100	setx 0x3000aa00, %l0, %g2 ! bits [21:18] select way
101	stx %g5, [%g2]
102	stx %g5, [%g2+8]
103	membar #Sync
104
105	mov 0x20,%i4
106	clr %i3
107	loop:
108	inc %i3
109	cmp %i3,%i4
110	bne loop
111	nop
112
113
114	L2_diag_load_ldac:
115	set 0x3ffff8, %l2 ! Mask for extracting [21:3]
116	setx L2_ENTRY_PA, %l0, %g4
117	and %g2, %l2, %g5 !g2 has L2 PA,
118	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
119	ldx [%g5], %g6
120	membar #Sync
121
122	! Flip one bits to inject error
123	xor %g6, 0x200, %g6
124	stx %g6, [%g5]
125	membar #Sync
126
127	mov 0x7,%i4
128	clr %i3
129	loop_next:
130	inc %i3
131	cmp %i3,%i4
132	bne loop_next
133	nop
134
135
136	store_for_wb: !Load to L2 again to get the error
137	set 0x55555555,%l6
138	set 0x2000aa00, %g2
139	stx %l6, [%g2]
140
141
142	set_DRAM_err_cnt_reg:
143	mov 0x1,%l2
144	setx DRAM_ERR_CNT_REG_PA_0,%l1,%g6
145	setx DRAM_ERR_CNT_REG_PA_1,%l1,%g3
146	setx DRAM_ERR_CNT_REG_PA_2,%l1,%g4
147	setx DRAM_ERR_CNT_REG_PA_3,%l1,%g5
148	stx %l2, [%g3]
149	stx %l2, [%g4]
150	stx %l2, [%g5]
151	stx %l2, [%g6]
152	membar 0x40
153
154	set_DRAM_fbr_count_reg:
155	set 0x10000, %g6 !<16>=countone=1
156	setx DRAM_FBR_CNT_REG_PA_0, %l7, %o2
157	setx DRAM_FBR_CNT_REG_PA_1, %l7, %o3
158	setx DRAM_FBR_CNT_REG_PA_2, %l7, %o4
159	setx DRAM_FBR_CNT_REG_PA_3, %l7, %o5
160	stx %g6, [%o2]
161	stx %g6, [%o3]
162	stx %g6, [%o4]
163	stx %g6, [%o5]
164	ldx [%o2], %i1
165	ldx [%o3], %i2
166	ldx [%o4], %i3
167	ldx [%o5], %i4
168
169
170
171	set_DRAM_error_inject_ch0_dac:
172	mov 0x2, %l1 ! ECC Mask (1-bit error)
173	mov 0x1, %l2
174	sllx %l2, DRAM_EI_SSHOT, %l3
175	or %l1, %l3, %l1 ! Set single shot ;
176	mov 0x1, %l2
177	sllx %l2, DRAM_EI_ENB, %l3
178	or %l1, %l3, %l1 ! Enable error injection for the next write
179	setx DRAM_ERR_INJ_REG_0, %l3, %g3
180	setx DRAM_ERR_INJ_REG_1, %l3, %g4
181	setx DRAM_ERR_INJ_REG_2, %l3, %g5
182	setx DRAM_ERR_INJ_REG_3, %l3, %g6
183	stx %l1, [%g3]
184	stx %l1, [%g4]
185	stx %l1, [%g5]
186	stx %l1, [%g6]
187	membar 0x40
188
189
190	store_to_L2_way0_dac:
191	set 0x55555555, %l0
192	set 0x22000000, %g7 ! bits [21:18] select way
193	set 0x80, %l1
194	set 0x100,%l2
195	set 0x180, %l3
196	add %g7,%l1,%g2
197	add %g7,%l2,%g3
198	add %g7,%l3,%g4
199	stx %l0, [%g2]
200	membar #Sync
201	stx %l0, [%g3]
202	membar #Sync
203	stx %l0, [%g4]
204	membar #Sync
205	stx %l0, [%g7]
206	membar #Sync
207
208	! Storing to same L2 way0 but different tag,this will write to mcu
209	write_mcu_channel_0_dac:
210	set 0x80,%l1
211	set 0x31000000, %i3 ! bits [21:18] select way
212	add %i3,%l1,%i2
213	add %i2,%l1,%i7
214	add %i7,%l1,%i4
215	stx %g5, [%i2]
216	stx %g5, [%i3]
217	stx %g5, [%i4]
218	stx %g5, [%i7]
219	membar #Sync
220
221	read_error_address0_dac:
222	ldx [%g2], %l0
223	ldx [%g3], %l1
224	ldx [%g4], %l2
225	ldx [%g7], %l3
226	membar #Sync
227
228	read_error_address1_dac:
229	ldx [%g2], %l0
230	ldx [%g3], %l1
231	ldx [%g4], %l2
232	ldx [%g7], %l3
233	membar #Sync
234
235
236	read_error_address2_dac:
237	ldx [%g2], %l0
238	ldx [%g3], %l1
239	ldx [%g4], %l2
240	ldx [%g7], %l3
241	membar #Sync
242
243	Check_L2_esr:
244	setx L2ES_PA0, %l6, %g1
245	ldx [%g1], %g2
246
247	Verify_L2_esr:
248	mov 0x1, %l1
249	sllx %l1, L2ES_MEC, %l0
250	sllx %l1, L2ES_LDWC, %l2
251	or %l0, %l2, %l2
252	sllx %l1, L2ES_DSC, %l3
253	sllx %l1, L2ES_VEC, %l4
254	or %l3, %l4, %l4
255	or %l2, %l4, %l4
256	cmp %l4, %g2
257	bne test_fail
258	nop
259
260	Check_Soc_esr:
261	setx SOC_ESR_REG, %l7, %i0
262	ldx [%i0], %i1
263	nop
264
265
266	Verify_Soc_esr:
267	setx 0x8000036d80000000, %l7, %o3 !valid bit
268	cmp %o3, %i1
269	bne test_fail
270	nop
271
272
273
274	ba test_pass
275	nop
276
277	test_pass:
278	EXIT_GOOD
279
280	test_fail:
281	EXIT_BAD