[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_adv_mcu_4_CRC_MULTI_ECC_FBU.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_mcu_4_CRC_MULTI_ECC_FBU.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA1         0x1000100081c3e008
#define  TEST_DATA2         0x2000200081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffff800000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define	 ERROR_ADDR	    0x20200000

#define  DRAM_SCRUB_FREQ_REG  0x8400000018
#define  DRAM_SCRUB_ENB_REG    0x8400000040

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main


main:
  ta T_CHANGE_HPRIV

! begin
get_th_id_o0:
  ta  T_RD_THID
  cmp  %o1, 0x0
  be  main_t0
  nop
  cmp  %o1, 0x1
  be  main_t1
  nop

main_t0:
  ba L2B0_Init
  nop

L2B0_Init:
disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

clear_DRAM_ESR_MCU0_BANK0:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400000280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_B0:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000000, %l1, %g7
  stx   %g4, [%g7]
  
set_DRAM_error_inject_mcu0_b0:
  mov   0x2, %l1
  !mov   0x1, %l2
  !sllx  %l2, DRAM_EI_SSHOT, %l2
  !or    %l1, %l2, %l1
  mov   0x1, %l3
  sllx  %l3, 31, %l3
  or    %l1, %l3, %l1
  setx  0x8400000290, %l0, %g4
  stx   %l1, [%g4]
  membar 0x40

set_L2_Direct_Mapped_Mode_b0:
  clr %l0
  clr %g1
  setx  0xa900000000, %l0, %g1
  mov   0x2, %l0
  stx   %l0, [%g1]
  membar 0x40
  
  clr %g1
  clr %g2
  clr %l1
  setx  0x0123456789abcdef, %l1, %g2
  clr %l2
  mov 0x1, %l2
  sllx %l2, 22, %l2
  clr %l3
  mov 100, %l3
st_to_L2_way0_and_MCU0:
  stx %g2, [%g1]
  membar 0x40
  clr %l4
  add %g1, %l2, %l4
  stx %g2, [%l4]
  membar 0x40
  add %g1, 0x200, %g1
  sub %l3, 1, %l3
  brnz %l3,st_to_L2_way0_and_MCU0
  nop

  clr %g1
  clr %l2
  mov 200, %l2
ld_from_error_and_nonerror_address_b0:
  ld [%g1], %l1
  membar 0x40
  add %g1, 0x100, %g1
  sub %l2, 1, %l2
  brnz %l2,ld_from_error_and_nonerror_address_b0
  nop

  clr %g1
  mov 0x1, %g1
  sllx %g1, 32, %g1
  clr %g2
  mov 0x1, %g2
  sllx %g2, 22, %g2
  clr %g3
  mov 100, %g3

ld_from_L2_bank0_for_CRC:
  ldx [%g1], %l1
  membar 0x40
  add %g1, %g2, %g1
  sub %g3, 1, %g3
  brnz %g3,ld_from_L2_bank0_for_CRC
  nop
  
check_DRAM_ESR_MCU0_L2B0_FBR:
  !clr %l1
  !mov   0xf, %l1
  !sllx  %l1, 60, %l1
  !clr %l2
  !mov   0x3, %l2
  !sllx  %l2, 54, %l2
  !or    %l1, %l2, %l1
  ldx   [%g6], %l0
  clr %l4
  set   0xffff, %l4
  andn  %l0, %l4, %l0
  !cmp   %l0, %l1
  !bne   %xcc, test_fail
  !nop

check_L2_ESR_Bank_0_DSC:
  !clr %l1
  !mov   0x3, %l1
  !sllx  %l1, 62, %l1
  !clr %l2
  !mov 0x3, %l2
  !sllx %l2, 41, %l2
  !or %l1, %l2, %l1
  !clr %l3
  !mov 0xb, %l3
  !sllx %l3, 35, %l3
  !or %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  !cmp   %l0, %l1
  !bne   %xcc, test_fail
  !nop

  ba    test_pass
  nop

main_t1:
  ba L2B1_Init
  nop

L2B1_Init:

clear_DRAM_ESR_MCU0_BANK1:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400000280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_B1:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000040, %l1, %g7
  stx   %g4, [%g7]
  
set_DRAM_error_inject_mcu0_b1:
  mov   0x2, %l1
  !mov   0x1, %l2
  !sllx  %l2, DRAM_EI_SSHOT, %l2
  !or    %l1, %l2, %l1
  mov   0x1, %l3
  sllx  %l3, 31, %l3
  or    %l1, %l3, %l1
  setx  0x8400000290, %l0, %g4
  stx   %l1, [%g4]
  membar 0x40

set_L2_Direct_Mapped_Mode_b1:
  clr %l0
  clr %g1
  setx  0xa900000040, %l0, %g1
  mov   0x2, %l0
  stx   %l0, [%g1]
  membar 0x40
  
  clr %g1
  add %g1, 0x40, %g1
  clr %g2
  clr %l1
  setx  0x0123456789abcdef, %l1, %g2
  clr %l2
  mov 0x1, %l2
  sllx %l2, 22, %l2
  clr %l3
  mov 100, %l3
st_to_L2_way1_and_MCU0:
  stx %g2, [%g1]
  membar 0x40
  clr %l4
  add %g1, %l2, %l4
  stx %g2, [%l4]
  membar 0x40
  add %g1, 0x200, %g1
  sub %l3, 1, %l3
  brnz %l3,st_to_L2_way1_and_MCU0
  nop

  clr %g1
  add %g1, 0x40, %g1
  clr %l2
  mov 200, %l2
ld_from_error_and_nonerror_address_b1:
  ld [%g1], %l1
  membar 0x40
  add %g1, 0x100, %g1
  sub %l2, 1, %l2
  brnz %l2,ld_from_error_and_nonerror_address_b1
  nop

  clr %g1
  mov 0x1, %g1
  sllx %g1, 32, %g1
  add %g1, 0x40, %g1
  clr %g2
  mov 0x1, %g2
  sllx %g2, 22, %g2
  clr %g3
  mov 100, %g3

ld_from_L2_bank1_for_CRC:
  ldx [%g1], %l1
  membar 0x40
  add %g1, %g2, %g1
  sub %g3, 1, %g3
  brnz %g3,ld_from_L2_bank1_for_CRC
  nop
  
check_DRAM_ESR_MCU0_L2B1_FBR:
  !clr %l1
  !mov   0xf, %l1
  !sllx  %l1, 60, %l1
  !clr %l2
  !mov   0x3, %l2
  !sllx  %l2, 54, %l2
  !or    %l1, %l2, %l1
  ldx   [%g6], %l0
  clr %l4
  set   0xffff, %l4
  andn  %l0, %l4, %l0
  !cmp   %l0, %l1
  !bne   %xcc, test_fail
  !nop

check_L2_ESR_Bank_1_DSC:
  !clr %l1
  !mov   0x3, %l1
  !sllx  %l1, 62, %l1
  !clr %l2
  !mov 0x3, %l2
  !sllx %l2, 41, %l2
  !or %l1, %l2, %l1
  !clr %l3
  !mov 0xb, %l3
  !sllx %l3, 35, %l3
  !or %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  !cmp   %l0, %l1
  !bne   %xcc, test_fail
  !nop

  ba    test_pass
  nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_mcu_4_CRC_MULTI_ECC_FBU.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define L2_ERR_STAT_REG 0xAB00000000
	42	#define L2_ERR_ADDR_REG 0xAC00000000
	43
	44	#define TEST_DATA1 0x1000100081c3e008
	45	#define TEST_DATA2 0x2000200081c3e008
	46	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	47	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	48
	49	#define DRAM_ERR_INJ_REG 0x8400000290
	50	#define DRAM_ERR_STAT_REG 0x8400000280
	51	#define ERROR_ADDR 0x20200000
	52
	53	#define DRAM_SCRUB_FREQ_REG 0x8400000018
	54	#define DRAM_SCRUB_ENB_REG 0x8400000040
	55
	56	#include "hboot.s"
	57	#include "asi_s.h"
	58	#include "err_defines.h"
	59
	60
	61	.text
	62	.global main
	63
	64
65	main:
66	ta T_CHANGE_HPRIV
67
68	! begin
69	get_th_id_o0:
70	ta T_RD_THID
71	cmp %o1, 0x0
72	be main_t0
73	nop
74	cmp %o1, 0x1
75	be main_t1
76	nop
77
78	main_t0:
79	ba L2B0_Init
80	nop
81
82	L2B0_Init:
83	disable_l1:
84	ldxa [%g0] ASI_LSU_CONTROL, %l0
85	! Remove the lower 2 bits (I-Cache and D-Cache enables)
86	andn %l0, 0x3, %l0
87	stxa %l0, [%g0] ASI_LSU_CONTROL
88
89	clear_DRAM_ESR_MCU0_BANK0:
90	clr %l0
91	clr %l1
92	setx DRAM_ES_W1C_VALUE, %l0, %g2
93	setx 0x8400000280, %l1, %g6
94	stx %g2, [%g6]
95	clear_L2_ESR_B0:
96	clr %l0
97	clr %l1
98	setx L2_ES_W1C_VALUE, %l0, %g4
99	setx 0xbb00000000, %l1, %g7
100	stx %g4, [%g7]
101
102	set_DRAM_error_inject_mcu0_b0:
103	mov 0x2, %l1
104	!mov 0x1, %l2
105	!sllx %l2, DRAM_EI_SSHOT, %l2
106	!or %l1, %l2, %l1
107	mov 0x1, %l3
108	sllx %l3, 31, %l3
109	or %l1, %l3, %l1
110	setx 0x8400000290, %l0, %g4
111	stx %l1, [%g4]
112	membar 0x40
113
114	set_L2_Direct_Mapped_Mode_b0:
115	clr %l0
116	clr %g1
117	setx 0xa900000000, %l0, %g1
118	mov 0x2, %l0
119	stx %l0, [%g1]
120	membar 0x40
121
122	clr %g1
123	clr %g2
124	clr %l1
125	setx 0x0123456789abcdef, %l1, %g2
126	clr %l2
127	mov 0x1, %l2
128	sllx %l2, 22, %l2
129	clr %l3
130	mov 100, %l3
131	st_to_L2_way0_and_MCU0:
132	stx %g2, [%g1]
133	membar 0x40
134	clr %l4
135	add %g1, %l2, %l4
136	stx %g2, [%l4]
137	membar 0x40
138	add %g1, 0x200, %g1
139	sub %l3, 1, %l3
140	brnz %l3,st_to_L2_way0_and_MCU0
141	nop
142
143	clr %g1
144	clr %l2
145	mov 200, %l2
146	ld_from_error_and_nonerror_address_b0:
147	ld [%g1], %l1
148	membar 0x40
149	add %g1, 0x100, %g1
150	sub %l2, 1, %l2
151	brnz %l2,ld_from_error_and_nonerror_address_b0
152	nop
153
154	clr %g1
155	mov 0x1, %g1
156	sllx %g1, 32, %g1
157	clr %g2
158	mov 0x1, %g2
159	sllx %g2, 22, %g2
160	clr %g3
161	mov 100, %g3
162
163	ld_from_L2_bank0_for_CRC:
164	ldx [%g1], %l1
165	membar 0x40
166	add %g1, %g2, %g1
167	sub %g3, 1, %g3
168	brnz %g3,ld_from_L2_bank0_for_CRC
169	nop
170
171	check_DRAM_ESR_MCU0_L2B0_FBR:
172	!clr %l1
173	!mov 0xf, %l1
174	!sllx %l1, 60, %l1
175	!clr %l2
176	!mov 0x3, %l2
177	!sllx %l2, 54, %l2
178	!or %l1, %l2, %l1
179	ldx [%g6], %l0
180	clr %l4
181	set 0xffff, %l4
182	andn %l0, %l4, %l0
183	!cmp %l0, %l1
184	!bne %xcc, test_fail
185	!nop
186
187	check_L2_ESR_Bank_0_DSC:
188	!clr %l1
189	!mov 0x3, %l1
190	!sllx %l1, 62, %l1
191	!clr %l2
192	!mov 0x3, %l2
193	!sllx %l2, 41, %l2
194	!or %l1, %l2, %l1
195	!clr %l3
196	!mov 0xb, %l3
197	!sllx %l3, 35, %l3
198	!or %l1, %l3, %l1
199	ldx [%g7], %l0
200	clr %l2
201	clr %l3
202	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
203	and %l0, %l3, %l0
204	!cmp %l0, %l1
205	!bne %xcc, test_fail
206	!nop
207
208	ba test_pass
209	nop
210
211	main_t1:
212	ba L2B1_Init
213	nop
214
215	L2B1_Init:
216
217	clear_DRAM_ESR_MCU0_BANK1:
218	clr %l0
219	clr %l1
220	setx DRAM_ES_W1C_VALUE, %l0, %g2
221	setx 0x8400000280, %l1, %g6
222	stx %g2, [%g6]
223	clear_L2_ESR_B1:
224	clr %l0
225	clr %l1
226	setx L2_ES_W1C_VALUE, %l0, %g4
227	setx 0xbb00000040, %l1, %g7
228	stx %g4, [%g7]
229
230	set_DRAM_error_inject_mcu0_b1:
231	mov 0x2, %l1
232	!mov 0x1, %l2
233	!sllx %l2, DRAM_EI_SSHOT, %l2
234	!or %l1, %l2, %l1
235	mov 0x1, %l3
236	sllx %l3, 31, %l3
237	or %l1, %l3, %l1
238	setx 0x8400000290, %l0, %g4
239	stx %l1, [%g4]
240	membar 0x40
241
242	set_L2_Direct_Mapped_Mode_b1:
243	clr %l0
244	clr %g1
245	setx 0xa900000040, %l0, %g1
246	mov 0x2, %l0
247	stx %l0, [%g1]
248	membar 0x40
249
250	clr %g1
251	add %g1, 0x40, %g1
252	clr %g2
253	clr %l1
254	setx 0x0123456789abcdef, %l1, %g2
255	clr %l2
256	mov 0x1, %l2
257	sllx %l2, 22, %l2
258	clr %l3
259	mov 100, %l3
260	st_to_L2_way1_and_MCU0:
261	stx %g2, [%g1]
262	membar 0x40
263	clr %l4
264	add %g1, %l2, %l4
265	stx %g2, [%l4]
266	membar 0x40
267	add %g1, 0x200, %g1
268	sub %l3, 1, %l3
269	brnz %l3,st_to_L2_way1_and_MCU0
270	nop
271
272	clr %g1
273	add %g1, 0x40, %g1
274	clr %l2
275	mov 200, %l2
276	ld_from_error_and_nonerror_address_b1:
277	ld [%g1], %l1
278	membar 0x40
279	add %g1, 0x100, %g1
280	sub %l2, 1, %l2
281	brnz %l2,ld_from_error_and_nonerror_address_b1
282	nop
283
284	clr %g1
285	mov 0x1, %g1
286	sllx %g1, 32, %g1
287	add %g1, 0x40, %g1
288	clr %g2
289	mov 0x1, %g2
290	sllx %g2, 22, %g2
291	clr %g3
292	mov 100, %g3
293
294	ld_from_L2_bank1_for_CRC:
295	ldx [%g1], %l1
296	membar 0x40
297	add %g1, %g2, %g1
298	sub %g3, 1, %g3
299	brnz %g3,ld_from_L2_bank1_for_CRC
300	nop
301
302	check_DRAM_ESR_MCU0_L2B1_FBR:
303	!clr %l1
304	!mov 0xf, %l1
305	!sllx %l1, 60, %l1
306	!clr %l2
307	!mov 0x3, %l2
308	!sllx %l2, 54, %l2
309	!or %l1, %l2, %l1
310	ldx [%g6], %l0
311	clr %l4
312	set 0xffff, %l4
313	andn %l0, %l4, %l0
314	!cmp %l0, %l1
315	!bne %xcc, test_fail
316	!nop
317
318	check_L2_ESR_Bank_1_DSC:
319	!clr %l1
320	!mov 0x3, %l1
321	!sllx %l1, 62, %l1
322	!clr %l2
323	!mov 0x3, %l2
324	!sllx %l2, 41, %l2
325	!or %l1, %l2, %l1
326	!clr %l3
327	!mov 0xb, %l3
328	!sllx %l3, 35, %l3
329	!or %l1, %l3, %l1
330	ldx [%g7], %l0
331	clr %l2
332	clr %l3
333	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
334	and %l0, %l3, %l0
335	!cmp %l0, %l1
336	!bne %xcc, test_fail
337	!nop
338
339	ba test_pass
340	nop
341
342	/*******************************************************
343	* Exit code
344	*******************************************************/
345
346	test_pass:
347	ta T_GOOD_TRAP
348
349	test_fail:
350	ta T_BAD_TRAP
351