[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_mcu_int_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_mcu_int_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO


#include "hboot.s"
#include "asi_s.h"

#define L20 0x0000134000
#define L21 0x0000134040

#define L22 0x0000134080
#define L23 0x00001340c0

#define L24 0x0000134100
#define L25 0x0000134140

#define L26 0x0000134180
#define L27 0x00001341c0

#ifdef MCU0
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_0

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_0

#define  DRAM_ERR_INJ_REG               0x8400000290
#define  DRAM_ERR_STAT_REG              0x8400000280
#define  L2_ERR_STAT_REG                0xAB00000000
#define  L2_ERR_ADDR_REG                0xAC00000000
#endif

#ifdef MCU1
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_1

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_1

#define  DRAM_ERR_INJ_REG               0x8400001290
#define  DRAM_ERR_STAT_REG              0x8400001280
#define  L2_ERR_STAT_REG                0xAB00000080
#define  L2_ERR_ADDR_REG                0xAC00000080
#endif

#ifdef MCU2
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_2

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_2

#define  DRAM_ERR_INJ_REG               0x8400002290
#define  DRAM_ERR_STAT_REG              0x8400002280
#define  L2_ERR_STAT_REG                0xAB00000100
#define  L2_ERR_ADDR_REG                0xAC00000100
#endif

#ifdef MCU3
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_3
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_3

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_3


#define  DRAM_ERR_INJ_REG               0x8400003290
#define  DRAM_ERR_STAT_REG              0x8400003280
#define  L2_ERR_STAT_REG                0xAB00000180
#define  L2_ERR_ADDR_REG                0xAC00000180
#endif

#ifdef ECC
#define CMP_ECC_CNT     0x0
#else
#define CMP_ECC_CNT     0x1
#endif

#ifdef L2_OFF
#define L2_ON_OFF_DM	0x1
#else
#define L2_ON_OFF_DM    0x0
#endif
 
#define TT      0x63

.text
.global	 main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap


main:
	ta	  T_CHANGE_HPRIV

	clr	%i6
	clr	%i7

L2_on_off_dm:
        setx  L2CS_PA0, %l6, %g1
	ldx   [%g1], %o1

	setx  0xfffffffffffffffc, %l6, %i1	! <1:0>=00
	and   %i1, %o1, %o2
	
        mov   L2_ON_OFF_DM, %l0
	or    %o2, %l0, %l1

        stx   %l1, [%g1]

	nop
	membar #Sync

write_mcu_fbr_count_reg:
	set	0x10000, %g6		!<16>=countone=1
	setx	DRAM_FBR_CNT_REG_PA, %l7, %o2
	stx     %g6, [%o2]
	ldx     [%o2], %i1


set_error_count_reg:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

clear_soc_esr:
        setx   	SOC_ESR_REG, %l7, %g5
        stx     %g0, [%g5]

clear_soc_per:
        setx    SOC_PER_REG, %l7, %g5
        stx     %g0, [%g5]

clear_mcu_esr:
        setx    DRAM_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_esr:
        setx    L2_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_ear:
        setx    L2_ERR_ADDR_REG, %l7, %g5
        stx     %g0, [%g5]

#ifdef FBR
set_inj_err_src_reg:
        set     INJ_ERR_SRC, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40
#endif

set_ejr:
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2 
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

set_eie:
        setx    SOC_EIE_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

L2_Init:
	 setx	0x1111111111111110, %g7, %o0
	setx	0x2222222222222220, %g7, %o1
	setx	0x3333333333333330, %g7, %o2
	setx	0x4444444444444440, %g7, %o3
	setx	0x5555555555555550, %g7, %o4
	setx	0x6666666666666660, %g7, %o5
	setx	0x8888888888888880, %g7, %o6
	setx	0x9999999999999990, %g7, %o7

	setx	L20, %g7, %l0
	setx	L21, %g7, %l1

	setx	L22, %g7, %l2
	setx	L23, %g7, %l3

	setx	L24, %g7, %l4
	setx	L25, %g7, %l5

	setx	L26, %g7, %l6
	setx	L27, %g7, %l7

L2_0:
		stx	%o0, [%l0]
	ldx	[%l0], %g1

L2_1:
		stx	%o1, [%l1]
	ldx	[%l1], %g1

L2_2:
		stx	%o2, [%l2]
	ldx	[%l2], %g1

L2_3:
		stx	%o3, [%l3]
	ldx	[%l3], %g1

L2_4:
	stx	%o4, [%l4]
	ldx	[%l4], %g1

L2_5:
		stx	%o5, [%l5]
	ldx	[%l5], %g1

L2_6:
		stx	%o6, [%l6]
	ldx	[%l6], %g1

L2_7:
	stx	%o7, [%l7]
	ldx	[%l7], %g1

	membar 0x40

next_line:
        add     %l0, 0x40, %l0
        add     %l1, 0x40, %l1
        add     %l2, 0x40, %l2
        add     %l3, 0x40, %l3
        add     %l4, 0x40, %l4
        add     %l5, 0x40, %l5
        add     %l6, 0x40, %l6
        add     %l7, 0x40, %l7

L2_4_again:
		stx	%o4, [%l4]
	ldx	[%l4], %g1

L2_5_again:
		stx	%o5, [%l5]
	ldx	[%l5], %g1

L2_6_again:
		stx	%o6, [%l6]
	ldx	[%l6], %g1

L2_7_again:
		stx	%o7, [%l7]
	ldx	[%l7], %g1

L2_0_again:
	stx	%o0, [%l0]
	ldx	[%l0], %g1

L2_1_again:
	stx	%o1, [%l1]
	ldx	[%l1], %g1

L2_2_again:
	stx	%o2, [%l2]
	ldx	[%l2], %g1

L2_3_again:
	stx	%o3, [%l3]
	ldx	[%l3], %g1


	membar 0x40


	! ESR should be cleared by INTERRUPT; so check PER

check_ncu_per:
        setx    SOC_PER_REG, %l7, %g5
        ldx     [%g5], %i1
	nop
        setx    0x8000000000000000, %l7, %g7    !valid bit
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2     
        or      %g7, %g2, %i3      
        subcc   %i1, %i3, %i4
        brnz    %i4, test_fail
        nop

/*
check_ncu_esr:
        setx    SOC_ESR_REG, %l7, %g5
        ldx     [%g5], %i1
        subcc   %i1, %g0, %i4
        brnz    %i4, test_fail
        nop
*/

#ifdef FBR
check_mcu_esr:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBR, %l6

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l1

        setx  0xffffffffffff0000, %l3, %l0
        andcc %l0, %l1, %l5                   ! Donot check L2ESR SYND bits

        sub     %l5, %l6, %i4
        brnz    %i4, test_fail
        nop
#endif

#ifdef ECC
check_mcu_esr:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAC, %l0

        mov     0x1, %l1
        sllx    %l1, DRAM_ES_MEC, %l2

        or      %l0, %l2, %l6

!       set   0x2000, %l3      ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed
!       or    %l0, %l3, %l0            ! %l0 has expected value

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l1

        setx  0xffffffffffff0000, %l3, %l0
        andcc %l0, %l1, %l5                   ! Donot check L2ESR SYND bits

        sub     %l5, %l6, %i4
        brnz    %i4, test_fail
        nop

check_L2_ESR_0:
	setx  L2_ERR_STAT_REG, %l3, %g5  
	ldx   [%g5], %l6

	setx  0xfffffffff0000000, %l3, %l0
	andcc %l0, %l6, %l5                   ! Donot check L2ESR SYND bits

	mov   0x1, %l1
	sllx  %l1, L2ES_DAC, %l0

	mov   0x1, %l1
	sllx  %l1, L2ES_VEC, %l2

        or    %l0, %l2, %i4

        mov   0x1, %l1
        sllx  %l1, L2ES_MEC, %i3

	or    %i3, %i4, %i5

	cmp   %l5, %i5
	bne   %xcc, test_fail
	nop

ch_L2_addr_ch0:
	setx  L2_ERR_ADDR_REG, %l3, %g5  
	ldx   [%g5], %l1
	membar 0x40
#endif

read_fbr_cnt_reg:
        setx    DRAM_FBR_CNT_REG_PA, %l7, %o2
	ldx	[%o2], %g1
        set     0x10000, %g6            !<16>=countone=1
	sub     %g1, %g6, %i4
        brnz    %i4, test_fail
        nop

read_err_cnt_reg:
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        ldx     [%o2], %g1
	set	CMP_ECC_CNT, %i1
        sub     %g1, %i1, %i4
        brnz    %i4, test_fail
        nop


#ifdef FBR
read_fbd_err_synd_reg:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
        ldx     [%o2], %g1

        setx    0x8000000000000000, %l7, %o3
        set     0x1, %o4
        sll     %o4, FBSYND, %o5
        or      %o3, %o5, %g2

        and     %g1, %g2, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
        nop
#endif

check_error_trap:
        setx  EXECUTED, %l1, %l0
        cmp   %i2, %l0
        bne   test_fail
        nop

        mov   TT, %l0
        cmp   %i0, %l0
        bne   test_fail
        nop

	!no TT=0x40
	cmp	%i6, %g0
        bne   	test_fail
        nop

	set	0x1, %i1
        cmp     %i7, %i1 
        bne   	test_fail
        nop

/******************************************************
 * Exit code
 *******************************************************/

test_pass:
EXIT_GOOD

test_fail:
EXIT_BAD


/************************************************************************
   Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %i2
        ! save trap type value
        rdpr  %tt, %i0

	inc %i6
       
 	retry
        nop

	!PER not cleared at the end of the TRAP Handler to avoid further Trap
My_Corrected_ECC_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %i2
        ! save trap type value
        rdpr  %tt, %i0
	
	inc %i7

        retry
        nop
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_mcu_int_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define MAIN_PAGE_NUCLEUS_ALSO
	42	#define MAIN_PAGE_HV_ALSO
	43
	44
	45	#include "hboot.s"
	46	#include "asi_s.h"
	47
	48	#define L20 0x0000134000
	49	#define L21 0x0000134040
	50
	51	#define L22 0x0000134080
	52	#define L23 0x00001340c0
	53
	54	#define L24 0x0000134100
	55	#define L25 0x0000134140
	56
	57	#define L26 0x0000134180
	58	#define L27 0x00001341c0
	59
	60	#ifdef MCU0
	61	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
	62	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
	63
	64	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
65	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
66
67	#define DRAM_ERR_INJ_REG 0x8400000290
68	#define DRAM_ERR_STAT_REG 0x8400000280
69	#define L2_ERR_STAT_REG 0xAB00000000
70	#define L2_ERR_ADDR_REG 0xAC00000000
71	#endif
72
73	#ifdef MCU1
74	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
75	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
76
77	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
78	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
79
80	#define DRAM_ERR_INJ_REG 0x8400001290
81	#define DRAM_ERR_STAT_REG 0x8400001280
82	#define L2_ERR_STAT_REG 0xAB00000080
83	#define L2_ERR_ADDR_REG 0xAC00000080
84	#endif
85
86	#ifdef MCU2
87	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
88	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
89
90	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
91	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
92
93	#define DRAM_ERR_INJ_REG 0x8400002290
94	#define DRAM_ERR_STAT_REG 0x8400002280
95	#define L2_ERR_STAT_REG 0xAB00000100
96	#define L2_ERR_ADDR_REG 0xAC00000100
97	#endif
98
99	#ifdef MCU3
100	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
101	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
102
103	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
104	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
105
106
107	#define DRAM_ERR_INJ_REG 0x8400003290
108	#define DRAM_ERR_STAT_REG 0x8400003280
109	#define L2_ERR_STAT_REG 0xAB00000180
110	#define L2_ERR_ADDR_REG 0xAC00000180
111	#endif
112
113	#ifdef ECC
114	#define CMP_ECC_CNT 0x0
115	#else
116	#define CMP_ECC_CNT 0x1
117	#endif
118
119	#ifdef L2_OFF
120	#define L2_ON_OFF_DM 0x1
121	#else
122	#define L2_ON_OFF_DM 0x0
123	#endif
124
125	#define TT 0x63
126
127	.text
128	.global main
129	.global My_Corrected_ECC_error_trap
130	.global My_Recoverable_Sw_error_trap
131
132
133	main:
134	ta T_CHANGE_HPRIV
135
136	clr %i6
137	clr %i7
138
139	L2_on_off_dm:
140	setx L2CS_PA0, %l6, %g1
141	ldx [%g1], %o1
142
143	setx 0xfffffffffffffffc, %l6, %i1 ! <1:0>=00
144	and %i1, %o1, %o2
145
146	mov L2_ON_OFF_DM, %l0
147	or %o2, %l0, %l1
148
149	stx %l1, [%g1]
150
151	nop
152	membar #Sync
153
154	write_mcu_fbr_count_reg:
155	set 0x10000, %g6 !<16>=countone=1
156	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
157	stx %g6, [%o2]
158	ldx [%o2], %i1
159
160
161	set_error_count_reg:
162	set 0x1, %g6 !<16>=countone=1
163	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
164	stx %g6, [%o2]
165
166	clear_soc_esr:
167	setx SOC_ESR_REG, %l7, %g5
168	stx %g0, [%g5]
169
170	clear_soc_per:
171	setx SOC_PER_REG, %l7, %g5
172	stx %g0, [%g5]
173
174	clear_mcu_esr:
175	setx DRAM_ERR_STAT_REG, %l7, %g5
176	stx %g0, [%g5]
177
178	clear_l2_esr:
179	setx L2_ERR_STAT_REG, %l7, %g5
180	stx %g0, [%g5]
181
182	clear_l2_ear:
183	setx L2_ERR_ADDR_REG, %l7, %g5
184	stx %g0, [%g5]
185
186	#ifdef FBR
187	set_inj_err_src_reg:
188	set INJ_ERR_SRC, %g1
189	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
190	stx %g1, [%g3]
191	membar 0x40
192	#endif
193
194	set_ejr:
195	set 0x1, %g1
196	sllx %g1, ERR_FIELD, %g2
197	setx SOC_EJR_REG, %l7, %g3
198	stx %g2, [%g3]
199	membar 0x40
200
201	set_eie:
202	setx SOC_EIE_REG, %l7, %g3
203	stx %g2, [%g3]
204	membar 0x40
205
206	L2_Init:
207	setx 0x1111111111111110, %g7, %o0
208	setx 0x2222222222222220, %g7, %o1
209	setx 0x3333333333333330, %g7, %o2
210	setx 0x4444444444444440, %g7, %o3
211	setx 0x5555555555555550, %g7, %o4
212	setx 0x6666666666666660, %g7, %o5
213	setx 0x8888888888888880, %g7, %o6
214	setx 0x9999999999999990, %g7, %o7
215
216	setx L20, %g7, %l0
217	setx L21, %g7, %l1
218
219	setx L22, %g7, %l2
220	setx L23, %g7, %l3
221
222	setx L24, %g7, %l4
223	setx L25, %g7, %l5
224
225	setx L26, %g7, %l6
226	setx L27, %g7, %l7
227
228	L2_0:
229	stx %o0, [%l0]
230	ldx [%l0], %g1
231
232	L2_1:
233	stx %o1, [%l1]
234	ldx [%l1], %g1
235
236	L2_2:
237	stx %o2, [%l2]
238	ldx [%l2], %g1
239
240	L2_3:
241	stx %o3, [%l3]
242	ldx [%l3], %g1
243
244	L2_4:
245	stx %o4, [%l4]
246	ldx [%l4], %g1
247
248	L2_5:
249	stx %o5, [%l5]
250	ldx [%l5], %g1
251
252	L2_6:
253	stx %o6, [%l6]
254	ldx [%l6], %g1
255
256	L2_7:
257	stx %o7, [%l7]
258	ldx [%l7], %g1
259
260	membar 0x40
261
262	next_line:
263	add %l0, 0x40, %l0
264	add %l1, 0x40, %l1
265	add %l2, 0x40, %l2
266	add %l3, 0x40, %l3
267	add %l4, 0x40, %l4
268	add %l5, 0x40, %l5
269	add %l6, 0x40, %l6
270	add %l7, 0x40, %l7
271
272	L2_4_again:
273	stx %o4, [%l4]
274	ldx [%l4], %g1
275
276	L2_5_again:
277	stx %o5, [%l5]
278	ldx [%l5], %g1
279
280	L2_6_again:
281	stx %o6, [%l6]
282	ldx [%l6], %g1
283
284	L2_7_again:
285	stx %o7, [%l7]
286	ldx [%l7], %g1
287
288	L2_0_again:
289	stx %o0, [%l0]
290	ldx [%l0], %g1
291
292	L2_1_again:
293	stx %o1, [%l1]
294	ldx [%l1], %g1
295
296	L2_2_again:
297	stx %o2, [%l2]
298	ldx [%l2], %g1
299
300	L2_3_again:
301	stx %o3, [%l3]
302	ldx [%l3], %g1
303
304
305	membar 0x40
306
307
308	! ESR should be cleared by INTERRUPT; so check PER
309
310	check_ncu_per:
311	setx SOC_PER_REG, %l7, %g5
312	ldx [%g5], %i1
313	nop
314	setx 0x8000000000000000, %l7, %g7 !valid bit
315	set 0x1, %g1
316	sllx %g1, ERR_FIELD, %g2
317	or %g7, %g2, %i3
318	subcc %i1, %i3, %i4
319	brnz %i4, test_fail
320	nop
321
322	/*
323	check_ncu_esr:
324	setx SOC_ESR_REG, %l7, %g5
325	ldx [%g5], %i1
326	subcc %i1, %g0, %i4
327	brnz %i4, test_fail
328	nop
329	*/
330
331	#ifdef FBR
332	check_mcu_esr:
333	mov 0x1, %l1
334	sllx %l1, DRAM_ES_FBR, %l6
335
336	setx DRAM_ERR_STAT_REG, %l3, %g5
337	ldx [%g5], %l1
338
339	setx 0xffffffffffff0000, %l3, %l0
340	andcc %l0, %l1, %l5 ! Donot check L2ESR SYND bits
341
342	sub %l5, %l6, %i4
343	brnz %i4, test_fail
344	nop
345	#endif
346
347	#ifdef ECC
348	check_mcu_esr:
349	mov 0x1, %l1
350	sllx %l1, DRAM_ES_DAC, %l0
351
352	mov 0x1, %l1
353	sllx %l1, DRAM_ES_MEC, %l2
354
355	or %l0, %l2, %l6
356
357	! set 0x2000, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed
358	! or %l0, %l3, %l0 ! %l0 has expected value
359
360	setx DRAM_ERR_STAT_REG, %l3, %g5
361	ldx [%g5], %l1
362
363	setx 0xffffffffffff0000, %l3, %l0
364	andcc %l0, %l1, %l5 ! Donot check L2ESR SYND bits
365
366	sub %l5, %l6, %i4
367	brnz %i4, test_fail
368	nop
369
370	check_L2_ESR_0:
371	setx L2_ERR_STAT_REG, %l3, %g5
372	ldx [%g5], %l6
373
374	setx 0xfffffffff0000000, %l3, %l0
375	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
376
377	mov 0x1, %l1
378	sllx %l1, L2ES_DAC, %l0
379
380	mov 0x1, %l1
381	sllx %l1, L2ES_VEC, %l2
382
383	or %l0, %l2, %i4
384
385	mov 0x1, %l1
386	sllx %l1, L2ES_MEC, %i3
387
388	or %i3, %i4, %i5
389
390	cmp %l5, %i5
391	bne %xcc, test_fail
392	nop
393
394	ch_L2_addr_ch0:
395	setx L2_ERR_ADDR_REG, %l3, %g5
396	ldx [%g5], %l1
397	membar 0x40
398	#endif
399
400	read_fbr_cnt_reg:
401	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
402	ldx [%o2], %g1
403	set 0x10000, %g6 !<16>=countone=1
404	sub %g1, %g6, %i4
405	brnz %i4, test_fail
406	nop
407
408	read_err_cnt_reg:
409	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
410	ldx [%o2], %g1
411	set CMP_ECC_CNT, %i1
412	sub %g1, %i1, %i4
413	brnz %i4, test_fail
414	nop
415
416
417	#ifdef FBR
418	read_fbd_err_synd_reg:
419	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
420	ldx [%o2], %g1
421
422	setx 0x8000000000000000, %l7, %o3
423	set 0x1, %o4
424	sll %o4, FBSYND, %o5
425	or %o3, %o5, %g2
426
427	and %g1, %g2, %g3
428	subcc %g2, %g3, %g4
429	brnz %g4, test_fail
430	nop
431	#endif
432
433	check_error_trap:
434	setx EXECUTED, %l1, %l0
435	cmp %i2, %l0
436	bne test_fail
437	nop
438
439	mov TT, %l0
440	cmp %i0, %l0
441	bne test_fail
442	nop
443
444	!no TT=0x40
445	cmp %i6, %g0
446	bne test_fail
447	nop
448
449	set 0x1, %i1
450	cmp %i7, %i1
451	bne test_fail
452	nop
453
454	/******************************************************
455	* Exit code
456	*******************************************************/
457
458	test_pass:
459	EXIT_GOOD
460
461	test_fail:
462	EXIT_BAD
463
464
465
466
467	/************************************************************************
468	Trap Handlers
469	************************************************************************/
470	My_Recoverable_Sw_error_trap:
471	! Signal trap taken
472	setx EXECUTED, %l0, %i2
473	! save trap type value
474	rdpr %tt, %i0
475
476	inc %i6
477
478	retry
479	nop
480
481	!PER not cleared at the end of the TRAP Handler to avoid further Trap
482	My_Corrected_ECC_error_trap:
483	! Signal trap taken
484	setx EXECUTED, %l0, %i2
485	! save trap type value
486	rdpr %tt, %i0
487
488	inc %i7
489
490	retry
491	nop
492