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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / ncu / n2_err_ncu_all_int.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_ncu_all_int.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define SOC_ERR_STEERING_REG 0x9001041000
46
47#include "err_defines.h"
48#include "hboot.s"
49
50/************************************************************************
51 Test case code start
52 ************************************************************************/
53.text
54.global main
55.global My_Corrected_ECC_error_trap
56.global My_Recoverable_Sw_error_trap
57
58main:
59 ta T_CHANGE_HPRIV
60 nop
61
62
63errorsteer:
64 ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
65 setx SOC_ERR_STEERING_REG, %g7, %g1
66 stx %o4, [%g1]
67 membar 0x40
68
69clear_esr_first:
70 setx SOC_ESR_REG, %l7, %i0
71
72 stx %g0, [%i0]
73
74 setx 43, %i0, %o3
75 clr %g1
76
77set_eie:
78 set 0x1, %i1
79 sllx %i1, %g1, %i2
80 setx SOC_EIE_REG, %l7, %i3
81 stx %i2, [%i3]
82 membar 0x40
83
84set_esr:
85 setx SOC_ESR_REG, %l7, %g5
86 stx %i2, [%g5]
87
88 nop; nop; nop
89 nop; nop; nop
90 nop; nop; nop
91 nop; nop; nop
92 nop; nop; nop
93
94read_esr:
95 setx SOC_ESR_REG, %l7, %g5
96 ldx [%g5], %l3
97 subcc %l3, %g0, %g2
98 brnz %g2, read_esr
99
100 nop; nop; nop
101 nop; nop; nop
102 nop; nop; nop
103 nop; nop; nop
104 nop; nop; nop
105
106 inc %g1
107
108 sub %g1, 24, %l5
109 brz %l5, skip_one
110 nop
111
112 sub %g1, 30, %l5
113 brz %l5, skip_one
114 nop
115
116 sub %g1, 33, %l5
117 brz %l5, skip_one
118 nop
119
120 sub %g1, 36, %l5
121 brz %l5, skip_one
122 nop
123
124 sub %g1, 39, %l5
125 brz %l5, skip_one
126 nop
127
128back_to_loop:
129 sub %o3, %g1, %l6
130 brnz %l6, set_eie
131 nop
132 nop; nop; nop
133
134 ba count_trap_0x40
135 nop
136
137skip_one:
138 inc %g1
139 ba back_to_loop
140 nop
141
142
143count_trap_0x40:
144 set 24, %l1
145 sub %l1, %i6, %l5
146 brnz %l5, test_failed
147 nop
148
149count_trap_0x63:
150 set 14, %l1
151 sub %l1, %i7, %l5
152 brnz %l5, test_failed
153 nop
154
155test_passed:
156 nop
157 EXIT_GOOD
158
159test_failed:
160 EXIT_BAD
161
162
163/************************************************************************
164 Trap Handlers
165 ************************************************************************/
166My_Recoverable_Sw_error_trap:
167 ! Signal trap taken
168 setx EXECUTED, %l0, %o6
169 ! save trap type value
170 rdpr %tt, %o7
171
172 !DESR
173 ldxa [%g0]0x4c, %g2
174 nop
175
176 setx SOC_PER_REG, %i0, %l1
177 stx %g0, [%l1]
178
179 inc %i6
180 retry
181 nop
182
183My_Corrected_ECC_error_trap:
184 ! Signal trap taken
185 setx EXECUTED, %l0, %o6
186 ! save trap type value
187 rdpr %tt, %o7
188
189 !DESR
190 ldxa [%g0]0x4c, %g2
191 nop
192
193 setx SOC_PER_REG, %i0, %l1
194 stx %g0, [%l1]
195 inc %i7
196 retry
197 nop
198
199
200/************************************************************************
201 Test case data start
202 ************************************************************************/
203/* These initialization is temporary, as there looks some bug in mempli */
204
205SECTION SetRngConfig_init data_va=0x100000000
206attr_data {
207 Name = SetRngConfig_init,
208 hypervisor,
209 compressimage
210 }
211.data
212SetRngConfig_init:
213 .xword 0x0060452301000484
214/************************************************************************/
215
216SECTION SetTxRingKick_init data_va=0x100000100
217attr_data {
218 Name = SetTxRingKick_init,
219 hypervisor,
220 compressimage
221 }
222.data
223SetTxRingKick_init:
224 .xword 0x0060452301000484
225/************************************************************************/
226
227SECTION SetTxLPMask1_init data_va=0x100000200
228attr_data {
229 Name = SetTxLPMask1_init,
230 hypervisor,
231 compressimage
232 }
233.data
234SetTxLPMask1_init:
235 .xword 0x0060452301000484
236/************************************************************************/
237
238SECTION SetTxLPValue1_init data_va=0x100000300
239attr_data {
240 Name = SetTxLPValue1_init,
241 hypervisor,
242 compressimage
243 }
244.data
245SetTxLPValue1_init:
246 .xword 0x0060452301000484
247/************************************************************************/
248
249SECTION SetTxLPRELOC1_init data_va=0x100000400
250attr_data {
251 Name = SetTxLPRELOC1_init,
252 hypervisor,
253 compressimage
254 }
255.data
256SetTxLPRELOC1_init:
257 .xword 0x0060452301000484
258/************************************************************************/
259SECTION SetTxLPMask2_init data_va=0x100000500
260attr_data {
261 Name = SetTxLPMask2_init,
262 hypervisor,
263 compressimage
264 }
265.data
266SetTxLPMask2_init:
267 .xword 0x0060452301000484
268/************************************************************************/
269SECTION SetTxLPValue2_init data_va=0x100000600
270attr_data {
271 Name = SetTxLPValue2_init,
272 hypervisor,
273 compressimage
274 }
275.data
276SetTxLPValue2_init:
277 .xword 0x0060452301000484
278
279/************************************************************************/
280SECTION SetTxLPRELOC2_init data_va=0x100000700
281attr_data {
282 Name = SetTxLPRELOC2_init,
283 hypervisor,
284 compressimage
285 }
286.data
287SetTxLPRELOC2_init:
288 .xword 0x0060452301000484
289
290/************************************************************************/
291SECTION SetTxLPValid_init data_va=0x100000800
292attr_data {
293 Name = SetTxLPValid_init,
294 hypervisor,
295 compressimage
296 }
297.data
298SetTxLPValid_init:
299 .xword 0x0060452301000484
300
301/************************************************************************/
302
303
Full OpenSPARC design & verification tarball including full HDL.