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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / siu / n2_err_siu_niu_tx_trap.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_siu_niu_tx_trap.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
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31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40#define NIU_TX_PKT_CNT 0x2
41
42
43/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
44#define MAIN_PAGE_HV_ALSO
45
46#include "err_defines.h"
47#include "hboot.s"
48#include "niu_defines.h"
49
50/************************************************************************
51 Test case code start
52 ************************************************************************/
53.text
54.global main
55.global My_Corrected_ECC_error_trap
56.global My_Recoverable_Sw_error_trap
57
58main:
59 ta T_CHANGE_HPRIV
60 nop
61
62! #include "niu_init.h"
63!
64! Thread 0 Start
65!
66!
67! thread_0:
68
69Init_flow:
70 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
71
72P_TxDMAActivate:
73 setx MAC_ID, %g1, %o0 ! 1st Parameter
74 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
75 call SetTxDMAActive
76 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
77
78P_AddTxChannels :
79 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
80
81 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
82 nop
83
84P_SetTxMaxBurst :
85 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
86 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
87 call SetTxMaxBurst
88 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
89
90 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
91 nop
92
93P_InitTxDma:
94 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
95 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
96 call InitTxDma
97 nop
98
99 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
100 nop
101
102
103 /************************************
104 RAS
105 *************************************/
106clear_esr_first:
107 setx SOC_ESR_REG, %l7, %i0
108 stx %g0, [%i0]
109
110set_ejr:
111 set 0x1, %i1
112 sllx %i1, ERR_FIELD, %i2
113 setx SOC_EJR_REG, %l7, %i3
114 stx %i2, [%i3]
115 membar 0x40
116
117eie_reg_ones:
118 setx SOC_EIE_REG, %l7, %g5
119 stx %i2, [%g5]
120 membar 0x40
121 /*************************************/
122
123Gen_Packet:
124 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
125 nop
126
127 setx 0x5, %g1, %g4
128delay_loop_tmp:
129 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
130 nop
131 nop
132 nop
133 nop
134 dec %g4
135 brnz %g4, delay_loop_tmp
136 nop
137
138
139SetTxRingKick:
140 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
141 setx NIU_TxDmaNo, %g1, %o0
142 ldx [%g2] , %g3
143 nop
144 mulx %o0, 0x200, %g5
145 setx TX_RING_KICK_Addr, %g1, %g2
146 add %g2, %g5, %g2
147 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
148 nop
149
150SetTxCs :
151 setx NIU_TxDmaNo, %g1, %o0
152 setx TX_CS_Data, %g1, %g3
153 mulx %o0, 0x200, %g5
154 setx TX_CS_Addr, %g1, %g2
155 add %g2, %g5, %g2
156 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
157 nop
158
159
160 /* Extra Delay for Jumbo packets to go out */
161 setx LDGIMGN, %g1, %g2
162
163 setx loop_count, %g1, %g4
164delay_loop:
165 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
166 nop
167 nop
168 nop
169 nop
170 dec %g4
171 brnz %g4, delay_loop
172 nop
173
174
175 setx 0x30, %g1, %g4
176delay_ras:
177 setx 0x2000000, %g1, %g2
178 ldx [%g2], %g3
179 nop
180 nop
181 dec %g4
182 brnz %g4, delay_ras
183 nop
184
185 /************************************
186 RAS
187 *************************************/
188 ! ESR is cleared in INT
189 !but dont expect it to be zero; as a follow up
190 ! transaction can again set it
191read_esr:
192 setx SOC_ESR_REG, %l7, %i0
193 ldx [%i0], %i1
194
195
196 ! Check if a Corrected ECC Trap happened
197check_error_trap:
198 setx EXECUTED, %l1, %l0
199 cmp %o6, %l0
200 bne test_fail
201 nop
202 mov TT, %l0
203 cmp %o7, %l0
204 bne test_fail
205 nop
206 /*************************************/
207
208
209
210test_passed:
211/*
212#ifdef CE
213 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
214#endif
215*/
216
217 EXIT_GOOD
218
219!.global test_failed
220!test_failed:
221! EXIT_BAD
222
223test_fail:
224 EXIT_BAD
225 nop
226/************************************************************************
227 RAS
228 Trap Handlers
229 ************************************************************************/
230My_Recoverable_Sw_error_trap:
231 ! Signal trap taken
232 setx EXECUTED, %l0, %o6
233 ! save trap type value
234 rdpr %tt, %o7
235
236check_desr_tt40:
237 ldxa [%g0]0x4c, %g2
238 nop
239 setx 0xb300000000000000, %l0, %g3
240 subcc %g2, %g3, %g4
241 brnz %g4, test_fail
242 nop
243
244check_per_tt40:
245 setx SOC_PER_REG, %l7, %i0
246 ldx [%i0], %i1
247 setx 0x8000000000000000, %l7, %o3 !valid bit
248 set 0x1, %i2
249 sllx %i2, ERR_FIELD, %i3
250 or %i3, %o3, %i4
251 sub %i1, %i4, %i5
252 brnz %i5, test_fail
253 nop
254
255clear_per_tt40:
256 setx SOC_PER_REG, %l7, %i0
257 stx %g0, [%i0]
258 nop
259 done
260 nop
261
262My_Corrected_ECC_error_trap:
263 ! Signal trap taken
264 setx EXECUTED, %l0, %o6
265 ! save trap type value
266 rdpr %tt, %o7
267
268check_desr_tt63:
269 ldxa [%g0]0x4c, %g2
270 nop
271 setx 0x8b00000000000000, %l0, %g3
272 subcc %g2, %g3, %g4
273 brnz %g4, test_fail
274
275check_per_tt63:
276 setx SOC_PER_REG, %l7, %i0
277 ldx [%i0], %i1
278 setx 0x8000000000000000, %l7, %o3 !valid bit
279 set 0x1, %i2
280 sllx %i2, ERR_FIELD, %i3
281 or %i3, %o3, %i4
282 sub %i1, %i4, %i5
283 brnz %i5, test_fail
284 nop
285
286clear_per_tt63:
287 setx SOC_PER_REG, %l7, %i0
288 stx %g0, [%i0]
289 nop
290 retry
291 nop
292
293
294/************************************************************************
295 Test case data start
296 ************************************************************************/
297/* These initialization is temporary, as there looks some bug in mempli */
298
299SECTION SetRngConfig_init data_va=0x100000000
300attr_data {
301 Name = SetRngConfig_init,
302 hypervisor,
303 compressimage
304 }
305.data
306SetRngConfig_init:
307 .xword 0x0060452301000484
308/************************************************************************/
309
310SECTION SetTxRingKick_init data_va=0x100000100
311attr_data {
312 Name = SetTxRingKick_init,
313 hypervisor,
314 compressimage
315 }
316.data
317SetTxRingKick_init:
318 .xword 0x0060452301000484
319/************************************************************************/
320
321SECTION SetTxLPMask1_init data_va=0x100000200
322attr_data {
323 Name = SetTxLPMask1_init,
324 hypervisor,
325 compressimage
326 }
327.data
328SetTxLPMask1_init:
329 .xword 0x0060452301000484
330/************************************************************************/
331
332SECTION SetTxLPValue1_init data_va=0x100000300
333attr_data {
334 Name = SetTxLPValue1_init,
335 hypervisor,
336 compressimage
337 }
338.data
339SetTxLPValue1_init:
340 .xword 0x0060452301000484
341/************************************************************************/
342
343SECTION SetTxLPRELOC1_init data_va=0x100000400
344attr_data {
345 Name = SetTxLPRELOC1_init,
346 hypervisor,
347 compressimage
348 }
349.data
350SetTxLPRELOC1_init:
351 .xword 0x0060452301000484
352/************************************************************************/
353SECTION SetTxLPMask2_init data_va=0x100000500
354attr_data {
355 Name = SetTxLPMask2_init,
356 hypervisor,
357 compressimage
358 }
359.data
360SetTxLPMask2_init:
361 .xword 0x0060452301000484
362/************************************************************************/
363SECTION SetTxLPValue2_init data_va=0x100000600
364attr_data {
365 Name = SetTxLPValue2_init,
366 hypervisor,
367 compressimage
368 }
369.data
370SetTxLPValue2_init:
371 .xword 0x0060452301000484
372
373/************************************************************************/
374SECTION SetTxLPRELOC2_init data_va=0x100000700
375attr_data {
376 Name = SetTxLPRELOC2_init,
377 hypervisor,
378 compressimage
379 }
380.data
381SetTxLPRELOC2_init:
382 .xword 0x0060452301000484
383
384/************************************************************************/
385SECTION SetTxLPValid_init data_va=0x100000800
386attr_data {
387 Name = SetTxLPValid_init,
388 hypervisor,
389 compressimage
390 }
391.data
392SetTxLPValid_init:
393 .xword 0x0060452301000484
394
395/************************************************************************/
396
Full OpenSPARC design & verification tarball including full HDL.