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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_ras_vec_l2_lvc_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | ||
41 | #define MAIN_PAGE_HV_ALSO | |
42 | ||
43 | #define L2_ENTRY_PA 0x517590000 | |
44 | #define TEST_DATA 0x555555555555555 | |
45 | #define L2_ES_W1C_VALUE 0xc03ffffc00000000 | |
46 | #define L2ES_LVC 34 | |
47 | ||
48 | ||
49 | #define L2_ESR_MASK 0xf03ffffff0000000 | |
50 | #define L2_VEC 36 | |
51 | #define L2_LDWC 51 | |
52 | #define L2_LDAC 53 | |
53 | #define L2_LVC 34 | |
54 | ||
55 | #include "hboot.s" | |
56 | #include "asi_s.h" | |
57 | #include "err_defines.h" | |
58 | ||
59 | .text | |
60 | .global main | |
61 | .global My_Corrected_ECC_error_trap | |
62 | ||
63 | ||
64 | main: | |
65 | ||
66 | ||
67 | ! Boot code does not provide TLB translation for IO address space | |
68 | ta T_CHANGE_HPRIV | |
69 | clr %i2 | |
70 | ||
71 | ||
72 | ! Now access L2 control and status registers | |
73 | disable_l1: | |
74 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
75 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
76 | andn %l0, 0x3, %l0 | |
77 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
78 | membar 0x40 | |
79 | ||
80 | ||
81 | ! Not in Direct map | |
82 | set_L2_errorsteer: | |
83 | setx L2CS_PA0, %l6, %g1 | |
84 | ldx [%g1], %o6 | |
85 | ||
86 | ! mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode | |
87 | ||
88 | ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable | |
89 | sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER | |
90 | ||
91 | ! or %o5, %o4, %o5 | |
92 | ||
93 | or %o6, %o4, %o6 | |
94 | ||
95 | stx %o6, [%g1] | |
96 | membar 0x40 | |
97 | ||
98 | ||
99 | enable_err_reporting: | |
100 | setx L2EE_PA0, %l0, %l1 | |
101 | ldx [%l1], %l2 | |
102 | mov 0x3, %l0 | |
103 | or %l2, %l0, %l2 | |
104 | stx %l2, [%l1] | |
105 | ||
106 | ||
107 | st_data: | |
108 | setx 0x44400000, %l0, %g1 | |
109 | setx 0x3ffc0, %l0, %g2 ! Mask for extracting [17:6] | |
110 | clr %i3 | |
111 | ||
112 | err_inj_loop: | |
113 | setx 0x5555555555555555, %g7, %g4 | |
114 | stx %g4, [%g1] | |
115 | !to confirm fill done | |
116 | ld [%g1], %l1 | |
117 | ||
118 | ! Generate L2 VD Diag read address | |
119 | ! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [8:6] bank, [2:0] = 0 | |
120 | ||
121 | and %g1, %g2, %g5 | |
122 | ||
123 | mov 0xb6, %g4 | |
124 | sllx %g4, 32, %g6 ! Bits [39:32] | |
125 | or %g5, %g6, %g7 | |
126 | ||
127 | mov UA_VD, %g4 | |
128 | sllx %g4, 22, %g5 ! Bit [22] | |
129 | or %g7, %g5, %g6 | |
130 | ||
131 | ldx [%g6], %g4 | |
132 | ||
133 | mov 0x1, %g5 | |
134 | sllx %g5, %i3, %g7 ! %i3=1,2,3,....16 | |
135 | ||
136 | xor %g4, %g7, %g5 ! inject single bit error | |
137 | ||
138 | inject_err: | |
139 | stx %g5,[%g6] | |
140 | ||
141 | ld_st_2: | |
142 | setx 0xaaaaaaaa, %g4, %g5 | |
143 | sllx %i3, 24, %g6 ! %i3=1,2,3,....16 | |
144 | ! to have different tag; same index | |
145 | ! to cause L2 miss | |
146 | or %g1, %g6, %g3 ! %g1 had the PA | |
147 | ldx [%g3], %o5 | |
148 | stx %g5, [%g3] | |
149 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
150 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
151 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
152 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
153 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
154 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
155 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
156 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
157 | ||
158 | ! wait for the trap | |
159 | set 0x100, %l1 | |
160 | loop: | |
161 | nop | |
162 | nop | |
163 | dec %l1 | |
164 | cmp %l1, %g0 | |
165 | be test_failed | |
166 | nop | |
167 | ||
168 | add %i3, 0x1, %g6 | |
169 | cmp %i2, %g6 | |
170 | bne %xcc, loop | |
171 | nop | |
172 | nop | |
173 | nop | |
174 | ||
175 | ||
176 | set 0x200, %g4 | |
177 | add %g1, %g4, %g1 ! to go to the next Set; <17:9> | |
178 | ||
179 | inc %i3 | |
180 | set INJ_LOOP, %l2 | |
181 | cmp %i3, %l2 | |
182 | bne %xcc, err_inj_loop | |
183 | nop | |
184 | nop | |
185 | nop | |
186 | ||
187 | check_err_trap_taken: | |
188 | cmp %i2, INJ_LOOP | |
189 | bne test_failed | |
190 | nop | |
191 | ||
192 | ||
193 | /******************************************************* | |
194 | * Exit code | |
195 | *******************************************************/ | |
196 | ||
197 | test_passed: | |
198 | ta T_GOOD_TRAP | |
199 | ||
200 | test_failed: | |
201 | ta T_BAD_TRAP | |
202 | ||
203 | ||
204 | My_Corrected_ECC_error_trap: | |
205 | inc %i2 | |
206 | ||
207 | l2_esr_ch_63: | |
208 | setx L2ES_PA0, %g7, %g2 | |
209 | ldx [%g2], %g1 | |
210 | setx L2_ESR_MASK, %g7, %g3 | |
211 | and %g1, %g3, %g5 | |
212 | ||
213 | mov 0x1, %g6 | |
214 | sllx %g6, L2_VEC, %g2 | |
215 | sllx %g6, L2_LVC, %g3 | |
216 | or %g2, %g3, %g4 | |
217 | ||
218 | cmp %g4, %g5 | |
219 | bne %xcc, test_failed | |
220 | nop | |
221 | ||
222 | synd_chk: | |
223 | setx LVC_MASK_ZERO, %g7, %g2 | |
224 | and %g1, %g2, %g2 ! %g1 has esr value | |
225 | cmp %g2, %g0 ! makes sure <27:14>, <6:0> are 0 for VD | |
226 | ! makes sure <27:14>, <13:7> are 0 for UA | |
227 | bne test_failed | |
228 | nop | |
229 | ||
230 | setx LVC_MASK_NONZERO, %g7, %g2 | |
231 | and %g1, %g2, %g2 ! %g1 has esr value | |
232 | cmp %g2, %g0 ! makes sure <13:7> nonzero for VD | |
233 | ! makes sure <6:0> nonzero for UA | |
234 | be %xcc, test_failed | |
235 | nop | |
236 | ||
237 | ||
238 | clear_l2esr: | |
239 | setx 0xc03ffffc00000000, %g7, %g2 | |
240 | setx L2ES_PA0, %g7, %g3 | |
241 | stx %g2, [%g3] | |
242 | ||
243 | load_DESR_L2C: | |
244 | ldxa [%g0] 0x4c, %g1 | |
245 | setx 0xff00000000000000, %g7, %g2 | |
246 | and %g1, %g2, %g3 | |
247 | setx 0x8900000000000000, %g7, %g4 | |
248 | cmp %g3, %g4 | |
249 | bne %xcc, test_failed | |
250 | nop | |
251 | ||
252 | retry | |
253 | nop | |
254 | ||
255 |