[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_siu_dmu_wr_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_siu_dmu_wr_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define SOC_ERR_STEERING_REG	0x9001041000
    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop


errorsteer:
	ldxa	[%g0]ASI_INTR_ID, %o4			! get the thread id; for core-portable
	setx	SOC_ERR_STEERING_REG, %g7, %g1
	stx	%o4, [%g1]
	membar	0x40

	/*********************************
		RAS
	*********************************/
set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

eie_reg_ones:
        setx    SOC_EIE_REG, %l7, %g5
        stx     %i2, [%g5]
        membar  0x40

	/********************************/

        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

XmtUsrEvnt1: nop;
        ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

	
        ! select a CSR in the PIU and transmit the command to NCU

        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
        setx    0x020, %g1, %g4

delay_loop:
        ldx     [%g2], %g5
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop
        nop

        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
        nop

        /*********************************
                RAS
        *********************************/
        ! ESR is cleared in INT
        ! but the next error causes it to log again;
        ! Get from Uday a diag which has just 1 DMA

/*
check_esr:
        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
!        sub     %i1, %g0, %i5
!        brnz    %i5, test_failed
!        nop

        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop
*/


  ! Check if a Corrected ECC Trap happened
check_error_trap:
        setx  EXECUTED, %l1, %l0
        cmp   %o6, %l0
        bne   test_failed
        nop
        mov   TT, %l0
        cmp   %o7, %l0
        bne   test_failed
        nop

        /********************************/

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

check_desr_tt40:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
	nop

check_per_tt40:
        setx    SOC_PER_REG, %l7, %i0
        ldx     [%i0], %i1
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %i0
        stx     %g0, [%i0]
        nop
       	done 
        nop


My_Corrected_ECC_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

check_desr_tt63:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0x8b00000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 

check_per_tt63:
        setx    SOC_PER_REG, %l7, %i0
        ldx     [%i0], %i1
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

clear_per_tt63:
        setx    SOC_PER_REG, %l7, %i0
        stx     %g0, [%i0]
        nop
        done
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_siu_dmu_wr_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "err_defines.h"
	46	#include "hboot.s"
	47	#include "peu_defines.h"
	48
	49	#define DMA_DATA_ADDR 0x0000000123456700
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53
	54	#define SOC_ERR_STEERING_REG 0x9001041000
	55
	56	/************************************************************************
	57	Test case code start
	58	************************************************************************/
	59	.text
	60	.global main
	61	.global My_Corrected_ECC_error_trap
	62	.global My_Recoverable_Sw_error_trap
	63
	64	main:
65	ta T_CHANGE_HPRIV
66	nop
67
68
69
70	errorsteer:
71	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
72	setx SOC_ERR_STEERING_REG, %g7, %g1
73	stx %o4, [%g1]
74	membar 0x40
75
76	/*********************************
77	RAS
78	*********************************/
79	set_ejr:
80	set 0x1, %i1
81	sllx %i1, ERR_FIELD, %i2
82	setx SOC_EJR_REG, %l7, %i3
83	stx %i2, [%i3]
84	membar 0x40
85
86	eie_reg_ones:
87	setx SOC_EIE_REG, %l7, %g5
88	stx %i2, [%g5]
89	membar 0x40
90
91	/********************************/
92
93	! enable bypass in IOMMU
94	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
95	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
96	stx %g3, [%g2]
97	ldx [%g2], %g3
98
99	XmtUsrEvnt1: nop;
100	! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
101	ldx [%g2], %g3
102	ldx [%g2], %g3
103	ldx [%g2], %g3
104	ldx [%g2], %g3
105
106
107	! select a CSR in the PIU and transmit the command to NCU
108
109	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
110	setx 0x020, %g1, %g4
111
112	delay_loop:
113	ldx [%g2], %g5
114	nop
115	nop
116	nop
117	nop
118	dec %g4
119	brnz %g4, delay_loop
120	nop
121
122	setx SOC_ESR_REG, %l7, %i0
123	ldx [%i0], %i1
124	nop
125
126	/*********************************
127	RAS
128	*********************************/
129	! ESR is cleared in INT
130	! but the next error causes it to log again;
131	! Get from Uday a diag which has just 1 DMA
132
133	/*
134	check_esr:
135	setx SOC_ESR_REG, %l7, %i0
136	ldx [%i0], %i1
137	! sub %i1, %g0, %i5
138	! brnz %i5, test_failed
139	! nop
140
141	setx 0x8000000000000000, %l7, %o3 !valid bit
142	set 0x1, %i2
143	sllx %i2, ERR_FIELD, %i3
144	or %i3, %o3, %i4
145	sub %i1, %i4, %i5
146	brnz %i5, test_failed
147	nop
148	*/
149
150
151	! Check if a Corrected ECC Trap happened
152	check_error_trap:
153	setx EXECUTED, %l1, %l0
154	cmp %o6, %l0
155	bne test_failed
156	nop
157	mov TT, %l0
158	cmp %o7, %l0
159	bne test_failed
160	nop
161
162	/********************************/
163
164
165	test_passed:
166	EXIT_GOOD
167
168	test_failed:
169	EXIT_BAD
170
171
172	/************************************************************************
173	RAS
174	Trap Handlers
175	************************************************************************/
176	My_Recoverable_Sw_error_trap:
177	! Signal trap taken
178	setx EXECUTED, %l0, %o6
179	! save trap type value
180	rdpr %tt, %o7
181
182	check_desr_tt40:
183	ldxa [%g0]0x4c, %g2
184	nop
185	setx 0xb300000000000000, %l0, %g3
186	subcc %g2, %g3, %g4
187	brnz %g4, test_failed
188	nop
189
190	check_per_tt40:
191	setx SOC_PER_REG, %l7, %i0
192	ldx [%i0], %i1
193	setx 0x8000000000000000, %l7, %o3 !valid bit
194	set 0x1, %i2
195	sllx %i2, ERR_FIELD, %i3
196	or %i3, %o3, %i4
197	sub %i1, %i4, %i5
198	brnz %i5, test_failed
199	nop
200
201	clear_per_tt40:
202	setx SOC_PER_REG, %l7, %i0
203	stx %g0, [%i0]
204	nop
205	done
206	nop
207
208
209
210	My_Corrected_ECC_error_trap:
211	! Signal trap taken
212	setx EXECUTED, %l0, %o6
213	! save trap type value
214	rdpr %tt, %o7
215
216	check_desr_tt63:
217	ldxa [%g0]0x4c, %g2
218	nop
219	setx 0x8b00000000000000, %l0, %g3
220	subcc %g2, %g3, %g4
221	brnz %g4, test_failed
222
223	check_per_tt63:
224	setx SOC_PER_REG, %l7, %i0
225	ldx [%i0], %i1
226	setx 0x8000000000000000, %l7, %o3 !valid bit
227	set 0x1, %i2
228	sllx %i2, ERR_FIELD, %i3
229	or %i3, %o3, %i4
230	sub %i1, %i4, %i5
231	brnz %i5, test_failed
232	nop
233
234	clear_per_tt63:
235	setx SOC_PER_REG, %l7, %i0
236	stx %g0, [%i0]
237	nop
238	done
239	nop
240
241
242	/************************************************************************
243	Test case data start
244	************************************************************************/
245
246	SECTION .DATA DATA_VA=DMA_DATA_ADDR
247	attr_data {
248	Name = .DATA,
249	hypervisor,
250	compressimage
251	}
252
253	.data
254	.global PCIAddr9
255	.xword 0x0001020304050607
256	.xword 0x08090a0b0c0d0e0f
257	.xword 0x1011121314151617
258	.xword 0x18191a1b1c1d1e1f
259	.xword 0x2021222324252627
260	.xword 0x28292a2b2c2d2e2f
261	.xword 0x3031323334353637
262	.xword 0x38393a3b3c3d3e3f
263
264	.xword 0x4041424344454647
265	.xword 0x48494a4b4c4d4e4f
266	.xword 0x5051525354555657
267	.xword 0x58595a5b5c5d5e5f
268	.xword 0x6061626364656667
269	.xword 0x68696a6b6c6d6e6f
270	.xword 0x7071727374757677
271	.xword 0x78797a7b7c7d7e7f
272
273	.xword 0x8081828384858687
274	.xword 0x88898a8b8c8d8e8f
275	.xword 0x9091929394959697
276	.xword 0x98999a9b9c9d9e9f
277	.xword 0xa0a1a2a3a4a5a6a7
278	.xword 0xa8a9aaabacadaeaf
279	.xword 0xb0b1b2b3b4b5b6b7
280	.xword 0xb8b9babbbcbdbebf
281
282	.xword 0xc0c1c2c3c4c5c6c7
283	.xword 0xc8c9cacbcccdcecf
284	.xword 0xd0d1d2d3d4d5d6d7
285	.xword 0xd8d9dadbdcdddedf
286	.xword 0xe0e1e2e3e4e5e6e7
287	.xword 0xe8e9eaebecedeeef
288	.xword 0xf0f1f2f3f4f5f6f7
289	.xword 0xf8f9fafbfcfdfeff
290
291	.xword 0x0001020304050607
292	.xword 0x08090a0b0c0d0e0f
293	.xword 0x1011121314151617
294	.xword 0x18191a1b1c1d1e1f
295	.xword 0x2021222324252627
296	.xword 0x28292a2b2c2d2e2f
297	.xword 0x3031323334353637
298	.xword 0x38393a3b3c3d3e3f
299
300	.xword 0x4041424344454647
301	.xword 0x48494a4b4c4d4e4f
302	.xword 0x5051525354555657
303	.xword 0x58595a5b5c5d5e5f
304	.xword 0x6061626364656667
305	.xword 0x68696a6b6c6d6e6f
306	.xword 0x7071727374757677
307	.xword 0x78797a7b7c7d7e7f
308
309	.xword 0x8081828384858687
310	.xword 0x88898a8b8c8d8e8f
311	.xword 0x9091929394959697
312	.xword 0x98999a9b9c9d9e9f
313	.xword 0xa0a1a2a3a4a5a6a7
314	.xword 0xa8a9aaabacadaeaf
315	.xword 0xb0b1b2b3b4b5b6b7
316	.xword 0xb8b9babbbcbdbebf
317
318	.xword 0xc0c1c2c3c4c5c6c7
319	.xword 0xc8c9cacbcccdcecf
320	.xword 0xd0d1d2d3d4d5d6d7
321	.xword 0xd8d9dadbdcdddedf
322	.xword 0xe0e1e2e3e4e5e6e7
323	.xword 0xe8e9eaebecedeeef
324	.xword 0xf0f1f2f3f4f5f6f7
325	.xword 0xf8f9fafbfcfdfeff
326
327	/************************************************************************/
328