[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / cmp / cmp_master_park_unpark_all_rw.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: cmp_master_park_unpark_all_rw.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "ncu_defines.h"


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

	/* Get thread ID */

        ta      T_RD_THID
	nop
	cmp	%o1, 0
	be	main_t0			! branch if thread 0
	nop

	ba	main_t1_t63		! branch if not thread 0
	nop

/************************************************************************
   Thread 0 Code
 ************************************************************************/

	/* Park all the other threads one by one. */
main_t0:
#ifndef PORTABLE_CORE
	setx	ASI_CMP_CORE_RUNNING_RW, %g1, %g2
	orn	%g0, %g0, %g1
	set	0x2, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 1
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 2
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 3
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 4
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 5
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 6
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 7
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 8
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 9
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 10
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 11
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 12
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 13
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 14
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 15
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 16
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 17
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 18
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 19
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 20
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 21
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 22
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 23
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 24
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 25
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 26
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 27
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 28
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 29
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 30
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 31
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 32
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 33
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 34
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 35
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 36
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 37
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 38
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 39
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 40
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 41
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 42
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 43
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 44
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 45
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 46
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 47
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 48
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 49
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 50
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 51
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 52
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 53
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 54
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 55
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 56
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 57
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 58
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 59
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 60
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 61
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 62
	sllx	%g3, 1, %g3
	xor	%g1, %g3, %g1
	stxa    %g1, [%g2]ASI_CMP_CORE		! thread 63
#else
	/* First get complete thr ID, then bit in CMP_CORE_RUNNING_RW */

	ldxa    [%g0]ASI_INTR_ID, %o2
	set	0xff, %g7
	set	1, %g3
	sllx	%g7, %o2, %g7			! %g7 threads in this core
	sllx	%g3, %o2, %g3
	sllx	%g3, 1, %g3			! %g3 thread to park

	/* Park all the other threads in this core. */
t0_core_portable_1:
	setx	ASI_CMP_CORE_RUNNING_RW, %g1, %g2
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 1 of this core
	sllx	%g3, 1, %g3
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 2 of this core
	sllx	%g3, 1, %g3
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 3 of this core
	sllx	%g3, 1, %g3
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 4 of this core
	sllx	%g3, 1, %g3
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 5 of this core
	sllx	%g3, 1, %g3
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 6 of this core
	sllx	%g3, 1, %g3
	xor	%g7, %g3, %g7
	stxa    %g7, [%g2]ASI_CMP_CORE		! thread 7 of this core
#endif

	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
t0_0:
        setx    ASI_CMP_CORE_RUNNING_RW, %g1, %g2
        setx    ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
	set	0x100, %g7
#ifdef	PORTABLE_CORE
	set	1, %o3
	sllx	%o3, %o2, %o3		! %o3 = this thread in CORE_RUNNING_RW
#endif

t0_loop_1_top:
	cmp	%g7, 0
	beq	local_test_failed		! fail on a timeout
	dec	%g7

	ldxa	[%g3]ASI_CMP_CORE, %g4		! CORE_RUNNING_STATUS
#ifndef	PORTABLE_CORE
	cmp	%g4, 1
#else
	cmp	%g4, %o3
#endif
	bne	t0_loop_1_top
	nop

t0_1:
	ldxa	[%g2]ASI_CMP_CORE, %g5		! CORE_RUNNING_RW
	cmp	%g4, %g5
	bne	local_test_failed		! fail on RW != STATUS
	nop

	/* Now unpark all the other threads one by one. */
t0_2:
#ifndef PORTABLE_CORE
	setx	ASI_CMP_CORE_RUNNING_RW, %g1, %g2
	set	1, %g1
	set	2, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 1
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 2
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 3
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 4
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 5
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 6
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 7
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 8
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 9
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 10
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 11
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 12
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 13
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 14
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 15
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 16
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 17
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 18
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 19
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 20
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 21
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 22
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 23
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 24
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 25
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 26
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 27
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 28
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 29
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 30
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 31
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 32
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 33
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 34
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 35
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 36
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 37
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 38
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 39
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 40
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 41
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 42
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 43
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 44
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 45
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 46
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 47
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 48
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 49
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 50
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 51
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 52
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 53
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 54
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 55
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 56
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 57
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 58
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 59
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 60
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 61
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 62
	sllx	%g3, 1, %g3
	or	%g1, %g3, %g1
	stxa	%g1, [%g2]ASI_CMP_CORE		! thread 63
#else
	/* Now unpark other threads in this core. */

	setx	ASI_CMP_CORE_RUNNING_RW, %g1, %g2
	set	1, %g7
	sllx	%g7, %o2, %g7			! %g7 this thread
	sllx	%g7, 1, %g6			! %g6 next thread to unpark
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 1
	sllx	%g6, 1, %g6
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 2
	sllx	%g6, 1, %g6
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 3
	sllx	%g6, 1, %g6
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 4
	sllx	%g6, 1, %g6
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 5
	sllx	%g6, 1, %g6
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 6
	sllx	%g6, 1, %g6
	or	%g7, %g6, %g7
	stxa	%g7, [%g2]ASI_CMP_CORE		! thread 7
#endif

	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
t0_3:
        setx    ASI_CMP_CORE_RUNNING_RW, %g1, %g2
        setx    ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
	set	0x100, %g7			! timeout value
#ifndef PORTABLE_CORE
	orn	%g0, %g0, %g6
#else
	set	0xff, %g6
	sllx	%g6, %o2, %g6
#endif

t0_loop_2_top:
	cmp	%g7, 0
	beq	local_test_failed		! fail on a timeout
	dec	%g7

	ldxa	[%g3]ASI_CMP_CORE, %g4		! CORE_RUNNING_STATUS
	cmp	%g4, %g6
	bne	t0_loop_2_top
	nop

t0_4:
	ldxa	[%g2]ASI_CMP_CORE, %g5		! CORE_RUNNING_RW
	cmp	%g4, %g5
	bne	local_test_failed		! fail on RW != STATUS
	nop

	/* Signal all the other threads that were done */
t0_5:
	setx	user_data_start, %g1, %g2
	set	1, %g3
	stx	%g3, [%g2]

	/* Done */

	ba	test_passed
	nop

/************************************************************************
   Thread 1 to 63 Code
 ************************************************************************/

	/* Wait till thread 0 says were done */
main_t1_t63:
	setx	0x1000, %g1, %g7
	setx	user_data_start, %g1, %g2

t1_t63_wait_loop_top:
	cmp	%g7, 0
	beq	local_test_failed		! fail on a timeout
	dec	%g7

	ldx	[%g2], %g4
	cmp	%g4, 1
	bne	t1_t63_wait_loop_top
	nop

	/* Done */

	ba	test_passed
	nop


test_passed:
	EXIT_GOOD

local_test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/

.align	1024
.data
user_data_start:
	.word	0x0
	.word	0x0
	.word	0x0
	.word	0x0
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: cmp_master_park_unpark_all_rw.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#include "hboot.s"
	41	#include "ncu_defines.h"
	42
	43
	44
	45	/************************************************************************
	46	Test case code start
	47	************************************************************************/
	48	.text
	49	.global main
	50
	51	main:
	52	ta T_CHANGE_HPRIV
	53	nop
	54
	55	/* Get thread ID */
	56
	57	ta T_RD_THID
	58	nop
	59	cmp %o1, 0
	60	be main_t0 ! branch if thread 0
	61	nop
	62
	63	ba main_t1_t63 ! branch if not thread 0
	64	nop
65
66	/************************************************************************
67	Thread 0 Code
68	************************************************************************/
69
70	/* Park all the other threads one by one. */
71	main_t0:
72	#ifndef PORTABLE_CORE
73	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
74	orn %g0, %g0, %g1
75	set 0x2, %g3
76	xor %g1, %g3, %g1
77	stxa %g1, [%g2]ASI_CMP_CORE ! thread 1
78	sllx %g3, 1, %g3
79	xor %g1, %g3, %g1
80	stxa %g1, [%g2]ASI_CMP_CORE ! thread 2
81	sllx %g3, 1, %g3
82	xor %g1, %g3, %g1
83	stxa %g1, [%g2]ASI_CMP_CORE ! thread 3
84	sllx %g3, 1, %g3
85	xor %g1, %g3, %g1
86	stxa %g1, [%g2]ASI_CMP_CORE ! thread 4
87	sllx %g3, 1, %g3
88	xor %g1, %g3, %g1
89	stxa %g1, [%g2]ASI_CMP_CORE ! thread 5
90	sllx %g3, 1, %g3
91	xor %g1, %g3, %g1
92	stxa %g1, [%g2]ASI_CMP_CORE ! thread 6
93	sllx %g3, 1, %g3
94	xor %g1, %g3, %g1
95	stxa %g1, [%g2]ASI_CMP_CORE ! thread 7
96	sllx %g3, 1, %g3
97	xor %g1, %g3, %g1
98	stxa %g1, [%g2]ASI_CMP_CORE ! thread 8
99	sllx %g3, 1, %g3
100	xor %g1, %g3, %g1
101	stxa %g1, [%g2]ASI_CMP_CORE ! thread 9
102	sllx %g3, 1, %g3
103	xor %g1, %g3, %g1
104	stxa %g1, [%g2]ASI_CMP_CORE ! thread 10
105	sllx %g3, 1, %g3
106	xor %g1, %g3, %g1
107	stxa %g1, [%g2]ASI_CMP_CORE ! thread 11
108	sllx %g3, 1, %g3
109	xor %g1, %g3, %g1
110	stxa %g1, [%g2]ASI_CMP_CORE ! thread 12
111	sllx %g3, 1, %g3
112	xor %g1, %g3, %g1
113	stxa %g1, [%g2]ASI_CMP_CORE ! thread 13
114	sllx %g3, 1, %g3
115	xor %g1, %g3, %g1
116	stxa %g1, [%g2]ASI_CMP_CORE ! thread 14
117	sllx %g3, 1, %g3
118	xor %g1, %g3, %g1
119	stxa %g1, [%g2]ASI_CMP_CORE ! thread 15
120	sllx %g3, 1, %g3
121	xor %g1, %g3, %g1
122	stxa %g1, [%g2]ASI_CMP_CORE ! thread 16
123	sllx %g3, 1, %g3
124	xor %g1, %g3, %g1
125	stxa %g1, [%g2]ASI_CMP_CORE ! thread 17
126	sllx %g3, 1, %g3
127	xor %g1, %g3, %g1
128	stxa %g1, [%g2]ASI_CMP_CORE ! thread 18
129	sllx %g3, 1, %g3
130	xor %g1, %g3, %g1
131	stxa %g1, [%g2]ASI_CMP_CORE ! thread 19
132	sllx %g3, 1, %g3
133	xor %g1, %g3, %g1
134	stxa %g1, [%g2]ASI_CMP_CORE ! thread 20
135	sllx %g3, 1, %g3
136	xor %g1, %g3, %g1
137	stxa %g1, [%g2]ASI_CMP_CORE ! thread 21
138	sllx %g3, 1, %g3
139	xor %g1, %g3, %g1
140	stxa %g1, [%g2]ASI_CMP_CORE ! thread 22
141	sllx %g3, 1, %g3
142	xor %g1, %g3, %g1
143	stxa %g1, [%g2]ASI_CMP_CORE ! thread 23
144	sllx %g3, 1, %g3
145	xor %g1, %g3, %g1
146	stxa %g1, [%g2]ASI_CMP_CORE ! thread 24
147	sllx %g3, 1, %g3
148	xor %g1, %g3, %g1
149	stxa %g1, [%g2]ASI_CMP_CORE ! thread 25
150	sllx %g3, 1, %g3
151	xor %g1, %g3, %g1
152	stxa %g1, [%g2]ASI_CMP_CORE ! thread 26
153	sllx %g3, 1, %g3
154	xor %g1, %g3, %g1
155	stxa %g1, [%g2]ASI_CMP_CORE ! thread 27
156	sllx %g3, 1, %g3
157	xor %g1, %g3, %g1
158	stxa %g1, [%g2]ASI_CMP_CORE ! thread 28
159	sllx %g3, 1, %g3
160	xor %g1, %g3, %g1
161	stxa %g1, [%g2]ASI_CMP_CORE ! thread 29
162	sllx %g3, 1, %g3
163	xor %g1, %g3, %g1
164	stxa %g1, [%g2]ASI_CMP_CORE ! thread 30
165	sllx %g3, 1, %g3
166	xor %g1, %g3, %g1
167	stxa %g1, [%g2]ASI_CMP_CORE ! thread 31
168	sllx %g3, 1, %g3
169	xor %g1, %g3, %g1
170	stxa %g1, [%g2]ASI_CMP_CORE ! thread 32
171	sllx %g3, 1, %g3
172	xor %g1, %g3, %g1
173	stxa %g1, [%g2]ASI_CMP_CORE ! thread 33
174	sllx %g3, 1, %g3
175	xor %g1, %g3, %g1
176	stxa %g1, [%g2]ASI_CMP_CORE ! thread 34
177	sllx %g3, 1, %g3
178	xor %g1, %g3, %g1
179	stxa %g1, [%g2]ASI_CMP_CORE ! thread 35
180	sllx %g3, 1, %g3
181	xor %g1, %g3, %g1
182	stxa %g1, [%g2]ASI_CMP_CORE ! thread 36
183	sllx %g3, 1, %g3
184	xor %g1, %g3, %g1
185	stxa %g1, [%g2]ASI_CMP_CORE ! thread 37
186	sllx %g3, 1, %g3
187	xor %g1, %g3, %g1
188	stxa %g1, [%g2]ASI_CMP_CORE ! thread 38
189	sllx %g3, 1, %g3
190	xor %g1, %g3, %g1
191	stxa %g1, [%g2]ASI_CMP_CORE ! thread 39
192	sllx %g3, 1, %g3
193	xor %g1, %g3, %g1
194	stxa %g1, [%g2]ASI_CMP_CORE ! thread 40
195	sllx %g3, 1, %g3
196	xor %g1, %g3, %g1
197	stxa %g1, [%g2]ASI_CMP_CORE ! thread 41
198	sllx %g3, 1, %g3
199	xor %g1, %g3, %g1
200	stxa %g1, [%g2]ASI_CMP_CORE ! thread 42
201	sllx %g3, 1, %g3
202	xor %g1, %g3, %g1
203	stxa %g1, [%g2]ASI_CMP_CORE ! thread 43
204	sllx %g3, 1, %g3
205	xor %g1, %g3, %g1
206	stxa %g1, [%g2]ASI_CMP_CORE ! thread 44
207	sllx %g3, 1, %g3
208	xor %g1, %g3, %g1
209	stxa %g1, [%g2]ASI_CMP_CORE ! thread 45
210	sllx %g3, 1, %g3
211	xor %g1, %g3, %g1
212	stxa %g1, [%g2]ASI_CMP_CORE ! thread 46
213	sllx %g3, 1, %g3
214	xor %g1, %g3, %g1
215	stxa %g1, [%g2]ASI_CMP_CORE ! thread 47
216	sllx %g3, 1, %g3
217	xor %g1, %g3, %g1
218	stxa %g1, [%g2]ASI_CMP_CORE ! thread 48
219	sllx %g3, 1, %g3
220	xor %g1, %g3, %g1
221	stxa %g1, [%g2]ASI_CMP_CORE ! thread 49
222	sllx %g3, 1, %g3
223	xor %g1, %g3, %g1
224	stxa %g1, [%g2]ASI_CMP_CORE ! thread 50
225	sllx %g3, 1, %g3
226	xor %g1, %g3, %g1
227	stxa %g1, [%g2]ASI_CMP_CORE ! thread 51
228	sllx %g3, 1, %g3
229	xor %g1, %g3, %g1
230	stxa %g1, [%g2]ASI_CMP_CORE ! thread 52
231	sllx %g3, 1, %g3
232	xor %g1, %g3, %g1
233	stxa %g1, [%g2]ASI_CMP_CORE ! thread 53
234	sllx %g3, 1, %g3
235	xor %g1, %g3, %g1
236	stxa %g1, [%g2]ASI_CMP_CORE ! thread 54
237	sllx %g3, 1, %g3
238	xor %g1, %g3, %g1
239	stxa %g1, [%g2]ASI_CMP_CORE ! thread 55
240	sllx %g3, 1, %g3
241	xor %g1, %g3, %g1
242	stxa %g1, [%g2]ASI_CMP_CORE ! thread 56
243	sllx %g3, 1, %g3
244	xor %g1, %g3, %g1
245	stxa %g1, [%g2]ASI_CMP_CORE ! thread 57
246	sllx %g3, 1, %g3
247	xor %g1, %g3, %g1
248	stxa %g1, [%g2]ASI_CMP_CORE ! thread 58
249	sllx %g3, 1, %g3
250	xor %g1, %g3, %g1
251	stxa %g1, [%g2]ASI_CMP_CORE ! thread 59
252	sllx %g3, 1, %g3
253	xor %g1, %g3, %g1
254	stxa %g1, [%g2]ASI_CMP_CORE ! thread 60
255	sllx %g3, 1, %g3
256	xor %g1, %g3, %g1
257	stxa %g1, [%g2]ASI_CMP_CORE ! thread 61
258	sllx %g3, 1, %g3
259	xor %g1, %g3, %g1
260	stxa %g1, [%g2]ASI_CMP_CORE ! thread 62
261	sllx %g3, 1, %g3
262	xor %g1, %g3, %g1
263	stxa %g1, [%g2]ASI_CMP_CORE ! thread 63
264	#else
265	/* First get complete thr ID, then bit in CMP_CORE_RUNNING_RW */
266
267	ldxa [%g0]ASI_INTR_ID, %o2
268	set 0xff, %g7
269	set 1, %g3
270	sllx %g7, %o2, %g7 ! %g7 threads in this core
271	sllx %g3, %o2, %g3
272	sllx %g3, 1, %g3 ! %g3 thread to park
273
274	/* Park all the other threads in this core. */
275	t0_core_portable_1:
276	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
277	xor %g7, %g3, %g7
278	stxa %g7, [%g2]ASI_CMP_CORE ! thread 1 of this core
279	sllx %g3, 1, %g3
280	xor %g7, %g3, %g7
281	stxa %g7, [%g2]ASI_CMP_CORE ! thread 2 of this core
282	sllx %g3, 1, %g3
283	xor %g7, %g3, %g7
284	stxa %g7, [%g2]ASI_CMP_CORE ! thread 3 of this core
285	sllx %g3, 1, %g3
286	xor %g7, %g3, %g7
287	stxa %g7, [%g2]ASI_CMP_CORE ! thread 4 of this core
288	sllx %g3, 1, %g3
289	xor %g7, %g3, %g7
290	stxa %g7, [%g2]ASI_CMP_CORE ! thread 5 of this core
291	sllx %g3, 1, %g3
292	xor %g7, %g3, %g7
293	stxa %g7, [%g2]ASI_CMP_CORE ! thread 6 of this core
294	sllx %g3, 1, %g3
295	xor %g7, %g3, %g7
296	stxa %g7, [%g2]ASI_CMP_CORE ! thread 7 of this core
297	#endif
298
299	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
300	t0_0:
301	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
302	setx ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
303	set 0x100, %g7
304	#ifdef PORTABLE_CORE
305	set 1, %o3
306	sllx %o3, %o2, %o3 ! %o3 = this thread in CORE_RUNNING_RW
307	#endif
308
309	t0_loop_1_top:
310	cmp %g7, 0
311	beq local_test_failed ! fail on a timeout
312	dec %g7
313
314	ldxa [%g3]ASI_CMP_CORE, %g4 ! CORE_RUNNING_STATUS
315	#ifndef PORTABLE_CORE
316	cmp %g4, 1
317	#else
318	cmp %g4, %o3
319	#endif
320	bne t0_loop_1_top
321	nop
322
323	t0_1:
324	ldxa [%g2]ASI_CMP_CORE, %g5 ! CORE_RUNNING_RW
325	cmp %g4, %g5
326	bne local_test_failed ! fail on RW != STATUS
327	nop
328
329	/* Now unpark all the other threads one by one. */
330	t0_2:
331	#ifndef PORTABLE_CORE
332	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
333	set 1, %g1
334	set 2, %g3
335	or %g1, %g3, %g1
336	stxa %g1, [%g2]ASI_CMP_CORE ! thread 1
337	sllx %g3, 1, %g3
338	or %g1, %g3, %g1
339	stxa %g1, [%g2]ASI_CMP_CORE ! thread 2
340	sllx %g3, 1, %g3
341	or %g1, %g3, %g1
342	stxa %g1, [%g2]ASI_CMP_CORE ! thread 3
343	sllx %g3, 1, %g3
344	or %g1, %g3, %g1
345	stxa %g1, [%g2]ASI_CMP_CORE ! thread 4
346	sllx %g3, 1, %g3
347	or %g1, %g3, %g1
348	stxa %g1, [%g2]ASI_CMP_CORE ! thread 5
349	sllx %g3, 1, %g3
350	or %g1, %g3, %g1
351	stxa %g1, [%g2]ASI_CMP_CORE ! thread 6
352	sllx %g3, 1, %g3
353	or %g1, %g3, %g1
354	stxa %g1, [%g2]ASI_CMP_CORE ! thread 7
355	sllx %g3, 1, %g3
356	or %g1, %g3, %g1
357	stxa %g1, [%g2]ASI_CMP_CORE ! thread 8
358	sllx %g3, 1, %g3
359	or %g1, %g3, %g1
360	stxa %g1, [%g2]ASI_CMP_CORE ! thread 9
361	sllx %g3, 1, %g3
362	or %g1, %g3, %g1
363	stxa %g1, [%g2]ASI_CMP_CORE ! thread 10
364	sllx %g3, 1, %g3
365	or %g1, %g3, %g1
366	stxa %g1, [%g2]ASI_CMP_CORE ! thread 11
367	sllx %g3, 1, %g3
368	or %g1, %g3, %g1
369	stxa %g1, [%g2]ASI_CMP_CORE ! thread 12
370	sllx %g3, 1, %g3
371	or %g1, %g3, %g1
372	stxa %g1, [%g2]ASI_CMP_CORE ! thread 13
373	sllx %g3, 1, %g3
374	or %g1, %g3, %g1
375	stxa %g1, [%g2]ASI_CMP_CORE ! thread 14
376	sllx %g3, 1, %g3
377	or %g1, %g3, %g1
378	stxa %g1, [%g2]ASI_CMP_CORE ! thread 15
379	sllx %g3, 1, %g3
380	or %g1, %g3, %g1
381	stxa %g1, [%g2]ASI_CMP_CORE ! thread 16
382	sllx %g3, 1, %g3
383	or %g1, %g3, %g1
384	stxa %g1, [%g2]ASI_CMP_CORE ! thread 17
385	sllx %g3, 1, %g3
386	or %g1, %g3, %g1
387	stxa %g1, [%g2]ASI_CMP_CORE ! thread 18
388	sllx %g3, 1, %g3
389	or %g1, %g3, %g1
390	stxa %g1, [%g2]ASI_CMP_CORE ! thread 19
391	sllx %g3, 1, %g3
392	or %g1, %g3, %g1
393	stxa %g1, [%g2]ASI_CMP_CORE ! thread 20
394	sllx %g3, 1, %g3
395	or %g1, %g3, %g1
396	stxa %g1, [%g2]ASI_CMP_CORE ! thread 21
397	sllx %g3, 1, %g3
398	or %g1, %g3, %g1
399	stxa %g1, [%g2]ASI_CMP_CORE ! thread 22
400	sllx %g3, 1, %g3
401	or %g1, %g3, %g1
402	stxa %g1, [%g2]ASI_CMP_CORE ! thread 23
403	sllx %g3, 1, %g3
404	or %g1, %g3, %g1
405	stxa %g1, [%g2]ASI_CMP_CORE ! thread 24
406	sllx %g3, 1, %g3
407	or %g1, %g3, %g1
408	stxa %g1, [%g2]ASI_CMP_CORE ! thread 25
409	sllx %g3, 1, %g3
410	or %g1, %g3, %g1
411	stxa %g1, [%g2]ASI_CMP_CORE ! thread 26
412	sllx %g3, 1, %g3
413	or %g1, %g3, %g1
414	stxa %g1, [%g2]ASI_CMP_CORE ! thread 27
415	sllx %g3, 1, %g3
416	or %g1, %g3, %g1
417	stxa %g1, [%g2]ASI_CMP_CORE ! thread 28
418	sllx %g3, 1, %g3
419	or %g1, %g3, %g1
420	stxa %g1, [%g2]ASI_CMP_CORE ! thread 29
421	sllx %g3, 1, %g3
422	or %g1, %g3, %g1
423	stxa %g1, [%g2]ASI_CMP_CORE ! thread 30
424	sllx %g3, 1, %g3
425	or %g1, %g3, %g1
426	stxa %g1, [%g2]ASI_CMP_CORE ! thread 31
427	sllx %g3, 1, %g3
428	or %g1, %g3, %g1
429	stxa %g1, [%g2]ASI_CMP_CORE ! thread 32
430	sllx %g3, 1, %g3
431	or %g1, %g3, %g1
432	stxa %g1, [%g2]ASI_CMP_CORE ! thread 33
433	sllx %g3, 1, %g3
434	or %g1, %g3, %g1
435	stxa %g1, [%g2]ASI_CMP_CORE ! thread 34
436	sllx %g3, 1, %g3
437	or %g1, %g3, %g1
438	stxa %g1, [%g2]ASI_CMP_CORE ! thread 35
439	sllx %g3, 1, %g3
440	or %g1, %g3, %g1
441	stxa %g1, [%g2]ASI_CMP_CORE ! thread 36
442	sllx %g3, 1, %g3
443	or %g1, %g3, %g1
444	stxa %g1, [%g2]ASI_CMP_CORE ! thread 37
445	sllx %g3, 1, %g3
446	or %g1, %g3, %g1
447	stxa %g1, [%g2]ASI_CMP_CORE ! thread 38
448	sllx %g3, 1, %g3
449	or %g1, %g3, %g1
450	stxa %g1, [%g2]ASI_CMP_CORE ! thread 39
451	sllx %g3, 1, %g3
452	or %g1, %g3, %g1
453	stxa %g1, [%g2]ASI_CMP_CORE ! thread 40
454	sllx %g3, 1, %g3
455	or %g1, %g3, %g1
456	stxa %g1, [%g2]ASI_CMP_CORE ! thread 41
457	sllx %g3, 1, %g3
458	or %g1, %g3, %g1
459	stxa %g1, [%g2]ASI_CMP_CORE ! thread 42
460	sllx %g3, 1, %g3
461	or %g1, %g3, %g1
462	stxa %g1, [%g2]ASI_CMP_CORE ! thread 43
463	sllx %g3, 1, %g3
464	or %g1, %g3, %g1
465	stxa %g1, [%g2]ASI_CMP_CORE ! thread 44
466	sllx %g3, 1, %g3
467	or %g1, %g3, %g1
468	stxa %g1, [%g2]ASI_CMP_CORE ! thread 45
469	sllx %g3, 1, %g3
470	or %g1, %g3, %g1
471	stxa %g1, [%g2]ASI_CMP_CORE ! thread 46
472	sllx %g3, 1, %g3
473	or %g1, %g3, %g1
474	stxa %g1, [%g2]ASI_CMP_CORE ! thread 47
475	sllx %g3, 1, %g3
476	or %g1, %g3, %g1
477	stxa %g1, [%g2]ASI_CMP_CORE ! thread 48
478	sllx %g3, 1, %g3
479	or %g1, %g3, %g1
480	stxa %g1, [%g2]ASI_CMP_CORE ! thread 49
481	sllx %g3, 1, %g3
482	or %g1, %g3, %g1
483	stxa %g1, [%g2]ASI_CMP_CORE ! thread 50
484	sllx %g3, 1, %g3
485	or %g1, %g3, %g1
486	stxa %g1, [%g2]ASI_CMP_CORE ! thread 51
487	sllx %g3, 1, %g3
488	or %g1, %g3, %g1
489	stxa %g1, [%g2]ASI_CMP_CORE ! thread 52
490	sllx %g3, 1, %g3
491	or %g1, %g3, %g1
492	stxa %g1, [%g2]ASI_CMP_CORE ! thread 53
493	sllx %g3, 1, %g3
494	or %g1, %g3, %g1
495	stxa %g1, [%g2]ASI_CMP_CORE ! thread 54
496	sllx %g3, 1, %g3
497	or %g1, %g3, %g1
498	stxa %g1, [%g2]ASI_CMP_CORE ! thread 55
499	sllx %g3, 1, %g3
500	or %g1, %g3, %g1
501	stxa %g1, [%g2]ASI_CMP_CORE ! thread 56
502	sllx %g3, 1, %g3
503	or %g1, %g3, %g1
504	stxa %g1, [%g2]ASI_CMP_CORE ! thread 57
505	sllx %g3, 1, %g3
506	or %g1, %g3, %g1
507	stxa %g1, [%g2]ASI_CMP_CORE ! thread 58
508	sllx %g3, 1, %g3
509	or %g1, %g3, %g1
510	stxa %g1, [%g2]ASI_CMP_CORE ! thread 59
511	sllx %g3, 1, %g3
512	or %g1, %g3, %g1
513	stxa %g1, [%g2]ASI_CMP_CORE ! thread 60
514	sllx %g3, 1, %g3
515	or %g1, %g3, %g1
516	stxa %g1, [%g2]ASI_CMP_CORE ! thread 61
517	sllx %g3, 1, %g3
518	or %g1, %g3, %g1
519	stxa %g1, [%g2]ASI_CMP_CORE ! thread 62
520	sllx %g3, 1, %g3
521	or %g1, %g3, %g1
522	stxa %g1, [%g2]ASI_CMP_CORE ! thread 63
523	#else
524	/* Now unpark other threads in this core. */
525
526	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
527	set 1, %g7
528	sllx %g7, %o2, %g7 ! %g7 this thread
529	sllx %g7, 1, %g6 ! %g6 next thread to unpark
530	or %g7, %g6, %g7
531	stxa %g7, [%g2]ASI_CMP_CORE ! thread 1
532	sllx %g6, 1, %g6
533	or %g7, %g6, %g7
534	stxa %g7, [%g2]ASI_CMP_CORE ! thread 2
535	sllx %g6, 1, %g6
536	or %g7, %g6, %g7
537	stxa %g7, [%g2]ASI_CMP_CORE ! thread 3
538	sllx %g6, 1, %g6
539	or %g7, %g6, %g7
540	stxa %g7, [%g2]ASI_CMP_CORE ! thread 4
541	sllx %g6, 1, %g6
542	or %g7, %g6, %g7
543	stxa %g7, [%g2]ASI_CMP_CORE ! thread 5
544	sllx %g6, 1, %g6
545	or %g7, %g6, %g7
546	stxa %g7, [%g2]ASI_CMP_CORE ! thread 6
547	sllx %g6, 1, %g6
548	or %g7, %g6, %g7
549	stxa %g7, [%g2]ASI_CMP_CORE ! thread 7
550	#endif
551
552	/* Check the CORE_RUNNING_RW and CORE_RUNNING_STATUS registers. */
553	t0_3:
554	setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
555	setx ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
556	set 0x100, %g7 ! timeout value
557	#ifndef PORTABLE_CORE
558	orn %g0, %g0, %g6
559	#else
560	set 0xff, %g6
561	sllx %g6, %o2, %g6
562	#endif
563
564	t0_loop_2_top:
565	cmp %g7, 0
566	beq local_test_failed ! fail on a timeout
567	dec %g7
568
569	ldxa [%g3]ASI_CMP_CORE, %g4 ! CORE_RUNNING_STATUS
570	cmp %g4, %g6
571	bne t0_loop_2_top
572	nop
573
574	t0_4:
575	ldxa [%g2]ASI_CMP_CORE, %g5 ! CORE_RUNNING_RW
576	cmp %g4, %g5
577	bne local_test_failed ! fail on RW != STATUS
578	nop
579
580	/* Signal all the other threads that were done */
581	t0_5:
582	setx user_data_start, %g1, %g2
583	set 1, %g3
584	stx %g3, [%g2]
585
586	/* Done */
587
588	ba test_passed
589	nop
590
591	/************************************************************************
592	Thread 1 to 63 Code
593	************************************************************************/
594
595	/* Wait till thread 0 says were done */
596	main_t1_t63:
597	setx 0x1000, %g1, %g7
598	setx user_data_start, %g1, %g2
599
600	t1_t63_wait_loop_top:
601	cmp %g7, 0
602	beq local_test_failed ! fail on a timeout
603	dec %g7
604
605	ldx [%g2], %g4
606	cmp %g4, 1
607	bne t1_t63_wait_loop_top
608	nop
609
610	/* Done */
611
612	ba test_passed
613	nop
614
615
616	test_passed:
617	EXIT_GOOD
618
619	local_test_failed:
620	EXIT_BAD
621
622
623
624	/************************************************************************
625	Test case data start
626	************************************************************************/
627
628	.align 1024
629	.data
630	user_data_start:
631	.word 0x0
632	.word 0x0
633	.word 0x0
634	.word 0x0