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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / cmp / cmp_park_self.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: cmp_park_self.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39
40#include "hboot.s"
41#include "ncu_defines.h"
42
43
44
45/************************************************************************
46 Test case code start
47 ************************************************************************/
48.text
49.global main
50
51main:
52 ta T_CHANGE_HPRIV
53 nop
54
55 ! Determine thread running on
56
57 ta T_RD_THID
58 cmp %o1, 0
59 be main_t0 ! Branch if thread 0
60 nop
61
62 ba main_t1 ! Branch if thread 1
63 nop
64
65
66/************************************************************************
67 Thread 0 code
68 ************************************************************************/
69
70main_t0:
71 ta T_CHANGE_HPRIV
72 nop
73
74 /* Signal thread 1 it can start. */
75
76t0_0:
77 setx user_data_start, %g1, %g2
78 set 1, %g4
79 stx %g4, [%g2]
80
81 /* Wait for thread 1 to do all its work. */
82
83t0_wait_loop_top:
84 ldx [%g2], %g3
85 cmp %g3, 2
86 bne t0_wait_loop_top
87 nop
88
89 /* Note that at this time thread 1 will be
90 waiting for thread 0 to do all of its work. */
91
92 /* Check that CORE_RUNNING_RW = CORE_RUNNING_STATUS */
93t0_1:
94 setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
95 setx ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
96 ldxa [%g2]ASI_CMP_CORE, %g4
97 ldxa [%g3]ASI_CMP_CORE, %g5
98 cmp %g4, %g5
99 bne local_test_failed
100 nop
101
102#ifndef PORTABLE_CORE
103 /* Park thread 1, i.e. set CORE_RUNNING_RW[63:0] = 0x1 */
104t0_2:
105 set 1, %g7
106#else
107 /* Park the other thread */
108t0_core_portable_2:
109 ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID
110 set 1, %g7
111 sllx %g7, %o2, %g7
112#endif
113 stxa %g7, [%g2]ASI_CMP_CORE
114
115 /* Wait long enough for thread 1 to park. */
116t0_3:
117 set 100, %g6
118
119t0_th1_park_loop_top:
120 cmp %g6, 0
121 beq local_test_failed ! Fails if thead 1 never parks
122 nop
123
124 ldxa [%g3]ASI_CMP_CORE, %g5
125#ifndef PORTABLE_CORE
126 cmp %g5, 1
127#else
128 cmp %g5, %g7
129#endif
130 bne t0_th1_park_loop_top
131 dec %g6 ! decrement loop count
132
133 /* Also check CORE_RUNING_RW = 1 */
134t0_4:
135 ldxa [%g2]ASI_CMP_CORE, %g4
136#ifndef PORTABLE_CORE
137 cmp %g4, 1
138#else
139 cmp %g4, %g7
140#endif
141 bne local_test_failed
142 nop
143
144 /* Thread 0 attempts to park all threads, i.e. CORE_RUNNING_RW = 0 */
145t0_5:
146 stxa %g0, [%g2]ASI_CMP_CORE
147
148 /* Wait long enough for a thread to park itself. */
149t0_6:
150 set 0x100, %g6
151
152t0_th0_park_loop_top:
153 cmp %g6, 0
154 bne t0_th0_park_loop_top ! Waited long enough
155 dec %g6 ! decrement loop count
156
157 /* Check that CORE_RUNNING_RW = CORE_RUNNING_STATUS = 0x1 */
158t0_7:
159 ldxa [%g2]ASI_CMP_CORE, %g4
160#ifndef PORTABLE_CORE
161 cmp %g4, 1
162#else
163 cmp %g4, %g7
164#endif
165 bne local_test_failed
166 nop
167
168 ldxa [%g3]ASI_CMP_CORE, %g5
169#ifndef PORTABLE_CORE
170 cmp %g5, 1
171#else
172 cmp %g5, %g7
173#endif
174 bne local_test_failed
175 nop
176
177 /* Unpark thread 1 */
178t0_8:
179#ifndef PORTABLE_CORE
180 set 3, %g6
181#else
182 sllx %g7, 1, %g6
183 or %g7, %g6, %g6
184#endif
185 stxa %g6, [%g2]ASI_CMP_CORE
186
187 /* Exit */
188t0_9:
189 setx user_data_start, %g1, %g7
190 set 3, %g6
191 stx %g6, [%g7] ! Signal thread 1 to exit
192t0_10:
193 ba test_passed
194 nop
195
196
197/************************************************************************
198 Thread 1 code
199 ************************************************************************/
200
201 /* Check that CORE_RUNNING_RW = CORE_RUNNING_STATUS */
202main_t1:
203 setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
204 setx ASI_CMP_CORE_RUNNING_STATUS, %g1, %g3
205 ldxa [%g2]ASI_CMP_CORE, %g4
206 ldxa [%g3]ASI_CMP_CORE, %g5
207 cmp %g4, %g5
208 bne local_test_failed
209 nop
210
211 /* Wait for thread 0 to signal it is ready. */
212
213 setx user_data_start, %g1, %g2
214
215t1_th0_startup_loop_top:
216 ldx [%g2], %g6
217 cmp %g6, 1
218 bne t1_th0_startup_loop_top
219 nop
220
221#ifndef PORTABLE_CORE
222 /* Park thread 0, i.e. set CORE_RUNNING_RW[63:0] = 0x2 */
223t1_0:
224 setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
225 set 2, %g7
226#else
227 /* Park first thread in this core */
228t1_core_portable_0:
229 setx ASI_CMP_CORE_RUNNING_RW, %g1, %g2
230 ldxa [%g0]ASI_INTR_ID, %o2 ! get full thread ID
231 set 1, %g7
232 sllx %g7, %o2, %g7
233#endif
234 stxa %g7, [%g2]ASI_CMP_CORE
235
236 /* Wait long enough for thread 0 to park. */
237t1_1:
238 set 0x100, %g6 ! loop count
239
240t1_th0_park_wait_loop_top:
241 cmp %g6, 0
242 beq local_test_failed
243 nop
244
245 ldxa [%g3]ASI_CMP_CORE, %g5
246#ifndef PORTABLE_CORE
247 cmp %g5, 2
248#else
249 cmp %g5, %g7
250#endif
251 bne t1_th0_park_wait_loop_top
252 dec %g6
253
254 /* Check that CORE_RUNNING_RW = 0x2 */
255t1_2:
256 ldxa [%g2]ASI_CMP_CORE, %g4
257#ifndef PORTABLE_CORE
258 cmp %g4, 2
259#else
260 cmp %g4, %g7
261#endif
262 bne local_test_failed
263 nop
264
265 /* Attempt to park all threads, i.e. set CORE_RUNNING_RW = 0 */
266t1_3:
267 stxa %g0, [%g2]ASI_CMP_CORE
268
269 /* Wait long enough for a thread to park. */
270t1_4:
271 set 0x100, %g6
272
273t1_th1_park_loop_top:
274 cmp %g6, 0
275 bne t1_th1_park_loop_top ! Waited long enough
276 dec %g6 ! decrement loop count
277
278 /* Check that CORE_RUNNING_RW = CORE_RUNNING_STATUS = 0x2 */
279t1_5:
280 ldxa [%g2]ASI_CMP_CORE, %g4
281#ifndef PORTABLE_CORE
282 cmp %g4, 2
283#else
284 cmp %g4, %g7
285#endif
286 bne local_test_failed
287 nop
288
289 ldxa [%g3]ASI_CMP_CORE, %g5
290#ifndef PORTABLE_CORE
291 cmp %g5, 2
292#else
293 cmp %g5, %g7
294#endif
295 bne local_test_failed
296 nop
297
298 /* Unpark thread 0 */
299t1_6:
300#ifndef PORTABLE_CORE
301 set 3, %g6
302#else
303 srlx %g7, 1, %g6
304 or %g7, %g6, %g6
305#endif
306 stxa %g6, [%g2]ASI_CMP_CORE
307
308 /* Signal thread 0 to stop waiting. */
309t1_7:
310 setx user_data_start, %g1, %g6
311 set 2, %g1
312 stx %g1, [%g6]
313
314 /* Wait for thread 0 to do all its work. */
315t1_wait_loop_top:
316 ldx [%g6], %g5
317 cmp %g5, 3
318 bne t1_wait_loop_top
319 nop
320
321 /* Done */
322t1_8:
323 ba test_passed
324 nop
325
326/**********************************************************************/
327
328test_passed:
329 EXIT_GOOD
330
331local_test_failed:
332 EXIT_BAD
333
334
335
336/************************************************************************
337 Test case data start
338 ************************************************************************/
339
340.align 1024
341.data
342user_data_start:
343 .word 0x0
344 .word 0x0
345 .word 0x0
346 .word 0x0
Full OpenSPARC design & verification tarball including full HDL.