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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / prm / interrupt / interrupt_INT_MAN_vector.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: interrupt_INT_MAN_vector.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_HV_ALSO
39#define INTR_WAIT_COUNT 0x10
40
41#define H_HT0_Interrupt_0x60
42#define My_HT0_Interrupt_0x60 \
43 call my_trap_code; \
44 nop; \
45 retry; \
46 nop;
47
48#include "hboot.s"
49#include "niu_defines.h"
50#include "ncu_defines.h"
51#include "niu_macros.h"
52
53
54
55/************************************************************************
56 Test case code start
57 ************************************************************************/
58.text
59.global main
60
61main:
62 ta T_CHANGE_HPRIV
63 nop
64
65/* Initialize the NCU for the interrupt. */
66
67 ! Disable interrupts
68
69no_intr:
70 rdpr %pstate, %g7
71 xor %g7, 0x2, %g7 ! Reset interrupt enable
72 wrpr %g7, %pstate
73
74ncu_init:
75 ! Initially set all the Interrupt Management Registers
76 ! Later will set all those not used to have a different vector number
77
78 setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
79 setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
80
81niu_init_loop_top:
82 stx %g0, [%g2]
83 add %g2, INT_MAN_STEP, %g2
84 cmp %g4, 1
85 bne niu_init_loop_top
86 add %g4, -1, %g4
87
88 ! Initialize the NIU for TX DMA interrupt.
89
90 NIU_TX_LD_IM0_INTR_ON_MARK( 0, %g1, %g2, %g3, %g4, 0, 0 )
91
92 ! Enable interrupts
93
94yes_intr:
95 rdpr %pstate, %g7
96 or %g7, 0x2, %g7 ! Set interrupt enable
97 wrpr %g7, %pstate
98
99 ! Generate the interrupt via PIO write
100
101gen_intr:
102 setx TDMC_INTR_DBG, %g1, %g2
103 mov %g0, %g7 ! DMA channel 0
104 setx TDMC_STEP, %g1, %g3
105 mulx %g7, %g3, %g7
106 add %g2, %g7, %g2
107
108 setx 0x8000, %g1, %g4
109 stxa %g4, [%g2]ASI_PRIMARY_LITTLE
110
111 ! Do all the interrupts, 64, occur?
112
113intr_check:
114 setx 0x1000, %g1, %g4 ! timeout loop count
115 setx user_data_start, %g1, %g2
116
117intr_check_loop:
118 ld [%g2], %g7
119 cmp %g7, 64
120 be test_passed
121 dec %g4
122
123 cmp %g4, 0
124 bne intr_check_loop
125 nop
126
127 ba local_test_failed
128 nop
129
130
131
132test_passed:
133 EXIT_GOOD
134
135local_test_failed:
136
137 ! Read related interrupt registers to aid debugging
138
139read_1:
140 ldxa [%g0]ASI_INTR_RECEIVE, %i0
141 ldxa [%g0]ASI_SWVR_INTR_R, %i1
142read_2:
143 setx INT_MAN, %g1, %g2
144 ldx [%g2], %i2
145read_3:
146 set 32, %g3 ! index for logical device number
147 setx LDG_NUM_STEP, %g1, %g4
148 mulx %g4, %g3, %g3
149 setx LDG_NUM, %g1, %g2
150 add %g3, %g2, %g2
151 ldxa [%g2]ASI_PRIMARY_LITTLE, %i3
152 setx LDSV0, %g1, %g2
153 ldxa [%g2]ASI_PRIMARY_LITTLE, %i4
154 setx LDSV1, %g1, %g2
155 ldxa [%g2]ASI_PRIMARY_LITTLE, %i5
156 setx LDSV2, %g1, %g2
157 ldxa [%g2]ASI_PRIMARY_LITTLE, %i6
158 set 32, %g3 ! index for logical device number
159 setx LD_IM0_STEP, %g1, %g4
160 mulx %g4, %g3, %g3
161 setx LD_IM0, %g1, %g2
162 add %g3, %g2, %g2
163 ldxa [%g2]ASI_PRIMARY_LITTLE, %i7
164 setx LDGIMGN, %g1, %g2
165 ldxa [%g2]ASI_PRIMARY_LITTLE, %o1
166 setx LDGITMRES, %g1, %g2
167 ldxa [%g2]ASI_PRIMARY_LITTLE, %o2
168 setx SID, %g1, %g2
169 ldxa [%g2]ASI_PRIMARY_LITTLE, %o3
170read_4:
171 setx TX_ENT_MSK, %g1, %g2
172 ldxa [%g2]ASI_PRIMARY_LITTLE, %o4
173 setx TX_CS, %g1, %g2
174 ldxa [%g2]ASI_PRIMARY_LITTLE, %o5
175 setx TDMC_INTR_DBG, %g1, %g2
176 ldxa [%g2]ASI_PRIMARY_LITTLE, %o6
177
178 EXIT_BAD
179
180
181/**********************************************************************
182 Interrupt trap handler.
183**********************************************************************/
184
185.global my_trap_code
186
187my_trap_code:
188
189 ! Get the expected vector number.
190
191 setx user_data_start, %l2, %l6
192 ld [%l6], %l5
193
194 ! Clear the interrupt in the core & get vector number
195Trap1:
196 ldxa [%g0]ASI_SWVR_INTR_R, %l3
197 cmp %l3, %l5
198 bne local_test_failed
199 nop
200
201 ! Increment the expected vector number.
202Trap2:
203 add %l5, 1, %l5
204 st %l5, [%l6]
205 membar #Sync
206
207 ! Change the vector number to use in the NCU
208Trap3:
209 setx INT_MAN, %l1, %l2 ! %g2 = INT_MAN reg. addr.
210 stx %l5, [%l2]
211 membar #Sync
212
213 ! Re-enable the interrupt in the NIU
214Trap4:
215 setx LDGIMGN, %g1, %g2 ! LDGIMGN
216 setx 0x80000001, %g1, %g3
217 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
218 nop
219
220 ! Re-enable the interrupt in the transmit DMA channel
221Trap5:
222 setx TX_CS, %g1, %g2 ! TX_CS
223 ldxa [%g2]ASI_PRIMARY_LITTLE, %g0 ! Reset MK
224 nop
225
226 ! Generate another interrupt, but no more that 64
227Trap6:
228 cmp %l5, 63
229 be Trap8 ! Branch if already done 64
230 nop
231
232Trap7:
233 setx TDMC_INTR_DBG, %g1, %g2
234 mov %g0, %g7 ! DMA channel 0
235 setx TDMC_STEP, %g1, %g3
236 mulx %g7, %g3, %g7
237 add %g2, %g7, %g2
238
239 setx 0x8000, %g1, %g4
240 stxa %g4, [%g2]ASI_PRIMARY_LITTLE
241
242 ! Done
243
244Trap8:
245 jmpl %o7+0x8, %g0
246 nop
247
248
249
250
251/************************************************************************
252 Test case data start
253 ************************************************************************/
254.align 1024
255.data
256user_data_start:
257 .word 0x0
258 .word 0x0
259 .word 0x0
260 .word 0x0
261
262/* These initialization is temporary, as there looks some bug in mempli */
263
264SECTION SetRngConfig_init data_va=0x100000000
265attr_data {
266 Name = SetRngConfig_init,
267 hypervisor,
268 compressimage
269 }
270.data
271SetRngConfig_init:
272 .xword 0x0060452301000484
273/************************************************************************/
274
275SECTION SetTxRingKick_init data_va=0x100000100
276attr_data {
277 Name = SetTxRingKick_init,
278 hypervisor,
279 compressimage
280 }
281.data
282SetTxRingKick_init:
283 .xword 0x0060452301000484
284/************************************************************************/
285
286SECTION SetTxLPMask1_init data_va=0x100000200
287attr_data {
288 Name = SetTxLPMask1_init,
289 hypervisor,
290 compressimage
291 }
292.data
293SetTxLPMask1_init:
294 .xword 0x0060452301000484
295/************************************************************************/
296
297SECTION SetTxLPValue1_init data_va=0x100000300
298attr_data {
299 Name = SetTxLPValue1_init,
300 hypervisor,
301 compressimage
302 }
303.data
304SetTxLPValue1_init:
305 .xword 0x0060452301000484
306/************************************************************************/
307
308SECTION SetTxLPRELOC1_init data_va=0x100000400
309attr_data {
310 Name = SetTxLPRELOC1_init,
311 hypervisor,
312 compressimage
313 }
314.data
315SetTxLPRELOC1_init:
316 .xword 0x0060452301000484
317/************************************************************************/
318SECTION SetTxLPMask2_init data_va=0x100000500
319attr_data {
320 Name = SetTxLPMask2_init,
321 hypervisor,
322 compressimage
323 }
324.data
325SetTxLPMask2_init:
326 .xword 0x0060452301000484
327/************************************************************************/
328SECTION SetTxLPValue2_init data_va=0x100000600
329attr_data {
330 Name = SetTxLPValue2_init,
331 hypervisor,
332 compressimage
333 }
334.data
335SetTxLPValue2_init:
336 .xword 0x0060452301000484
337
338/************************************************************************/
339SECTION SetTxLPRELOC2_init data_va=0x100000700
340attr_data {
341 Name = SetTxLPRELOC2_init,
342 hypervisor,
343 compressimage
344 }
345.data
346SetTxLPRELOC2_init:
347 .xword 0x0060452301000484
348
349/************************************************************************/
350SECTION SetTxLPValid_init data_va=0x100000800
351attr_data {
352 Name = SetTxLPValid_init,
353 hypervisor,
354 compressimage
355 }
356.data
357SetTxLPValid_init:
358 .xword 0x0060452301000484
359
360/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.